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ldivmod, uldivmod: fix qdivrem calls
[minix.git] / libexec / ld.elf_so / arch / sparc64 / mdreloc.c
blobf36cd02f687f7db9bfb75b12bce14dde39e9a74e
1 /* $NetBSD: mdreloc.c,v 1.53 2012/07/22 09:21:03 martin Exp $ */
2
3 /*-
4 * Copyright (c) 2000 Eduardo Horvath.
5 * Copyright (c) 1999, 2002 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Paul Kranenburg and by Charles M. Hannum.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 #include <sys/cdefs.h>
34 #ifndef lint
35 __RCSID("$NetBSD: mdreloc.c,v 1.53 2012/07/22 09:21:03 martin Exp $");
36 #endif /* not lint */
37
38 #include <errno.h>
39 #include <stdio.h>
40 #include <stdlib.h>
41 #include <string.h>
42 #include <unistd.h>
43
44 #include "rtldenv.h"
45 #include "debug.h"
46 #include "rtld.h"
47
48 /*
49 * The following table holds for each relocation type:
50 * - the width in bits of the memory location the relocation
51 * applies to (not currently used)
52 * - the number of bits the relocation value must be shifted to the
53 * right (i.e. discard least significant bits) to fit into
54 * the appropriate field in the instruction word.
55 * - flags indicating whether
56 * * the relocation involves a symbol
57 * * the relocation is relative to the current position
58 * * the relocation is for a GOT entry
59 * * the relocation is relative to the load address
60 *
61 */
62 #define _RF_S 0x80000000 /* Resolve symbol */
63 #define _RF_A 0x40000000 /* Use addend */
64 #define _RF_P 0x20000000 /* Location relative */
65 #define _RF_G 0x10000000 /* GOT offset */
66 #define _RF_B 0x08000000 /* Load address relative */
67 #define _RF_U 0x04000000 /* Unaligned */
68 #define _RF_SZ(s) (((s) & 0xff) << 8) /* memory target size */
69 #define _RF_RS(s) ( (s) & 0xff) /* right shift */
70 static const int reloc_target_flags[R_TYPE(TLS_TPOFF64)+1] = {
71 0, /* NONE */
72 _RF_S|_RF_A| _RF_SZ(8) | _RF_RS(0), /* RELOC_8 */
73 _RF_S|_RF_A| _RF_SZ(16) | _RF_RS(0), /* RELOC_16 */
74 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* RELOC_32 */
75 _RF_S|_RF_A|_RF_P| _RF_SZ(8) | _RF_RS(0), /* DISP_8 */
76 _RF_S|_RF_A|_RF_P| _RF_SZ(16) | _RF_RS(0), /* DISP_16 */
77 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(0), /* DISP_32 */
78 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(2), /* WDISP_30 */
79 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(2), /* WDISP_22 */
80 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(10), /* HI22 */
81 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 22 */
82 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 13 */
83 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* LO10 */
84 _RF_G| _RF_SZ(32) | _RF_RS(0), /* GOT10 */
85 _RF_G| _RF_SZ(32) | _RF_RS(0), /* GOT13 */
86 _RF_G| _RF_SZ(32) | _RF_RS(10), /* GOT22 */
87 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(0), /* PC10 */
88 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(10), /* PC22 */
89 _RF_A|_RF_P| _RF_SZ(32) | _RF_RS(2), /* WPLT30 */
90 _RF_SZ(32) | _RF_RS(0), /* COPY */
91 _RF_S|_RF_A| _RF_SZ(64) | _RF_RS(0), /* GLOB_DAT */
92 _RF_SZ(32) | _RF_RS(0), /* JMP_SLOT */
93 _RF_A| _RF_B| _RF_SZ(64) | _RF_RS(0), /* RELATIVE */
94 _RF_S|_RF_A| _RF_U| _RF_SZ(32) | _RF_RS(0), /* UA_32 */
95
96 _RF_A| _RF_SZ(32) | _RF_RS(0), /* PLT32 */
97 _RF_A| _RF_SZ(32) | _RF_RS(10), /* HIPLT22 */
98 _RF_A| _RF_SZ(32) | _RF_RS(0), /* LOPLT10 */
99 _RF_A|_RF_P| _RF_SZ(32) | _RF_RS(0), /* PCPLT32 */
100 _RF_A|_RF_P| _RF_SZ(32) | _RF_RS(10), /* PCPLT22 */
101 _RF_A|_RF_P| _RF_SZ(32) | _RF_RS(0), /* PCPLT10 */
102 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 10 */
103 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 11 */
104 _RF_S|_RF_A| _RF_SZ(64) | _RF_RS(0), /* 64 */
105 _RF_S|_RF_A|/*extra*/ _RF_SZ(32) | _RF_RS(0), /* OLO10 */
106 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(42), /* HH22 */
107 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(32), /* HM10 */
108 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(10), /* LM22 */
109 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(42), /* PC_HH22 */
110 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(32), /* PC_HM10 */
111 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(10), /* PC_LM22 */
112 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(2), /* WDISP16 */
113 _RF_S|_RF_A|_RF_P| _RF_SZ(32) | _RF_RS(2), /* WDISP19 */
114 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* GLOB_JMP */
115 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 7 */
116 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 5 */
117 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* 6 */
118 _RF_S|_RF_A|_RF_P| _RF_SZ(64) | _RF_RS(0), /* DISP64 */
119 _RF_A| _RF_SZ(64) | _RF_RS(0), /* PLT64 */
120 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(10), /* HIX22 */
121 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* LOX10 */
122 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(22), /* H44 */
123 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(12), /* M44 */
124 _RF_S|_RF_A| _RF_SZ(32) | _RF_RS(0), /* L44 */
125 _RF_S|_RF_A| _RF_SZ(64) | _RF_RS(0), /* REGISTER */
126 _RF_S|_RF_A| _RF_U| _RF_SZ(64) | _RF_RS(0), /* UA64 */
127 _RF_S|_RF_A| _RF_U| _RF_SZ(16) | _RF_RS(0), /* UA16 */
128 /* TLS relocs not represented here! */
129 };
130
131 #ifdef RTLD_DEBUG_RELOC
132 static const char *reloc_names[] = {
133 "NONE", "RELOC_8", "RELOC_16", "RELOC_32", "DISP_8",
134 "DISP_16", "DISP_32", "WDISP_30", "WDISP_22", "HI22",
135 "22", "13", "LO10", "GOT10", "GOT13",
136 "GOT22", "PC10", "PC22", "WPLT30", "COPY",
137 "GLOB_DAT", "JMP_SLOT", "RELATIVE", "UA_32", "PLT32",
138 "HIPLT22", "LOPLT10", "LOPLT10", "PCPLT22", "PCPLT32",
139 "10", "11", "64", "OLO10", "HH22",
140 "HM10", "LM22", "PC_HH22", "PC_HM10", "PC_LM22",
141 "WDISP16", "WDISP19", "GLOB_JMP", "7", "5", "6",
142 "DISP64", "PLT64", "HIX22", "LOX10", "H44", "M44",
143 "L44", "REGISTER", "UA64", "UA16",
144 "TLS_GD_HI22", "TLS_GD_LO10", "TLS_GD_ADD", "TLS_GD_CALL",
145 "TLS_LDM_HI22", "TLS_LDM_LO10", "TLS_LDM_ADD", "TLS_LDM_CALL",
146 "TLS_LDO_HIX22", "TLS_LDO_LOX10", "TLS_LDO_ADD", "TLS_IE_HI22",
147 "TLS_IE_LO10", "TLS_IE_LD", "TLS_IE_LDX", "TLS_IE_ADD", "TLS_LE_HIX22",
148 "TLS_LE_LOX10", "TLS_DTPMOD32", "TLS_DTPMOD64", "TLS_DTPOFF32",
149 "TLS_DTPOFF64", "TLS_TPOFF32", "TLS_TPOFF64",
150 };
151 #endif
152
153 #define RELOC_RESOLVE_SYMBOL(t) ((reloc_target_flags[t] & _RF_S) != 0)
154 #define RELOC_PC_RELATIVE(t) ((reloc_target_flags[t] & _RF_P) != 0)
155 #define RELOC_BASE_RELATIVE(t) ((reloc_target_flags[t] & _RF_B) != 0)
156 #define RELOC_UNALIGNED(t) ((reloc_target_flags[t] & _RF_U) != 0)
157 #define RELOC_USE_ADDEND(t) ((reloc_target_flags[t] & _RF_A) != 0)
158 #define RELOC_TARGET_SIZE(t) ((reloc_target_flags[t] >> 8) & 0xff)
159 #define RELOC_VALUE_RIGHTSHIFT(t) (reloc_target_flags[t] & 0xff)
160 #define RELOC_TLS(t) (t >= R_TYPE(TLS_GD_HI22))
161
162 static const long reloc_target_bitmask[] = {
163 #define _BM(x) (~(-(1ULL << (x))))
164 0, /* NONE */
165 _BM(8), _BM(16), _BM(32), /* RELOC_8, _16, _32 */
166 _BM(8), _BM(16), _BM(32), /* DISP8, DISP16, DISP32 */
167 _BM(30), _BM(22), /* WDISP30, WDISP22 */
168 _BM(22), _BM(22), /* HI22, _22 */
169 _BM(13), _BM(10), /* RELOC_13, _LO10 */
170 _BM(10), _BM(13), _BM(22), /* GOT10, GOT13, GOT22 */
171 _BM(10), _BM(22), /* _PC10, _PC22 */
172 _BM(30), 0, /* _WPLT30, _COPY */
173 _BM(32), _BM(32), _BM(32), /* _GLOB_DAT, JMP_SLOT, _RELATIVE */
174 _BM(32), _BM(32), /* _UA32, PLT32 */
175 _BM(22), _BM(10), /* _HIPLT22, LOPLT10 */
176 _BM(32), _BM(22), _BM(10), /* _PCPLT32, _PCPLT22, _PCPLT10 */
177 _BM(10), _BM(11), -1, /* _10, _11, _64 */
178 _BM(10), _BM(22), /* _OLO10, _HH22 */
179 _BM(10), _BM(22), /* _HM10, _LM22 */
180 _BM(22), _BM(10), _BM(22), /* _PC_HH22, _PC_HM10, _PC_LM22 */
181 _BM(16), _BM(19), /* _WDISP16, _WDISP19 */
182 -1, /* GLOB_JMP */
183 _BM(7), _BM(5), _BM(6) /* _7, _5, _6 */
184 -1, -1, /* DISP64, PLT64 */
185 _BM(22), _BM(13), /* HIX22, LOX10 */
186 _BM(22), _BM(10), _BM(13), /* H44, M44, L44 */
187 -1, -1, _BM(16), /* REGISTER, UA64, UA16 */
188 #undef _BM
189 };
190 #define RELOC_VALUE_BITMASK(t) (reloc_target_bitmask[t])
191
192 /*
193 * Instruction templates:
194 */
195 #define BAA 0x10400000 /* ba,a %xcc, 0 */
196 #define SETHI 0x03000000 /* sethi %hi(0), %g1 */
197 #define JMP 0x81c06000 /* jmpl %g1+%lo(0), %g0 */
198 #define NOP 0x01000000 /* sethi %hi(0), %g0 */
199 #define OR 0x82806000 /* or %g1, 0, %g1 */
200 #define XOR 0x82c06000 /* xor %g1, 0, %g1 */
201 #define MOV71 0x8283a000 /* or %o7, 0, %g1 */
202 #define MOV17 0x9c806000 /* or %g1, 0, %o7 */
203 #define CALL 0x40000000 /* call 0 */
204 #define SLLX 0x8b407000 /* sllx %g1, 0, %g1 */
205 #define SETHIG5 0x0b000000 /* sethi %hi(0), %g5 */
206 #define ORG5 0x82804005 /* or %g1, %g5, %g1 */
207
208
209 /* %hi(v)/%lo(v) with variable shift */
210 #define HIVAL(v, s) (((v) >> (s)) & 0x003fffff)
211 #define LOVAL(v, s) (((v) >> (s)) & 0x000003ff)
212
213 void _rtld_bind_start_0(long, long);
214 void _rtld_bind_start_1(long, long);
215 void _rtld_relocate_nonplt_self(Elf_Dyn *, Elf_Addr);
216 caddr_t _rtld_bind(const Obj_Entry *, Elf_Word);
217
218 /*
219 * Install rtld function call into this PLT slot.
220 */
221 #define SAVE 0x9de3bf50 /* i.e. `save %sp,-176,%sp' */
222 #define SETHI_l0 0x21000000
223 #define SETHI_l1 0x23000000
224 #define OR_l0_l0 0xa0142000
225 #define SLLX_l0_32_l0 0xa12c3020
226 #define OR_l0_l1_l0 0xa0140011
227 #define JMPL_l0_o0 0x91c42000
228 #define MOV_g1_o1 0x92100001
229
230 void _rtld_install_plt(Elf_Word *, Elf_Addr);
231 static inline int _rtld_relocate_plt_object(const Obj_Entry *,
232 const Elf_Rela *, Elf_Addr *);
233
234 void
235 _rtld_install_plt(Elf_Word *pltgot, Elf_Addr proc)
236 {
237 pltgot[0] = SAVE;
238 pltgot[1] = SETHI_l0 | HIVAL(proc, 42);
239 pltgot[2] = SETHI_l1 | HIVAL(proc, 10);
240 pltgot[3] = OR_l0_l0 | LOVAL(proc, 32);
241 pltgot[4] = SLLX_l0_32_l0;
242 pltgot[5] = OR_l0_l1_l0;
243 pltgot[6] = JMPL_l0_o0 | LOVAL(proc, 0);
244 pltgot[7] = MOV_g1_o1;
245 }
246
247 void
248 _rtld_setup_pltgot(const Obj_Entry *obj)
249 {
250 /*
251 * On sparc64 we got troubles.
252 *
253 * Instructions are 4 bytes long.
254 * Elf[64]_Addr is 8 bytes long, so are our pltglot[]
255 * array entries.
256 * Each PLT entry jumps to PLT0 to enter the dynamic
257 * linker.
258 * Loading an arbitrary 64-bit pointer takes 6
259 * instructions and 2 registers.
260 *
261 * Somehow we need to issue a save to get a new stack
262 * frame, load the address of the dynamic linker, and
263 * jump there, in 8 instructions or less.
264 *
265 * Oh, we need to fill out both PLT0 and PLT1.
266 */
267 {
268 Elf_Word *entry = (Elf_Word *)obj->pltgot;
269
270 /* Install in entries 0 and 1 */
271 _rtld_install_plt(&entry[0], (Elf_Addr) &_rtld_bind_start_0);
272 _rtld_install_plt(&entry[8], (Elf_Addr) &_rtld_bind_start_1);
273
274 /*
275 * Install the object reference in first slot
276 * of entry 2.
277 */
278 obj->pltgot[8] = (Elf_Addr) obj;
279 }
280 }
281
282 void
283 _rtld_relocate_nonplt_self(Elf_Dyn *dynp, Elf_Addr relocbase)
284 {
285 const Elf_Rela *rela = 0, *relalim;
286 Elf_Addr relasz = 0;
287 Elf_Addr *where;
288
289 for (; dynp->d_tag != DT_NULL; dynp++) {
290 switch (dynp->d_tag) {
291 case DT_RELA:
292 rela = (const Elf_Rela *)(relocbase + dynp->d_un.d_ptr);
293 break;
294 case DT_RELASZ:
295 relasz = dynp->d_un.d_val;
296 break;
297 }
298 }
299 relalim = (const Elf_Rela *)((const uint8_t *)rela + relasz);
300 for (; rela < relalim; rela++) {
301 where = (Elf_Addr *)(relocbase + rela->r_offset);
302 *where = (Elf_Addr)(relocbase + rela->r_addend);
303 }
304 }
305
306 int
307 _rtld_relocate_nonplt_objects(Obj_Entry *obj)
308 {
309 const Elf_Rela *rela;
310 const Elf_Sym *def = NULL;
311 const Obj_Entry *defobj = NULL;
312
313 for (rela = obj->rela; rela < obj->relalim; rela++) {
314 Elf_Addr *where;
315 Elf_Word type;
316 Elf_Addr value = 0, mask;
317 unsigned long symnum;
318
319 where = (Elf_Addr *) (obj->relocbase + rela->r_offset);
320 symnum = ELF_R_SYM(rela->r_info);
321
322 type = ELF_R_TYPE(rela->r_info);
323 if (type == R_TYPE(NONE))
324 continue;
325
326 /* OLO10 relocations have extra info */
327 if ((type & 0x00ff) == R_SPARC_OLO10)
328 type = R_SPARC_OLO10;
329
330 /* We do JMP_SLOTs in _rtld_bind() below */
331 if (type == R_TYPE(JMP_SLOT))
332 continue;
333
334 /* COPY relocs are also handled elsewhere */
335 if (type == R_TYPE(COPY))
336 continue;
337
338 /*
339 * We use the fact that relocation types are an `enum'
340 * Note: R_SPARC_TLS_TPOFF64 is currently numerically largest.
341 */
342 if (type > R_TYPE(TLS_TPOFF64)) {
343 dbg(("unknown relocation type %x at %p", type, rela));
344 return -1;
345 }
346
347 value = rela->r_addend;
348
349 /*
350 * Handle TLS relocations here, they are different.
351 */
352 if (RELOC_TLS(type)) {
353 switch (type) {
354 case R_TYPE(TLS_DTPMOD64):
355 def = _rtld_find_symdef(symnum, obj,
356 &defobj, false);
357 if (def == NULL)
358 return -1;
359
360 *where = (Elf64_Addr)defobj->tlsindex;
361
362 rdbg(("TLS_DTPMOD64 %s in %s --> %p",
363 obj->strtab +
364 obj->symtab[symnum].st_name,
365 obj->path, (void *)*where));
366
367 break;
368
369 case R_TYPE(TLS_DTPOFF64):
370 def = _rtld_find_symdef(symnum, obj,
371 &defobj, false);
372 if (def == NULL)
373 return -1;
374
375 *where = (Elf64_Addr)(def->st_value
376 + rela->r_addend);
377
378 rdbg(("DTPOFF64 %s in %s --> %p",
379 obj->strtab +
380 obj->symtab[symnum].st_name,
381 obj->path, (void *)*where));
382
383 break;
384
385 case R_TYPE(TLS_TPOFF64):
386 def = _rtld_find_symdef(symnum, obj,
387 &defobj, false);
388 if (def == NULL)
389 return -1;
390
391 if (!defobj->tls_done &&
392 _rtld_tls_offset_allocate(obj))
393 return -1;
394
395 *where = (Elf64_Addr)(def->st_value -
396 defobj->tlsoffset +
397 rela->r_addend);
398
399 rdbg(("TLS_TPOFF64 %s in %s --> %p",
400 obj->strtab +
401 obj->symtab[symnum].st_name,
402 obj->path, (void *)*where));
403
404 break;
405 }
406 continue;
407 }
408
409 /*
410 * Handle relative relocs here, as an optimization.
411 */
412 if (type == R_TYPE(RELATIVE)) {
413 *where = (Elf_Addr)(obj->relocbase + value);
414 rdbg(("RELATIVE in %s --> %p", obj->path,
415 (void *)*where));
416 continue;
417 }
418
419 if (RELOC_RESOLVE_SYMBOL(type)) {
420
421 /* Find the symbol */
422 def = _rtld_find_symdef(symnum, obj, &defobj,
423 false);
424 if (def == NULL)
425 return -1;
426
427 /* Add in the symbol's absolute address */
428 value += (Elf_Addr)(defobj->relocbase + def->st_value);
429 }
430
431 if (type == R_SPARC_OLO10) {
432 value = (value & 0x3ff)
433 + (((Elf64_Xword)rela->r_info<<32)>>40);
434 }
435
436 if (RELOC_PC_RELATIVE(type)) {
437 value -= (Elf_Addr)where;
438 }
439
440 if (RELOC_BASE_RELATIVE(type)) {
441 /*
442 * Note that even though sparcs use `Elf_rela'
443 * exclusively we still need the implicit memory addend
444 * in relocations referring to GOT entries.
445 * Undoubtedly, someone f*cked this up in the distant
446 * past, and now we're stuck with it in the name of
447 * compatibility for all eternity..
448 *
449 * In any case, the implicit and explicit should be
450 * mutually exclusive. We provide a check for that
451 * here.
452 */
453 #ifdef DIAGNOSTIC
454 if (value != 0 && *where != 0) {
455 xprintf("BASE_REL(%s): where=%p, *where 0x%lx, "
456 "addend=0x%lx, base %p\n",
457 obj->path, where, *where,
458 rela->r_addend, obj->relocbase);
459 }
460 #endif
461 /* XXXX -- apparently we ignore the preexisting value */
462 value += (Elf_Addr)(obj->relocbase);
463 }
464
465 mask = RELOC_VALUE_BITMASK(type);
466 value >>= RELOC_VALUE_RIGHTSHIFT(type);
467 value &= mask;
468
469 if (RELOC_UNALIGNED(type)) {
470 /* Handle unaligned relocations. */
471 Elf_Addr tmp = 0;
472 char *ptr = (char *)where;
473 int i, size = RELOC_TARGET_SIZE(type)/8;
474
475 /* Read it in one byte at a time. */
476 for (i=0; i<size; i++)
477 tmp = (tmp << 8) | ptr[i];
478
479 tmp &= ~mask;
480 tmp |= value;
481
482 /* Write it back out. */
483 for (i=0; i<size; i++)
484 ptr[i] = ((tmp >> (8*i)) & 0xff);
485 #ifdef RTLD_DEBUG_RELOC
486 value = (Elf_Addr)tmp;
487 #endif
488
489 } else if (RELOC_TARGET_SIZE(type) > 32) {
490 *where &= ~mask;
491 *where |= value;
492 #ifdef RTLD_DEBUG_RELOC
493 value = (Elf_Addr)*where;
494 #endif
495 } else {
496 Elf32_Addr *where32 = (Elf32_Addr *)where;
497
498 *where32 &= ~mask;
499 *where32 |= value;
500 #ifdef RTLD_DEBUG_RELOC
501 value = (Elf_Addr)*where32;
502 #endif
503 }
504
505 #ifdef RTLD_DEBUG_RELOC
506 if (RELOC_RESOLVE_SYMBOL(type)) {
507 rdbg(("%s %s in %s --> %p in %s", reloc_names[type],
508 obj->strtab + obj->symtab[symnum].st_name,
509 obj->path, (void *)value, defobj->path));
510 } else {
511 rdbg(("%s in %s --> %p", reloc_names[type],
512 obj->path, (void *)value));
513 }
514 #endif
515 }
516 return (0);
517 }
518
519 int
520 _rtld_relocate_plt_lazy(const Obj_Entry *obj)
521 {
522 return (0);
523 }
524
525 caddr_t
526 _rtld_bind(const Obj_Entry *obj, Elf_Word reloff)
527 {
528 const Elf_Rela *rela = obj->pltrela + reloff;
529 Elf_Addr result;
530 int err;
531
532 result = 0; /* XXX gcc */
533
534 if (ELF_R_TYPE(obj->pltrela->r_info) == R_TYPE(JMP_SLOT)) {
535 /*
536 * XXXX
537 *
538 * The first four PLT entries are reserved. There is some
539 * disagreement whether they should have associated relocation
540 * entries. Both the SPARC 32-bit and 64-bit ELF
541 * specifications say that they should have relocation entries,
542 * but the 32-bit SPARC binutils do not generate them, and now
543 * the 64-bit SPARC binutils have stopped generating them too.
544 *
545 * So, to provide binary compatibility, we will check the first
546 * entry, if it is reserved it should not be of the type
547 * JMP_SLOT. If it is JMP_SLOT, then the 4 reserved entries
548 * were not generated and our index is 4 entries too far.
549 */
550 rela -= 4;
551 }
552
553 _rtld_shared_enter();
554 err = _rtld_relocate_plt_object(obj, rela, &result);
555 if (err)
556 _rtld_die();
557 _rtld_shared_exit();
558
559 return (caddr_t)result;
560 }
561
562 int
563 _rtld_relocate_plt_objects(const Obj_Entry *obj)
564 {
565 const Elf_Rela *rela;
566
567 rela = obj->pltrela;
568
569 /*
570 * Check for first four reserved entries - and skip them.
571 * See above for details.
572 */
573 if (ELF_R_TYPE(obj->pltrela->r_info) != R_TYPE(JMP_SLOT))
574 rela += 4;
575
576 for (; rela < obj->pltrelalim; rela++)
577 if (_rtld_relocate_plt_object(obj, rela, NULL) < 0)
578 return -1;
579
580 return 0;
581 }
582
583 /*
584 * New inline function that is called by _rtld_relocate_plt_object and
585 * _rtld_bind
586 */
587 static inline int
588 _rtld_relocate_plt_object(const Obj_Entry *obj, const Elf_Rela *rela,
589 Elf_Addr *tp)
590 {
591 Elf_Word *where = (Elf_Word *)(obj->relocbase + rela->r_offset);
592 const Elf_Sym *def;
593 const Obj_Entry *defobj;
594 Elf_Addr value, offset;
595 unsigned long info = rela->r_info;
596
597 assert(ELF_R_TYPE(info) == R_TYPE(JMP_SLOT));
598
599 def = _rtld_find_plt_symdef(ELF_R_SYM(info), obj, &defobj, tp != NULL);
600 if (__predict_false(def == NULL))
601 return -1;
602 if (__predict_false(def == &_rtld_sym_zero))
603 return 0;
604
605 value = (Elf_Addr)(defobj->relocbase + def->st_value);
606 rdbg(("bind now/fixup in %s --> new=%p",
607 defobj->strtab + def->st_name, (void *)value));
608
609 /*
610 * At the PLT entry pointed at by `where', we now construct a direct
611 * transfer to the now fully resolved function address.
612 *
613 * A PLT entry is supposed to start by looking like this:
614 *
615 * sethi %hi(. - .PLT0), %g1
616 * ba,a %xcc, .PLT1
617 * nop
618 * nop
619 * nop
620 * nop
621 * nop
622 * nop
623 *
624 * When we replace these entries we start from the last instruction
625 * and do it in reverse order so the last thing we do is replace the
626 * branch. That allows us to change this atomically.
627 *
628 * We now need to find out how far we need to jump. We have a choice
629 * of several different relocation techniques which are increasingly
630 * expensive.
631 */
632
633 offset = ((Elf_Addr)where) - value;
634 if (rela->r_addend) {
635 Elf_Addr *ptr = (Elf_Addr *)where;
636 /*
637 * This entry is >= 32768. The relocations points to a
638 * PC-relative pointer to the bind_0 stub at the top of the
639 * PLT section. Update it to point to the target function.
640 */
641 ptr[0] += value - (Elf_Addr)obj->pltgot;
642
643 } else if (offset <= (1L<<20) && (Elf_SOff)offset >= -(1L<<20)) {
644 /*
645 * We're within 1MB -- we can use a direct branch insn.
646 *
647 * We can generate this pattern:
648 *
649 * sethi %hi(. - .PLT0), %g1
650 * ba,a %xcc, addr
651 * nop
652 * nop
653 * nop
654 * nop
655 * nop
656 * nop
657 *
658 */
659 where[1] = BAA | ((offset >> 2) & 0x3fffff);
660 __asm volatile("iflush %0+4" : : "r" (where));
661 } else if (value < (1L<<32)) {
662 /*
663 * We're within 32-bits of address zero.
664 *
665 * The resulting code in the jump slot is:
666 *
667 * sethi %hi(. - .PLT0), %g1
668 * sethi %hi(addr), %g1
669 * jmp %g1+%lo(addr)
670 * nop
671 * nop
672 * nop
673 * nop
674 * nop
675 *
676 */
677 where[2] = JMP | LOVAL(value, 0);
678 where[1] = SETHI | HIVAL(value, 10);
679 __asm volatile("iflush %0+8" : : "r" (where));
680 __asm volatile("iflush %0+4" : : "r" (where));
681
682 } else if ((Elf_SOff)value <= 0 && (Elf_SOff)value > -(1L<<32)) {
683 /*
684 * We're within 32-bits of address -1.
685 *
686 * The resulting code in the jump slot is:
687 *
688 * sethi %hi(. - .PLT0), %g1
689 * sethi %hix(addr), %g1
690 * xor %g1, %lox(addr), %g1
691 * jmp %g1
692 * nop
693 * nop
694 * nop
695 * nop
696 *
697 */
698 where[3] = JMP;
699 where[2] = XOR | ((~value) & 0x00001fff);
700 where[1] = SETHI | HIVAL(~value, 10);
701 __asm volatile("iflush %0+12" : : "r" (where));
702 __asm volatile("iflush %0+8" : : "r" (where));
703 __asm volatile("iflush %0+4" : : "r" (where));
704
705 } else if (offset <= (1L<<32) && (Elf_SOff)offset >= -((1L<<32) - 4)) {
706 /*
707 * We're within 32-bits -- we can use a direct call insn
708 *
709 * The resulting code in the jump slot is:
710 *
711 * sethi %hi(. - .PLT0), %g1
712 * mov %o7, %g1
713 * call (.+offset)
714 * mov %g1, %o7
715 * nop
716 * nop
717 * nop
718 * nop
719 *
720 */
721 where[3] = MOV17;
722 where[2] = CALL | ((offset >> 4) & 0x3fffffff);
723 where[1] = MOV71;
724 __asm volatile("iflush %0+12" : : "r" (where));
725 __asm volatile("iflush %0+8" : : "r" (where));
726 __asm volatile("iflush %0+4" : : "r" (where));
727
728 } else if (offset < (1L<<44)) {
729 /*
730 * We're within 44 bits. We can generate this pattern:
731 *
732 * The resulting code in the jump slot is:
733 *
734 * sethi %hi(. - .PLT0), %g1
735 * sethi %h44(addr), %g1
736 * or %g1, %m44(addr), %g1
737 * sllx %g1, 12, %g1
738 * jmp %g1+%l44(addr)
739 * nop
740 * nop
741 * nop
742 *
743 */
744 where[4] = JMP | LOVAL(offset, 0);
745 where[3] = SLLX | 12;
746 where[2] = OR | (((offset) >> 12) & 0x00001fff);
747 where[1] = SETHI | HIVAL(offset, 22);
748 __asm volatile("iflush %0+16" : : "r" (where));
749 __asm volatile("iflush %0+12" : : "r" (where));
750 __asm volatile("iflush %0+8" : : "r" (where));
751 __asm volatile("iflush %0+4" : : "r" (where));
752
753 } else if ((Elf_SOff)offset < 0 && (Elf_SOff)offset > -(1L<<44)) {
754 /*
755 * We're within 44 bits. We can generate this pattern:
756 *
757 * The resulting code in the jump slot is:
758 *
759 * sethi %hi(. - .PLT0), %g1
760 * sethi %h44(-addr), %g1
761 * xor %g1, %m44(-addr), %g1
762 * sllx %g1, 12, %g1
763 * jmp %g1+%l44(addr)
764 * nop
765 * nop
766 * nop
767 *
768 */
769 where[4] = JMP | LOVAL(offset, 0);
770 where[3] = SLLX | 12;
771 where[2] = XOR | (((~offset) >> 12) & 0x00001fff);
772 where[1] = SETHI | HIVAL(~offset, 22);
773 __asm volatile("iflush %0+16" : : "r" (where));
774 __asm volatile("iflush %0+12" : : "r" (where));
775 __asm volatile("iflush %0+8" : : "r" (where));
776 __asm volatile("iflush %0+4" : : "r" (where));
777
778 } else {
779 /*
780 * We need to load all 64-bits
781 *
782 * The resulting code in the jump slot is:
783 *
784 * sethi %hi(. - .PLT0), %g1
785 * sethi %hh(addr), %g1
786 * sethi %lm(addr), %g5
787 * or %g1, %hm(addr), %g1
788 * sllx %g1, 32, %g1
789 * or %g1, %g5, %g1
790 * jmp %g1+%lo(addr)
791 * nop
792 *
793 */
794 where[6] = JMP | LOVAL(value, 0);
795 where[5] = ORG5;
796 where[4] = SLLX | 32;
797 where[3] = OR | LOVAL(value, 32);
798 where[2] = SETHIG5 | HIVAL(value, 10);
799 where[1] = SETHI | HIVAL(value, 42);
800 __asm volatile("iflush %0+24" : : "r" (where));
801 __asm volatile("iflush %0+20" : : "r" (where));
802 __asm volatile("iflush %0+16" : : "r" (where));
803 __asm volatile("iflush %0+12" : : "r" (where));
804 __asm volatile("iflush %0+8" : : "r" (where));
805 __asm volatile("iflush %0+4" : : "r" (where));
806
807 }
808
809 if (tp)
810 *tp = value;
811
812 return 0;
813 }
MINIX 3 (repo.or.cz mirror)