sys/arch/arm/include/cpuconf.h

   1 /*      $NetBSD: cpuconf.h,v 1.21 2013/05/19 15:51:10 rkujawa Exp $     */
   2
   3 /*
   4  * Copyright (c) 2002 Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed for the NetBSD Project by
  20  *      Wasabi Systems, Inc.
  21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  22  *    or promote products derived from this software without specific prior
  23  *    written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef _ARM_CPUCONF_H_
  39 #define _ARM_CPUCONF_H_
  40
  41 #if defined(_KERNEL_OPT)
  42 #include "opt_cputypes.h"
  43 #include "opt_cpuoptions.h"
  44 #endif /* _KERNEL_OPT */
  45
  46 #if defined(CPU_XSCALE_PXA250) || defined(CPU_XSCALE_PXA270)
  47 #define __CPU_XSCALE_PXA2XX
  48 #endif
  49
  50 #ifdef CPU_XSCALE_PXA2X0
  51 #warning option CPU_XSCALE_PXA2X0 is obsolete. Use CPU_XSCALE_PXA250 and/or CPU_XSCALE_PXA270.
  52 #endif
  53
  54 /*
  55  * IF YOU CHANGE THIS FILE, MAKE SURE TO UPDATE THE DEFINITION OF
  56  * "PMAP_NEEDS_PTE_SYNC" IN <arm/arm32/pmap.h> FOR THE CPU TYPE
  57  * YOU ARE ADDING SUPPORT FOR.
  58  */
  59
  60 #if 0
  61 /*
  62  * Step 1: Count the number of CPU types configured into the kernel.
  63  */
  64 #if defined(_KERNEL_OPT)
  65 #define CPU_NTYPES      (defined(CPU_ARM2) + defined(CPU_ARM250) +      \
  66                          defined(CPU_ARM3) +                            \
  67                          defined(CPU_ARM6) + defined(CPU_ARM7) +        \
  68                          defined(CPU_ARM7TDMI) +                        \
  69                          defined(CPU_ARM8) + defined(CPU_ARM9) +        \
  70                          defined(CPU_ARM9E) +                           \
  71                          defined(CPU_ARM10) +                           \
  72                          defined(CPU_ARM11) +                           \
  73                          defined(CPU_ARM1136) +                         \
  74                          defined(CPU_ARM1176) +                         \
  75                          defined(CPU_ARM11MPCORE) +                     \
  76                          defined(CPU_CORTEX) +                          \
  77                          defined(CPU_CORTEXA8) +                        \
  78                          defined(CPU_CORTEXA9) +                        \
  79                          defined(CPU_SA110) + defined(CPU_SA1100) +     \
  80                          defined(CPU_SA1110) +                          \
  81                          defined(CPU_FA526) +                           \
  82                          defined(CPU_IXP12X0) +                         \
  83                          defined(CPU_XSCALE_80200) +                    \
  84                          defined(CPU_XSCALE_80321) +                    \
  85                          defined(__CPU_XSCALE_PXA2XX) +                 \
  86                          defined(CPU_XSCALE_IXP425)) +                  \
  87                          defined(CPU_SHEEVA))
  88 #else
  89 #define CPU_NTYPES      2
  90 #endif /* _KERNEL_OPT */
  91 #endif
  92
  93 /*
  94  * Step 2: Determine which ARM architecture versions are configured.
  95  */
  96 #if !defined(_KERNEL_OPT) ||                                            \
  97     (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3))
  98 #define ARM_ARCH_2      1
  99 #else
 100 #define ARM_ARCH_2      0
 101 #endif
 102
 103 #if !defined(_KERNEL_OPT) ||                                            \
 104     (defined(CPU_ARM6) || defined(CPU_ARM7))
 105 #define ARM_ARCH_3      1
 106 #else
 107 #define ARM_ARCH_3      0
 108 #endif
 109
 110 #if !defined(_KERNEL_OPT) ||                                            \
 111     (defined(CPU_ARM7TDMI) || defined(CPU_ARM8) || defined(CPU_ARM9) || \
 112      defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_FA526) || \
 113      defined(CPU_SA1110) || defined(CPU_IXP12X0))
 114 #define ARM_ARCH_4      1
 115 #else
 116 #define ARM_ARCH_4      0
 117 #endif
 118
 119 #if !defined(_KERNEL_OPT) ||                                            \
 120     (defined(CPU_ARM9E) || defined(CPU_ARM10) ||                        \
 121      defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||          \
 122      defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425)) ||     \
 123      defined(CPU_SHEEVA)
 124 #define ARM_ARCH_5      1
 125 #else
 126 #define ARM_ARCH_5      0
 127 #endif
 128
 129 #if defined(CPU_ARM11) || defined(CPU_CORTEXA8) || defined(CPU_ARM11MPCORE)
 130 #define ARM_ARCH_6      1
 131 #else
 132 #define ARM_ARCH_6      0
 133 #endif
 134
 135 #if defined(CPU_CORTEX) || defined(CPU_PJ4B)
 136 #define ARM_ARCH_7      1
 137 #else
 138 #define ARM_ARCH_7      0
 139 #endif
 140
 141 #define ARM_NARCH       (ARM_ARCH_2 + ARM_ARCH_3 + ARM_ARCH_4 + \
 142                          ARM_ARCH_5 + ARM_ARCH_6 + ARM_ARCH_7)
 143 #if ARM_NARCH == 0
 144 #error ARM_NARCH is 0
 145 #endif
 146
 147 #if ARM_ARCH_5 || ARM_ARCH_6 || ARM_ARCH_7
 148 /*
 149  * We could support Thumb code on v4T, but the lack of clean interworking
 150  * makes that hard.
 151  */
 152 #define THUMB_CODE
 153 #endif
 154
 155 /*
 156  * Step 3: Define which MMU classes are configured:
 157  *
 158  *      ARM_MMU_MEMC            Prehistoric, external memory controller
 159  *                              and MMU for ARMv2 CPUs.
 160  *
 161  *      ARM_MMU_GENERIC         Generic ARM MMU, compatible with ARM6.
 162  *
 163  *      ARM_MMU_SA1             StrongARM SA-1 MMU.  Compatible with generic
 164  *                              ARM MMU, but has no write-through cache mode.
 165  *
 166  *      ARM_MMU_XSCALE          XScale MMU.  Compatible with generic ARM
 167  *                              MMU, but also has several extensions which
 168  *                              require different PTE layout to use.
 169  *
 170  *      ARM_MMU_V6C             ARM v6 MMU in backward compatible mode.
 171  *                              Compatible with generic ARM MMU, but
 172  *                              also has several extensions which
 173  *                              require different PTE layouts to use.
 174  *                              XP bit in CP15 control reg is cleared.
 175  *
 176  *      ARM_MMU_V6N             ARM v6 MMU with XP bit of CP15 control reg
 177  *                              set.  New features such as shared-bit
 178  *                              and excute-never bit are available.
 179  *                              Multiprocessor support needs this mode.
 180  *
 181  *      ARM_MMU_V7              ARM v7 MMU.
 182  */
 183 #if !defined(_KERNEL_OPT) ||                                            \
 184     (defined(CPU_ARM2) || defined(CPU_ARM250) || defined(CPU_ARM3))
 185 #define ARM_MMU_MEMC            1
 186 #else
 187 #define ARM_MMU_MEMC            0
 188 #endif
 189
 190 #if !defined(_KERNEL_OPT) ||                                            \
 191     (defined(CPU_ARM6) || defined(CPU_ARM7) || defined(CPU_ARM7TDMI) || \
 192      defined(CPU_ARM8) || defined(CPU_ARM9) || defined(CPU_ARM9E) ||    \
 193      defined(CPU_ARM10) || defined(CPU_FA526)) || defined(CPU_SHEEVA)
 194 #define ARM_MMU_GENERIC         1
 195 #else
 196 #define ARM_MMU_GENERIC         0
 197 #endif
 198
 199 #if !defined(_KERNEL_OPT) ||                                            \
 200     (defined(CPU_SA110) || defined(CPU_SA1100) || defined(CPU_SA1110) ||\
 201      defined(CPU_IXP12X0))
 202 #define ARM_MMU_SA1             1
 203 #else
 204 #define ARM_MMU_SA1             0
 205 #endif
 206
 207 #if !defined(_KERNEL_OPT) ||                                            \
 208     (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) ||          \
 209      defined(__CPU_XSCALE_PXA2XX) || defined(CPU_XSCALE_IXP425))
 210 #define ARM_MMU_XSCALE          1
 211 #else
 212 #define ARM_MMU_XSCALE          0
 213 #endif
 214
 215 #if !defined(_KERNEL_OPT) ||                                            \
 216         defined(CPU_ARM11MPCORE) && defined(ARM11MPCORE_COMPAT_MMU) ||  \
 217         defined(CPU_ARM1136) || \
 218         defined(CPU_ARM1176) || \
 219         defined(CPU_ARM11) && \
 220         !defined(CPU_CORTEX) && \
 221         !defined(CPU_ARM11MPCORE) && !defined(CPU_PJ4B)
 222 #define ARM_MMU_V6C             1
 223 #else
 224 #define ARM_MMU_V6C             0
 225 #endif
 226
 227 #if !defined(_KERNEL_OPT) ||                                            \
 228         defined(CPU_ARM11MPCORE) && !defined(ARM11MPCORE_COMPAT_MMU)
 229 #define ARM_MMU_V6N             1
 230 #else
 231 #define ARM_MMU_V6N             0
 232 #endif
 233
 234 #define ARM_MMU_V6      (ARM_MMU_V6C + ARM_MMU_V6N)
 235
 236
 237 #if !defined(_KERNEL_OPT) ||                                            \
 238          defined(CPU_CORTEX) || defined(CPU_PJ4B)
 239 #define ARM_MMU_V7              1
 240 #else
 241 #define ARM_MMU_V7              0
 242 #endif
 243
 244 #define ARM_NMMUS               (ARM_MMU_MEMC + ARM_MMU_GENERIC +       \
 245                                  ARM_MMU_SA1 + ARM_MMU_XSCALE +         \
 246                                  ARM_MMU_V6N + ARM_MMU_V6C + ARM_MMU_V7)
 247 #if ARM_NMMUS == 0
 248 #error ARM_NMMUS is 0
 249 #endif
 250
 251 /*
 252  * Step 4: Define features that may be present on a subset of CPUs
 253  *
 254  *      ARM_XSCALE_PMU          Performance Monitoring Unit on 80200 and 80321
 255  */
 256
 257 #if !defined(_KERNEL_OPT) ||                                            \
 258     (defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321))
 259 #define ARM_XSCALE_PMU  1
 260 #else
 261 #define ARM_XSCALE_PMU  0
 262 #endif
 263
 264 #endif /* _ARM_CPUCONF_H_ */