1 /* $NetBSD: if_cs.c,v 1.5 2009/05/12 06:57:51 cegger Exp $ */
4 * Copyright (c) 2004 Christopher Gilbert
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
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13 * derived from this software without specific prior written permission.
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22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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60 #include <sys/cdefs.h>
61 __KERNEL_RCSID(0, "$NetBSD: if_cs.c,v 1.5 2009/05/12 06:57:51 cegger Exp $");
63 #include <sys/param.h>
64 #include <sys/systm.h>
65 #include <sys/socket.h>
66 #include <sys/device.h>
74 #include <net/if_ether.h>
75 #include <net/if_media.h>
77 #include <machine/bus.h>
78 #include <machine/intr.h>
80 #include <acorn32/eb7500atx/rsbus.h>
82 #include <dev/ic/cs89x0reg.h>
83 #include <dev/ic/cs89x0var.h>
86 * the CS network interface is accessed at the following address locations:
87 * 030104f1 CS8920 PNP Low
88 * 03010600 03010640 CS8920 Default I/O registers
89 * 030114f1 CS8920 PNP High
90 * 03014000 03016000 CS8920 Default Memory
95 * It must be configured as the following:
96 * The CS8920 PNP address should be configured for ISA base at 0x300
97 * to achieve the default register mapping as specified.
98 * Note memory addresses are all have bit 23 tied high in hardware.
99 * This only effects the value programmed into the CS8920 memory offset
102 * Just to add to the fun the I/O registers are layed out as:
107 * This works fine for 16bit accesses, but it makes access to single
108 * register hard (which does happen on a reset, as we've got to toggle
109 * the chip into 16bit mode)
111 * Network DRQ is connected to DRQ5
115 * make a private tag so that we can use rsbus's map/unmap
117 static struct bus_space cs_rsbus_bs_tag
;
119 int cs_rsbus_probe(device_t
, cfdata_t
, void *);
120 void cs_rsbus_attach(device_t
, device_t
, void *);
122 static u_int8_t
cs_rbus_read_1(struct cs_softc
*, bus_size_t
);
124 CFATTACH_DECL_NEW(cs_rsbus
, sizeof(struct cs_softc
),
125 cs_rsbus_probe
, cs_rsbus_attach
, NULL
, NULL
);
127 /* Available media */
128 int cs_rbus_media
[] = {
129 IFM_ETHER
|IFM_10_T
|IFM_FDX
,
134 cs_rsbus_probe(device_t parent
, cfdata_t cf
, void *aux
)
136 /* for now it'll always attach */
141 cs_rsbus_attach(device_t parent
, device_t self
, void *aux
)
143 struct cs_softc
*sc
= device_private(self
);
144 struct rsbus_attach_args
*rs
= aux
;
150 cs_rsbus_bs_tag
= *rs
->sa_iot
;
152 /* registers are normally accessed in pairs, on a 4 byte aligned */
153 cs_rsbus_bs_tag
.bs_cookie
= (void *) 1;
155 sc
->sc_iot
= sc
->sc_memt
= &cs_rsbus_bs_tag
;
157 #if 0 /* Do DMA later */
159 isc
->sc_drq
= ia
->ia_drq
[0].ir_drq
;
164 /* device always interrupts on 3 but that routes to IRQ 5 */
173 if (bus_space_map(sc
->sc_iot
, iobase
, CS8900_IOSIZE
* 4,
175 printf("%s: unable to map i/o space\n", device_xname(self
));
180 if (bus_space_map(sc
->sc_memt
, iobase
+ 0x3A00,
181 CS8900_MEMSIZE
* 4, 0, &sc
->sc_memh
)) {
182 printf("%s: unable to map memory space\n", device_xname(self
));
184 sc
->sc_cfgflags
|= CFGFLG_MEM_MODE
| CFGFLG_USE_SA
;
185 sc
->sc_pktpgaddr
= 1<<23;
186 //(0x4000 >> 1) | (1<<23);
189 sc
->sc_ih
= intr_claim(IRQ_INT5
, IPL_NET
, "cs", cs_intr
, sc
);
190 if (sc
->sc_ih
== NULL
) {
191 printf("%s: unable to establish interrupt\n",
192 device_xname(sc
->sc_dev
));
196 /* DMA is for later */
197 sc
->sc_dma_chipinit
= NULL
;
198 sc
->sc_dma_attach
= NULL
;
199 sc
->sc_dma_process_rx
= NULL
;
201 sc
->sc_cfgflags
|= CFGFLG_PARSE_EEPROM
;
202 sc
->sc_io_read_1
= cs_rbus_read_1
;
205 * also provide media, otherwise it attempts to read the media from
206 * the EEPROM, which again fails
208 cs_attach(sc
, NULL
, cs_rbus_media
, sizeof(cs_rbus_media
) / sizeof(cs_rbus_media
[0]),
209 IFM_ETHER
|IFM_10_T
|IFM_FDX
);
213 * Provide a function to correctly do reading from oddly numbered registers
214 * as you can't simply shift the register number
217 cs_rbus_read_1(struct cs_softc
*sc
, bus_size_t a
)
221 * if it's an even address then just use the bus_space_read_1
225 return bus_space_read_1(sc
->sc_iot
, sc
->sc_ioh
, a
);
228 * otherwise we've get to work out the aligned address and then add
231 offset
= (a
& ~1) << 1;
234 /* and read it, with no shift (cookie is 0) */
235 return sc
->sc_iot
->bs_r_1(0, (sc
)->sc_ioh
, offset
);