1 /* $NetBSD: gem.c,v 1.89 2009/12/05 16:43:25 jdc Exp $ */
5 * Copyright (C) 2001 Eduardo Horvath.
6 * Copyright (c) 2001-2003 Thomas Moestl
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * Driver for Apple GMAC, Sun ERI and Sun GEM Ethernet controllers
35 * See `GEM Gigabit Ethernet ASIC Specification'
36 * http://www.sun.com/processors/manuals/ge.pdf
39 #include <sys/cdefs.h>
40 __KERNEL_RCSID(0, "$NetBSD: gem.c,v 1.89 2009/12/05 16:43:25 jdc Exp $");
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/callout.h>
49 #include <sys/syslog.h>
50 #include <sys/malloc.h>
51 #include <sys/kernel.h>
52 #include <sys/socket.h>
53 #include <sys/ioctl.h>
54 #include <sys/errno.h>
55 #include <sys/device.h>
57 #include <machine/endian.h>
59 #include <uvm/uvm_extern.h>
62 #include <net/if_dl.h>
63 #include <net/if_media.h>
64 #include <net/if_ether.h>
67 #include <netinet/in.h>
68 #include <netinet/in_systm.h>
69 #include <netinet/in_var.h>
70 #include <netinet/ip.h>
71 #include <netinet/tcp.h>
72 #include <netinet/udp.h>
82 #include <dev/mii/mii.h>
83 #include <dev/mii/miivar.h>
84 #include <dev/mii/mii_bitbang.h>
86 #include <dev/ic/gemreg.h>
87 #include <dev/ic/gemvar.h>
91 static void gem_inten(struct gem_softc
*);
92 static void gem_start(struct ifnet
*);
93 static void gem_stop(struct ifnet
*, int);
94 int gem_ioctl(struct ifnet
*, u_long
, void *);
95 void gem_tick(void *);
96 void gem_watchdog(struct ifnet
*);
97 void gem_pcs_start(struct gem_softc
*sc
);
98 void gem_pcs_stop(struct gem_softc
*sc
, int);
99 int gem_init(struct ifnet
*);
100 void gem_init_regs(struct gem_softc
*sc
);
101 static int gem_ringsize(int sz
);
102 static int gem_meminit(struct gem_softc
*);
103 void gem_mifinit(struct gem_softc
*);
104 static int gem_bitwait(struct gem_softc
*sc
, bus_space_handle_t
, int,
105 u_int32_t
, u_int32_t
);
106 void gem_reset(struct gem_softc
*);
107 int gem_reset_rx(struct gem_softc
*sc
);
108 static void gem_reset_rxdma(struct gem_softc
*sc
);
109 static void gem_rx_common(struct gem_softc
*sc
);
110 int gem_reset_tx(struct gem_softc
*sc
);
111 int gem_disable_rx(struct gem_softc
*sc
);
112 int gem_disable_tx(struct gem_softc
*sc
);
113 static void gem_rxdrain(struct gem_softc
*sc
);
114 int gem_add_rxbuf(struct gem_softc
*sc
, int idx
);
115 void gem_setladrf(struct gem_softc
*);
117 /* MII methods & callbacks */
118 static int gem_mii_readreg(device_t
, int, int);
119 static void gem_mii_writereg(device_t
, int, int, int);
120 static void gem_mii_statchg(device_t
);
122 static int gem_ifflags_cb(struct ethercom
*);
124 void gem_statuschange(struct gem_softc
*);
126 int gem_ser_mediachange(struct ifnet
*);
127 void gem_ser_mediastatus(struct ifnet
*, struct ifmediareq
*);
129 static void gem_partial_detach(struct gem_softc
*, enum gem_attach_stage
);
131 struct mbuf
*gem_get(struct gem_softc
*, int, int);
132 int gem_put(struct gem_softc
*, int, struct mbuf
*);
133 void gem_read(struct gem_softc
*, int, int);
134 int gem_pint(struct gem_softc
*);
135 int gem_eint(struct gem_softc
*, u_int
);
136 int gem_rint(struct gem_softc
*);
137 int gem_tint(struct gem_softc
*);
138 void gem_power(int, void *);
141 static void gem_txsoft_print(const struct gem_softc
*, int, int);
142 #define DPRINTF(sc, x) if ((sc)->sc_ethercom.ec_if.if_flags & IFF_DEBUG) \
145 #define DPRINTF(sc, x) /* nothing */
148 #define ETHER_MIN_TX (ETHERMIN + sizeof(struct ether_header))
151 gem_detach(struct gem_softc
*sc
, int flags
)
154 struct ifnet
*ifp
= &sc
->sc_ethercom
.ec_if
;
157 * Free any resources we've allocated during the attach.
158 * Do this in reverse order and fall through.
160 switch (sc
->sc_att_stage
) {
161 case GEM_ATT_BACKEND_2
:
162 case GEM_ATT_BACKEND_1
:
163 case GEM_ATT_FINISHED
:
164 gem_stop(&sc
->sc_ethercom
.ec_if
, 1);
167 for (i
= __arraycount(sc
->sc_ev_rxhist
); --i
>= 0; )
168 evcnt_detach(&sc
->sc_ev_rxhist
[i
]);
169 evcnt_detach(&sc
->sc_ev_rxnobuf
);
170 evcnt_detach(&sc
->sc_ev_rxfull
);
171 evcnt_detach(&sc
->sc_ev_rxint
);
172 evcnt_detach(&sc
->sc_ev_txint
);
174 evcnt_detach(&sc
->sc_ev_intr
);
177 rnd_detach_source(&sc
->rnd_source
);
181 ifmedia_delete_instance(&sc
->sc_mii
.mii_media
, IFM_INST_ANY
);
183 callout_destroy(&sc
->sc_tick_ch
);
187 sc
->sc_att_stage
= GEM_ATT_MII
;
188 mii_detach(&sc
->sc_mii
, MII_PHY_ANY
, MII_OFFSET_ANY
);
191 for (i
= 0; i
< GEM_NRXDESC
; i
++) {
192 if (sc
->sc_rxsoft
[i
].rxs_dmamap
!= NULL
)
193 bus_dmamap_destroy(sc
->sc_dmatag
,
194 sc
->sc_rxsoft
[i
].rxs_dmamap
);
198 for (i
= 0; i
< GEM_TXQUEUELEN
; i
++) {
199 if (sc
->sc_txsoft
[i
].txs_dmamap
!= NULL
)
200 bus_dmamap_destroy(sc
->sc_dmatag
,
201 sc
->sc_txsoft
[i
].txs_dmamap
);
203 bus_dmamap_unload(sc
->sc_dmatag
, sc
->sc_cddmamap
);
206 bus_dmamap_unload(sc
->sc_dmatag
, sc
->sc_nulldmamap
);
209 bus_dmamap_destroy(sc
->sc_dmatag
, sc
->sc_nulldmamap
);
212 bus_dmamap_destroy(sc
->sc_dmatag
, sc
->sc_cddmamap
);
215 bus_dmamem_unmap(sc
->sc_dmatag
, sc
->sc_control_data
,
216 sizeof(struct gem_control_data
));
219 bus_dmamem_free(sc
->sc_dmatag
, &sc
->sc_cdseg
, sc
->sc_cdnseg
);
222 sc
->sc_att_stage
= GEM_ATT_0
;
224 case GEM_ATT_BACKEND_0
:
231 gem_partial_detach(struct gem_softc
*sc
, enum gem_attach_stage stage
)
233 cfattach_t ca
= device_cfattach(sc
->sc_dev
);
235 sc
->sc_att_stage
= stage
;
236 (*ca
->ca_detach
)(sc
->sc_dev
, 0);
242 * Attach a Gem interface to the system.
245 gem_attach(struct gem_softc
*sc
, const uint8_t *enaddr
)
247 struct ifnet
*ifp
= &sc
->sc_ethercom
.ec_if
;
248 struct mii_data
*mii
= &sc
->sc_mii
;
249 bus_space_tag_t t
= sc
->sc_bustag
;
250 bus_space_handle_t h
= sc
->sc_h1
;
251 struct ifmedia_entry
*ifm
;
252 int i
, error
, phyaddr
;
256 /* Make sure the chip is stopped. */
261 * Allocate the control data structures, and create and load the
262 * DMA map for it. gem_control_data is 9216 bytes, we have space for
263 * the padding buffer in the bus_dmamem_alloc()'d memory.
265 if ((error
= bus_dmamem_alloc(sc
->sc_dmatag
,
266 sizeof(struct gem_control_data
) + ETHER_MIN_TX
, PAGE_SIZE
,
267 0, &sc
->sc_cdseg
, 1, &sc
->sc_cdnseg
, 0)) != 0) {
268 aprint_error_dev(sc
->sc_dev
,
269 "unable to allocate control data, error = %d\n",
271 gem_partial_detach(sc
, GEM_ATT_0
);
275 /* XXX should map this in with correct endianness */
276 if ((error
= bus_dmamem_map(sc
->sc_dmatag
, &sc
->sc_cdseg
, sc
->sc_cdnseg
,
277 sizeof(struct gem_control_data
), (void **)&sc
->sc_control_data
,
278 BUS_DMA_COHERENT
)) != 0) {
279 aprint_error_dev(sc
->sc_dev
,
280 "unable to map control data, error = %d\n", error
);
281 gem_partial_detach(sc
, GEM_ATT_1
);
286 (char *)sc
->sc_control_data
+ sizeof(struct gem_control_data
);
288 if ((error
= bus_dmamap_create(sc
->sc_dmatag
,
289 sizeof(struct gem_control_data
), 1,
290 sizeof(struct gem_control_data
), 0, 0, &sc
->sc_cddmamap
)) != 0) {
291 aprint_error_dev(sc
->sc_dev
,
292 "unable to create control data DMA map, error = %d\n",
294 gem_partial_detach(sc
, GEM_ATT_2
);
298 if ((error
= bus_dmamap_load(sc
->sc_dmatag
, sc
->sc_cddmamap
,
299 sc
->sc_control_data
, sizeof(struct gem_control_data
), NULL
,
301 aprint_error_dev(sc
->sc_dev
,
302 "unable to load control data DMA map, error = %d\n",
304 gem_partial_detach(sc
, GEM_ATT_3
);
308 memset(nullbuf
, 0, ETHER_MIN_TX
);
309 if ((error
= bus_dmamap_create(sc
->sc_dmatag
,
310 ETHER_MIN_TX
, 1, ETHER_MIN_TX
, 0, 0, &sc
->sc_nulldmamap
)) != 0) {
311 aprint_error_dev(sc
->sc_dev
,
312 "unable to create padding DMA map, error = %d\n", error
);
313 gem_partial_detach(sc
, GEM_ATT_4
);
317 if ((error
= bus_dmamap_load(sc
->sc_dmatag
, sc
->sc_nulldmamap
,
318 nullbuf
, ETHER_MIN_TX
, NULL
, 0)) != 0) {
319 aprint_error_dev(sc
->sc_dev
,
320 "unable to load padding DMA map, error = %d\n", error
);
321 gem_partial_detach(sc
, GEM_ATT_5
);
325 bus_dmamap_sync(sc
->sc_dmatag
, sc
->sc_nulldmamap
, 0, ETHER_MIN_TX
,
326 BUS_DMASYNC_PREWRITE
);
329 * Initialize the transmit job descriptors.
331 SIMPLEQ_INIT(&sc
->sc_txfreeq
);
332 SIMPLEQ_INIT(&sc
->sc_txdirtyq
);
335 * Create the transmit buffer DMA maps.
337 for (i
= 0; i
< GEM_TXQUEUELEN
; i
++) {
338 struct gem_txsoft
*txs
;
340 txs
= &sc
->sc_txsoft
[i
];
341 txs
->txs_mbuf
= NULL
;
342 if ((error
= bus_dmamap_create(sc
->sc_dmatag
,
343 ETHER_MAX_LEN_JUMBO
, GEM_NTXSEGS
,
344 ETHER_MAX_LEN_JUMBO
, 0, 0,
345 &txs
->txs_dmamap
)) != 0) {
346 aprint_error_dev(sc
->sc_dev
,
347 "unable to create tx DMA map %d, error = %d\n",
349 gem_partial_detach(sc
, GEM_ATT_6
);
352 SIMPLEQ_INSERT_TAIL(&sc
->sc_txfreeq
, txs
, txs_q
);
356 * Create the receive buffer DMA maps.
358 for (i
= 0; i
< GEM_NRXDESC
; i
++) {
359 if ((error
= bus_dmamap_create(sc
->sc_dmatag
, MCLBYTES
, 1,
360 MCLBYTES
, 0, 0, &sc
->sc_rxsoft
[i
].rxs_dmamap
)) != 0) {
361 aprint_error_dev(sc
->sc_dev
,
362 "unable to create rx DMA map %d, error = %d\n",
364 gem_partial_detach(sc
, GEM_ATT_7
);
367 sc
->sc_rxsoft
[i
].rxs_mbuf
= NULL
;
370 /* Initialize ifmedia structures and MII info */
372 mii
->mii_readreg
= gem_mii_readreg
;
373 mii
->mii_writereg
= gem_mii_writereg
;
374 mii
->mii_statchg
= gem_mii_statchg
;
376 sc
->sc_ethercom
.ec_mii
= mii
;
379 * Initialization based on `GEM Gigabit Ethernet ASIC Specification'
380 * Section 3.2.1 `Initialization Sequence'.
381 * However, we can't assume SERDES or Serialink if neither
382 * GEM_MIF_CONFIG_MDI0 nor GEM_MIF_CONFIG_MDI1 are set
383 * being set, as both are set on Sun X1141A (with SERDES). So,
384 * we rely on our bus attachment setting GEM_SERDES or GEM_SERIAL.
385 * Also, for variants that report 2 PHY's, we prefer the external
386 * PHY over the internal PHY, so we look for that first.
390 if ((sc
->sc_flags
& (GEM_SERDES
| GEM_SERIAL
)) == 0) {
391 ifmedia_init(&mii
->mii_media
, IFM_IMASK
, ether_mediachange
,
393 /* Look for external PHY */
394 if (sc
->sc_mif_config
& GEM_MIF_CONFIG_MDI1
) {
395 sc
->sc_mif_config
|= GEM_MIF_CONFIG_PHY_SEL
;
396 bus_space_write_4(t
, h
, GEM_MIF_CONFIG
,
398 switch (sc
->sc_variant
) {
400 phyaddr
= GEM_PHYAD_EXTERNAL
;
403 phyaddr
= MII_PHY_ANY
;
406 mii_attach(sc
->sc_dev
, mii
, 0xffffffff, phyaddr
,
407 MII_OFFSET_ANY
, MIIF_FORCEANEG
);
411 aprint_debug_dev(sc
->sc_dev
, "using external PHY\n");
413 /* Look for internal PHY if no external PHY was found */
414 if (LIST_EMPTY(&mii
->mii_phys
) &&
415 sc
->sc_mif_config
& GEM_MIF_CONFIG_MDI0
) {
416 sc
->sc_mif_config
&= ~GEM_MIF_CONFIG_PHY_SEL
;
417 bus_space_write_4(t
, h
, GEM_MIF_CONFIG
,
419 switch (sc
->sc_variant
) {
421 case GEM_APPLE_K2_GMAC
:
422 phyaddr
= GEM_PHYAD_INTERNAL
;
425 phyaddr
= GEM_PHYAD_EXTERNAL
;
428 phyaddr
= MII_PHY_ANY
;
431 mii_attach(sc
->sc_dev
, mii
, 0xffffffff, phyaddr
,
432 MII_OFFSET_ANY
, MIIF_FORCEANEG
);
434 if (!LIST_EMPTY(&mii
->mii_phys
))
435 aprint_debug_dev(sc
->sc_dev
,
436 "using internal PHY\n");
439 if (LIST_EMPTY(&mii
->mii_phys
)) {
440 /* No PHY attached */
441 aprint_error_dev(sc
->sc_dev
,
442 "PHY probe failed\n");
443 gem_partial_detach(sc
, GEM_ATT_MII
);
446 struct mii_softc
*child
;
449 * Walk along the list of attached MII devices and
450 * establish an `MII instance' to `PHY number'
453 LIST_FOREACH(child
, &mii
->mii_phys
, mii_list
) {
455 * Note: we support just one PHY: the internal
456 * or external MII is already selected for us
457 * by the GEM_MIF_CONFIG register.
459 if (child
->mii_phy
> 1 || child
->mii_inst
> 0) {
460 aprint_error_dev(sc
->sc_dev
,
461 "cannot accommodate MII device"
462 " %s at PHY %d, instance %d\n",
463 device_xname(child
->mii_dev
),
464 child
->mii_phy
, child
->mii_inst
);
467 sc
->sc_phys
[child
->mii_inst
] = child
->mii_phy
;
470 if (sc
->sc_variant
!= GEM_SUN_ERI
)
471 bus_space_write_4(t
, h
, GEM_MII_DATAPATH_MODE
,
472 GEM_MII_DATAPATH_MII
);
475 * XXX - we can really do the following ONLY if the
476 * PHY indeed has the auto negotiation capability!!
478 ifmedia_set(&sc
->sc_mii
.mii_media
, IFM_ETHER
|IFM_AUTO
);
481 ifmedia_init(&mii
->mii_media
, IFM_IMASK
, gem_ser_mediachange
,
482 gem_ser_mediastatus
);
483 /* SERDES or Serialink */
484 if (sc
->sc_flags
& GEM_SERDES
) {
485 bus_space_write_4(t
, h
, GEM_MII_DATAPATH_MODE
,
486 GEM_MII_DATAPATH_SERDES
);
488 sc
->sc_flags
|= GEM_SERIAL
;
489 bus_space_write_4(t
, h
, GEM_MII_DATAPATH_MODE
,
490 GEM_MII_DATAPATH_SERIAL
);
493 aprint_normal_dev(sc
->sc_dev
, "using external PCS %s: ",
494 sc
->sc_flags
& GEM_SERDES
? "SERDES" : "Serialink");
496 ifmedia_add(&sc
->sc_mii
.mii_media
, IFM_ETHER
|IFM_AUTO
, 0, NULL
);
497 /* Check for FDX and HDX capabilities */
498 sc
->sc_mii_anar
= bus_space_read_4(t
, h
, GEM_MII_ANAR
);
499 if (sc
->sc_mii_anar
& GEM_MII_ANEG_FUL_DUPLX
) {
500 ifmedia_add(&sc
->sc_mii
.mii_media
,
501 IFM_ETHER
|IFM_1000_SX
|IFM_MANUAL
|IFM_FDX
, 0, NULL
);
502 aprint_normal("1000baseSX-FDX, ");
504 if (sc
->sc_mii_anar
& GEM_MII_ANEG_HLF_DUPLX
) {
505 ifmedia_add(&sc
->sc_mii
.mii_media
,
506 IFM_ETHER
|IFM_1000_SX
|IFM_MANUAL
|IFM_HDX
, 0, NULL
);
507 aprint_normal("1000baseSX-HDX, ");
509 ifmedia_set(&sc
->sc_mii
.mii_media
, IFM_ETHER
|IFM_AUTO
);
510 sc
->sc_mii_media
= IFM_AUTO
;
511 aprint_normal("auto\n");
517 * From this point forward, the attachment cannot fail. A failure
518 * before this point releases all resources that may have been
522 /* Announce ourselves. */
523 aprint_normal_dev(sc
->sc_dev
, "Ethernet address %s",
524 ether_sprintf(enaddr
));
526 /* Get RX FIFO size */
527 sc
->sc_rxfifosize
= 64 *
528 bus_space_read_4(t
, h
, GEM_RX_FIFO_SIZE
);
529 aprint_normal(", %uKB RX fifo", sc
->sc_rxfifosize
/ 1024);
531 /* Get TX FIFO size */
532 v
= bus_space_read_4(t
, h
, GEM_TX_FIFO_SIZE
);
533 aprint_normal(", %uKB TX fifo\n", v
/ 16);
535 /* Initialize ifnet structure. */
536 strlcpy(ifp
->if_xname
, device_xname(sc
->sc_dev
), IFNAMSIZ
);
539 IFF_BROADCAST
| IFF_SIMPLEX
| IFF_NOTRAILERS
| IFF_MULTICAST
;
540 sc
->sc_if_flags
= ifp
->if_flags
;
543 * The GEM hardware supports basic TCP checksum offloading only.
544 * Several (all?) revisions (Sun rev. 01 and Apple rev. 00 and 80)
545 * have bugs in the receive checksum, so don't enable it for now.
547 if ((GEM_IS_SUN(sc
) && sc
->sc_chiprev
!= 1) ||
549 (sc
->sc_chiprev
!= 0 && sc
->sc_chiprev
!= 0x80)))
550 ifp
->if_capabilities
|= IFCAP_CSUM_TCPv4_Rx
;
552 ifp
->if_capabilities
|= IFCAP_CSUM_TCPv4_Tx
;
553 ifp
->if_start
= gem_start
;
554 ifp
->if_ioctl
= gem_ioctl
;
555 ifp
->if_watchdog
= gem_watchdog
;
556 ifp
->if_stop
= gem_stop
;
557 ifp
->if_init
= gem_init
;
558 IFQ_SET_READY(&ifp
->if_snd
);
561 * If we support GigE media, we support jumbo frames too.
562 * Unless we are Apple.
564 TAILQ_FOREACH(ifm
, &sc
->sc_mii
.mii_media
.ifm_list
, ifm_list
) {
565 if (IFM_SUBTYPE(ifm
->ifm_media
) == IFM_1000_T
||
566 IFM_SUBTYPE(ifm
->ifm_media
) == IFM_1000_SX
||
567 IFM_SUBTYPE(ifm
->ifm_media
) == IFM_1000_LX
||
568 IFM_SUBTYPE(ifm
->ifm_media
) == IFM_1000_CX
) {
569 if (!GEM_IS_APPLE(sc
))
570 sc
->sc_ethercom
.ec_capabilities
571 |= ETHERCAP_JUMBO_MTU
;
572 sc
->sc_flags
|= GEM_GIGABIT
;
577 /* claim 802.1q capability */
578 sc
->sc_ethercom
.ec_capabilities
|= ETHERCAP_VLAN_MTU
;
580 /* Attach the interface. */
582 ether_ifattach(ifp
, enaddr
);
583 ether_set_ifflags_cb(&sc
->sc_ethercom
, gem_ifflags_cb
);
586 rnd_attach_source(&sc
->rnd_source
, device_xname(sc
->sc_dev
),
590 evcnt_attach_dynamic(&sc
->sc_ev_intr
, EVCNT_TYPE_INTR
,
591 NULL
, device_xname(sc
->sc_dev
), "interrupts");
593 evcnt_attach_dynamic(&sc
->sc_ev_txint
, EVCNT_TYPE_INTR
,
594 &sc
->sc_ev_intr
, device_xname(sc
->sc_dev
), "tx interrupts");
595 evcnt_attach_dynamic(&sc
->sc_ev_rxint
, EVCNT_TYPE_INTR
,
596 &sc
->sc_ev_intr
, device_xname(sc
->sc_dev
), "rx interrupts");
597 evcnt_attach_dynamic(&sc
->sc_ev_rxfull
, EVCNT_TYPE_INTR
,
598 &sc
->sc_ev_rxint
, device_xname(sc
->sc_dev
), "rx ring full");
599 evcnt_attach_dynamic(&sc
->sc_ev_rxnobuf
, EVCNT_TYPE_INTR
,
600 &sc
->sc_ev_rxint
, device_xname(sc
->sc_dev
), "rx malloc failure");
601 evcnt_attach_dynamic(&sc
->sc_ev_rxhist
[0], EVCNT_TYPE_INTR
,
602 &sc
->sc_ev_rxint
, device_xname(sc
->sc_dev
), "rx 0desc");
603 evcnt_attach_dynamic(&sc
->sc_ev_rxhist
[1], EVCNT_TYPE_INTR
,
604 &sc
->sc_ev_rxint
, device_xname(sc
->sc_dev
), "rx 1desc");
605 evcnt_attach_dynamic(&sc
->sc_ev_rxhist
[2], EVCNT_TYPE_INTR
,
606 &sc
->sc_ev_rxint
, device_xname(sc
->sc_dev
), "rx 2desc");
607 evcnt_attach_dynamic(&sc
->sc_ev_rxhist
[3], EVCNT_TYPE_INTR
,
608 &sc
->sc_ev_rxint
, device_xname(sc
->sc_dev
), "rx 3desc");
609 evcnt_attach_dynamic(&sc
->sc_ev_rxhist
[4], EVCNT_TYPE_INTR
,
610 &sc
->sc_ev_rxint
, device_xname(sc
->sc_dev
), "rx >3desc");
611 evcnt_attach_dynamic(&sc
->sc_ev_rxhist
[5], EVCNT_TYPE_INTR
,
612 &sc
->sc_ev_rxint
, device_xname(sc
->sc_dev
), "rx >7desc");
613 evcnt_attach_dynamic(&sc
->sc_ev_rxhist
[6], EVCNT_TYPE_INTR
,
614 &sc
->sc_ev_rxint
, device_xname(sc
->sc_dev
), "rx >15desc");
615 evcnt_attach_dynamic(&sc
->sc_ev_rxhist
[7], EVCNT_TYPE_INTR
,
616 &sc
->sc_ev_rxint
, device_xname(sc
->sc_dev
), "rx >31desc");
617 evcnt_attach_dynamic(&sc
->sc_ev_rxhist
[8], EVCNT_TYPE_INTR
,
618 &sc
->sc_ev_rxint
, device_xname(sc
->sc_dev
), "rx >63desc");
621 callout_init(&sc
->sc_tick_ch
, 0);
623 sc
->sc_att_stage
= GEM_ATT_FINISHED
;
631 struct gem_softc
*sc
= arg
;
634 if ((sc
->sc_flags
& (GEM_SERDES
| GEM_SERIAL
)) != 0) {
636 * We have to reset everything if we failed to get a
637 * PCS interrupt. Restarting the callout is handled
638 * in gem_pcs_start().
640 gem_init(&sc
->sc_ethercom
.ec_if
);
643 mii_tick(&sc
->sc_mii
);
645 callout_reset(&sc
->sc_tick_ch
, hz
, gem_tick
, sc
);
650 gem_bitwait(struct gem_softc
*sc
, bus_space_handle_t h
, int r
, u_int32_t clr
, u_int32_t set
)
655 for (i
= TRIES
; i
--; DELAY(100)) {
656 reg
= bus_space_read_4(sc
->sc_bustag
, h
, r
);
657 if ((reg
& clr
) == 0 && (reg
& set
) == set
)
664 gem_reset(struct gem_softc
*sc
)
666 bus_space_tag_t t
= sc
->sc_bustag
;
667 bus_space_handle_t h
= sc
->sc_h2
;
671 DPRINTF(sc
, ("%s: gem_reset\n", device_xname(sc
->sc_dev
)));
675 /* Do a full reset */
676 bus_space_write_4(t
, h
, GEM_RESET
, GEM_RESET_RX
|GEM_RESET_TX
);
677 if (!gem_bitwait(sc
, h
, GEM_RESET
, GEM_RESET_RX
| GEM_RESET_TX
, 0))
678 aprint_error_dev(sc
->sc_dev
, "cannot reset device\n");
686 * Drain the receive queue.
689 gem_rxdrain(struct gem_softc
*sc
)
691 struct gem_rxsoft
*rxs
;
694 for (i
= 0; i
< GEM_NRXDESC
; i
++) {
695 rxs
= &sc
->sc_rxsoft
[i
];
696 if (rxs
->rxs_mbuf
!= NULL
) {
697 bus_dmamap_sync(sc
->sc_dmatag
, rxs
->rxs_dmamap
, 0,
698 rxs
->rxs_dmamap
->dm_mapsize
, BUS_DMASYNC_POSTREAD
);
699 bus_dmamap_unload(sc
->sc_dmatag
, rxs
->rxs_dmamap
);
700 m_freem(rxs
->rxs_mbuf
);
701 rxs
->rxs_mbuf
= NULL
;
707 * Reset the whole thing.
710 gem_stop(struct ifnet
*ifp
, int disable
)
712 struct gem_softc
*sc
= ifp
->if_softc
;
713 struct gem_txsoft
*txs
;
715 DPRINTF(sc
, ("%s: gem_stop\n", device_xname(sc
->sc_dev
)));
717 callout_stop(&sc
->sc_tick_ch
);
718 if ((sc
->sc_flags
& (GEM_SERDES
| GEM_SERIAL
)) != 0)
719 gem_pcs_stop(sc
, disable
);
721 mii_down(&sc
->sc_mii
);
723 /* XXX - Should we reset these instead? */
728 * Release any queued transmit buffers.
730 while ((txs
= SIMPLEQ_FIRST(&sc
->sc_txdirtyq
)) != NULL
) {
731 SIMPLEQ_REMOVE_HEAD(&sc
->sc_txdirtyq
, txs_q
);
732 if (txs
->txs_mbuf
!= NULL
) {
733 bus_dmamap_sync(sc
->sc_dmatag
, txs
->txs_dmamap
, 0,
734 txs
->txs_dmamap
->dm_mapsize
, BUS_DMASYNC_POSTWRITE
);
735 bus_dmamap_unload(sc
->sc_dmatag
, txs
->txs_dmamap
);
736 m_freem(txs
->txs_mbuf
);
737 txs
->txs_mbuf
= NULL
;
739 SIMPLEQ_INSERT_TAIL(&sc
->sc_txfreeq
, txs
, txs_q
);
743 * Mark the interface down and cancel the watchdog timer.
745 ifp
->if_flags
&= ~(IFF_RUNNING
| IFF_OACTIVE
);
746 sc
->sc_if_flags
= ifp
->if_flags
;
758 gem_reset_rx(struct gem_softc
*sc
)
760 bus_space_tag_t t
= sc
->sc_bustag
;
761 bus_space_handle_t h
= sc
->sc_h1
, h2
= sc
->sc_h2
;
764 * Resetting while DMA is in progress can cause a bus hang, so we
768 bus_space_write_4(t
, h
, GEM_RX_CONFIG
, 0);
769 bus_space_barrier(t
, h
, GEM_RX_CONFIG
, 4, BUS_SPACE_BARRIER_WRITE
);
770 /* Wait till it finishes */
771 if (!gem_bitwait(sc
, h
, GEM_RX_CONFIG
, 1, 0))
772 aprint_error_dev(sc
->sc_dev
, "cannot disable read dma\n");
774 /* Finally, reset the ERX */
775 bus_space_write_4(t
, h2
, GEM_RESET
, GEM_RESET_RX
);
776 bus_space_barrier(t
, h
, GEM_RESET
, 4, BUS_SPACE_BARRIER_WRITE
);
777 /* Wait till it finishes */
778 if (!gem_bitwait(sc
, h2
, GEM_RESET
, GEM_RESET_RX
, 0)) {
779 aprint_error_dev(sc
->sc_dev
, "cannot reset receiver\n");
787 * Reset the receiver DMA engine.
789 * Intended to be used in case of GEM_INTR_RX_TAG_ERR, GEM_MAC_RX_OVERFLOW
790 * etc in order to reset the receiver DMA engine only and not do a full
791 * reset which amongst others also downs the link and clears the FIFOs.
794 gem_reset_rxdma(struct gem_softc
*sc
)
796 struct ifnet
*ifp
= &sc
->sc_ethercom
.ec_if
;
797 bus_space_tag_t t
= sc
->sc_bustag
;
798 bus_space_handle_t h
= sc
->sc_h1
;
801 if (gem_reset_rx(sc
) != 0) {
805 for (i
= 0; i
< GEM_NRXDESC
; i
++)
806 if (sc
->sc_rxsoft
[i
].rxs_mbuf
!= NULL
)
807 GEM_UPDATE_RXDESC(sc
, i
);
809 GEM_CDSYNC(sc
, BUS_DMASYNC_PREWRITE
);
810 GEM_CDSYNC(sc
, BUS_DMASYNC_PREREAD
);
812 /* Reprogram Descriptor Ring Base Addresses */
813 /* NOTE: we use only 32-bit DMA addresses here. */
814 bus_space_write_4(t
, h
, GEM_RX_RING_PTR_HI
, 0);
815 bus_space_write_4(t
, h
, GEM_RX_RING_PTR_LO
, GEM_CDRXADDR(sc
, 0));
817 /* Redo ERX Configuration */
820 /* Give the reciever a swift kick */
821 bus_space_write_4(t
, h
, GEM_RX_KICK
, GEM_NRXDESC
- 4);
825 * Common RX configuration for gem_init() and gem_reset_rxdma().
828 gem_rx_common(struct gem_softc
*sc
)
830 bus_space_tag_t t
= sc
->sc_bustag
;
831 bus_space_handle_t h
= sc
->sc_h1
;
834 /* Encode Receive Descriptor ring size: four possible values */
835 v
= gem_ringsize(GEM_NRXDESC
/*XXX*/);
837 /* Set receive h/w checksum offset */
839 v
|= (ETHER_HDR_LEN
+ sizeof(struct ip
) +
840 ((sc
->sc_ethercom
.ec_capenable
& ETHERCAP_VLAN_MTU
) ?
841 ETHER_VLAN_ENCAP_LEN
: 0)) << GEM_RX_CONFIG_CXM_START_SHFT
;
845 bus_space_write_4(t
, h
, GEM_RX_CONFIG
,
846 v
| (GEM_THRSH_1024
<< GEM_RX_CONFIG_FIFO_THRS_SHIFT
) |
847 (2 << GEM_RX_CONFIG_FBOFF_SHFT
) | GEM_RX_CONFIG_RXDMA_EN
);
850 * The following value is for an OFF Threshold of about 3/4 full
851 * and an ON Threshold of 1/4 full.
853 bus_space_write_4(t
, h
, GEM_RX_PAUSE_THRESH
,
854 (3 * sc
->sc_rxfifosize
/ 256) |
855 ((sc
->sc_rxfifosize
/ 256) << 12));
856 bus_space_write_4(t
, h
, GEM_RX_BLANKING
,
857 (6 << GEM_RX_BLANKING_TIME_SHIFT
) | 6);
861 * Reset the transmitter
864 gem_reset_tx(struct gem_softc
*sc
)
866 bus_space_tag_t t
= sc
->sc_bustag
;
867 bus_space_handle_t h
= sc
->sc_h1
, h2
= sc
->sc_h2
;
870 * Resetting while DMA is in progress can cause a bus hang, so we
874 bus_space_write_4(t
, h
, GEM_TX_CONFIG
, 0);
875 bus_space_barrier(t
, h
, GEM_TX_CONFIG
, 4, BUS_SPACE_BARRIER_WRITE
);
876 /* Wait till it finishes */
877 if (!gem_bitwait(sc
, h
, GEM_TX_CONFIG
, 1, 0))
878 aprint_error_dev(sc
->sc_dev
, "cannot disable read dma\n");
879 /* Wait 5ms extra. */
882 /* Finally, reset the ETX */
883 bus_space_write_4(t
, h2
, GEM_RESET
, GEM_RESET_TX
);
884 bus_space_barrier(t
, h
, GEM_RESET
, 4, BUS_SPACE_BARRIER_WRITE
);
885 /* Wait till it finishes */
886 if (!gem_bitwait(sc
, h2
, GEM_RESET
, GEM_RESET_TX
, 0)) {
887 aprint_error_dev(sc
->sc_dev
, "cannot reset receiver\n");
897 gem_disable_rx(struct gem_softc
*sc
)
899 bus_space_tag_t t
= sc
->sc_bustag
;
900 bus_space_handle_t h
= sc
->sc_h1
;
903 /* Flip the enable bit */
904 cfg
= bus_space_read_4(t
, h
, GEM_MAC_RX_CONFIG
);
905 cfg
&= ~GEM_MAC_RX_ENABLE
;
906 bus_space_write_4(t
, h
, GEM_MAC_RX_CONFIG
, cfg
);
907 bus_space_barrier(t
, h
, GEM_MAC_RX_CONFIG
, 4, BUS_SPACE_BARRIER_WRITE
);
908 /* Wait for it to finish */
909 return (gem_bitwait(sc
, h
, GEM_MAC_RX_CONFIG
, GEM_MAC_RX_ENABLE
, 0));
913 * disable transmitter.
916 gem_disable_tx(struct gem_softc
*sc
)
918 bus_space_tag_t t
= sc
->sc_bustag
;
919 bus_space_handle_t h
= sc
->sc_h1
;
922 /* Flip the enable bit */
923 cfg
= bus_space_read_4(t
, h
, GEM_MAC_TX_CONFIG
);
924 cfg
&= ~GEM_MAC_TX_ENABLE
;
925 bus_space_write_4(t
, h
, GEM_MAC_TX_CONFIG
, cfg
);
926 bus_space_barrier(t
, h
, GEM_MAC_TX_CONFIG
, 4, BUS_SPACE_BARRIER_WRITE
);
927 /* Wait for it to finish */
928 return (gem_bitwait(sc
, h
, GEM_MAC_TX_CONFIG
, GEM_MAC_TX_ENABLE
, 0));
932 * Initialize interface.
935 gem_meminit(struct gem_softc
*sc
)
937 struct gem_rxsoft
*rxs
;
941 * Initialize the transmit descriptor ring.
943 memset(sc
->sc_txdescs
, 0, sizeof(sc
->sc_txdescs
));
944 for (i
= 0; i
< GEM_NTXDESC
; i
++) {
945 sc
->sc_txdescs
[i
].gd_flags
= 0;
946 sc
->sc_txdescs
[i
].gd_addr
= 0;
948 GEM_CDTXSYNC(sc
, 0, GEM_NTXDESC
,
949 BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
950 sc
->sc_txfree
= GEM_NTXDESC
-1;
955 * Initialize the receive descriptor and receive job
958 for (i
= 0; i
< GEM_NRXDESC
; i
++) {
959 rxs
= &sc
->sc_rxsoft
[i
];
960 if (rxs
->rxs_mbuf
== NULL
) {
961 if ((error
= gem_add_rxbuf(sc
, i
)) != 0) {
962 aprint_error_dev(sc
->sc_dev
,
963 "unable to allocate or map rx "
964 "buffer %d, error = %d\n",
967 * XXX Should attempt to run with fewer receive
968 * XXX buffers instead of just failing.
974 GEM_INIT_RXDESC(sc
, i
);
977 sc
->sc_meminited
= 1;
978 GEM_CDSYNC(sc
, BUS_DMASYNC_PREWRITE
);
979 GEM_CDSYNC(sc
, BUS_DMASYNC_PREREAD
);
989 return GEM_RING_SZ_32
;
991 return GEM_RING_SZ_64
;
993 return GEM_RING_SZ_128
;
995 return GEM_RING_SZ_256
;
997 return GEM_RING_SZ_512
;
999 return GEM_RING_SZ_1024
;
1001 return GEM_RING_SZ_2048
;
1003 return GEM_RING_SZ_4096
;
1005 return GEM_RING_SZ_8192
;
1007 printf("gem: invalid Receive Descriptor ring size %d\n", sz
);
1008 return GEM_RING_SZ_32
;
1017 gem_pcs_start(struct gem_softc
*sc
)
1019 bus_space_tag_t t
= sc
->sc_bustag
;
1020 bus_space_handle_t h
= sc
->sc_h1
;
1024 aprint_debug_dev(sc
->sc_dev
, "gem_pcs_start()\n");
1028 * Set up. We must disable the MII before modifying the
1029 * GEM_MII_ANAR register
1031 if (sc
->sc_flags
& GEM_SERDES
) {
1032 bus_space_write_4(t
, h
, GEM_MII_DATAPATH_MODE
,
1033 GEM_MII_DATAPATH_SERDES
);
1034 bus_space_write_4(t
, h
, GEM_MII_SLINK_CONTROL
,
1035 GEM_MII_SLINK_LOOPBACK
);
1037 bus_space_write_4(t
, h
, GEM_MII_DATAPATH_MODE
,
1038 GEM_MII_DATAPATH_SERIAL
);
1039 bus_space_write_4(t
, h
, GEM_MII_SLINK_CONTROL
, 0);
1041 bus_space_write_4(t
, h
, GEM_MII_CONFIG
, 0);
1042 v
= bus_space_read_4(t
, h
, GEM_MII_ANAR
);
1043 v
|= (GEM_MII_ANEG_SYM_PAUSE
| GEM_MII_ANEG_ASYM_PAUSE
);
1044 if (sc
->sc_mii_media
== IFM_AUTO
)
1045 v
|= (GEM_MII_ANEG_FUL_DUPLX
| GEM_MII_ANEG_HLF_DUPLX
);
1046 else if (sc
->sc_mii_media
== IFM_FDX
) {
1047 v
|= GEM_MII_ANEG_FUL_DUPLX
;
1048 v
&= ~GEM_MII_ANEG_HLF_DUPLX
;
1049 } else if (sc
->sc_mii_media
== IFM_HDX
) {
1050 v
&= ~GEM_MII_ANEG_FUL_DUPLX
;
1051 v
|= GEM_MII_ANEG_HLF_DUPLX
;
1054 /* Configure link. */
1055 bus_space_write_4(t
, h
, GEM_MII_ANAR
, v
);
1056 bus_space_write_4(t
, h
, GEM_MII_CONTROL
,
1057 GEM_MII_CONTROL_AUTONEG
| GEM_MII_CONTROL_RAN
);
1058 bus_space_write_4(t
, h
, GEM_MII_CONFIG
, GEM_MII_CONFIG_ENABLE
);
1059 gem_bitwait(sc
, h
, GEM_MII_STATUS
, 0, GEM_MII_STATUS_ANEG_CPT
);
1061 /* Start the 10 second timer */
1062 callout_reset(&sc
->sc_tick_ch
, hz
* 10, gem_tick
, sc
);
1069 gem_pcs_stop(struct gem_softc
*sc
, int disable
)
1071 bus_space_tag_t t
= sc
->sc_bustag
;
1072 bus_space_handle_t h
= sc
->sc_h1
;
1075 aprint_debug_dev(sc
->sc_dev
, "gem_pcs_stop()\n");
1078 /* Tell link partner that we're going away */
1079 bus_space_write_4(t
, h
, GEM_MII_ANAR
, GEM_MII_ANEG_RF
);
1082 * Disable PCS MII. The documentation suggests that setting
1083 * GEM_MII_CONFIG_ENABLE to zero and then restarting auto-
1084 * negotiation will shut down the link. However, it appears
1085 * that we also need to unset the datapath mode.
1087 bus_space_write_4(t
, h
, GEM_MII_CONFIG
, 0);
1088 bus_space_write_4(t
, h
, GEM_MII_CONTROL
,
1089 GEM_MII_CONTROL_AUTONEG
| GEM_MII_CONTROL_RAN
);
1090 bus_space_write_4(t
, h
, GEM_MII_DATAPATH_MODE
, GEM_MII_DATAPATH_MII
);
1091 bus_space_write_4(t
, h
, GEM_MII_CONFIG
, 0);
1094 if (sc
->sc_flags
& GEM_SERDES
)
1095 bus_space_write_4(t
, h
, GEM_MII_SLINK_CONTROL
,
1096 GEM_MII_SLINK_POWER_OFF
);
1098 bus_space_write_4(t
, h
, GEM_MII_SLINK_CONTROL
,
1099 GEM_MII_SLINK_LOOPBACK
| GEM_MII_SLINK_POWER_OFF
);
1102 sc
->sc_flags
&= ~GEM_LINK
;
1103 sc
->sc_mii
.mii_media_active
= IFM_ETHER
| IFM_NONE
;
1104 sc
->sc_mii
.mii_media_status
= IFM_AVALID
;
1109 * Initialization of interface; set up initialization block
1110 * and transmit/receive descriptor rings.
1113 gem_init(struct ifnet
*ifp
)
1115 struct gem_softc
*sc
= ifp
->if_softc
;
1116 bus_space_tag_t t
= sc
->sc_bustag
;
1117 bus_space_handle_t h
= sc
->sc_h1
;
1119 u_int max_frame_size
;
1124 DPRINTF(sc
, ("%s: gem_init: calling stop\n", device_xname(sc
->sc_dev
)));
1126 * Initialization sequence. The numbered steps below correspond
1127 * to the sequence outlined in section 6.3.5.1 in the Ethernet
1128 * Channel Engine manual (part of the PCIO manual).
1129 * See also the STP2002-STQ document from Sun Microsystems.
1132 /* step 1 & 2. Reset the Ethernet Channel */
1135 DPRINTF(sc
, ("%s: gem_init: restarting\n", device_xname(sc
->sc_dev
)));
1137 /* Re-initialize the MIF */
1140 /* Set up correct datapath for non-SERDES/Serialink */
1141 if ((sc
->sc_flags
& (GEM_SERDES
| GEM_SERIAL
)) == 0 &&
1142 sc
->sc_variant
!= GEM_SUN_ERI
)
1143 bus_space_write_4(t
, h
, GEM_MII_DATAPATH_MODE
,
1144 GEM_MII_DATAPATH_MII
);
1146 /* Call MI reset function if any */
1148 (*sc
->sc_hwreset
)(sc
);
1150 /* step 3. Setup data structures in host memory */
1151 if (gem_meminit(sc
) != 0)
1154 /* step 4. TX MAC registers & counters */
1156 max_frame_size
= max(sc
->sc_ethercom
.ec_if
.if_mtu
, ETHERMTU
);
1157 max_frame_size
+= ETHER_HDR_LEN
+ ETHER_CRC_LEN
;
1158 if (sc
->sc_ethercom
.ec_capenable
& ETHERCAP_VLAN_MTU
)
1159 max_frame_size
+= ETHER_VLAN_ENCAP_LEN
;
1160 bus_space_write_4(t
, h
, GEM_MAC_MAC_MAX_FRAME
,
1161 max_frame_size
|/* burst size */(0x2000<<16));
1163 /* step 5. RX MAC registers & counters */
1166 /* step 6 & 7. Program Descriptor Ring Base Addresses */
1167 /* NOTE: we use only 32-bit DMA addresses here. */
1168 bus_space_write_4(t
, h
, GEM_TX_RING_PTR_HI
, 0);
1169 bus_space_write_4(t
, h
, GEM_TX_RING_PTR_LO
, GEM_CDTXADDR(sc
, 0));
1171 bus_space_write_4(t
, h
, GEM_RX_RING_PTR_HI
, 0);
1172 bus_space_write_4(t
, h
, GEM_RX_RING_PTR_LO
, GEM_CDRXADDR(sc
, 0));
1174 /* step 8. Global Configuration & Interrupt Mask */
1176 bus_space_write_4(t
, h
, GEM_MAC_RX_MASK
,
1177 GEM_MAC_RX_DONE
| GEM_MAC_RX_FRAME_CNT
);
1178 bus_space_write_4(t
, h
, GEM_MAC_TX_MASK
, 0xffff); /* XXX */
1179 bus_space_write_4(t
, h
, GEM_MAC_CONTROL_MASK
,
1180 GEM_MAC_PAUSED
| GEM_MAC_PAUSE
| GEM_MAC_RESUME
);
1182 /* step 9. ETX Configuration: use mostly default values */
1185 v
= gem_ringsize(GEM_NTXDESC
/*XXX*/);
1186 bus_space_write_4(t
, h
, GEM_TX_CONFIG
,
1187 v
| GEM_TX_CONFIG_TXDMA_EN
|
1188 (((sc
->sc_flags
& GEM_GIGABIT
? 0x4FF : 0x100) << 10) &
1189 GEM_TX_CONFIG_TXFIFO_TH
));
1190 bus_space_write_4(t
, h
, GEM_TX_KICK
, sc
->sc_txnext
);
1192 /* step 10. ERX Configuration */
1195 /* step 11. Configure Media */
1196 if ((sc
->sc_flags
& (GEM_SERDES
| GEM_SERIAL
)) == 0 &&
1197 (rc
= mii_ifmedia_change(&sc
->sc_mii
)) != 0)
1200 /* step 12. RX_MAC Configuration Register */
1201 v
= bus_space_read_4(t
, h
, GEM_MAC_RX_CONFIG
);
1202 v
|= GEM_MAC_RX_ENABLE
| GEM_MAC_RX_STRIP_CRC
;
1203 bus_space_write_4(t
, h
, GEM_MAC_RX_CONFIG
, v
);
1205 /* step 14. Issue Transmit Pending command */
1207 /* Call MI initialization function if any */
1209 (*sc
->sc_hwinit
)(sc
);
1212 /* step 15. Give the reciever a swift kick */
1213 bus_space_write_4(t
, h
, GEM_RX_KICK
, GEM_NRXDESC
-4);
1215 if ((sc
->sc_flags
& (GEM_SERDES
| GEM_SERIAL
)) != 0)
1219 /* Start the one second timer. */
1220 callout_reset(&sc
->sc_tick_ch
, hz
, gem_tick
, sc
);
1222 sc
->sc_flags
&= ~GEM_LINK
;
1223 ifp
->if_flags
|= IFF_RUNNING
;
1224 ifp
->if_flags
&= ~IFF_OACTIVE
;
1226 sc
->sc_if_flags
= ifp
->if_flags
;
1234 gem_init_regs(struct gem_softc
*sc
)
1236 struct ifnet
*ifp
= &sc
->sc_ethercom
.ec_if
;
1237 bus_space_tag_t t
= sc
->sc_bustag
;
1238 bus_space_handle_t h
= sc
->sc_h1
;
1239 const u_char
*laddr
= CLLADDR(ifp
->if_sadl
);
1242 /* These regs are not cleared on reset */
1243 if (!sc
->sc_inited
) {
1245 /* Load recommended values */
1246 bus_space_write_4(t
, h
, GEM_MAC_IPG0
, 0x00);
1247 bus_space_write_4(t
, h
, GEM_MAC_IPG1
, 0x08);
1248 bus_space_write_4(t
, h
, GEM_MAC_IPG2
, 0x04);
1250 bus_space_write_4(t
, h
, GEM_MAC_MAC_MIN_FRAME
, ETHER_MIN_LEN
);
1251 /* Max frame and max burst size */
1252 bus_space_write_4(t
, h
, GEM_MAC_MAC_MAX_FRAME
,
1253 ETHER_MAX_LEN
| (0x2000<<16));
1255 bus_space_write_4(t
, h
, GEM_MAC_PREAMBLE_LEN
, 0x07);
1256 bus_space_write_4(t
, h
, GEM_MAC_JAM_SIZE
, 0x04);
1257 bus_space_write_4(t
, h
, GEM_MAC_ATTEMPT_LIMIT
, 0x10);
1258 bus_space_write_4(t
, h
, GEM_MAC_CONTROL_TYPE
, 0x8088);
1259 bus_space_write_4(t
, h
, GEM_MAC_RANDOM_SEED
,
1260 ((laddr
[5]<<8)|laddr
[4])&0x3ff);
1262 /* Secondary MAC addr set to 0:0:0:0:0:0 */
1263 bus_space_write_4(t
, h
, GEM_MAC_ADDR3
, 0);
1264 bus_space_write_4(t
, h
, GEM_MAC_ADDR4
, 0);
1265 bus_space_write_4(t
, h
, GEM_MAC_ADDR5
, 0);
1267 /* MAC control addr set to 01:80:c2:00:00:01 */
1268 bus_space_write_4(t
, h
, GEM_MAC_ADDR6
, 0x0001);
1269 bus_space_write_4(t
, h
, GEM_MAC_ADDR7
, 0xc200);
1270 bus_space_write_4(t
, h
, GEM_MAC_ADDR8
, 0x0180);
1272 /* MAC filter addr set to 0:0:0:0:0:0 */
1273 bus_space_write_4(t
, h
, GEM_MAC_ADDR_FILTER0
, 0);
1274 bus_space_write_4(t
, h
, GEM_MAC_ADDR_FILTER1
, 0);
1275 bus_space_write_4(t
, h
, GEM_MAC_ADDR_FILTER2
, 0);
1277 bus_space_write_4(t
, h
, GEM_MAC_ADR_FLT_MASK1_2
, 0);
1278 bus_space_write_4(t
, h
, GEM_MAC_ADR_FLT_MASK0
, 0);
1283 /* Counters need to be zeroed */
1284 bus_space_write_4(t
, h
, GEM_MAC_NORM_COLL_CNT
, 0);
1285 bus_space_write_4(t
, h
, GEM_MAC_FIRST_COLL_CNT
, 0);
1286 bus_space_write_4(t
, h
, GEM_MAC_EXCESS_COLL_CNT
, 0);
1287 bus_space_write_4(t
, h
, GEM_MAC_LATE_COLL_CNT
, 0);
1288 bus_space_write_4(t
, h
, GEM_MAC_DEFER_TMR_CNT
, 0);
1289 bus_space_write_4(t
, h
, GEM_MAC_PEAK_ATTEMPTS
, 0);
1290 bus_space_write_4(t
, h
, GEM_MAC_RX_FRAME_COUNT
, 0);
1291 bus_space_write_4(t
, h
, GEM_MAC_RX_LEN_ERR_CNT
, 0);
1292 bus_space_write_4(t
, h
, GEM_MAC_RX_ALIGN_ERR
, 0);
1293 bus_space_write_4(t
, h
, GEM_MAC_RX_CRC_ERR_CNT
, 0);
1294 bus_space_write_4(t
, h
, GEM_MAC_RX_CODE_VIOL
, 0);
1296 /* Set XOFF PAUSE time. */
1297 bus_space_write_4(t
, h
, GEM_MAC_SEND_PAUSE_CMD
, 0x1BF0);
1300 * Set the internal arbitration to "infinite" bursts of the
1301 * maximum length of 31 * 64 bytes so DMA transfers aren't
1302 * split up in cache line size chunks. This greatly improves
1303 * especially RX performance.
1304 * Enable silicon bug workarounds for the Apple variants.
1306 bus_space_write_4(t
, h
, GEM_CONFIG
,
1307 GEM_CONFIG_TXDMA_LIMIT
| GEM_CONFIG_RXDMA_LIMIT
|
1308 ((sc
->sc_flags
& GEM_PCI
) ?
1309 GEM_CONFIG_BURST_INF
: GEM_CONFIG_BURST_64
) | (GEM_IS_APPLE(sc
) ?
1310 GEM_CONFIG_RONPAULBIT
| GEM_CONFIG_BUG2FIX
: 0));
1313 * Set the station address.
1315 bus_space_write_4(t
, h
, GEM_MAC_ADDR0
, (laddr
[4]<<8)|laddr
[5]);
1316 bus_space_write_4(t
, h
, GEM_MAC_ADDR1
, (laddr
[2]<<8)|laddr
[3]);
1317 bus_space_write_4(t
, h
, GEM_MAC_ADDR2
, (laddr
[0]<<8)|laddr
[1]);
1320 * Enable MII outputs. Enable GMII if there is a gigabit PHY.
1322 sc
->sc_mif_config
= bus_space_read_4(t
, h
, GEM_MIF_CONFIG
);
1323 v
= GEM_MAC_XIF_TX_MII_ENA
;
1324 if ((sc
->sc_flags
& (GEM_SERDES
| GEM_SERIAL
)) == 0) {
1325 if (sc
->sc_mif_config
& GEM_MIF_CONFIG_MDI1
) {
1326 v
|= GEM_MAC_XIF_FDPLX_LED
;
1327 if (sc
->sc_flags
& GEM_GIGABIT
)
1328 v
|= GEM_MAC_XIF_GMII_MODE
;
1331 v
|= GEM_MAC_XIF_GMII_MODE
;
1333 bus_space_write_4(t
, h
, GEM_MAC_XIF_CONFIG
, v
);
1338 gem_txsoft_print(const struct gem_softc
*sc
, int firstdesc
, int lastdesc
)
1342 for (i
= firstdesc
;; i
= GEM_NEXTTX(i
)) {
1343 printf("descriptor %d:\t", i
);
1344 printf("gd_flags: 0x%016" PRIx64
"\t",
1345 GEM_DMA_READ(sc
, sc
->sc_txdescs
[i
].gd_flags
));
1346 printf("gd_addr: 0x%016" PRIx64
"\n",
1347 GEM_DMA_READ(sc
, sc
->sc_txdescs
[i
].gd_addr
));
1355 gem_start(struct ifnet
*ifp
)
1357 struct gem_softc
*sc
= ifp
->if_softc
;
1358 struct mbuf
*m0
, *m
;
1359 struct gem_txsoft
*txs
;
1360 bus_dmamap_t dmamap
;
1361 int error
, firsttx
, nexttx
= -1, lasttx
= -1, ofree
, seg
;
1364 if ((ifp
->if_flags
& (IFF_RUNNING
| IFF_OACTIVE
)) != IFF_RUNNING
)
1368 * Remember the previous number of free descriptors and
1369 * the first descriptor we'll use.
1371 ofree
= sc
->sc_txfree
;
1372 firsttx
= sc
->sc_txnext
;
1374 DPRINTF(sc
, ("%s: gem_start: txfree %d, txnext %d\n",
1375 device_xname(sc
->sc_dev
), ofree
, firsttx
));
1378 * Loop through the send queue, setting up transmit descriptors
1379 * until we drain the queue, or use up all available transmit
1382 while ((txs
= SIMPLEQ_FIRST(&sc
->sc_txfreeq
)) != NULL
&&
1383 sc
->sc_txfree
!= 0) {
1385 * Grab a packet off the queue.
1387 IFQ_POLL(&ifp
->if_snd
, m0
);
1392 dmamap
= txs
->txs_dmamap
;
1395 * Load the DMA map. If this fails, the packet either
1396 * didn't fit in the alloted number of segments, or we were
1397 * short on resources. In this case, we'll copy and try
1400 if (bus_dmamap_load_mbuf(sc
->sc_dmatag
, dmamap
, m0
,
1401 BUS_DMA_WRITE
|BUS_DMA_NOWAIT
) != 0 ||
1402 (m0
->m_pkthdr
.len
< ETHER_MIN_TX
&&
1403 dmamap
->dm_nsegs
== GEM_NTXSEGS
)) {
1404 if (m0
->m_pkthdr
.len
> MCLBYTES
) {
1405 aprint_error_dev(sc
->sc_dev
,
1406 "unable to allocate jumbo Tx cluster\n");
1407 IFQ_DEQUEUE(&ifp
->if_snd
, m0
);
1411 MGETHDR(m
, M_DONTWAIT
, MT_DATA
);
1413 aprint_error_dev(sc
->sc_dev
,
1414 "unable to allocate Tx mbuf\n");
1417 MCLAIM(m
, &sc
->sc_ethercom
.ec_tx_mowner
);
1418 if (m0
->m_pkthdr
.len
> MHLEN
) {
1419 MCLGET(m
, M_DONTWAIT
);
1420 if ((m
->m_flags
& M_EXT
) == 0) {
1421 aprint_error_dev(sc
->sc_dev
,
1422 "unable to allocate Tx cluster\n");
1427 m_copydata(m0
, 0, m0
->m_pkthdr
.len
, mtod(m
, void *));
1428 m
->m_pkthdr
.len
= m
->m_len
= m0
->m_pkthdr
.len
;
1429 error
= bus_dmamap_load_mbuf(sc
->sc_dmatag
, dmamap
,
1430 m
, BUS_DMA_WRITE
|BUS_DMA_NOWAIT
);
1432 aprint_error_dev(sc
->sc_dev
,
1433 "unable to load Tx buffer, error = %d\n",
1440 * Ensure we have enough descriptors free to describe
1443 if (dmamap
->dm_nsegs
> ((m0
->m_pkthdr
.len
< ETHER_MIN_TX
) ?
1444 (sc
->sc_txfree
- 1) : sc
->sc_txfree
)) {
1446 * Not enough free descriptors to transmit this
1447 * packet. We haven't committed to anything yet,
1448 * so just unload the DMA map, put the packet
1449 * back on the queue, and punt. Notify the upper
1450 * layer that there are no more slots left.
1452 * XXX We could allocate an mbuf and copy, but
1453 * XXX it is worth it?
1455 ifp
->if_flags
|= IFF_OACTIVE
;
1456 sc
->sc_if_flags
= ifp
->if_flags
;
1457 bus_dmamap_unload(sc
->sc_dmatag
, dmamap
);
1463 IFQ_DEQUEUE(&ifp
->if_snd
, m0
);
1470 * WE ARE NOW COMMITTED TO TRANSMITTING THE PACKET.
1473 /* Sync the DMA map. */
1474 bus_dmamap_sync(sc
->sc_dmatag
, dmamap
, 0, dmamap
->dm_mapsize
,
1475 BUS_DMASYNC_PREWRITE
);
1478 * Initialize the transmit descriptors.
1480 for (nexttx
= sc
->sc_txnext
, seg
= 0;
1481 seg
< dmamap
->dm_nsegs
;
1482 seg
++, nexttx
= GEM_NEXTTX(nexttx
)) {
1485 * If this is the first descriptor we're
1486 * enqueueing, set the start of packet flag,
1487 * and the checksum stuff if we want the hardware
1490 sc
->sc_txdescs
[nexttx
].gd_addr
=
1491 GEM_DMA_WRITE(sc
, dmamap
->dm_segs
[seg
].ds_addr
);
1492 flags
= dmamap
->dm_segs
[seg
].ds_len
& GEM_TD_BUFSIZE
;
1493 if (nexttx
== firsttx
) {
1494 flags
|= GEM_TD_START_OF_PACKET
;
1495 if (++sc
->sc_txwin
> GEM_NTXSEGS
* 2 / 3) {
1497 flags
|= GEM_TD_INTERRUPT_ME
;
1502 if (ifp
->if_csum_flags_tx
& M_CSUM_TCPv4
&&
1503 m0
->m_pkthdr
.csum_flags
& M_CSUM_TCPv4
) {
1504 struct ether_header
*eh
;
1505 uint16_t offset
, start
;
1507 eh
= mtod(m0
, struct ether_header
*);
1508 switch (ntohs(eh
->ether_type
)) {
1510 start
= ETHER_HDR_LEN
;
1512 case ETHERTYPE_VLAN
:
1513 start
= ETHER_HDR_LEN
+
1514 ETHER_VLAN_ENCAP_LEN
;
1517 /* unsupported, drop it */
1521 start
+= M_CSUM_DATA_IPv4_IPHL(m0
->m_pkthdr
.csum_data
);
1522 offset
= M_CSUM_DATA_IPv4_OFFSET(m0
->m_pkthdr
.csum_data
) + start
;
1524 GEM_TD_CXSUM_STARTSHFT
) |
1526 GEM_TD_CXSUM_STUFFSHFT
) |
1527 GEM_TD_CXSUM_ENABLE
;
1531 if (seg
== dmamap
->dm_nsegs
- 1) {
1532 flags
|= GEM_TD_END_OF_PACKET
;
1534 /* last flag set outside of loop */
1535 sc
->sc_txdescs
[nexttx
].gd_flags
=
1536 GEM_DMA_WRITE(sc
, flags
);
1540 if (m0
->m_pkthdr
.len
< ETHER_MIN_TX
) {
1541 /* add padding buffer at end of chain */
1542 flags
&= ~GEM_TD_END_OF_PACKET
;
1543 sc
->sc_txdescs
[lasttx
].gd_flags
=
1544 GEM_DMA_WRITE(sc
, flags
);
1546 sc
->sc_txdescs
[nexttx
].gd_addr
=
1548 sc
->sc_nulldmamap
->dm_segs
[0].ds_addr
);
1549 flags
= ((ETHER_MIN_TX
- m0
->m_pkthdr
.len
) &
1550 GEM_TD_BUFSIZE
) | GEM_TD_END_OF_PACKET
;
1552 nexttx
= GEM_NEXTTX(nexttx
);
1555 sc
->sc_txdescs
[lasttx
].gd_flags
= GEM_DMA_WRITE(sc
, flags
);
1557 KASSERT(lasttx
!= -1);
1560 * Store a pointer to the packet so we can free it later,
1561 * and remember what txdirty will be once the packet is
1565 txs
->txs_firstdesc
= sc
->sc_txnext
;
1566 txs
->txs_lastdesc
= lasttx
;
1567 txs
->txs_ndescs
= seg
;
1570 if (ifp
->if_flags
& IFF_DEBUG
) {
1571 printf(" gem_start %p transmit chain:\n", txs
);
1572 gem_txsoft_print(sc
, txs
->txs_firstdesc
,
1577 /* Sync the descriptors we're using. */
1578 GEM_CDTXSYNC(sc
, txs
->txs_firstdesc
, txs
->txs_ndescs
,
1579 BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
1581 /* Advance the tx pointer. */
1582 sc
->sc_txfree
-= txs
->txs_ndescs
;
1583 sc
->sc_txnext
= nexttx
;
1585 SIMPLEQ_REMOVE_HEAD(&sc
->sc_txfreeq
, txs_q
);
1586 SIMPLEQ_INSERT_TAIL(&sc
->sc_txdirtyq
, txs
, txs_q
);
1590 * Pass the packet to any BPF listeners.
1593 bpf_mtap(ifp
->if_bpf
, m0
);
1594 #endif /* NBPFILTER > 0 */
1597 if (txs
== NULL
|| sc
->sc_txfree
== 0) {
1598 /* No more slots left; notify upper layer. */
1599 ifp
->if_flags
|= IFF_OACTIVE
;
1600 sc
->sc_if_flags
= ifp
->if_flags
;
1603 if (sc
->sc_txfree
!= ofree
) {
1604 DPRINTF(sc
, ("%s: packets enqueued, IC on %d, OWN on %d\n",
1605 device_xname(sc
->sc_dev
), lasttx
, firsttx
));
1607 * The entire packet chain is set up.
1608 * Kick the transmitter.
1610 DPRINTF(sc
, ("%s: gem_start: kicking tx %d\n",
1611 device_xname(sc
->sc_dev
), nexttx
));
1612 bus_space_write_4(sc
->sc_bustag
, sc
->sc_h1
, GEM_TX_KICK
,
1615 /* Set a watchdog timer in case the chip flakes out. */
1617 DPRINTF(sc
, ("%s: gem_start: watchdog %d\n",
1618 device_xname(sc
->sc_dev
), ifp
->if_timer
));
1623 * Transmit interrupt.
1626 gem_tint(struct gem_softc
*sc
)
1628 struct ifnet
*ifp
= &sc
->sc_ethercom
.ec_if
;
1629 bus_space_tag_t t
= sc
->sc_bustag
;
1630 bus_space_handle_t mac
= sc
->sc_h1
;
1631 struct gem_txsoft
*txs
;
1636 DPRINTF(sc
, ("%s: gem_tint\n", device_xname(sc
->sc_dev
)));
1638 /* Unload collision counters ... */
1639 v
= bus_space_read_4(t
, mac
, GEM_MAC_EXCESS_COLL_CNT
) +
1640 bus_space_read_4(t
, mac
, GEM_MAC_LATE_COLL_CNT
);
1641 ifp
->if_collisions
+= v
+
1642 bus_space_read_4(t
, mac
, GEM_MAC_NORM_COLL_CNT
) +
1643 bus_space_read_4(t
, mac
, GEM_MAC_FIRST_COLL_CNT
);
1644 ifp
->if_oerrors
+= v
;
1646 /* ... then clear the hardware counters. */
1647 bus_space_write_4(t
, mac
, GEM_MAC_NORM_COLL_CNT
, 0);
1648 bus_space_write_4(t
, mac
, GEM_MAC_FIRST_COLL_CNT
, 0);
1649 bus_space_write_4(t
, mac
, GEM_MAC_EXCESS_COLL_CNT
, 0);
1650 bus_space_write_4(t
, mac
, GEM_MAC_LATE_COLL_CNT
, 0);
1653 * Go through our Tx list and free mbufs for those
1654 * frames that have been transmitted.
1656 while ((txs
= SIMPLEQ_FIRST(&sc
->sc_txdirtyq
)) != NULL
) {
1658 * In theory, we could harvest some descriptors before
1659 * the ring is empty, but that's a bit complicated.
1661 * GEM_TX_COMPLETION points to the last descriptor
1664 * Let's assume that the NIC writes back to the Tx
1665 * descriptors before it updates the completion
1666 * register. If the NIC has posted writes to the
1667 * Tx descriptors, PCI ordering requires that the
1668 * posted writes flush to RAM before the register-read
1669 * finishes. So let's read the completion register,
1670 * before syncing the descriptors, so that we
1671 * examine Tx descriptors that are at least as
1672 * current as the completion register.
1674 txlast
= bus_space_read_4(t
, mac
, GEM_TX_COMPLETION
);
1676 ("gem_tint: txs->txs_lastdesc = %d, txlast = %d\n",
1677 txs
->txs_lastdesc
, txlast
));
1678 if (txs
->txs_firstdesc
<= txs
->txs_lastdesc
) {
1679 if (txlast
>= txs
->txs_firstdesc
&&
1680 txlast
<= txs
->txs_lastdesc
)
1682 } else if (txlast
>= txs
->txs_firstdesc
||
1683 txlast
<= txs
->txs_lastdesc
)
1686 GEM_CDTXSYNC(sc
, txs
->txs_firstdesc
, txs
->txs_ndescs
,
1687 BUS_DMASYNC_POSTREAD
|BUS_DMASYNC_POSTWRITE
);
1689 #ifdef GEM_DEBUG /* XXX DMA synchronization? */
1690 if (ifp
->if_flags
& IFF_DEBUG
) {
1691 printf(" txsoft %p transmit chain:\n", txs
);
1692 gem_txsoft_print(sc
, txs
->txs_firstdesc
,
1698 DPRINTF(sc
, ("gem_tint: releasing a desc\n"));
1699 SIMPLEQ_REMOVE_HEAD(&sc
->sc_txdirtyq
, txs_q
);
1701 sc
->sc_txfree
+= txs
->txs_ndescs
;
1703 bus_dmamap_sync(sc
->sc_dmatag
, txs
->txs_dmamap
,
1704 0, txs
->txs_dmamap
->dm_mapsize
,
1705 BUS_DMASYNC_POSTWRITE
);
1706 bus_dmamap_unload(sc
->sc_dmatag
, txs
->txs_dmamap
);
1707 if (txs
->txs_mbuf
!= NULL
) {
1708 m_freem(txs
->txs_mbuf
);
1709 txs
->txs_mbuf
= NULL
;
1712 SIMPLEQ_INSERT_TAIL(&sc
->sc_txfreeq
, txs
, txs_q
);
1719 DPRINTF(sc
, ("gem_tint: GEM_TX_STATE_MACHINE %x "
1720 "GEM_TX_DATA_PTR %" PRIx64
"GEM_TX_COMPLETION %" PRIx32
"\n",
1721 bus_space_read_4(sc
->sc_bustag
, sc
->sc_h1
, GEM_TX_STATE_MACHINE
),
1722 ((uint64_t)bus_space_read_4(sc
->sc_bustag
, sc
->sc_h1
,
1723 GEM_TX_DATA_PTR_HI
) << 32) |
1724 bus_space_read_4(sc
->sc_bustag
, sc
->sc_h1
,
1725 GEM_TX_DATA_PTR_LO
),
1726 bus_space_read_4(sc
->sc_bustag
, sc
->sc_h1
, GEM_TX_COMPLETION
)));
1730 if (sc
->sc_txfree
== GEM_NTXDESC
- 1)
1733 /* Freed some descriptors, so reset IFF_OACTIVE and restart. */
1734 ifp
->if_flags
&= ~IFF_OACTIVE
;
1735 sc
->sc_if_flags
= ifp
->if_flags
;
1736 ifp
->if_timer
= SIMPLEQ_EMPTY(&sc
->sc_txdirtyq
) ? 0 : 5;
1739 DPRINTF(sc
, ("%s: gem_tint: watchdog %d\n",
1740 device_xname(sc
->sc_dev
), ifp
->if_timer
));
1746 * Receive interrupt.
1749 gem_rint(struct gem_softc
*sc
)
1751 struct ifnet
*ifp
= &sc
->sc_ethercom
.ec_if
;
1752 bus_space_tag_t t
= sc
->sc_bustag
;
1753 bus_space_handle_t h
= sc
->sc_h1
;
1754 struct gem_rxsoft
*rxs
;
1758 int i
, len
, progress
= 0;
1760 DPRINTF(sc
, ("%s: gem_rint\n", device_xname(sc
->sc_dev
)));
1763 * Ignore spurious interrupt that sometimes occurs before
1764 * we are set up when we network boot.
1766 if (!sc
->sc_meminited
)
1770 * Read the completion register once. This limits
1771 * how long the following loop can execute.
1773 rxcomp
= bus_space_read_4(t
, h
, GEM_RX_COMPLETION
);
1776 * XXX Read the lastrx only once at the top for speed.
1778 DPRINTF(sc
, ("gem_rint: sc->rxptr %d, complete %d\n",
1779 sc
->sc_rxptr
, rxcomp
));
1782 * Go into the loop at least once.
1784 for (i
= sc
->sc_rxptr
; i
== sc
->sc_rxptr
|| i
!= rxcomp
;
1785 i
= GEM_NEXTRX(i
)) {
1786 rxs
= &sc
->sc_rxsoft
[i
];
1789 BUS_DMASYNC_POSTREAD
|BUS_DMASYNC_POSTWRITE
);
1791 rxstat
= GEM_DMA_READ(sc
, sc
->sc_rxdescs
[i
].gd_flags
);
1793 if (rxstat
& GEM_RD_OWN
) {
1794 GEM_CDRXSYNC(sc
, i
, BUS_DMASYNC_PREREAD
);
1796 * We have processed all of the receive buffers.
1804 if (rxstat
& GEM_RD_BAD_CRC
) {
1806 aprint_error_dev(sc
->sc_dev
,
1807 "receive error: CRC error\n");
1808 GEM_INIT_RXDESC(sc
, i
);
1812 bus_dmamap_sync(sc
->sc_dmatag
, rxs
->rxs_dmamap
, 0,
1813 rxs
->rxs_dmamap
->dm_mapsize
, BUS_DMASYNC_POSTREAD
);
1815 if (ifp
->if_flags
& IFF_DEBUG
) {
1816 printf(" rxsoft %p descriptor %d: ", rxs
, i
);
1817 printf("gd_flags: 0x%016llx\t", (long long)
1818 GEM_DMA_READ(sc
, sc
->sc_rxdescs
[i
].gd_flags
));
1819 printf("gd_addr: 0x%016llx\n", (long long)
1820 GEM_DMA_READ(sc
, sc
->sc_rxdescs
[i
].gd_addr
));
1824 /* No errors; receive the packet. */
1825 len
= GEM_RD_BUFLEN(rxstat
);
1828 * Allocate a new mbuf cluster. If that fails, we are
1829 * out of memory, and must drop the packet and recycle
1830 * the buffer that's already attached to this descriptor.
1833 if (gem_add_rxbuf(sc
, i
) != 0) {
1834 GEM_COUNTER_INCR(sc
, sc_ev_rxnobuf
);
1836 GEM_INIT_RXDESC(sc
, i
);
1837 bus_dmamap_sync(sc
->sc_dmatag
, rxs
->rxs_dmamap
, 0,
1838 rxs
->rxs_dmamap
->dm_mapsize
, BUS_DMASYNC_PREREAD
);
1841 m
->m_data
+= 2; /* We're already off by two */
1843 m
->m_pkthdr
.rcvif
= ifp
;
1844 m
->m_pkthdr
.len
= m
->m_len
= len
;
1848 * Pass this up to any BPF listeners, but only
1849 * pass it up the stack if it's for us.
1852 bpf_mtap(ifp
->if_bpf
, m
);
1853 #endif /* NBPFILTER > 0 */
1856 /* hardware checksum */
1857 if (ifp
->if_csum_flags_rx
& M_CSUM_TCPv4
) {
1858 struct ether_header
*eh
;
1860 int32_t hlen
, pktlen
;
1862 if (sc
->sc_ethercom
.ec_capenable
& ETHERCAP_VLAN_MTU
) {
1863 pktlen
= m
->m_pkthdr
.len
- ETHER_HDR_LEN
-
1864 ETHER_VLAN_ENCAP_LEN
;
1865 eh
= (struct ether_header
*) (mtod(m
, char *) +
1866 ETHER_VLAN_ENCAP_LEN
);
1868 pktlen
= m
->m_pkthdr
.len
- ETHER_HDR_LEN
;
1869 eh
= mtod(m
, struct ether_header
*);
1871 if (ntohs(eh
->ether_type
) != ETHERTYPE_IP
)
1873 ip
= (struct ip
*) ((char *)eh
+ ETHER_HDR_LEN
);
1876 if (ip
->ip_v
!= IPVERSION
)
1879 hlen
= ip
->ip_hl
<< 2;
1880 if (hlen
< sizeof(struct ip
))
1884 * bail if too short, has random trailing garbage,
1885 * truncated, fragment, or has ethernet pad.
1887 if ((ntohs(ip
->ip_len
) < hlen
) ||
1888 (ntohs(ip
->ip_len
) != pktlen
) ||
1889 (ntohs(ip
->ip_off
) & (IP_MF
| IP_OFFMASK
)))
1894 if (! (ifp
->if_csum_flags_rx
& M_CSUM_TCPv4
))
1896 if (pktlen
< (hlen
+ sizeof(struct tcphdr
)))
1898 m
->m_pkthdr
.csum_flags
= M_CSUM_TCPv4
;
1906 /* the uncomplemented sum is expected */
1907 m
->m_pkthdr
.csum_data
= (~rxstat
) & GEM_RD_CHECKSUM
;
1909 /* if the pkt had ip options, we have to deduct them */
1910 if (hlen
> sizeof(struct ip
)) {
1912 uint32_t optsum
, temp
;
1915 temp
= hlen
- sizeof(struct ip
);
1916 opts
= (uint16_t *) ((char *) ip
+
1920 optsum
+= ntohs(*opts
++);
1923 while (optsum
>> 16)
1924 optsum
= (optsum
>> 16) +
1927 /* Deduct ip opts sum from hwsum. */
1928 m
->m_pkthdr
.csum_data
+= (uint16_t)~optsum
;
1930 while (m
->m_pkthdr
.csum_data
>> 16)
1931 m
->m_pkthdr
.csum_data
=
1932 (m
->m_pkthdr
.csum_data
>> 16) +
1933 (m
->m_pkthdr
.csum_data
&
1937 m
->m_pkthdr
.csum_flags
|= M_CSUM_DATA
|
1938 M_CSUM_NO_PSEUDOHDR
;
1941 m
->m_pkthdr
.csum_flags
= 0;
1944 (*ifp
->if_input
)(ifp
, m
);
1948 /* Update the receive pointer. */
1949 if (i
== sc
->sc_rxptr
) {
1950 GEM_COUNTER_INCR(sc
, sc_ev_rxfull
);
1952 if (ifp
->if_flags
& IFF_DEBUG
)
1953 printf("%s: rint: ring wrap\n",
1954 device_xname(sc
->sc_dev
));
1958 bus_space_write_4(t
, h
, GEM_RX_KICK
, GEM_PREVRX(i
));
1961 if (progress
<= 4) {
1962 GEM_COUNTER_INCR(sc
, sc_ev_rxhist
[progress
]);
1963 } else if (progress
< 32) {
1965 GEM_COUNTER_INCR(sc
, sc_ev_rxhist
[5]);
1967 GEM_COUNTER_INCR(sc
, sc_ev_rxhist
[6]);
1971 GEM_COUNTER_INCR(sc
, sc_ev_rxhist
[7]);
1973 GEM_COUNTER_INCR(sc
, sc_ev_rxhist
[8]);
1977 DPRINTF(sc
, ("gem_rint: done sc->rxptr %d, complete %d\n",
1978 sc
->sc_rxptr
, bus_space_read_4(t
, h
, GEM_RX_COMPLETION
)));
1980 /* Read error counters ... */
1982 bus_space_read_4(t
, h
, GEM_MAC_RX_LEN_ERR_CNT
) +
1983 bus_space_read_4(t
, h
, GEM_MAC_RX_ALIGN_ERR
) +
1984 bus_space_read_4(t
, h
, GEM_MAC_RX_CRC_ERR_CNT
) +
1985 bus_space_read_4(t
, h
, GEM_MAC_RX_CODE_VIOL
);
1987 /* ... then clear the hardware counters. */
1988 bus_space_write_4(t
, h
, GEM_MAC_RX_LEN_ERR_CNT
, 0);
1989 bus_space_write_4(t
, h
, GEM_MAC_RX_ALIGN_ERR
, 0);
1990 bus_space_write_4(t
, h
, GEM_MAC_RX_CRC_ERR_CNT
, 0);
1991 bus_space_write_4(t
, h
, GEM_MAC_RX_CODE_VIOL
, 0);
2000 * Add a receive buffer to the indicated descriptor.
2003 gem_add_rxbuf(struct gem_softc
*sc
, int idx
)
2005 struct gem_rxsoft
*rxs
= &sc
->sc_rxsoft
[idx
];
2009 MGETHDR(m
, M_DONTWAIT
, MT_DATA
);
2013 MCLAIM(m
, &sc
->sc_ethercom
.ec_rx_mowner
);
2014 MCLGET(m
, M_DONTWAIT
);
2015 if ((m
->m_flags
& M_EXT
) == 0) {
2021 /* bzero the packet to check DMA */
2022 memset(m
->m_ext
.ext_buf
, 0, m
->m_ext
.ext_size
);
2025 if (rxs
->rxs_mbuf
!= NULL
)
2026 bus_dmamap_unload(sc
->sc_dmatag
, rxs
->rxs_dmamap
);
2030 error
= bus_dmamap_load(sc
->sc_dmatag
, rxs
->rxs_dmamap
,
2031 m
->m_ext
.ext_buf
, m
->m_ext
.ext_size
, NULL
,
2032 BUS_DMA_READ
|BUS_DMA_NOWAIT
);
2034 aprint_error_dev(sc
->sc_dev
,
2035 "can't load rx DMA map %d, error = %d\n", idx
, error
);
2036 panic("gem_add_rxbuf"); /* XXX */
2039 bus_dmamap_sync(sc
->sc_dmatag
, rxs
->rxs_dmamap
, 0,
2040 rxs
->rxs_dmamap
->dm_mapsize
, BUS_DMASYNC_PREREAD
);
2042 GEM_INIT_RXDESC(sc
, idx
);
2049 gem_eint(struct gem_softc
*sc
, u_int status
)
2054 if ((status
& GEM_INTR_MIF
) != 0) {
2055 printf("%s: XXXlink status changed\n", device_xname(sc
->sc_dev
));
2059 if ((status
& GEM_INTR_RX_TAG_ERR
) != 0) {
2060 gem_reset_rxdma(sc
);
2064 if (status
& GEM_INTR_BERR
) {
2065 if (sc
->sc_flags
& GEM_PCI
)
2066 r
= GEM_ERROR_STATUS
;
2068 r
= GEM_SBUS_ERROR_STATUS
;
2069 bus_space_read_4(sc
->sc_bustag
, sc
->sc_h2
, r
);
2070 v
= bus_space_read_4(sc
->sc_bustag
, sc
->sc_h2
, r
);
2071 aprint_error_dev(sc
->sc_dev
, "bus error interrupt: 0x%02x\n",
2075 snprintb(bits
, sizeof(bits
), GEM_INTR_BITS
, status
);
2076 printf("%s: status=%s\n", device_xname(sc
->sc_dev
), bits
);
2084 * We should receive these when the link status changes, but sometimes
2085 * we don't receive them for link up. We compensate for this in the
2086 * gem_tick() callout.
2089 gem_pint(struct gem_softc
*sc
)
2091 struct ifnet
*ifp
= &sc
->sc_ethercom
.ec_if
;
2092 bus_space_tag_t t
= sc
->sc_bustag
;
2093 bus_space_handle_t h
= sc
->sc_h1
;
2097 * Clear the PCS interrupt from GEM_STATUS. The PCS register is
2098 * latched, so we have to read it twice. There is only one bit in
2099 * use, so the value is meaningless.
2101 bus_space_read_4(t
, h
, GEM_MII_INTERRUP_STATUS
);
2102 bus_space_read_4(t
, h
, GEM_MII_INTERRUP_STATUS
);
2104 if ((ifp
->if_flags
& IFF_UP
) == 0)
2107 if ((sc
->sc_flags
& (GEM_SERDES
| GEM_SERIAL
)) == 0)
2110 v
= bus_space_read_4(t
, h
, GEM_MII_STATUS
);
2111 /* If we see remote fault, our link partner is probably going away */
2112 if ((v
& GEM_MII_STATUS_REM_FLT
) != 0) {
2113 gem_bitwait(sc
, h
, GEM_MII_STATUS
, GEM_MII_STATUS_REM_FLT
, 0);
2114 v
= bus_space_read_4(t
, h
, GEM_MII_STATUS
);
2115 /* Otherwise, we may need to wait after auto-negotiation completes */
2116 } else if ((v
& (GEM_MII_STATUS_LINK_STS
| GEM_MII_STATUS_ANEG_CPT
)) ==
2117 GEM_MII_STATUS_ANEG_CPT
) {
2118 gem_bitwait(sc
, h
, GEM_MII_STATUS
, 0, GEM_MII_STATUS_LINK_STS
);
2119 v
= bus_space_read_4(t
, h
, GEM_MII_STATUS
);
2121 if ((v
& GEM_MII_STATUS_LINK_STS
) != 0) {
2122 if (sc
->sc_flags
& GEM_LINK
) {
2125 callout_stop(&sc
->sc_tick_ch
);
2126 v
= bus_space_read_4(t
, h
, GEM_MII_ANAR
);
2127 v2
= bus_space_read_4(t
, h
, GEM_MII_ANLPAR
);
2128 sc
->sc_mii
.mii_media_active
= IFM_ETHER
| IFM_1000_SX
;
2129 sc
->sc_mii
.mii_media_status
= IFM_AVALID
| IFM_ACTIVE
;
2131 if (v
& GEM_MII_ANEG_FUL_DUPLX
) {
2132 sc
->sc_mii
.mii_media_active
|= IFM_FDX
;
2134 aprint_debug_dev(sc
->sc_dev
, "link up: full duplex\n");
2136 } else if (v
& GEM_MII_ANEG_HLF_DUPLX
) {
2137 sc
->sc_mii
.mii_media_active
|= IFM_HDX
;
2139 aprint_debug_dev(sc
->sc_dev
, "link up: half duplex\n");
2143 aprint_debug_dev(sc
->sc_dev
, "duplex mismatch\n");
2146 gem_statuschange(sc
);
2148 if ((sc
->sc_flags
& GEM_LINK
) == 0) {
2151 sc
->sc_mii
.mii_media_active
= IFM_ETHER
| IFM_NONE
;
2152 sc
->sc_mii
.mii_media_status
= IFM_AVALID
;
2154 aprint_debug_dev(sc
->sc_dev
, "link down\n");
2156 gem_statuschange(sc
);
2158 /* Start the 10 second timer */
2159 callout_reset(&sc
->sc_tick_ch
, hz
* 10, gem_tick
, sc
);
2169 struct gem_softc
*sc
= v
;
2170 struct ifnet
*ifp
= &sc
->sc_ethercom
.ec_if
;
2171 bus_space_tag_t t
= sc
->sc_bustag
;
2172 bus_space_handle_t h
= sc
->sc_h1
;
2179 /* XXX We should probably mask out interrupts until we're done */
2181 sc
->sc_ev_intr
.ev_count
++;
2183 status
= bus_space_read_4(t
, h
, GEM_STATUS
);
2185 snprintb(bits
, sizeof(bits
), GEM_INTR_BITS
, status
);
2187 DPRINTF(sc
, ("%s: gem_intr: cplt 0x%x status %s\n",
2188 device_xname(sc
->sc_dev
), (status
>> 19), bits
));
2191 if ((status
& (GEM_INTR_RX_TAG_ERR
| GEM_INTR_BERR
)) != 0)
2192 r
|= gem_eint(sc
, status
);
2194 /* We don't bother with GEM_INTR_TX_DONE */
2195 if ((status
& (GEM_INTR_TX_EMPTY
| GEM_INTR_TX_INTME
)) != 0) {
2196 GEM_COUNTER_INCR(sc
, sc_ev_txint
);
2200 if ((status
& (GEM_INTR_RX_DONE
| GEM_INTR_RX_NOBUF
)) != 0) {
2201 GEM_COUNTER_INCR(sc
, sc_ev_rxint
);
2205 /* We should eventually do more than just print out error stats. */
2206 if (status
& GEM_INTR_TX_MAC
) {
2207 int txstat
= bus_space_read_4(t
, h
, GEM_MAC_TX_STATUS
);
2208 if (txstat
& ~GEM_MAC_TX_XMIT_DONE
)
2209 printf("%s: MAC tx fault, status %x\n",
2210 device_xname(sc
->sc_dev
), txstat
);
2211 if (txstat
& (GEM_MAC_TX_UNDERRUN
| GEM_MAC_TX_PKT_TOO_LONG
))
2214 if (status
& GEM_INTR_RX_MAC
) {
2215 int rxstat
= bus_space_read_4(t
, h
, GEM_MAC_RX_STATUS
);
2217 * At least with GEM_SUN_GEM and some GEM_SUN_ERI
2218 * revisions GEM_MAC_RX_OVERFLOW happen often due to a
2219 * silicon bug so handle them silently. Moreover, it's
2220 * likely that the receiver has hung so we reset it.
2222 if (rxstat
& GEM_MAC_RX_OVERFLOW
) {
2224 gem_reset_rxdma(sc
);
2225 } else if (rxstat
& ~(GEM_MAC_RX_DONE
| GEM_MAC_RX_FRAME_CNT
))
2226 printf("%s: MAC rx fault, status 0x%02x\n",
2227 device_xname(sc
->sc_dev
), rxstat
);
2229 if (status
& GEM_INTR_PCS
) {
2233 /* Do we need to do anything with these?
2234 if ((status & GEM_MAC_CONTROL_STATUS) != 0) {
2235 status2 = bus_read_4(sc->sc_res[0], GEM_MAC_CONTROL_STATUS);
2236 if ((status2 & GEM_MAC_PAUSED) != 0)
2237 aprintf_debug_dev(sc->sc_dev, "PAUSE received (%d slots)\n",
2238 GEM_MAC_PAUSE_TIME(status2));
2239 if ((status2 & GEM_MAC_PAUSE) != 0)
2240 aprintf_debug_dev(sc->sc_dev, "transited to PAUSE state\n");
2241 if ((status2 & GEM_MAC_RESUME) != 0)
2242 aprintf_debug_dev(sc->sc_dev, "transited to non-PAUSE state\n");
2244 if ((status & GEM_INTR_MIF) != 0)
2245 aprintf_debug_dev(sc->sc_dev, "MIF interrupt\n");
2248 rnd_add_uint32(&sc
->rnd_source
, status
);
2255 gem_watchdog(struct ifnet
*ifp
)
2257 struct gem_softc
*sc
= ifp
->if_softc
;
2259 DPRINTF(sc
, ("gem_watchdog: GEM_RX_CONFIG %x GEM_MAC_RX_STATUS %x "
2260 "GEM_MAC_RX_CONFIG %x\n",
2261 bus_space_read_4(sc
->sc_bustag
, sc
->sc_h1
, GEM_RX_CONFIG
),
2262 bus_space_read_4(sc
->sc_bustag
, sc
->sc_h1
, GEM_MAC_RX_STATUS
),
2263 bus_space_read_4(sc
->sc_bustag
, sc
->sc_h1
, GEM_MAC_RX_CONFIG
)));
2265 log(LOG_ERR
, "%s: device timeout\n", device_xname(sc
->sc_dev
));
2268 /* Try to get more packets going. */
2273 * Initialize the MII Management Interface
2276 gem_mifinit(struct gem_softc
*sc
)
2278 bus_space_tag_t t
= sc
->sc_bustag
;
2279 bus_space_handle_t mif
= sc
->sc_h1
;
2281 /* Configure the MIF in frame mode */
2282 sc
->sc_mif_config
= bus_space_read_4(t
, mif
, GEM_MIF_CONFIG
);
2283 sc
->sc_mif_config
&= ~GEM_MIF_CONFIG_BB_ENA
;
2284 bus_space_write_4(t
, mif
, GEM_MIF_CONFIG
, sc
->sc_mif_config
);
2290 * The GEM MII interface supports at least three different operating modes:
2292 * Bitbang mode is implemented using data, clock and output enable registers.
2294 * Frame mode is implemented by loading a complete frame into the frame
2295 * register and polling the valid bit for completion.
2297 * Polling mode uses the frame register but completion is indicated by
2302 gem_mii_readreg(device_t self
, int phy
, int reg
)
2304 struct gem_softc
*sc
= device_private(self
);
2305 bus_space_tag_t t
= sc
->sc_bustag
;
2306 bus_space_handle_t mif
= sc
->sc_h1
;
2312 printf("gem_mii_readreg: PHY %d reg %d\n", phy
, reg
);
2315 /* Construct the frame command */
2316 v
= (reg
<< GEM_MIF_REG_SHIFT
) | (phy
<< GEM_MIF_PHY_SHIFT
) |
2319 bus_space_write_4(t
, mif
, GEM_MIF_FRAME
, v
);
2320 for (n
= 0; n
< 100; n
++) {
2322 v
= bus_space_read_4(t
, mif
, GEM_MIF_FRAME
);
2323 if (v
& GEM_MIF_FRAME_TA0
)
2324 return (v
& GEM_MIF_FRAME_DATA
);
2327 printf("%s: mii_read timeout\n", device_xname(sc
->sc_dev
));
2332 gem_mii_writereg(device_t self
, int phy
, int reg
, int val
)
2334 struct gem_softc
*sc
= device_private(self
);
2335 bus_space_tag_t t
= sc
->sc_bustag
;
2336 bus_space_handle_t mif
= sc
->sc_h1
;
2342 printf("gem_mii_writereg: PHY %d reg %d val %x\n",
2346 /* Construct the frame command */
2347 v
= GEM_MIF_FRAME_WRITE
|
2348 (phy
<< GEM_MIF_PHY_SHIFT
) |
2349 (reg
<< GEM_MIF_REG_SHIFT
) |
2350 (val
& GEM_MIF_FRAME_DATA
);
2352 bus_space_write_4(t
, mif
, GEM_MIF_FRAME
, v
);
2353 for (n
= 0; n
< 100; n
++) {
2355 v
= bus_space_read_4(t
, mif
, GEM_MIF_FRAME
);
2356 if (v
& GEM_MIF_FRAME_TA0
)
2360 printf("%s: mii_write timeout\n", device_xname(sc
->sc_dev
));
2364 gem_mii_statchg(device_t self
)
2366 struct gem_softc
*sc
= device_private(self
);
2368 int instance
= IFM_INST(sc
->sc_mii
.mii_media
.ifm_cur
->ifm_media
);
2373 printf("gem_mii_statchg: status change: phy = %d\n",
2374 sc
->sc_phys
[instance
]);
2376 gem_statuschange(sc
);
2380 * Common status change for gem_mii_statchg() and gem_pint()
2383 gem_statuschange(struct gem_softc
* sc
)
2385 struct ifnet
*ifp
= &sc
->sc_ethercom
.ec_if
;
2386 bus_space_tag_t t
= sc
->sc_bustag
;
2387 bus_space_handle_t mac
= sc
->sc_h1
;
2389 u_int32_t rxcfg
, txcfg
, v
;
2391 if ((sc
->sc_mii
.mii_media_status
& IFM_ACTIVE
) != 0 &&
2392 IFM_SUBTYPE(sc
->sc_mii
.mii_media_active
) != IFM_NONE
)
2393 sc
->sc_flags
|= GEM_LINK
;
2395 sc
->sc_flags
&= ~GEM_LINK
;
2397 if (sc
->sc_ethercom
.ec_if
.if_baudrate
== IF_Mbps(1000))
2403 * The configuration done here corresponds to the steps F) and
2404 * G) and as far as enabling of RX and TX MAC goes also step H)
2405 * of the initialization sequence outlined in section 3.2.1 of
2406 * the GEM Gigabit Ethernet ASIC Specification.
2409 rxcfg
= bus_space_read_4(t
, mac
, GEM_MAC_RX_CONFIG
);
2410 rxcfg
&= ~(GEM_MAC_RX_CARR_EXTEND
| GEM_MAC_RX_ENABLE
);
2411 txcfg
= GEM_MAC_TX_ENA_IPG0
| GEM_MAC_TX_NGU
| GEM_MAC_TX_NGU_LIMIT
;
2412 if ((IFM_OPTIONS(sc
->sc_mii
.mii_media_active
) & IFM_FDX
) != 0)
2413 txcfg
|= GEM_MAC_TX_IGN_CARRIER
| GEM_MAC_TX_IGN_COLLIS
;
2415 rxcfg
|= GEM_MAC_RX_CARR_EXTEND
;
2416 txcfg
|= GEM_MAC_RX_CARR_EXTEND
;
2418 bus_space_write_4(t
, mac
, GEM_MAC_TX_CONFIG
, 0);
2419 bus_space_barrier(t
, mac
, GEM_MAC_TX_CONFIG
, 4,
2420 BUS_SPACE_BARRIER_WRITE
);
2421 if (!gem_bitwait(sc
, mac
, GEM_MAC_TX_CONFIG
, GEM_MAC_TX_ENABLE
, 0))
2422 aprint_normal_dev(sc
->sc_dev
, "cannot disable TX MAC\n");
2423 bus_space_write_4(t
, mac
, GEM_MAC_TX_CONFIG
, txcfg
);
2424 bus_space_write_4(t
, mac
, GEM_MAC_RX_CONFIG
, 0);
2425 bus_space_barrier(t
, mac
, GEM_MAC_RX_CONFIG
, 4,
2426 BUS_SPACE_BARRIER_WRITE
);
2427 if (!gem_bitwait(sc
, mac
, GEM_MAC_RX_CONFIG
, GEM_MAC_RX_ENABLE
, 0))
2428 aprint_normal_dev(sc
->sc_dev
, "cannot disable RX MAC\n");
2429 bus_space_write_4(t
, mac
, GEM_MAC_RX_CONFIG
, rxcfg
);
2431 v
= bus_space_read_4(t
, mac
, GEM_MAC_CONTROL_CONFIG
) &
2432 ~(GEM_MAC_CC_RX_PAUSE
| GEM_MAC_CC_TX_PAUSE
);
2433 bus_space_write_4(t
, mac
, GEM_MAC_CONTROL_CONFIG
, v
);
2435 if ((IFM_OPTIONS(sc
->sc_mii
.mii_media_active
) & IFM_FDX
) == 0 &&
2437 bus_space_write_4(t
, mac
, GEM_MAC_SLOT_TIME
,
2438 GEM_MAC_SLOT_TIME_CARR_EXTEND
);
2440 bus_space_write_4(t
, mac
, GEM_MAC_SLOT_TIME
,
2441 GEM_MAC_SLOT_TIME_NORMAL
);
2443 /* XIF Configuration */
2444 if (sc
->sc_flags
& GEM_LINK
)
2445 v
= GEM_MAC_XIF_LINK_LED
;
2448 v
|= GEM_MAC_XIF_TX_MII_ENA
;
2450 /* If an external transceiver is connected, enable its MII drivers */
2451 sc
->sc_mif_config
= bus_space_read_4(t
, mac
, GEM_MIF_CONFIG
);
2452 if ((sc
->sc_flags
&(GEM_SERDES
| GEM_SERIAL
)) == 0) {
2453 if ((sc
->sc_mif_config
& GEM_MIF_CONFIG_MDI1
) != 0) {
2454 /* External MII needs echo disable if half duplex. */
2455 if ((IFM_OPTIONS(sc
->sc_mii
.mii_media_active
) &
2457 /* turn on full duplex LED */
2458 v
|= GEM_MAC_XIF_FDPLX_LED
;
2460 /* half duplex -- disable echo */
2461 v
|= GEM_MAC_XIF_ECHO_DISABL
;
2463 v
|= GEM_MAC_XIF_GMII_MODE
;
2465 v
&= ~GEM_MAC_XIF_GMII_MODE
;
2467 /* Internal MII needs buf enable */
2468 v
|= GEM_MAC_XIF_MII_BUF_ENA
;
2470 if ((IFM_OPTIONS(sc
->sc_mii
.mii_media_active
) & IFM_FDX
) != 0)
2471 v
|= GEM_MAC_XIF_FDPLX_LED
;
2472 v
|= GEM_MAC_XIF_GMII_MODE
;
2474 bus_space_write_4(t
, mac
, GEM_MAC_XIF_CONFIG
, v
);
2476 if ((ifp
->if_flags
& IFF_RUNNING
) != 0 &&
2477 (sc
->sc_flags
& GEM_LINK
) != 0) {
2478 bus_space_write_4(t
, mac
, GEM_MAC_TX_CONFIG
,
2479 txcfg
| GEM_MAC_TX_ENABLE
);
2480 bus_space_write_4(t
, mac
, GEM_MAC_RX_CONFIG
,
2481 rxcfg
| GEM_MAC_RX_ENABLE
);
2486 gem_ser_mediachange(struct ifnet
*ifp
)
2488 struct gem_softc
*sc
= ifp
->if_softc
;
2491 if (IFM_TYPE(sc
->sc_mii
.mii_media
.ifm_media
) != IFM_ETHER
)
2494 s
= IFM_SUBTYPE(sc
->sc_mii
.mii_media
.ifm_media
);
2495 if (s
== IFM_AUTO
) {
2496 if (sc
->sc_mii_media
!= s
) {
2498 aprint_debug_dev(sc
->sc_dev
, "setting media to auto\n");
2500 sc
->sc_mii_media
= s
;
2501 if (ifp
->if_flags
& IFF_UP
) {
2502 gem_pcs_stop(sc
, 0);
2508 if (s
== IFM_1000_SX
) {
2509 t
= IFM_OPTIONS(sc
->sc_mii
.mii_media
.ifm_media
);
2510 if (t
== IFM_FDX
|| t
== IFM_HDX
) {
2511 if (sc
->sc_mii_media
!= t
) {
2512 sc
->sc_mii_media
= t
;
2514 aprint_debug_dev(sc
->sc_dev
,
2515 "setting media to 1000baseSX-%s\n",
2516 t
== IFM_FDX
? "FDX" : "HDX");
2518 if (ifp
->if_flags
& IFF_UP
) {
2519 gem_pcs_stop(sc
, 0);
2530 gem_ser_mediastatus(struct ifnet
*ifp
, struct ifmediareq
*ifmr
)
2532 struct gem_softc
*sc
= ifp
->if_softc
;
2534 if ((ifp
->if_flags
& IFF_UP
) == 0)
2536 ifmr
->ifm_active
= sc
->sc_mii
.mii_media_active
;
2537 ifmr
->ifm_status
= sc
->sc_mii
.mii_media_status
;
2541 gem_ifflags_cb(struct ethercom
*ec
)
2543 struct ifnet
*ifp
= &ec
->ec_if
;
2544 struct gem_softc
*sc
= ifp
->if_softc
;
2545 int change
= ifp
->if_flags
^ sc
->sc_if_flags
;
2547 if ((change
& ~(IFF_CANTCHANGE
|IFF_DEBUG
)) != 0)
2549 else if ((change
& IFF_PROMISC
) != 0)
2555 * Process an ioctl request.
2558 gem_ioctl(struct ifnet
*ifp
, unsigned long cmd
, void *data
)
2560 struct gem_softc
*sc
= ifp
->if_softc
;
2565 if ((error
= ether_ioctl(ifp
, cmd
, data
)) == ENETRESET
) {
2567 if (cmd
!= SIOCADDMULTI
&& cmd
!= SIOCDELMULTI
)
2569 else if (ifp
->if_flags
& IFF_RUNNING
) {
2571 * Multicast list has changed; set the hardware filter
2578 /* Try to get things going again */
2579 if (ifp
->if_flags
& IFF_UP
)
2586 gem_inten(struct gem_softc
*sc
)
2588 bus_space_tag_t t
= sc
->sc_bustag
;
2589 bus_space_handle_t h
= sc
->sc_h1
;
2592 if ((sc
->sc_flags
& (GEM_SERDES
| GEM_SERIAL
)) != 0)
2596 bus_space_write_4(t
, h
, GEM_INTMASK
,
2597 ~(GEM_INTR_TX_INTME
|
2600 GEM_INTR_RX_DONE
| GEM_INTR_RX_NOBUF
|
2601 GEM_INTR_RX_TAG_ERR
| GEM_INTR_MAC_CONTROL
|
2602 GEM_INTR_BERR
| v
));
2606 gem_resume(device_t self
, pmf_qual_t qual
)
2608 struct gem_softc
*sc
= device_private(self
);
2616 gem_suspend(device_t self
, pmf_qual_t qual
)
2618 struct gem_softc
*sc
= device_private(self
);
2619 bus_space_tag_t t
= sc
->sc_bustag
;
2620 bus_space_handle_t h
= sc
->sc_h1
;
2622 bus_space_write_4(t
, h
, GEM_INTMASK
, ~(uint32_t)0);
2628 gem_shutdown(device_t self
, int howto
)
2630 struct gem_softc
*sc
= device_private(self
);
2631 struct ifnet
*ifp
= &sc
->sc_ethercom
.ec_if
;
2639 * Set up the logical address filter.
2642 gem_setladrf(struct gem_softc
*sc
)
2644 struct ethercom
*ec
= &sc
->sc_ethercom
;
2645 struct ifnet
*ifp
= &ec
->ec_if
;
2646 struct ether_multi
*enm
;
2647 struct ether_multistep step
;
2648 bus_space_tag_t t
= sc
->sc_bustag
;
2649 bus_space_handle_t h
= sc
->sc_h1
;
2655 /* Get current RX configuration */
2656 v
= bus_space_read_4(t
, h
, GEM_MAC_RX_CONFIG
);
2659 * Turn off promiscuous mode, promiscuous group mode (all multicast),
2660 * and hash filter. Depending on the case, the right bit will be
2663 v
&= ~(GEM_MAC_RX_PROMISCUOUS
|GEM_MAC_RX_HASH_FILTER
|
2664 GEM_MAC_RX_PROMISC_GRP
);
2666 if ((ifp
->if_flags
& IFF_PROMISC
) != 0) {
2667 /* Turn on promiscuous mode */
2668 v
|= GEM_MAC_RX_PROMISCUOUS
;
2669 ifp
->if_flags
|= IFF_ALLMULTI
;
2674 * Set up multicast address filter by passing all multicast addresses
2675 * through a crc generator, and then using the high order 8 bits as an
2676 * index into the 256 bit logical address filter. The high order 4
2677 * bits selects the word, while the other 4 bits select the bit within
2678 * the word (where bit 0 is the MSB).
2681 /* Clear hash table */
2682 memset(hash
, 0, sizeof(hash
));
2684 ETHER_FIRST_MULTI(step
, ec
, enm
);
2685 while (enm
!= NULL
) {
2686 if (memcmp(enm
->enm_addrlo
, enm
->enm_addrhi
, ETHER_ADDR_LEN
)) {
2688 * We must listen to a range of multicast addresses.
2689 * For now, just accept all multicasts, rather than
2690 * trying to set only those filter bits needed to match
2691 * the range. (At this time, the only use of address
2692 * ranges is for IP multicast routing, for which the
2693 * range is big enough to require all bits set.)
2694 * XXX should use the address filters for this
2696 ifp
->if_flags
|= IFF_ALLMULTI
;
2697 v
|= GEM_MAC_RX_PROMISC_GRP
;
2701 /* Get the LE CRC32 of the address */
2702 crc
= ether_crc32_le(enm
->enm_addrlo
, sizeof(enm
->enm_addrlo
));
2704 /* Just want the 8 most significant bits. */
2707 /* Set the corresponding bit in the filter. */
2708 hash
[crc
>> 4] |= 1 << (15 - (crc
& 15));
2710 ETHER_NEXT_MULTI(step
, enm
);
2713 v
|= GEM_MAC_RX_HASH_FILTER
;
2714 ifp
->if_flags
&= ~IFF_ALLMULTI
;
2716 /* Now load the hash table into the chip (if we are using it) */
2717 for (i
= 0; i
< 16; i
++) {
2718 bus_space_write_4(t
, h
,
2719 GEM_MAC_HASH0
+ i
* (GEM_MAC_HASH1
-GEM_MAC_HASH0
),
2724 sc
->sc_if_flags
= ifp
->if_flags
;
2725 bus_space_write_4(t
, h
, GEM_MAC_RX_CONFIG
, v
);