sys/arch/arm/include/arm32/pte.h

   1 /*      $NetBSD: pte.h,v 1.7.82.2 2007/11/09 05:37:39 matt Exp $        */
   2
   3 /*
   4  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
   5  * All rights reserved.
   6  *
   7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed for the NetBSD Project by
  20  *      Wasabi Systems, Inc.
  21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
  22  *    or promote products derived from this software without specific prior
  23  *    written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
  26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
  29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  35  * POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef _ARM_PTE_H_
  39 #define _ARM_PTE_H_
  40
  41 /*
  42  * The ARM MMU architecture was introduced with ARM v3 (previous ARM
  43  * architecture versions used an optional off-CPU memory controller
  44  * to perform address translation).
  45  *
  46  * The ARM MMU consists of a TLB and translation table walking logic.
  47  * There is typically one TLB per memory interface (or, put another
  48  * way, one TLB per software-visible cache).
  49  *
  50  * The ARM MMU is capable of mapping memory in the following chunks:
  51  *
  52  *      16M     SuperSections (L1 table, ARMv6+)
  53  *
  54  *      1M      Sections (L1 table)
  55  *
  56  *      64K     Large Pages (L2 table)
  57  *
  58  *      4K      Small Pages (L2 table)
  59  *
  60  *      1K      Tiny Pages (L2 table)
  61  *
  62  * There are two types of L2 tables: Coarse Tables and Fine Tables (not
  63  * available on ARMv6+).  Coarse Tables can map Large and Small Pages.
  64  * Fine Tables can map Tiny Pages.
  65  *
  66  * Coarse Tables can define 4 Subpages within Large and Small pages.
  67  * Subpages define different permissions for each Subpage within
  68  * a Page.  ARMv6 format Coarse Tables have no subpages.
  69  *
  70  * Coarse Tables are 1K in length.  Fine tables are 4K in length.
  71  *
  72  * The Translation Table Base register holds the pointer to the
  73  * L1 Table.  The L1 Table is a 16K contiguous chunk of memory
  74  * aligned to a 16K boundary.  Each entry in the L1 Table maps
  75  * 1M of virtual address space, either via a Section mapping or
  76  * via an L2 Table.
  77  *
  78  * ARMv6+ has a second TTBR register which can be used if any of the
  79  * upper address bits are non-zero (think kernel).  For NetBSD, this
  80  * would be 1 upper bit splitting user/kernel in a 2GB/2GB split.
  81  * This would also reduce the size of the L1 Table to 8K.
  82  *
  83  * In addition, the Fast Context Switching Extension (FCSE) is available
  84  * on some ARM v4 and ARM v5 processors.  FCSE is a way of eliminating
  85  * TLB/cache flushes on context switch by use of a smaller address space
  86  * and a "process ID" that modifies the virtual address before being
  87  * presented to the translation logic.
  88  */
  89
  90 #ifndef _LOCORE
  91 typedef uint32_t        pd_entry_t;     /* L1 table entry */
  92 typedef uint32_t        pt_entry_t;     /* L2 table entry */
  93 #endif /* _LOCORE */
  94
  95 #define L1_SS_SIZE      0x01000000      /* 16M */
  96 #define L1_SS_OFFSET    (L1_SS_SIZE - 1)
  97 #define L1_SS_FRAME     (~L1_SS_OFFSET)
  98 #define L1_SS_SHIFT     24
  99
 100 #define L1_S_SIZE       0x00100000      /* 1M */
 101 #define L1_S_OFFSET     (L1_S_SIZE - 1)
 102 #define L1_S_FRAME      (~L1_S_OFFSET)
 103 #define L1_S_SHIFT      20
 104
 105 #define L2_L_SIZE       0x00010000      /* 64K */
 106 #define L2_L_OFFSET     (L2_L_SIZE - 1)
 107 #define L2_L_FRAME      (~L2_L_OFFSET)
 108 #define L2_L_SHIFT      16
 109
 110 #define L2_S_SIZE       0x00001000      /* 4K */
 111 #define L2_S_OFFSET     (L2_S_SIZE - 1)
 112 #define L2_S_FRAME      (~L2_S_OFFSET)
 113 #define L2_S_SHIFT      12
 114
 115 #define L2_T_SIZE       0x00000400      /* 1K */
 116 #define L2_T_OFFSET     (L2_T_SIZE - 1)
 117 #define L2_T_FRAME      (~L2_T_OFFSET)
 118 #define L2_T_SHIFT      10
 119
 120 /*
 121  * The NetBSD VM implementation only works on whole pages (4K),
 122  * whereas the ARM MMU's Coarse tables are sized in terms of 1K
 123  * (16K L1 table, 1K L2 table).
 124  *
 125  * So, we allocate L2 tables 4 at a time, thus yielding a 4K L2
 126  * table.
 127  */
 128 #define L1_ADDR_BITS    0xfff00000      /* L1 PTE address bits */
 129 #define L2_ADDR_BITS    0x000ff000      /* L2 PTE address bits */
 130
 131 #define L1_TABLE_SIZE   0x4000          /* 16K */
 132 #define L2_TABLE_SIZE   0x1000          /* 4K */
 133 /*
 134  * The new pmap deals with the 1KB coarse L2 tables by
 135  * allocating them from a pool. Until every port has been converted,
 136  * keep the old L2_TABLE_SIZE define lying around. Converted ports
 137  * should use L2_TABLE_SIZE_REAL until then.
 138  */
 139 #define L2_TABLE_SIZE_REAL      0x400   /* 1K */
 140
 141 /*
 142  * ARM L1 Descriptors
 143  */
 144
 145 #define L1_TYPE_INV     0x00            /* Invalid (fault) */
 146 #define L1_TYPE_C       0x01            /* Coarse L2 */
 147 #define L1_TYPE_S       0x02            /* Section */
 148 #define L1_TYPE_F       0x03            /* Fine L2 */
 149 #define L1_TYPE_MASK    0x03            /* mask of type bits */
 150
 151 /* L1 Section Descriptor */
 152 #define L1_S_B          0x00000004      /* bufferable Section */
 153 #define L1_S_C          0x00000008      /* cacheable Section */
 154 #define L1_S_IMP        0x00000010      /* implementation defined */
 155 #define L1_S_DOM(x)     ((x) << 5)      /* domain */
 156 #define L1_S_DOM_MASK   L1_S_DOM(0xf)
 157 #define L1_S_AP(x)      ((x) << 10)     /* access permissions */
 158 #define L1_S_ADDR_MASK  0xfff00000      /* phys address of section */
 159
 160 #define L1_S_XSCALE_P   0x00000200      /* ECC enable for this section */
 161 #define L1_S_XS_TEX(x) ((x) << 12)      /* Type Extension */
 162 #define L1_S_V6_TEX(x)  ((x) << 12)     /* Type Extension */
 163 #define L1_S_V6_P       0x00000200      /* ECC enable for this section */
 164 #define L1_S_V6_SUPER   0x00040000      /* ARMv6 SuperSection (16MB) bit */
 165 #define L1_S_V6_XN      L1_S_IMP        /* ARMv6 eXecute Never */
 166 #define L1_S_V6_APX     0x00008000      /* ARMv6 AP eXtension */
 167 #define L1_S_V6_S       0x00010000      /* ARMv6 Shared */
 168 #define L1_S_V6_nG      0x00020000      /* ARMv6 not-Global */
 169
 170 /* L1 Coarse Descriptor */
 171 #define L1_C_IMP0       0x00000004      /* implementation defined */
 172 #define L1_C_IMP1       0x00000008      /* implementation defined */
 173 #define L1_C_IMP2       0x00000010      /* implementation defined */
 174 #define L1_C_DOM(x)     ((x) << 5)      /* domain */
 175 #define L1_C_DOM_MASK   L1_C_DOM(0xf)
 176 #define L1_C_ADDR_MASK  0xfffffc00      /* phys address of L2 Table */
 177
 178 #define L1_C_XSCALE_P   0x00000200      /* ECC enable for this section */
 179 #define L1_C_V6_P       0x00000200      /* ECC enable for this section */
 180
 181 /* L1 Fine Descriptor */
 182 #define L1_F_IMP0       0x00000004      /* implementation defined */
 183 #define L1_F_IMP1       0x00000008      /* implementation defined */
 184 #define L1_F_IMP2       0x00000010      /* implementation defined */
 185 #define L1_F_DOM(x)     ((x) << 5)      /* domain */
 186 #define L1_F_DOM_MASK   L1_F_DOM(0xf)
 187 #define L1_F_ADDR_MASK  0xfffff000      /* phys address of L2 Table */
 188
 189 #define L1_F_XSCALE_P   0x00000200      /* ECC enable for this section */
 190
 191 /*
 192  * ARM L2 Descriptors
 193  */
 194
 195 #define L2_TYPE_INV     0x00            /* Invalid (fault) */
 196 #define L2_TYPE_L       0x01            /* Large Page */
 197 #define L2_TYPE_S       0x02            /* Small Page */
 198 #define L2_TYPE_T       0x03            /* Tiny Page */
 199 #define L2_TYPE_MASK    0x03            /* mask of type bits */
 200
 201         /*
 202          * This L2 Descriptor type is available on XScale processors
 203          * when using a Coarse L1 Descriptor.  The Extended Small
 204          * Descriptor has the same format as the XScale Tiny Descriptor,
 205          * but describes a 4K page, rather than a 1K page.
 206          */
 207 #define L2_TYPE_XS      0x03            /* XScale/ARMv6 Extended Small Page */
 208
 209 #define L2_B            0x00000004      /* Bufferable page */
 210 #define L2_C            0x00000008      /* Cacheable page */
 211 #define L2_AP0(x)       ((x) << 4)      /* access permissions (sp 0) */
 212 #define L2_AP1(x)       ((x) << 6)      /* access permissions (sp 1) */
 213 #define L2_AP2(x)       ((x) << 8)      /* access permissions (sp 2) */
 214 #define L2_AP3(x)       ((x) << 10)     /* access permissions (sp 3) */
 215 #define L2_AP(x)        (L2_AP0(x) | L2_AP1(x) | L2_AP2(x) | L2_AP3(x))
 216
 217 #define L2_XS_L_TEX(x)  ((x) << 12)     /* Type Extension */
 218 #define L2_XS_T_TEX(x)  ((x) << 6)      /* Type Extension */
 219 #define L2_XS_XN        0x00000001      /* ARMv6 eXecute Never */
 220 #define L2_XS_APX       0x00000200      /* ARMv6 AP eXtension */
 221 #define L2_XS_S         0x00000400      /* ARMv6 Shared */
 222 #define L2_XS_nG        0x00000800      /* ARMv6 Not-Global */
 223
 224 /*
 225  * Access Permissions for L1 and L2 Descriptors.
 226  */
 227 #define AP_W            0x01            /* writable */
 228 #define AP_U            0x02            /* user */
 229
 230 /*
 231  * Short-hand for common AP_* constants.
 232  *
 233  * Note: These values assume the S (System) bit is set and
 234  * the R (ROM) bit is clear in CP15 register 1.
 235  */
 236 #define AP_KR           0x00            /* kernel read */
 237 #define AP_KRW          0x01            /* kernel read/write */
 238 #define AP_KRWUR        0x02            /* kernel read/write usr read */
 239 #define AP_KRWURW       0x03            /* kernel read/write usr read/write */
 240
 241 /*
 242  * Note: These values assume the S (System) and the R (ROM) bits are clear and
 243  * the XP (eXtended page table) bit is set in CP15 register 1.  ARMv6 only.
 244  */
 245 #define APX_KR(APX)     (APX|0x01)      /* kernel read */
 246 #define APX_KRUR(APX)   (APX|0x02)      /* kernel read user read */
 247 #define APX_KRW(APX)    (    0x01)      /* kernel read/write */
 248 #define APX_KRWUR(APX)  (    0x02)      /* kernel read/write user read */
 249 #define APX_KRWURW(APX) (    0x03)      /* kernel read/write user read/write */
 250
 251 /*
 252  * Domain Types for the Domain Access Control Register.
 253  */
 254 #define DOMAIN_FAULT    0x00            /* no access */
 255 #define DOMAIN_CLIENT   0x01            /* client */
 256 #define DOMAIN_RESERVED 0x02            /* reserved */
 257 #define DOMAIN_MANAGER  0x03            /* manager */
 258
 259 /*
 260  * Type Extension bits for XScale processors.
 261  *
 262  * Behavior of C and B when X == 0:
 263  *
 264  * C B  Cacheable  Bufferable  Write Policy  Line Allocate Policy
 265  * 0 0      N          N            -                 -
 266  * 0 1      N          Y            -                 -
 267  * 1 0      Y          Y       Write-through    Read Allocate
 268  * 1 1      Y          Y        Write-back      Read Allocate
 269  *
 270  * Behavior of C and B when X == 1:
 271  * C B  Cacheable  Bufferable  Write Policy  Line Allocate Policy
 272  * 0 0      -          -            -                 -           DO NOT USE
 273  * 0 1      N          Y            -                 -
 274  * 1 0  Mini-Data      -            -                 -
 275  * 1 1      Y          Y        Write-back       R/W Allocate
 276  */
 277 #define TEX_XSCALE_X    0x01            /* X modifies C and B */
 278
 279 #endif /* _ARM_PTE_H_ */