radio/src/targets/taranis/startup_stm32f40_41xxx.s

   1 /**
   2   ******************************************************************************
   3   * @file      startup_stm32f40_41xxx.s
   4   * @author    MCD Application Team
   5   * @version   V1.3.0
   6   * @date      08-November-2013
   7   * @brief     STM32F40xxx/41xxx Devices vector table for RIDE7 toolchain.
   8   *            This module performs:
   9   *                - Set the initial SP
  10   *                - Set the initial PC == Reset_Handler,
  11   *                - Set the vector table entries with the exceptions ISR address
  12   *                - Configure the clock system and the external SRAM mounted on
  13   *                  STM324xG-EVAL board to be used as data memory (optional,
  14   *                  to be enabled by user)
  15   *                - Branches to main in the C library (which eventually
  16   *                  calls main()).
  17   *            After Reset the Cortex-M4 processor is in Thread mode,
  18   *            priority is Privileged, and the Stack is set to Main.
  19   ******************************************************************************
  20   * @attention
  21   *
  22   * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
  23   *
  24   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
  25   * You may not use this file except in compliance with the License.
  26   * You may obtain a copy of the License at:
  27   *
  28   *        http://www.st.com/software_license_agreement_liberty_v2
  29   *
  30   * Unless required by applicable law or agreed to in writing, software
  31   * distributed under the License is distributed on an "AS IS" BASIS,
  32   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  33   * See the License for the specific language governing permissions and
  34   * limitations under the License.
  35   *
  36   ******************************************************************************
  37   */
  38
  39   .syntax unified
  40   .cpu cortex-m3
  41   .fpu softvfp
  42   .thumb
  43
  44 .global  g_pfnVectors
  45 .global  Default_Handler
  46
  47 /* start address for the initialization values of the .data section.
  48 defined in linker script */
  49 .word  _sidata
  50 /* start address for the .data section. defined in linker script */
  51 .word  _sdata
  52 /* end address for the .data section. defined in linker script */
  53 .word  _edata
  54 /* start address for the .bss section. defined in linker script */
  55 .word  _sbss
  56 /* end address for the .bss section. defined in linker script */
  57 .word  _ebss
  58 /* stack used for SystemInit_ExtMemCtl; always internal RAM used */
  59
  60 /**
  61  * @brief  This is the code that gets called when the processor first
  62  *          starts execution following a reset event. Only the absolutely
  63  *          necessary set is performed, after which the application
  64  *          supplied main() routine is called.
  65  * @param  None
  66  * @retval : None
  67 */
  68
  69     .section  .text.Reset_Handler
  70   .weak  Reset_Handler
  71   .type  Reset_Handler, %function
  72 Reset_Handler:
  73
  74   bl pwrResetHandler    /*jump to WDT reset handler where soft power control pin is turned on as soon as possible */
  75
  76 /* Copy the data segment initializers from flash to SRAM */
  77   movs  r1, #0
  78   b  LoopCopyDataInit
  79
  80 CopyDataInit:
  81   ldr  r3, =_sidata
  82   ldr  r3, [r3, r1]
  83   str  r3, [r0, r1]
  84   adds  r1, r1, #4
  85
  86 LoopCopyDataInit:
  87   ldr  r0, =_sdata
  88   ldr  r3, =_edata
  89   adds  r2, r0, r1
  90   cmp  r2, r3
  91   bcc  CopyDataInit
  92   ldr  r2, =_sbss
  93   b  LoopFillZerobss
  94 /* Zero fill the bss segment. */
  95 FillZerobss:
  96   movs  r3, #0
  97   str  r3, [r2], #4
  98
  99 LoopFillZerobss:
 100   ldr  r3, = _ebss
 101   cmp  r2, r3
 102   bcc  FillZerobss
 103
 104 /*Paint Main Stack */
 105   ldr  r2, = _main_stack_start
 106 PaintMainStack:
 107   movs r3, #0x55555555
 108   str  r3, [r2], #4
 109 LoopPaintMainStack:
 110   ldr  r3, = _estack
 111   cmp  r2, r3
 112   bcc  PaintMainStack
 113
 114 /* Call the clock system intitialization function.*/
 115   bl  SystemInit
 116
 117 /* Call C++ constructors for static objects */
 118   bl  __libc_init_array
 119
 120 /* Call the application's entry point.*/
 121   bl  main
 122   bx  lr
 123 .size  Reset_Handler, .-Reset_Handler
 124
 125 /**
 126  * @brief  This is the code that gets called when the processor receives an
 127  *         unexpected interrupt.  This simply enters an infinite loop, preserving
 128  *         the system state for examination by a debugger.
 129  * @param  None
 130  * @retval None
 131 */
 132     .section  .text.Default_Handler,"ax",%progbits
 133 Default_Handler:
 134 Infinite_Loop:
 135   b  Infinite_Loop
 136   .size  Default_Handler, .-Default_Handler
 137 /******************************************************************************
 138 *
 139 * The minimal vector table for a Cortex M3. Note that the proper constructs
 140 * must be placed on this to ensure that it ends up at physical address
 141 * 0x0000.0000.
 142 *
 143 *******************************************************************************/
 144    .section  .isr_vector,"a",%progbits
 145   .type  g_pfnVectors, %object
 146   .size  g_pfnVectors, .-g_pfnVectors
 147
 148
 149 g_pfnVectors:
 150   .word  _estack
 151   .word  Reset_Handler
 152   .word  NMI_Handler
 153   .word  HardFault_Handler
 154   .word  MemManage_Handler
 155   .word  BusFault_Handler
 156   .word  UsageFault_Handler
 157   .word  0
 158   .word  0
 159   .word  0
 160   .word  0
 161   .word  SVC_Handler
 162   .word  DebugMon_Handler
 163   .word  0
 164   .word  PendSV_Handler
 165   .word  SysTick_Handler
 166
 167   /* External Interrupts */
 168   .word     WWDG_IRQHandler                   /* Window WatchDog              */
 169   .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
 170   .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */
 171   .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */
 172   .word     FLASH_IRQHandler                  /* FLASH                        */
 173   .word     RCC_IRQHandler                    /* RCC                          */
 174   .word     EXTI0_IRQHandler                  /* EXTI Line0                   */
 175   .word     EXTI1_IRQHandler                  /* EXTI Line1                   */
 176   .word     EXTI2_IRQHandler                  /* EXTI Line2                   */
 177   .word     EXTI3_IRQHandler                  /* EXTI Line3                   */
 178   .word     EXTI4_IRQHandler                  /* EXTI Line4                   */
 179   .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */
 180   .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */
 181   .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */
 182   .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */
 183   .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */
 184   .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */
 185   .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */
 186   .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */
 187   .word     CAN1_TX_IRQHandler                /* CAN1 TX                      */
 188   .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                     */
 189   .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                     */
 190   .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                     */
 191   .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */
 192   .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */
 193   .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */
 194   .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */
 195   .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */
 196   .word     TIM2_IRQHandler                   /* TIM2                         */
 197   .word     TIM3_IRQHandler                   /* TIM3                         */
 198   .word     TIM4_IRQHandler                   /* TIM4                         */
 199   .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */
 200   .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */
 201   .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */
 202   .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */
 203   .word     SPI1_IRQHandler                   /* SPI1                         */
 204   .word     SPI2_IRQHandler                   /* SPI2                         */
 205   .word     USART1_IRQHandler                 /* USART1                       */
 206   .word     USART2_IRQHandler                 /* USART2                       */
 207   .word     USART3_IRQHandler                 /* USART3                       */
 208   .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */
 209   .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */
 210   .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */
 211   .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */
 212   .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */
 213   .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
 214   .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */
 215   .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */
 216   .word     FSMC_IRQHandler                   /* FSMC                         */
 217   .word     SDIO_IRQHandler                   /* SDIO                         */
 218   .word     TIM5_IRQHandler                   /* TIM5                         */
 219   .word     SPI3_IRQHandler                   /* SPI3                         */
 220   .word     UART4_IRQHandler                  /* UART4                        */
 221   .word     UART5_IRQHandler                  /* UART5                        */
 222   .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */
 223   .word     TIM7_IRQHandler                   /* TIM7                         */
 224   .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */
 225   .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */
 226   .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */
 227   .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */
 228   .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */
 229   .word     ETH_IRQHandler                    /* Ethernet                     */
 230   .word     ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */
 231   .word     CAN2_TX_IRQHandler                /* CAN2 TX                      */
 232   .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                     */
 233   .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                     */
 234   .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                     */
 235   .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */
 236   .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */
 237   .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */
 238   .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */
 239   .word     USART6_IRQHandler                 /* USART6                       */
 240   .word     I2C3_EV_IRQHandler                /* I2C3 event                   */
 241   .word     I2C3_ER_IRQHandler                /* I2C3 error                   */
 242   .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */
 243   .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */
 244   .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */
 245   .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */
 246   .word     DCMI_IRQHandler                   /* DCMI                         */
 247   .word     CRYP_IRQHandler                   /* CRYP crypto                  */
 248   .word     HASH_RNG_IRQHandler               /* Hash and Rng                 */
 249   .word     FPU_IRQHandler                    /* FPU                          */
 250
 251 /*******************************************************************************
 252 *
 253 * Provide weak aliases for each Exception handler to the Default_Handler.
 254 * As they are weak aliases, any function with the same name will override
 255 * this definition.
 256 *
 257 *******************************************************************************/
 258    .weak      NMI_Handler
 259    .thumb_set NMI_Handler,Default_Handler
 260
 261    .weak      HardFault_Handler
 262    .thumb_set HardFault_Handler,Default_Handler
 263
 264    .weak      MemManage_Handler
 265    .thumb_set MemManage_Handler,Default_Handler
 266
 267    .weak      BusFault_Handler
 268    .thumb_set BusFault_Handler,Default_Handler
 269
 270    .weak      UsageFault_Handler
 271    .thumb_set UsageFault_Handler,Default_Handler
 272
 273    .weak      SVC_Handler
 274    .thumb_set SVC_Handler,Default_Handler
 275
 276    .weak      DebugMon_Handler
 277    .thumb_set DebugMon_Handler,Default_Handler
 278
 279    .weak      PendSV_Handler
 280    .thumb_set PendSV_Handler,Default_Handler
 281
 282    .weak      SysTick_Handler
 283    .thumb_set SysTick_Handler,Default_Handler
 284
 285    .weak      WWDG_IRQHandler
 286    .thumb_set WWDG_IRQHandler,Default_Handler
 287
 288    .weak      PVD_IRQHandler
 289    .thumb_set PVD_IRQHandler,Default_Handler
 290
 291    .weak      TAMP_STAMP_IRQHandler
 292    .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
 293
 294    .weak      RTC_WKUP_IRQHandler
 295    .thumb_set RTC_WKUP_IRQHandler,Default_Handler
 296
 297    .weak      FLASH_IRQHandler
 298    .thumb_set FLASH_IRQHandler,Default_Handler
 299
 300    .weak      RCC_IRQHandler
 301    .thumb_set RCC_IRQHandler,Default_Handler
 302
 303    .weak      EXTI0_IRQHandler
 304    .thumb_set EXTI0_IRQHandler,Default_Handler
 305
 306    .weak      EXTI1_IRQHandler
 307    .thumb_set EXTI1_IRQHandler,Default_Handler
 308
 309    .weak      EXTI2_IRQHandler
 310    .thumb_set EXTI2_IRQHandler,Default_Handler
 311
 312    .weak      EXTI3_IRQHandler
 313    .thumb_set EXTI3_IRQHandler,Default_Handler
 314
 315    .weak      EXTI4_IRQHandler
 316    .thumb_set EXTI4_IRQHandler,Default_Handler
 317
 318    .weak      DMA1_Stream0_IRQHandler
 319    .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
 320
 321    .weak      DMA1_Stream1_IRQHandler
 322    .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
 323
 324    .weak      DMA1_Stream2_IRQHandler
 325    .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
 326
 327    .weak      DMA1_Stream3_IRQHandler
 328    .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
 329
 330    .weak      DMA1_Stream4_IRQHandler
 331    .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
 332
 333    .weak      DMA1_Stream5_IRQHandler
 334    .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
 335
 336    .weak      DMA1_Stream6_IRQHandler
 337    .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
 338
 339    .weak      ADC_IRQHandler
 340    .thumb_set ADC_IRQHandler,Default_Handler
 341
 342    .weak      CAN1_TX_IRQHandler
 343    .thumb_set CAN1_TX_IRQHandler,Default_Handler
 344
 345    .weak      CAN1_RX0_IRQHandler
 346    .thumb_set CAN1_RX0_IRQHandler,Default_Handler
 347
 348    .weak      CAN1_RX1_IRQHandler
 349    .thumb_set CAN1_RX1_IRQHandler,Default_Handler
 350
 351    .weak      CAN1_SCE_IRQHandler
 352    .thumb_set CAN1_SCE_IRQHandler,Default_Handler
 353
 354    .weak      EXTI9_5_IRQHandler
 355    .thumb_set EXTI9_5_IRQHandler,Default_Handler
 356
 357    .weak      TIM1_BRK_TIM9_IRQHandler
 358    .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
 359
 360    .weak      TIM1_UP_TIM10_IRQHandler
 361    .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
 362
 363    .weak      TIM1_TRG_COM_TIM11_IRQHandler
 364    .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
 365
 366    .weak      TIM1_CC_IRQHandler
 367    .thumb_set TIM1_CC_IRQHandler,Default_Handler
 368
 369    .weak      TIM2_IRQHandler
 370    .thumb_set TIM2_IRQHandler,Default_Handler
 371
 372    .weak      TIM3_IRQHandler
 373    .thumb_set TIM3_IRQHandler,Default_Handler
 374
 375    .weak      TIM4_IRQHandler
 376    .thumb_set TIM4_IRQHandler,Default_Handler
 377
 378    .weak      I2C1_EV_IRQHandler
 379    .thumb_set I2C1_EV_IRQHandler,Default_Handler
 380
 381    .weak      I2C1_ER_IRQHandler
 382    .thumb_set I2C1_ER_IRQHandler,Default_Handler
 383
 384    .weak      I2C2_EV_IRQHandler
 385    .thumb_set I2C2_EV_IRQHandler,Default_Handler
 386
 387    .weak      I2C2_ER_IRQHandler
 388    .thumb_set I2C2_ER_IRQHandler,Default_Handler
 389
 390    .weak      SPI1_IRQHandler
 391    .thumb_set SPI1_IRQHandler,Default_Handler
 392
 393    .weak      SPI2_IRQHandler
 394    .thumb_set SPI2_IRQHandler,Default_Handler
 395
 396    .weak      USART1_IRQHandler
 397    .thumb_set USART1_IRQHandler,Default_Handler
 398
 399    .weak      USART2_IRQHandler
 400    .thumb_set USART2_IRQHandler,Default_Handler
 401
 402    .weak      USART3_IRQHandler
 403    .thumb_set USART3_IRQHandler,Default_Handler
 404
 405    .weak      EXTI15_10_IRQHandler
 406    .thumb_set EXTI15_10_IRQHandler,Default_Handler
 407
 408    .weak      RTC_Alarm_IRQHandler
 409    .thumb_set RTC_Alarm_IRQHandler,Default_Handler
 410
 411    .weak      OTG_FS_WKUP_IRQHandler
 412    .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
 413
 414    .weak      TIM8_BRK_TIM12_IRQHandler
 415    .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
 416
 417    .weak      TIM8_UP_TIM13_IRQHandler
 418    .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
 419
 420    .weak      TIM8_TRG_COM_TIM14_IRQHandler
 421    .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
 422
 423    .weak      TIM8_CC_IRQHandler
 424    .thumb_set TIM8_CC_IRQHandler,Default_Handler
 425
 426    .weak      DMA1_Stream7_IRQHandler
 427    .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
 428
 429    .weak      FSMC_IRQHandler
 430    .thumb_set FSMC_IRQHandler,Default_Handler
 431
 432    .weak      SDIO_IRQHandler
 433    .thumb_set SDIO_IRQHandler,Default_Handler
 434
 435    .weak      TIM5_IRQHandler
 436    .thumb_set TIM5_IRQHandler,Default_Handler
 437
 438    .weak      SPI3_IRQHandler
 439    .thumb_set SPI3_IRQHandler,Default_Handler
 440
 441    .weak      UART4_IRQHandler
 442    .thumb_set UART4_IRQHandler,Default_Handler
 443
 444    .weak      UART5_IRQHandler
 445    .thumb_set UART5_IRQHandler,Default_Handler
 446
 447    .weak      TIM6_DAC_IRQHandler
 448    .thumb_set TIM6_DAC_IRQHandler,Default_Handler
 449
 450    .weak      TIM7_IRQHandler
 451    .thumb_set TIM7_IRQHandler,Default_Handler
 452
 453    .weak      DMA2_Stream0_IRQHandler
 454    .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
 455
 456    .weak      DMA2_Stream1_IRQHandler
 457    .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
 458
 459    .weak      DMA2_Stream2_IRQHandler
 460    .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
 461
 462    .weak      DMA2_Stream3_IRQHandler
 463    .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
 464
 465    .weak      DMA2_Stream4_IRQHandler
 466    .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
 467
 468    .weak      ETH_IRQHandler
 469    .thumb_set ETH_IRQHandler,Default_Handler
 470
 471    .weak      ETH_WKUP_IRQHandler
 472    .thumb_set ETH_WKUP_IRQHandler,Default_Handler
 473
 474    .weak      CAN2_TX_IRQHandler
 475    .thumb_set CAN2_TX_IRQHandler,Default_Handler
 476
 477    .weak      CAN2_RX0_IRQHandler
 478    .thumb_set CAN2_RX0_IRQHandler,Default_Handler
 479
 480    .weak      CAN2_RX1_IRQHandler
 481    .thumb_set CAN2_RX1_IRQHandler,Default_Handler
 482
 483    .weak      CAN2_SCE_IRQHandler
 484    .thumb_set CAN2_SCE_IRQHandler,Default_Handler
 485
 486    .weak      OTG_FS_IRQHandler
 487    .thumb_set OTG_FS_IRQHandler,Default_Handler
 488
 489    .weak      DMA2_Stream5_IRQHandler
 490    .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
 491
 492    .weak      DMA2_Stream6_IRQHandler
 493    .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
 494
 495    .weak      DMA2_Stream7_IRQHandler
 496    .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
 497
 498    .weak      USART6_IRQHandler
 499    .thumb_set USART6_IRQHandler,Default_Handler
 500
 501    .weak      I2C3_EV_IRQHandler
 502    .thumb_set I2C3_EV_IRQHandler,Default_Handler
 503
 504    .weak      I2C3_ER_IRQHandler
 505    .thumb_set I2C3_ER_IRQHandler,Default_Handler
 506
 507    .weak      OTG_HS_EP1_OUT_IRQHandler
 508    .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
 509
 510    .weak      OTG_HS_EP1_IN_IRQHandler
 511    .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
 512
 513    .weak      OTG_HS_WKUP_IRQHandler
 514    .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
 515
 516    .weak      OTG_HS_IRQHandler
 517    .thumb_set OTG_HS_IRQHandler,Default_Handler
 518
 519    .weak      DCMI_IRQHandler
 520    .thumb_set DCMI_IRQHandler,Default_Handler
 521
 522    .weak      CRYP_IRQHandler
 523    .thumb_set CRYP_IRQHandler,Default_Handler
 524
 525    .weak      HASH_RNG_IRQHandler
 526    .thumb_set HASH_RNG_IRQHandler,Default_Handler
 527
 528    .weak      FPU_IRQHandler
 529    .thumb_set FPU_IRQHandler,Default_Handler
 530
 531 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/