rtl/verilog/or1200_genpc.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  OR1200's generate PC                                        ////
   4 ////                                                              ////
   5 ////  This file is part of the OpenRISC 1200 project              ////
   6 ////  http://www.opencores.org/cores/or1k/                        ////
   7 ////                                                              ////
   8 ////  Description                                                 ////
   9 ////  PC, interface to IC.                                        ////
  10 ////                                                              ////
  11 ////  To Do:                                                      ////
  12 ////   - make it smaller and faster                               ////
  13 ////                                                              ////
  14 ////  Author(s):                                                  ////
  15 ////      - Damjan Lampret, lampret@opencores.org                 ////
  16 ////                                                              ////
  17 //////////////////////////////////////////////////////////////////////
  18 ////                                                              ////
  19 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
  20 ////                                                              ////
  21 //// This source file may be used and distributed without         ////
  22 //// restriction provided that this copyright statement is not    ////
  23 //// removed from the file and that any derivative work contains  ////
  24 //// the original copyright notice and the associated disclaimer. ////
  25 ////                                                              ////
  26 //// This source file is free software; you can redistribute it   ////
  27 //// and/or modify it under the terms of the GNU Lesser General   ////
  28 //// Public License as published by the Free Software Foundation; ////
  29 //// either version 2.1 of the License, or (at your option) any   ////
  30 //// later version.                                               ////
  31 ////                                                              ////
  32 //// This source is distributed in the hope that it will be       ////
  33 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  34 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  35 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  36 //// details.                                                     ////
  37 ////                                                              ////
  38 //// You should have received a copy of the GNU Lesser General    ////
  39 //// Public License along with this source; if not, download it   ////
  40 //// from http://www.opencores.org/lgpl.shtml                     ////
  41 ////                                                              ////
  42 //////////////////////////////////////////////////////////////////////
  43 //
  44 // CVS Revision History
  45 //
  46 // $Log$
  47 // Revision 1.6  2002/03/29 15:16:55  lampret
  48 // Some of the warnings fixed.
  49 //
  50 // Revision 1.5  2002/02/11 04:33:17  lampret
  51 // Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
  52 //
  53 // Revision 1.4  2002/01/28 01:16:00  lampret
  54 // Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
  55 //
  56 // Revision 1.3  2002/01/18 07:56:00  lampret
  57 // No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
  58 //
  59 // Revision 1.2  2002/01/14 06:18:22  lampret
  60 // Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
  61 //
  62 // Revision 1.1  2002/01/03 08:16:15  lampret
  63 // New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
  64 //
  65 // Revision 1.10  2001/11/20 18:46:15  simons
  66 // Break point bug fixed
  67 //
  68 // Revision 1.9  2001/11/18 09:58:28  lampret
  69 // Fixed some l.trap typos.
  70 //
  71 // Revision 1.8  2001/11/18 08:36:28  lampret
  72 // For GDB changed single stepping and disabled trap exception.
  73 //
  74 // Revision 1.7  2001/10/21 17:57:16  lampret
  75 // Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
  76 //
  77 // Revision 1.6  2001/10/14 13:12:09  lampret
  78 // MP3 version.
  79 //
  80 // Revision 1.1.1.1  2001/10/06 10:18:36  igorm
  81 // no message
  82 //
  83 // Revision 1.1  2001/08/09 13:39:33  lampret
  84 // Major clean-up.
  85 //
  86 //
  87
  88 // synopsys translate_off
  89 `include "timescale.v"
  90 // synopsys translate_on
  91 `include "or1200_defines.v"
  92
  93 module or1200_genpc(
  94         // Clock and reset
  95         clk, rst,
  96
  97         // External i/f to IC
  98         icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
  99         icpu_rty_i, icpu_adr_i,
 100
 101         // Internal i/f
 102         branch_op, except_type, except_prefix,
 103         branch_addrofs, lr_restor, flag, taken, except_start,
 104         binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
 105         genpc_freeze, no_more_dslot
 106 );
 107
 108 //
 109 // I/O
 110 //
 111
 112 //
 113 // Clock and reset
 114 //
 115 input                           clk;
 116 input                           rst;
 117
 118 //
 119 // External i/f to IC
 120 //
 121 output  [31:0]                  icpu_adr_o;
 122 output                          icpu_cycstb_o;
 123 output  [3:0]                   icpu_sel_o;
 124 output  [3:0]                   icpu_tag_o;
 125 input                           icpu_rty_i;
 126 input   [31:0]                  icpu_adr_i;
 127
 128 //
 129 // Internal i/f
 130 //
 131 input   [`OR1200_BRANCHOP_WIDTH-1:0]    branch_op;
 132 input   [`OR1200_EXCEPT_WIDTH-1:0]      except_type;
 133 input                                   except_prefix;
 134 input   [31:2]                  branch_addrofs;
 135 input   [31:0]                  lr_restor;
 136 input                           flag;
 137 output                          taken;
 138 input                           except_start;
 139 input   [31:2]                  binsn_addr;
 140 input   [31:0]                  epcr;
 141 input   [31:0]                  spr_dat_i;
 142 input                           spr_pc_we;
 143 input                           genpc_refetch;
 144 input                           genpc_freeze;
 145 input                           no_more_dslot;
 146
 147 //
 148 // Internal wires and regs
 149 //
 150 reg     [31:2]                  pcreg;
 151 reg     [31:0]                  pc;
 152 reg                             taken;  /* Set to in case of jump or taken branch */
 153
 154 //
 155 // Address of insn to be fecthed
 156 //
 157 assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
 158 // assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
 159
 160 //
 161 // Control access to IC subsystem
 162 //
 163 // assign icpu_cycstb_o = !genpc_freeze & !no_more_dslot;
 164 assign icpu_cycstb_o = !genpc_freeze;
 165 assign icpu_sel_o = 4'b1111;
 166 assign icpu_tag_o = `OR1200_ITAG_NI;
 167
 168 //
 169 // Async calculation of new PC value. This value is used for addressing the IC.
 170 //
 171 always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type
 172         or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
 173         casex ({spr_pc_we, except_start, branch_op})    // synopsys parallel_case
 174                 {2'b00, `OR1200_BRANCHOP_NOP}: begin
 175                         pc = {pcreg + 'd1, 2'b0};
 176                         taken = 1'b0;
 177                 end
 178                 {2'b00, `OR1200_BRANCHOP_J}: begin
 179 `ifdef OR1200_VERBOSE
 180 // synopsys translate_off
 181                         $display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs);
 182 // synopsys translate_on
 183 `endif
 184                         pc = {branch_addrofs, 2'b0};
 185                         taken = 1'b1;
 186                 end
 187                 {2'b00, `OR1200_BRANCHOP_JR}: begin
 188 `ifdef OR1200_VERBOSE
 189 // synopsys translate_off
 190                         $display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor);
 191 // synopsys translate_on
 192 `endif
 193                         pc = lr_restor;
 194                         taken = 1'b1;
 195                 end
 196                 {2'b00, `OR1200_BRANCHOP_BAL}: begin
 197 `ifdef OR1200_VERBOSE
 198 // synopsys translate_off
 199                         $display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
 200 // synopsys translate_on
 201 `endif
 202                         pc = {binsn_addr + branch_addrofs, 2'b0};
 203                         taken = 1'b1;
 204                 end
 205                 {2'b00, `OR1200_BRANCHOP_BF}:
 206                         if (flag) begin
 207 `ifdef OR1200_VERBOSE
 208 // synopsys translate_off
 209                                 $display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
 210 // synopsys translate_on
 211 `endif
 212                                 pc = {binsn_addr + branch_addrofs, 2'b0};
 213                                 taken = 1'b1;
 214                         end
 215                         else begin
 216 `ifdef OR1200_VERBOSE
 217 // synopsys translate_off
 218                                 $display("%t: BRANCHOP_BF: not taken", $time);
 219 // synopsys translate_on
 220 `endif
 221                                 pc = {pcreg + 'd1, 2'b0};
 222                                 taken = 1'b0;
 223                         end
 224                 {2'b00, `OR1200_BRANCHOP_BNF}:
 225                         if (flag) begin
 226                                 pc = {pcreg + 'd1, 2'b0};
 227 `ifdef OR1200_VERBOSE
 228 // synopsys translate_off
 229                                 $display("%t: BRANCHOP_BNF: not taken", $time);
 230 // synopsys translate_on
 231 `endif
 232                                 taken = 1'b0;
 233                         end
 234                         else begin
 235 `ifdef OR1200_VERBOSE
 236 // synopsys translate_off
 237                                 $display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
 238 // synopsys translate_on
 239 `endif
 240                                 pc = {binsn_addr + branch_addrofs, 2'b0};
 241                                 taken = 1'b1;
 242                         end
 243                 {2'b00, `OR1200_BRANCHOP_RFE}: begin
 244 `ifdef OR1200_VERBOSE
 245 // synopsys translate_off
 246                         $display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);
 247 // synopsys translate_on
 248 `endif
 249                         pc = epcr;
 250                         taken = 1'b1;
 251                 end
 252                 {2'b01, 3'bxxx}: begin
 253 `ifdef OR1200_VERBOSE
 254 // synopsys translate_off
 255                         $display("Starting exception: %h.", except_type);
 256 // synopsys translate_on
 257 `endif
 258                         pc = { {4{except_prefix}}, 16'h0000, except_type, 8'h00};
 259                         taken = 1'b1;
 260                 end
 261                 default: begin
 262 `ifdef OR1200_VERBOSE
 263 // synopsys translate_off
 264                         $display("l.mtspr writing into PC: %h.", spr_dat_i);
 265 // synopsys translate_on
 266 `endif
 267                         pc = spr_dat_i;
 268                         taken = 1'b0;
 269                 end
 270         endcase
 271 end
 272
 273 //
 274 // PC register
 275 //
 276 always @(posedge clk or posedge rst)
 277         if (rst)
 278                 pcreg <= #1 30'd63;
 279         else if (spr_pc_we)
 280                 pcreg <= #1 spr_dat_i[31:2];
 281         else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
 282 //      else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
 283                 pcreg <= #1 pc[31:2];
 284
 285 endmodule