rtl/verilog/or1200_genpc.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  OR1200's generate PC                                        ////
   4 ////                                                              ////
   5 ////  This file is part of the OpenRISC 1200 project              ////
   6 ////  http://www.opencores.org/cores/or1k/                        ////
   7 ////                                                              ////
   8 ////  Description                                                 ////
   9 ////  PC, interface to IC.                                        ////
  10 ////                                                              ////
  11 ////  To Do:                                                      ////
  12 ////   - make it smaller and faster                               ////
  13 ////                                                              ////
  14 ////  Author(s):                                                  ////
  15 ////      - Damjan Lampret, lampret@opencores.org                 ////
  16 ////                                                              ////
  17 //////////////////////////////////////////////////////////////////////
  18 ////                                                              ////
  19 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
  20 ////                                                              ////
  21 //// This source file may be used and distributed without         ////
  22 //// restriction provided that this copyright statement is not    ////
  23 //// removed from the file and that any derivative work contains  ////
  24 //// the original copyright notice and the associated disclaimer. ////
  25 ////                                                              ////
  26 //// This source file is free software; you can redistribute it   ////
  27 //// and/or modify it under the terms of the GNU Lesser General   ////
  28 //// Public License as published by the Free Software Foundation; ////
  29 //// either version 2.1 of the License, or (at your option) any   ////
  30 //// later version.                                               ////
  31 ////                                                              ////
  32 //// This source is distributed in the hope that it will be       ////
  33 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  34 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  35 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  36 //// details.                                                     ////
  37 ////                                                              ////
  38 //// You should have received a copy of the GNU Lesser General    ////
  39 //// Public License along with this source; if not, download it   ////
  40 //// from http://www.opencores.org/lgpl.shtml                     ////
  41 ////                                                              ////
  42 //////////////////////////////////////////////////////////////////////
  43 //
  44 // CVS Revision History
  45 //
  46 // $Log$
  47 // Revision 1.10  2004/06/08 18:17:36  lampret
  48 // Non-functional changes. Coding style fixes.
  49 //
  50 // Revision 1.9  2004/04/05 08:29:57  lampret
  51 // Merged branch_qmem into main tree.
  52 //
  53 // Revision 1.7.4.3  2003/12/17 13:43:38  simons
  54 // Exception prefix configuration changed.
  55 //
  56 // Revision 1.7.4.2  2003/12/04 23:44:31  lampret
  57 // Static exception prefix.
  58 //
  59 // Revision 1.7.4.1  2003/07/08 15:36:37  lampret
  60 // Added embedded memory QMEM.
  61 //
  62 // Revision 1.7  2003/04/20 22:23:57  lampret
  63 // No functional change. Only added customization for exception vectors.
  64 //
  65 // Revision 1.6  2002/03/29 15:16:55  lampret
  66 // Some of the warnings fixed.
  67 //
  68 // Revision 1.5  2002/02/11 04:33:17  lampret
  69 // Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
  70 //
  71 // Revision 1.4  2002/01/28 01:16:00  lampret
  72 // Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
  73 //
  74 // Revision 1.3  2002/01/18 07:56:00  lampret
  75 // No more low/high priority interrupts (PICPR removed). Added tick timer exception. Added exception prefix (SR[EPH]). Fixed single-step bug whenreading NPC.
  76 //
  77 // Revision 1.2  2002/01/14 06:18:22  lampret
  78 // Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
  79 //
  80 // Revision 1.1  2002/01/03 08:16:15  lampret
  81 // New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
  82 //
  83 // Revision 1.10  2001/11/20 18:46:15  simons
  84 // Break point bug fixed
  85 //
  86 // Revision 1.9  2001/11/18 09:58:28  lampret
  87 // Fixed some l.trap typos.
  88 //
  89 // Revision 1.8  2001/11/18 08:36:28  lampret
  90 // For GDB changed single stepping and disabled trap exception.
  91 //
  92 // Revision 1.7  2001/10/21 17:57:16  lampret
  93 // Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
  94 //
  95 // Revision 1.6  2001/10/14 13:12:09  lampret
  96 // MP3 version.
  97 //
  98 // Revision 1.1.1.1  2001/10/06 10:18:36  igorm
  99 // no message
 100 //
 101 // Revision 1.1  2001/08/09 13:39:33  lampret
 102 // Major clean-up.
 103 //
 104 //
 105
 106 // synopsys translate_off
 107 `include "timescale.v"
 108 // synopsys translate_on
 109 `include "or1200_defines.v"
 110
 111 module or1200_genpc(
 112         // Clock and reset
 113         clk, rst,
 114
 115         // External i/f to IC
 116         icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
 117         icpu_rty_i, icpu_adr_i,
 118
 119         // Internal i/f
 120         branch_op, except_type, except_prefix,
 121         branch_addrofs, lr_restor, flag, taken, except_start,
 122         binsn_addr, epcr, spr_dat_i, spr_pc_we, genpc_refetch,
 123         genpc_freeze, genpc_stop_prefetch, no_more_dslot
 124 );
 125
 126 //
 127 // I/O
 128 //
 129
 130 //
 131 // Clock and reset
 132 //
 133 input                           clk;
 134 input                           rst;
 135
 136 //
 137 // External i/f to IC
 138 //
 139 output  [31:0]                  icpu_adr_o;
 140 output                          icpu_cycstb_o;
 141 output  [3:0]                   icpu_sel_o;
 142 output  [3:0]                   icpu_tag_o;
 143 input                           icpu_rty_i;
 144 input   [31:0]                  icpu_adr_i;
 145
 146 //
 147 // Internal i/f
 148 //
 149 input   [`OR1200_BRANCHOP_WIDTH-1:0]    branch_op;
 150 input   [`OR1200_EXCEPT_WIDTH-1:0]      except_type;
 151 input                                   except_prefix;
 152 input   [31:2]                  branch_addrofs;
 153 input   [31:0]                  lr_restor;
 154 input                           flag;
 155 output                          taken;
 156 input                           except_start;
 157 input   [31:2]                  binsn_addr;
 158 input   [31:0]                  epcr;
 159 input   [31:0]                  spr_dat_i;
 160 input                           spr_pc_we;
 161 input                           genpc_refetch;
 162 input                           genpc_stop_prefetch;
 163 input                           genpc_freeze;
 164 input                           no_more_dslot;
 165
 166 //
 167 // Internal wires and regs
 168 //
 169 reg     [31:2]                  pcreg;
 170 reg     [31:0]                  pc;
 171 reg                             taken;  /* Set to in case of jump or taken branch */
 172 reg                             genpc_refetch_r;
 173
 174 //
 175 // Address of insn to be fecthed
 176 //
 177 assign icpu_adr_o = !no_more_dslot & !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
 178 // assign icpu_adr_o = !except_start & !spr_pc_we & (icpu_rty_i | genpc_refetch) ? icpu_adr_i : pc;
 179
 180 //
 181 // Control access to IC subsystem
 182 //
 183 // assign icpu_cycstb_o = !genpc_freeze & !no_more_dslot;
 184 assign icpu_cycstb_o = !genpc_freeze; // works, except remaining raised cycstb during long load/store
 185 //assign icpu_cycstb_o = !(genpc_freeze | genpc_refetch & genpc_refetch_r);
 186 //assign icpu_cycstb_o = !(genpc_freeze | genpc_stop_prefetch);
 187 assign icpu_sel_o = 4'b1111;
 188 assign icpu_tag_o = `OR1200_ITAG_NI;
 189
 190 //
 191 // genpc_freeze_r
 192 //
 193 always @(posedge clk or posedge rst)
 194         if (rst)
 195                 genpc_refetch_r <= #1 1'b0;
 196         else if (genpc_refetch)
 197                 genpc_refetch_r <= #1 1'b1;
 198         else
 199                 genpc_refetch_r <= #1 1'b0;
 200
 201 //
 202 // Async calculation of new PC value. This value is used for addressing the IC.
 203 //
 204 always @(pcreg or branch_addrofs or binsn_addr or flag or branch_op or except_type
 205         or except_start or lr_restor or epcr or spr_pc_we or spr_dat_i or except_prefix) begin
 206         casex ({spr_pc_we, except_start, branch_op})    // synopsys parallel_case
 207                 {2'b00, `OR1200_BRANCHOP_NOP}: begin
 208                         pc = {pcreg + 30'd1, 2'b0};
 209                         taken = 1'b0;
 210                 end
 211                 {2'b00, `OR1200_BRANCHOP_J}: begin
 212 `ifdef OR1200_VERBOSE
 213 // synopsys translate_off
 214                         $display("%t: BRANCHOP_J: pc <= branch_addrofs %h", $time, branch_addrofs);
 215 // synopsys translate_on
 216 `endif
 217                         pc = {branch_addrofs, 2'b0};
 218                         taken = 1'b1;
 219                 end
 220                 {2'b00, `OR1200_BRANCHOP_JR}: begin
 221 `ifdef OR1200_VERBOSE
 222 // synopsys translate_off
 223                         $display("%t: BRANCHOP_JR: pc <= lr_restor %h", $time, lr_restor);
 224 // synopsys translate_on
 225 `endif
 226                         pc = lr_restor;
 227                         taken = 1'b1;
 228                 end
 229                 {2'b00, `OR1200_BRANCHOP_BAL}: begin
 230 `ifdef OR1200_VERBOSE
 231 // synopsys translate_off
 232                         $display("%t: BRANCHOP_BAL: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
 233 // synopsys translate_on
 234 `endif
 235                         pc = {binsn_addr + branch_addrofs, 2'b0};
 236                         taken = 1'b1;
 237                 end
 238                 {2'b00, `OR1200_BRANCHOP_BF}:
 239                         if (flag) begin
 240 `ifdef OR1200_VERBOSE
 241 // synopsys translate_off
 242                                 $display("%t: BRANCHOP_BF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
 243 // synopsys translate_on
 244 `endif
 245                                 pc = {binsn_addr + branch_addrofs, 2'b0};
 246                                 taken = 1'b1;
 247                         end
 248                         else begin
 249 `ifdef OR1200_VERBOSE
 250 // synopsys translate_off
 251                                 $display("%t: BRANCHOP_BF: not taken", $time);
 252 // synopsys translate_on
 253 `endif
 254                                 pc = {pcreg + 30'd1, 2'b0};
 255                                 taken = 1'b0;
 256                         end
 257                 {2'b00, `OR1200_BRANCHOP_BNF}:
 258                         if (flag) begin
 259                                 pc = {pcreg + 30'd1, 2'b0};
 260 `ifdef OR1200_VERBOSE
 261 // synopsys translate_off
 262                                 $display("%t: BRANCHOP_BNF: not taken", $time);
 263 // synopsys translate_on
 264 `endif
 265                                 taken = 1'b0;
 266                         end
 267                         else begin
 268 `ifdef OR1200_VERBOSE
 269 // synopsys translate_off
 270                                 $display("%t: BRANCHOP_BNF: pc %h = binsn_addr %h + branch_addrofs %h", $time, binsn_addr + branch_addrofs, binsn_addr, branch_addrofs);
 271 // synopsys translate_on
 272 `endif
 273                                 pc = {binsn_addr + branch_addrofs, 2'b0};
 274                                 taken = 1'b1;
 275                         end
 276                 {2'b00, `OR1200_BRANCHOP_RFE}: begin
 277 `ifdef OR1200_VERBOSE
 278 // synopsys translate_off
 279                         $display("%t: BRANCHOP_RFE: pc <= epcr %h", $time, epcr);
 280 // synopsys translate_on
 281 `endif
 282                         pc = epcr;
 283                         taken = 1'b1;
 284                 end
 285                 {2'b01, 3'bxxx}: begin
 286 `ifdef OR1200_VERBOSE
 287 // synopsys translate_off
 288                         $display("Starting exception: %h.", except_type);
 289 // synopsys translate_on
 290 `endif
 291                         pc = {(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), except_type, `OR1200_EXCEPT_V};
 292                         taken = 1'b1;
 293                 end
 294                 default: begin
 295 `ifdef OR1200_VERBOSE
 296 // synopsys translate_off
 297                         $display("l.mtspr writing into PC: %h.", spr_dat_i);
 298 // synopsys translate_on
 299 `endif
 300                         pc = spr_dat_i;
 301                         taken = 1'b0;
 302                 end
 303         endcase
 304 end
 305
 306 //
 307 // PC register
 308 //
 309 always @(posedge clk or posedge rst)
 310         if (rst)
 311 //              pcreg <= #1 30'd63;
 312                 pcreg <= #1 ({(except_prefix ? `OR1200_EXCEPT_EPH1_P : `OR1200_EXCEPT_EPH0_P), `OR1200_EXCEPT_RESET, `OR1200_EXCEPT_V} - 1) >> 2;
 313         else if (spr_pc_we)
 314                 pcreg <= #1 spr_dat_i[31:2];
 315         else if (no_more_dslot | except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
 316 //      else if (except_start | !genpc_freeze & !icpu_rty_i & !genpc_refetch)
 317                 pcreg <= #1 pc[31:2];
 318
 319 endmodule