rtl/verilog/or1200_spram_1024x32.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  Generic Single-Port Synchronous RAM                         ////
   4 ////                                                              ////
   5 ////  This file is part of memory library available from          ////
   6 ////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
   7 ////                                                              ////
   8 ////  Description                                                 ////
   9 ////  This block is a wrapper with common single-port             ////
  10 ////  synchronous memory interface for different                  ////
  11 ////  types of ASIC and FPGA RAMs. Beside universal memory        ////
  12 ////  interface it also provides behavioral model of generic      ////
  13 ////  single-port synchronous RAM.                                ////
  14 ////  It should be used in all OPENCORES designs that want to be  ////
  15 ////  portable accross different target technologies and          ////
  16 ////  independent of target memory.                               ////
  17 ////                                                              ////
  18 ////  Supported ASIC RAMs are:                                    ////
  19 ////  - Artisan Single-Port Sync RAM                              ////
  20 ////  - Avant! Two-Port Sync RAM (*)                              ////
  21 ////  - Virage Single-Port Sync RAM                               ////
  22 ////  - Virtual Silicon Single-Port Sync RAM                      ////
  23 ////                                                              ////
  24 ////  Supported FPGA RAMs are:                                    ////
  25 ////  - Xilinx Virtex RAMB4_S16                                   ////
  26 ////  - Altera LPM                                                ////
  27 ////                                                              ////
  28 ////  To Do:                                                      ////
  29 ////   - xilinx rams need external tri-state logic                ////
  30 ////   - fix avant! two-port ram                                  ////
  31 ////   - add additional RAMs                                      ////
  32 ////                                                              ////
  33 ////  Author(s):                                                  ////
  34 ////      - Damjan Lampret, lampret@opencores.org                 ////
  35 ////                                                              ////
  36 //////////////////////////////////////////////////////////////////////
  37 ////                                                              ////
  38 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
  39 ////                                                              ////
  40 //// This source file may be used and distributed without         ////
  41 //// restriction provided that this copyright statement is not    ////
  42 //// removed from the file and that any derivative work contains  ////
  43 //// the original copyright notice and the associated disclaimer. ////
  44 ////                                                              ////
  45 //// This source file is free software; you can redistribute it   ////
  46 //// and/or modify it under the terms of the GNU Lesser General   ////
  47 //// Public License as published by the Free Software Foundation; ////
  48 //// either version 2.1 of the License, or (at your option) any   ////
  49 //// later version.                                               ////
  50 ////                                                              ////
  51 //// This source is distributed in the hope that it will be       ////
  52 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  53 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  54 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  55 //// details.                                                     ////
  56 ////                                                              ////
  57 //// You should have received a copy of the GNU Lesser General    ////
  58 //// Public License along with this source; if not, download it   ////
  59 //// from http://www.opencores.org/lgpl.shtml                     ////
  60 ////                                                              ////
  61 //////////////////////////////////////////////////////////////////////
  62 //
  63 // CVS Revision History
  64 //
  65 // $Log$
  66 // Revision 1.8  2004/06/08 18:15:32  lampret
  67 // Changed behavior of the simulation generic models
  68 //
  69 // Revision 1.7  2004/04/05 08:29:57  lampret
  70 // Merged branch_qmem into main tree.
  71 //
  72 // Revision 1.3.4.2  2003/12/09 11:46:48  simons
  73 // Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
  74 //
  75 // Revision 1.3.4.1  2003/07/08 15:36:37  lampret
  76 // Added embedded memory QMEM.
  77 //
  78 // Revision 1.3  2003/04/07 01:19:07  lampret
  79 // Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
  80 //
  81 // Revision 1.2  2002/10/17 20:04:40  lampret
  82 // Added BIST scan. Special VS RAMs need to be used to implement BIST.
  83 //
  84 // Revision 1.1  2002/01/03 08:16:15  lampret
  85 // New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
  86 //
  87 // Revision 1.8  2001/11/02 18:57:14  lampret
  88 // Modified virtual silicon instantiations.
  89 //
  90 // Revision 1.7  2001/10/21 17:57:16  lampret
  91 // Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
  92 //
  93 // Revision 1.6  2001/10/14 13:12:09  lampret
  94 // MP3 version.
  95 //
  96 // Revision 1.1.1.1  2001/10/06 10:18:36  igorm
  97 // no message
  98 //
  99 // Revision 1.1  2001/08/09 13:39:33  lampret
 100 // Major clean-up.
 101 //
 102 // Revision 1.2  2001/07/30 05:38:02  lampret
 103 // Adding empty directories required by HDL coding guidelines
 104 //
 105 //
 106
 107 // synopsys translate_off
 108 `include "timescale.v"
 109 // synopsys translate_on
 110 `include "or1200_defines.v"
 111
 112 module or1200_spram_1024x32(
 113 `ifdef OR1200_BIST
 114         // RAM BIST
 115         mbist_si_i, mbist_so_o, mbist_ctrl_i,
 116 `endif
 117         // Generic synchronous single-port RAM interface
 118         clk, rst, ce, we, oe, addr, di, doq
 119 );
 120
 121 //
 122 // Default address and data buses width
 123 //
 124 parameter aw = 10;
 125 parameter dw = 32;
 126
 127 `ifdef OR1200_BIST
 128 //
 129 // RAM BIST
 130 //
 131 input mbist_si_i;
 132 input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
 133 output mbist_so_o;
 134 `endif
 135
 136 //
 137 // Generic synchronous single-port RAM interface
 138 //
 139 input                   clk;    // Clock
 140 input                   rst;    // Reset
 141 input                   ce;     // Chip enable input
 142 input                   we;     // Write enable input
 143 input                   oe;     // Output enable input
 144 input   [aw-1:0]        addr;   // address bus inputs
 145 input   [dw-1:0]        di;     // input data bus
 146 output  [dw-1:0]        doq;    // output data bus
 147
 148 //
 149 // Internal wires and registers
 150 //
 151
 152 `ifdef OR1200_ARTISAN_SSP
 153 `else
 154 `ifdef OR1200_VIRTUALSILICON_SSP
 155 `else
 156 `ifdef OR1200_BIST
 157 assign mbist_so_o = mbist_si_i;
 158 `endif
 159 `endif
 160 `endif
 161
 162 `ifdef OR1200_ARTISAN_SSP
 163
 164 //
 165 // Instantiation of ASIC memory:
 166 //
 167 // Artisan Synchronous Single-Port RAM (ra1sh)
 168 //
 169 `ifdef UNUSED
 170 art_hssp_1024x32 #(dw, 1<<aw, aw) artisan_ssp(
 171 `else
 172 `ifdef OR1200_BIST
 173 art_hssp_1024x32_bist artisan_ssp(
 174 `else
 175 art_hssp_1024x32 artisan_ssp(
 176 `endif
 177 `endif
 178 `ifdef OR1200_BIST
 179         // RAM BIST
 180         .mbist_si_i(mbist_si_i),
 181         .mbist_so_o(mbist_so_o),
 182         .mbist_ctrl_i(mbist_ctrl_i),
 183 `endif
 184         .CLK(clk),
 185         .CEN(~ce),
 186         .WEN(~we),
 187         .A(addr),
 188         .D(di),
 189         .OEN(~oe),
 190         .Q(doq)
 191 );
 192
 193 `else
 194
 195 `ifdef OR1200_AVANT_ATP
 196
 197 //
 198 // Instantiation of ASIC memory:
 199 //
 200 // Avant! Asynchronous Two-Port RAM
 201 //
 202 avant_atp avant_atp(
 203         .web(~we),
 204         .reb(),
 205         .oeb(~oe),
 206         .rcsb(),
 207         .wcsb(),
 208         .ra(addr),
 209         .wa(addr),
 210         .di(di),
 211         .doq(doq)
 212 );
 213
 214 `else
 215
 216 `ifdef OR1200_VIRAGE_SSP
 217
 218 //
 219 // Instantiation of ASIC memory:
 220 //
 221 // Virage Synchronous 1-port R/W RAM
 222 //
 223 virage_ssp virage_ssp(
 224         .clk(clk),
 225         .adr(addr),
 226         .d(di),
 227         .we(we),
 228         .oe(oe),
 229         .me(ce),
 230         .q(doq)
 231 );
 232
 233 `else
 234
 235 `ifdef OR1200_VIRTUALSILICON_SSP
 236
 237 //
 238 // Instantiation of ASIC memory:
 239 //
 240 // Virtual Silicon Single-Port Synchronous SRAM
 241 //
 242 `ifdef UNUSED
 243 vs_hdsp_1024x32 #(1<<aw, aw-1, dw-1) vs_ssp(
 244 `else
 245 `ifdef OR1200_BIST
 246 vs_hdsp_1024x32_bist vs_ssp(
 247 `else
 248 vs_hdsp_1024x32 vs_ssp(
 249 `endif
 250 `endif
 251 `ifdef OR1200_BIST
 252         // RAM BIST
 253         .mbist_si_i(mbist_si_i),
 254         .mbist_so_o(mbist_so_o),
 255         .mbist_ctrl_i(mbist_ctrl_i),
 256 `endif
 257         .CK(clk),
 258         .ADR(addr),
 259         .DI(di),
 260         .WEN(~we),
 261         .CEN(~ce),
 262         .OEN(~oe),
 263         .DOUT(doq)
 264 );
 265
 266 `else
 267
 268 `ifdef OR1200_XILINX_RAMB4
 269
 270 //
 271 // Instantiation of FPGA memory:
 272 //
 273 // Virtex/Spartan2
 274 //
 275
 276 //
 277 // Block 0
 278 //
 279 RAMB4_S4 ramb4_s4_0(
 280         .CLK(clk),
 281         .RST(rst),
 282         .ADDR(addr),
 283         .DI(di[3:0]),
 284         .EN(ce),
 285         .WE(we),
 286         .DO(doq[3:0])
 287 );
 288
 289 //
 290 // Block 1
 291 //
 292 RAMB4_S4 ramb4_s4_1(
 293         .CLK(clk),
 294         .RST(rst),
 295         .ADDR(addr),
 296         .DI(di[7:4]),
 297         .EN(ce),
 298         .WE(we),
 299         .DO(doq[7:4])
 300 );
 301
 302 //
 303 // Block 2
 304 //
 305 RAMB4_S4 ramb4_s4_2(
 306         .CLK(clk),
 307         .RST(rst),
 308         .ADDR(addr),
 309         .DI(di[11:8]),
 310         .EN(ce),
 311         .WE(we),
 312         .DO(doq[11:8])
 313 );
 314
 315 //
 316 // Block 3
 317 //
 318 RAMB4_S4 ramb4_s4_3(
 319         .CLK(clk),
 320         .RST(rst),
 321         .ADDR(addr),
 322         .DI(di[15:12]),
 323         .EN(ce),
 324         .WE(we),
 325         .DO(doq[15:12])
 326 );
 327
 328 //
 329 // Block 4
 330 //
 331 RAMB4_S4 ramb4_s4_4(
 332         .CLK(clk),
 333         .RST(rst),
 334         .ADDR(addr),
 335         .DI(di[19:16]),
 336         .EN(ce),
 337         .WE(we),
 338         .DO(doq[19:16])
 339 );
 340
 341 //
 342 // Block 5
 343 //
 344 RAMB4_S4 ramb4_s4_5(
 345         .CLK(clk),
 346         .RST(rst),
 347         .ADDR(addr),
 348         .DI(di[23:20]),
 349         .EN(ce),
 350         .WE(we),
 351         .DO(doq[23:20])
 352 );
 353
 354 //
 355 // Block 6
 356 //
 357 RAMB4_S4 ramb4_s4_6(
 358         .CLK(clk),
 359         .RST(rst),
 360         .ADDR(addr),
 361         .DI(di[27:24]),
 362         .EN(ce),
 363         .WE(we),
 364         .DO(doq[27:24])
 365 );
 366
 367 //
 368 // Block 7
 369 //
 370 RAMB4_S4 ramb4_s4_7(
 371         .CLK(clk),
 372         .RST(rst),
 373         .ADDR(addr),
 374         .DI(di[31:28]),
 375         .EN(ce),
 376         .WE(we),
 377         .DO(doq[31:28])
 378 );
 379
 380 `else
 381
 382 `ifdef OR1200_ALTERA_LPM
 383
 384 //
 385 // Instantiation of FPGA memory:
 386 //
 387 // Altera LPM
 388 //
 389 // Added By Jamil Khatib
 390 //
 391
 392 wire    wr;
 393
 394 assign  wr = ce & we;
 395
 396 initial $display("Using Altera LPM.");
 397
 398 lpm_ram_dq lpm_ram_dq_component (
 399         .address(addr),
 400         .inclock(clk),
 401         .outclock(clk),
 402         .data(di),
 403         .we(wr),
 404         .q(doq)
 405 );
 406
 407 defparam lpm_ram_dq_component.lpm_width = dw,
 408         lpm_ram_dq_component.lpm_widthad = aw,
 409         lpm_ram_dq_component.lpm_indata = "REGISTERED",
 410         lpm_ram_dq_component.lpm_address_control = "REGISTERED",
 411         lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
 412         lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
 413         // examplar attribute lpm_ram_dq_component NOOPT TRUE
 414
 415 `else
 416
 417 //
 418 // Generic single-port synchronous RAM model
 419 //
 420
 421 //
 422 // Generic RAM's registers and wires
 423 //
 424 reg     [dw-1:0]        mem [(1<<aw)-1:0];      // RAM content
 425 reg     [aw-1:0]        addr_reg;               // RAM address register
 426
 427 //
 428 // Data output drivers
 429 //
 430 assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
 431
 432 //
 433 // RAM address register
 434 //
 435 always @(posedge clk or posedge rst)
 436         if (rst)
 437                 addr_reg <= #1 {aw{1'b0}};
 438         else if (ce)
 439                 addr_reg <= #1 addr;
 440
 441 //
 442 // RAM write
 443 //
 444 always @(posedge clk)
 445         if (ce && we)
 446                 mem[addr] <= #1 di;
 447
 448 `endif  // !OR1200_ALTERA_LPM
 449 `endif  // !OR1200_XILINX_RAMB4_S16
 450 `endif  // !OR1200_VIRTUALSILICON_SSP
 451 `endif  // !OR1200_VIRAGE_SSP
 452 `endif  // !OR1200_AVANT_ATP
 453 `endif  // !OR1200_ARTISAN_SSP
 454
 455 endmodule