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(parent: d101279) | patch

commit	670dd00c11bf030fc7226768be1612419bc70f22
author	lampret <lampret>
	Tue, 8 Jun 2004 18:15:32 +0000 (8 18:15 +0000)
committer	lampret <lampret>
	Tue, 8 Jun 2004 18:15:32 +0000 (8 18:15 +0000)
tree	44f1dce94ecd1c36adea1de04671d7aeff827927	tree \| snapshot (tar.gz zip)
parent	d101279dd18ed93c9a2ea1d9e2de12ccfe61e34d	commit \| diff

Changed behavior of the simulation generic models

15 files changed:

rtl/verilog/or1200_dpram_32x32.v		diff \| blob \| blame \| history
rtl/verilog/or1200_spram_1024x32.v		diff \| blob \| blame \| history
rtl/verilog/or1200_spram_1024x32_bw.v		diff \| blob \| blame \| history
rtl/verilog/or1200_spram_1024x8.v		diff \| blob \| blame \| history
rtl/verilog/or1200_spram_128x32.v		diff \| blob \| blame \| history
rtl/verilog/or1200_spram_2048x32.v		diff \| blob \| blame \| history
rtl/verilog/or1200_spram_2048x32_bw.v		diff \| blob \| blame \| history
rtl/verilog/or1200_spram_2048x8.v		diff \| blob \| blame \| history
rtl/verilog/or1200_spram_256x21.v		diff \| blob \| blame \| history
rtl/verilog/or1200_spram_32x24.v		diff \| blob \| blame \| history
rtl/verilog/or1200_spram_512x20.v		diff \| blob \| blame \| history
rtl/verilog/or1200_spram_64x14.v		diff \| blob \| blame \| history
rtl/verilog/or1200_spram_64x22.v		diff \| blob \| blame \| history
rtl/verilog/or1200_spram_64x24.v		diff \| blob \| blame \| history
rtl/verilog/or1200_tpram_32x32.v		diff \| blob \| blame \| history

32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities