rtl/verilog/or1200_spram_32x24.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  Generic Single-Port Synchronous RAM                         ////
   4 ////                                                              ////
   5 ////  This file is part of memory library available from          ////
   6 ////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
   7 ////                                                              ////
   8 ////  Description                                                 ////
   9 ////  This block is a wrapper with common single-port             ////
  10 ////  synchronous memory interface for different                  ////
  11 ////  types of ASIC and FPGA RAMs. Beside universal memory        ////
  12 ////  interface it also provides behavioral model of generic      ////
  13 ////  single-port synchronous RAM.                                ////
  14 ////  It should be used in all OPENCORES designs that want to be  ////
  15 ////  portable accross different target technologies and          ////
  16 ////  independent of target memory.                               ////
  17 ////                                                              ////
  18 ////  Supported ASIC RAMs are:                                    ////
  19 ////  - Artisan Single-Port Sync RAM                              ////
  20 ////  - Avant! Two-Port Sync RAM (*)                              ////
  21 ////  - Virage Single-Port Sync RAM                               ////
  22 ////  - Virtual Silicon Single-Port Sync RAM                      ////
  23 ////                                                              ////
  24 ////  Supported FPGA RAMs are:                                    ////
  25 ////  - Xilinx Virtex RAMB4_S16                                   ////
  26 ////  - Altera LPM                                                ////
  27 ////                                                              ////
  28 ////  To Do:                                                      ////
  29 ////   - xilinx rams need external tri-state logic                ////
  30 ////   - fix avant! two-port ram                                  ////
  31 ////   - add additional RAMs                                      ////
  32 ////                                                              ////
  33 ////  Author(s):                                                  ////
  34 ////      - Damjan Lampret, lampret@opencores.org                 ////
  35 ////                                                              ////
  36 //////////////////////////////////////////////////////////////////////
  37 ////                                                              ////
  38 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
  39 ////                                                              ////
  40 //// This source file may be used and distributed without         ////
  41 //// restriction provided that this copyright statement is not    ////
  42 //// removed from the file and that any derivative work contains  ////
  43 //// the original copyright notice and the associated disclaimer. ////
  44 ////                                                              ////
  45 //// This source file is free software; you can redistribute it   ////
  46 //// and/or modify it under the terms of the GNU Lesser General   ////
  47 //// Public License as published by the Free Software Foundation; ////
  48 //// either version 2.1 of the License, or (at your option) any   ////
  49 //// later version.                                               ////
  50 ////                                                              ////
  51 //// This source is distributed in the hope that it will be       ////
  52 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  53 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  54 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  55 //// details.                                                     ////
  56 ////                                                              ////
  57 //// You should have received a copy of the GNU Lesser General    ////
  58 //// Public License along with this source; if not, download it   ////
  59 //// from http://www.opencores.org/lgpl.shtml                     ////
  60 ////                                                              ////
  61 //////////////////////////////////////////////////////////////////////
  62 //
  63 // CVS Revision History
  64 //
  65 // $Log$
  66 // Revision 1.2  2004/06/08 18:15:32  lampret
  67 // Changed behavior of the simulation generic models
  68 //
  69 // Revision 1.1  2004/04/08 11:00:46  simont
  70 // Add support for 512B instruction cache.
  71 //
  72 //
  73 //
  74
  75 // synopsys translate_off
  76 `include "timescale.v"
  77 // synopsys translate_on
  78 `include "or1200_defines.v"
  79
  80 module or1200_spram_32x24(
  81 `ifdef OR1200_BIST
  82         // RAM BIST
  83         mbist_si_i, mbist_so_o, mbist_ctrl_i,
  84 `endif
  85         // Generic synchronous single-port RAM interface
  86         clk, rst, ce, we, oe, addr, di, doq
  87 );
  88
  89 //
  90 // Default address and data buses width
  91 //
  92 parameter aw = 5;
  93 parameter dw = 24;
  94
  95 `ifdef OR1200_BIST
  96 //
  97 // RAM BIST
  98 //
  99 input mbist_si_i;
 100 input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
 101 output mbist_so_o;
 102 `endif
 103
 104 //
 105 // Generic synchronous single-port RAM interface
 106 //
 107 input                   clk;    // Clock
 108 input                   rst;    // Reset
 109 input                   ce;     // Chip enable input
 110 input                   we;     // Write enable input
 111 input                   oe;     // Output enable input
 112 input   [aw-1:0]        addr;   // address bus inputs
 113 input   [dw-1:0]        di;     // input data bus
 114 output  [dw-1:0]        doq;    // output data bus
 115
 116 //
 117 // Internal wires and registers
 118 //
 119 wire [31:24] unconnected;
 120
 121 `ifdef OR1200_ARTISAN_SSP
 122 `else
 123 `ifdef OR1200_VIRTUALSILICON_SSP
 124 `else
 125 `ifdef OR1200_BIST
 126 `endif
 127 `endif
 128 `endif
 129
 130 `ifdef OR1200_ARTISAN_SSP
 131
 132 //
 133 // Instantiation of ASIC memory:
 134 //
 135 // Artisan Synchronous Single-Port RAM (ra1sh)
 136 //
 137 `ifdef UNUSED
 138 `else
 139 `ifdef OR1200_BIST
 140 `else
 141 `endif
 142 `endif
 143 `ifdef OR1200_BIST
 144         // RAM BIST
 145 `endif
 146
 147 `else
 148
 149 `ifdef OR1200_AVANT_ATP
 150
 151 //
 152 // Instantiation of ASIC memory:
 153 //
 154 // Avant! Asynchronous Two-Port RAM
 155 //
 156
 157 `else
 158
 159 `ifdef OR1200_VIRAGE_SSP
 160
 161 //
 162 // Instantiation of ASIC memory:
 163 //
 164 // Virage Synchronous 1-port R/W RAM
 165 //
 166
 167 `else
 168
 169 `ifdef OR1200_VIRTUALSILICON_SSP
 170
 171 //
 172 // Instantiation of ASIC memory:
 173 //
 174 // Virtual Silicon Single-Port Synchronous SRAM
 175 //
 176 `ifdef UNUSED
 177 `else
 178 `ifdef OR1200_BIST
 179 `else
 180 `endif
 181 `endif
 182 `ifdef OR1200_BIST
 183         // RAM BIST
 184 `endif
 185
 186 `else
 187
 188 `ifdef OR1200_XILINX_RAMB4
 189
 190 //
 191 // Instantiation of FPGA memory:
 192 //
 193 // Virtex/Spartan2
 194 //
 195
 196 //
 197 // Block 0
 198 //
 199 RAMB4_S16 ramb4_s16_0(
 200         .CLK(clk),
 201         .RST(rst),
 202         .ADDR({3'h0, addr}),
 203         .DI(di[15:0]),
 204         .EN(ce),
 205         .WE(we),
 206         .DO(doq[15:0])
 207 );
 208
 209 //
 210 // Block 1
 211 //
 212 RAMB4_S16 ramb4_s16_1(
 213         .CLK(clk),
 214         .RST(rst),
 215         .ADDR({3'h0, addr}),
 216         .DI({8'h00, di[23:16]}),
 217         .EN(ce),
 218         .WE(we),
 219         .DO({unconnected, doq[23:16]})
 220 );
 221
 222 `else
 223
 224 `ifdef OR1200_ALTERA_LPM
 225
 226 //
 227 // Instantiation of FPGA memory:
 228 //
 229 // Altera LPM
 230 //
 231 // Added By Jamil Khatib
 232 //
 233
 234
 235 `else
 236
 237 //
 238 // Generic single-port synchronous RAM model
 239 //
 240
 241 //
 242 // Generic RAM's registers and wires
 243 //
 244 reg     [dw-1:0]        mem [(1<<aw)-1:0];      // RAM content
 245 reg     [aw-1:0]        addr_reg;               // RAM address register
 246
 247 //
 248 // Data output drivers
 249 //
 250 assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
 251
 252 //
 253 // RAM address register
 254 //
 255 always @(posedge clk or posedge rst)
 256         if (rst)
 257                 addr_reg <= #1 {aw{1'b0}};
 258         else if (ce)
 259                 addr_reg <= #1 addr;
 260
 261 //
 262 // RAM write
 263 //
 264 always @(posedge clk)
 265         if (ce && we)
 266                 mem[addr] <= #1 di;
 267
 268 `endif  // !OR1200_ALTERA_LPM
 269 `endif  // !OR1200_XILINX_RAMB4_S16
 270 `endif  // !OR1200_VIRTUALSILICON_SSP
 271 `endif  // !OR1200_VIRAGE_SSP
 272 `endif  // !OR1200_AVANT_ATP
 273 `endif  // !OR1200_ARTISAN_SSP
 274
 275 endmodule