rtl/verilog/or1200_freeze.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  OR1200's Freeze logic                                       ////
   4 ////                                                              ////
   5 ////  This file is part of the OpenRISC 1200 project              ////
   6 ////  http://www.opencores.org/cores/or1k/                        ////
   7 ////                                                              ////
   8 ////  Description                                                 ////
   9 ////  Generates all freezes and stalls inside RISC                ////
  10 ////                                                              ////
  11 ////  To Do:                                                      ////
  12 ////   - make it smaller and faster                               ////
  13 ////                                                              ////
  14 ////  Author(s):                                                  ////
  15 ////      - Damjan Lampret, lampret@opencores.org                 ////
  16 ////                                                              ////
  17 //////////////////////////////////////////////////////////////////////
  18 ////                                                              ////
  19 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
  20 ////                                                              ////
  21 //// This source file may be used and distributed without         ////
  22 //// restriction provided that this copyright statement is not    ////
  23 //// removed from the file and that any derivative work contains  ////
  24 //// the original copyright notice and the associated disclaimer. ////
  25 ////                                                              ////
  26 //// This source file is free software; you can redistribute it   ////
  27 //// and/or modify it under the terms of the GNU Lesser General   ////
  28 //// Public License as published by the Free Software Foundation; ////
  29 //// either version 2.1 of the License, or (at your option) any   ////
  30 //// later version.                                               ////
  31 ////                                                              ////
  32 //// This source is distributed in the hope that it will be       ////
  33 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  34 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  35 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  36 //// details.                                                     ////
  37 ////                                                              ////
  38 //// You should have received a copy of the GNU Lesser General    ////
  39 //// Public License along with this source; if not, download it   ////
  40 //// from http://www.opencores.org/lgpl.shtml                     ////
  41 ////                                                              ////
  42 //////////////////////////////////////////////////////////////////////
  43 //
  44 // CVS Revision History
  45 //
  46 // $Log$
  47 // Revision 1.7  2004/04/05 08:29:57  lampret
  48 // Merged branch_qmem into main tree.
  49 //
  50 // Revision 1.6.4.2  2003/12/05 00:09:49  lampret
  51 // No functional change.
  52 //
  53 // Revision 1.6.4.1  2003/07/08 15:36:37  lampret
  54 // Added embedded memory QMEM.
  55 //
  56 // Revision 1.6  2002/07/31 02:04:35  lampret
  57 // MAC now follows software convention (signed multiply instead of unsigned).
  58 //
  59 // Revision 1.5  2002/07/14 22:17:17  lampret
  60 // Added simple trace buffer [only for Xilinx Virtex target]. Fixed instruction fetch abort when new exception is recognized.
  61 //
  62 // Revision 1.4  2002/03/29 15:16:55  lampret
  63 // Some of the warnings fixed.
  64 //
  65 // Revision 1.3  2002/01/28 01:16:00  lampret
  66 // Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
  67 //
  68 // Revision 1.2  2002/01/14 06:18:22  lampret
  69 // Fixed mem2reg bug in FAST implementation. Updated debug unit to work with new genpc/if.
  70 //
  71 // Revision 1.1  2002/01/03 08:16:15  lampret
  72 // New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
  73 //
  74 // Revision 1.10  2001/11/13 10:02:21  lampret
  75 // Added 'setpc'. Renamed some signals (except_flushpipe into flushpipe etc)
  76 //
  77 // Revision 1.9  2001/10/21 17:57:16  lampret
  78 // Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
  79 //
  80 // Revision 1.8  2001/10/19 23:28:46  lampret
  81 // Fixed some synthesis warnings. Configured with caches and MMUs.
  82 //
  83 // Revision 1.7  2001/10/14 13:12:09  lampret
  84 // MP3 version.
  85 //
  86 // Revision 1.1.1.1  2001/10/06 10:18:36  igorm
  87 // no message
  88 //
  89 // Revision 1.2  2001/08/09 13:39:33  lampret
  90 // Major clean-up.
  91 //
  92 // Revision 1.1  2001/07/20 00:46:03  lampret
  93 // Development version of RTL. Libraries are missing.
  94 //
  95 //
  96
  97 // synopsys translate_off
  98 `include "timescale.v"
  99 // synopsys translate_on
 100 `include "or1200_defines.v"
 101
 102 `define OR1200_NO_FREEZE        3'd0
 103 `define OR1200_FREEZE_BYDC      3'd1
 104 `define OR1200_FREEZE_BYMULTICYCLE      3'd2
 105 `define OR1200_WAIT_LSU_TO_FINISH       3'd3
 106 `define OR1200_WAIT_IC                  3'd4
 107
 108 //
 109 // Freeze logic (stalls CPU pipeline, ifetcher etc.)
 110 //
 111 module or1200_freeze(
 112         // Clock and reset
 113         clk, rst,
 114
 115         // Internal i/f
 116         multicycle, flushpipe, extend_flush, lsu_stall, if_stall,
 117         lsu_unstall, du_stall, mac_stall,
 118         force_dslot_fetch, abort_ex,
 119         genpc_freeze, if_freeze, id_freeze, ex_freeze, wb_freeze,
 120         icpu_ack_i, icpu_err_i
 121 );
 122
 123 //
 124 // I/O
 125 //
 126 input                           clk;
 127 input                           rst;
 128 input   [`OR1200_MULTICYCLE_WIDTH-1:0]  multicycle;
 129 input                           flushpipe;
 130 input                           extend_flush;
 131 input                           lsu_stall;
 132 input                           if_stall;
 133 input                           lsu_unstall;
 134 input                           force_dslot_fetch;
 135 input                           abort_ex;
 136 input                           du_stall;
 137 input                           mac_stall;
 138 output                          genpc_freeze;
 139 output                          if_freeze;
 140 output                          id_freeze;
 141 output                          ex_freeze;
 142 output                          wb_freeze;
 143 input                           icpu_ack_i;
 144 input                           icpu_err_i;
 145
 146 //
 147 // Internal wires and regs
 148 //
 149 wire                            multicycle_freeze;
 150 reg     [`OR1200_MULTICYCLE_WIDTH-1:0]  multicycle_cnt;
 151 reg                             flushpipe_r;
 152
 153 //
 154 // Pipeline freeze
 155 //
 156 // Rules how to create freeze signals:
 157 // 1. Not overwriting pipeline stages:
 158 // Freze signals at the beginning of pipeline (such as if_freeze) can be asserted more
 159 // often than freeze signals at the of pipeline (such as wb_freeze). In other words, wb_freeze must never
 160 // be asserted when ex_freeze is not. ex_freeze must never be asserted when id_freeze is not etc.
 161 //
 162 // 2. Inserting NOPs in the middle of pipeline only if supported:
 163 // At this time, only ex_freeze (and wb_freeze) can be deassrted when id_freeze (and if_freeze) are asserted.
 164 // This way NOP is asserted from stage ID into EX stage.
 165 //
 166 //assign genpc_freeze = du_stall | flushpipe_r | lsu_stall;
 167 assign genpc_freeze = du_stall | flushpipe_r;
 168 assign if_freeze = id_freeze | extend_flush;
 169 //assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) & ~flushpipe | du_stall;
 170 assign id_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze | force_dslot_fetch) | du_stall | mac_stall;
 171 assign ex_freeze = wb_freeze;
 172 //assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) & ~flushpipe | du_stall | mac_stall;
 173 assign wb_freeze = (lsu_stall | (~lsu_unstall & if_stall) | multicycle_freeze) | du_stall | mac_stall | abort_ex;
 174
 175 //
 176 // registered flushpipe
 177 //
 178 always @(posedge clk or posedge rst)
 179         if (rst)
 180                 flushpipe_r <= #1 1'b0;
 181         else if (icpu_ack_i | icpu_err_i)
 182 //      else if (!if_stall)
 183                 flushpipe_r <= #1 flushpipe;
 184         else if (!flushpipe)
 185                 flushpipe_r <= #1 1'b0;
 186
 187 //
 188 // Multicycle freeze
 189 //
 190 assign multicycle_freeze = |multicycle_cnt;
 191
 192 //
 193 // Multicycle counter
 194 //
 195 always @(posedge clk or posedge rst)
 196         if (rst)
 197                 multicycle_cnt <= #1 3'b0;
 198         else if (multicycle_cnt)
 199                 multicycle_cnt <= #1 multicycle_cnt - 1'd1;
 200         else if (multicycle & !ex_freeze)
 201                 multicycle_cnt <= #1 multicycle;
 202
 203 endmodule