Public Git Hosting - or1200.git/commit

commit	673c79ee0866c2786701eca0e132f7dcdb2d8f9c
author	lampret <lampret>
	Mon, 5 Apr 2004 08:29:57 +0000 (5 08:29 +0000)
committer	lampret <lampret>
	Mon, 5 Apr 2004 08:29:57 +0000 (5 08:29 +0000)
tree	389c4268024843effd64f35c7a64af5863d7258b	tree \| snapshot (tar.gz zip)
parent	af528f9affa32a04bc0a87781a01ce0fe8af6854	commit \| diff

Merged branch_qmem into main tree.

37 files changed:

rtl/verilog/or1200_alu.v		diff \| blob \| blame \| history
rtl/verilog/or1200_cpu.v		diff \| blob \| blame \| history
rtl/verilog/or1200_ctrl.v		diff \| blob \| blame \| history
rtl/verilog/or1200_dc_fsm.v		diff \| blob \| blame \| history
rtl/verilog/or1200_dc_ram.v		diff \| blob \| blame \| history
rtl/verilog/or1200_dc_tag.v		diff \| blob \| blame \| history
rtl/verilog/or1200_dc_top.v		diff \| blob \| blame \| history
rtl/verilog/or1200_defines.v		diff \| blob \| blame \| history
rtl/verilog/or1200_dmmu_tlb.v		diff \| blob \| blame \| history
rtl/verilog/or1200_dmmu_top.v		diff \| blob \| blame \| history
rtl/verilog/or1200_dpram_32x32.v		diff \| blob \| blame \| history
rtl/verilog/or1200_du.v		diff \| blob \| blame \| history
rtl/verilog/or1200_except.v		diff \| blob \| blame \| history
rtl/verilog/or1200_freeze.v		diff \| blob \| blame \| history
rtl/verilog/or1200_genpc.v		diff \| blob \| blame \| history
rtl/verilog/or1200_ic_fsm.v		diff \| blob \| blame \| history
rtl/verilog/or1200_ic_ram.v		diff \| blob \| blame \| history
rtl/verilog/or1200_ic_tag.v		diff \| blob \| blame \| history
rtl/verilog/or1200_ic_top.v		diff \| blob \| blame \| history
rtl/verilog/or1200_if.v		diff \| blob \| blame \| history
rtl/verilog/or1200_immu_tlb.v		diff \| blob \| blame \| history
rtl/verilog/or1200_immu_top.v		diff \| blob \| blame \| history
rtl/verilog/or1200_iwb_biu.v		diff \| blob \| blame \| history
rtl/verilog/or1200_lsu.v		diff \| blob \| blame \| history
rtl/verilog/or1200_spram_1024x32.v		diff \| blob \| blame \| history
rtl/verilog/or1200_spram_1024x8.v		diff \| blob \| blame \| history
rtl/verilog/or1200_spram_2048x32.v		diff \| blob \| blame \| history
rtl/verilog/or1200_spram_2048x8.v		diff \| blob \| blame \| history
rtl/verilog/or1200_spram_256x21.v		diff \| blob \| blame \| history
rtl/verilog/or1200_spram_512x20.v		diff \| blob \| blame \| history
rtl/verilog/or1200_spram_64x14.v		diff \| blob \| blame \| history
rtl/verilog/or1200_spram_64x22.v		diff \| blob \| blame \| history
rtl/verilog/or1200_spram_64x24.v		diff \| blob \| blame \| history
rtl/verilog/or1200_sprs.v		diff \| blob \| blame \| history
rtl/verilog/or1200_top.v		diff \| blob \| blame \| history
rtl/verilog/or1200_tpram_32x32.v		diff \| blob \| blame \| history
rtl/verilog/or1200_wb_biu.v		diff \| blob \| blame \| history

32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities

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