rtl/verilog/or1200_spram_64x22.v

   1 //////////////////////////////////////////////////////////////////////
   2 ////                                                              ////
   3 ////  Generic Single-Port Synchronous RAM                         ////
   4 ////                                                              ////
   5 ////  This file is part of memory library available from          ////
   6 ////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
   7 ////                                                              ////
   8 ////  Description                                                 ////
   9 ////  This block is a wrapper with common single-port             ////
  10 ////  synchronous memory interface for different                  ////
  11 ////  types of ASIC and FPGA RAMs. Beside universal memory        ////
  12 ////  interface it also provides behavioral model of generic      ////
  13 ////  single-port synchronous RAM.                                ////
  14 ////  It should be used in all OPENCORES designs that want to be  ////
  15 ////  portable accross different target technologies and          ////
  16 ////  independent of target memory.                               ////
  17 ////                                                              ////
  18 ////  Supported ASIC RAMs are:                                    ////
  19 ////  - Artisan Single-Port Sync RAM                              ////
  20 ////  - Avant! Two-Port Sync RAM (*)                              ////
  21 ////  - Virage Single-Port Sync RAM                               ////
  22 ////  - Virtual Silicon Single-Port Sync RAM                      ////
  23 ////                                                              ////
  24 ////  Supported FPGA RAMs are:                                    ////
  25 ////  - Xilinx Virtex RAMB4_S16                                   ////
  26 ////  - Altera LPM                                                ////
  27 ////                                                              ////
  28 ////  To Do:                                                      ////
  29 ////   - xilinx rams need external tri-state logic                ////
  30 ////   - fix avant! two-port ram                                  ////
  31 ////   - add additional RAMs                                      ////
  32 ////                                                              ////
  33 ////  Author(s):                                                  ////
  34 ////      - Damjan Lampret, lampret@opencores.org                 ////
  35 ////                                                              ////
  36 //////////////////////////////////////////////////////////////////////
  37 ////                                                              ////
  38 //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
  39 ////                                                              ////
  40 //// This source file may be used and distributed without         ////
  41 //// restriction provided that this copyright statement is not    ////
  42 //// removed from the file and that any derivative work contains  ////
  43 //// the original copyright notice and the associated disclaimer. ////
  44 ////                                                              ////
  45 //// This source file is free software; you can redistribute it   ////
  46 //// and/or modify it under the terms of the GNU Lesser General   ////
  47 //// Public License as published by the Free Software Foundation; ////
  48 //// either version 2.1 of the License, or (at your option) any   ////
  49 //// later version.                                               ////
  50 ////                                                              ////
  51 //// This source is distributed in the hope that it will be       ////
  52 //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  53 //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  54 //// PURPOSE.  See the GNU Lesser General Public License for more ////
  55 //// details.                                                     ////
  56 ////                                                              ////
  57 //// You should have received a copy of the GNU Lesser General    ////
  58 //// Public License along with this source; if not, download it   ////
  59 //// from http://www.opencores.org/lgpl.shtml                     ////
  60 ////                                                              ////
  61 //////////////////////////////////////////////////////////////////////
  62 //
  63 // CVS Revision History
  64 //
  65 // $Log$
  66 // Revision 1.7  2004/04/05 08:29:57  lampret
  67 // Merged branch_qmem into main tree.
  68 //
  69 // Revision 1.3.4.1  2003/12/09 11:46:48  simons
  70 // Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
  71 //
  72 // Revision 1.3  2003/04/07 01:19:07  lampret
  73 // Added Altera LPM RAMs. Changed generic RAM output when OE inactive.
  74 //
  75 // Revision 1.2  2002/10/17 20:04:41  lampret
  76 // Added BIST scan. Special VS RAMs need to be used to implement BIST.
  77 //
  78 // Revision 1.1  2002/01/03 08:16:15  lampret
  79 // New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
  80 //
  81 // Revision 1.7  2001/11/02 18:57:14  lampret
  82 // Modified virtual silicon instantiations.
  83 //
  84 // Revision 1.6  2001/10/21 17:57:16  lampret
  85 // Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
  86 //
  87 // Revision 1.5  2001/10/14 13:12:09  lampret
  88 // MP3 version.
  89 //
  90 // Revision 1.1.1.1  2001/10/06 10:18:36  igorm
  91 // no message
  92 //
  93 // Revision 1.1  2001/08/09 13:39:33  lampret
  94 // Major clean-up.
  95 //
  96 // Revision 1.2  2001/07/30 05:38:02  lampret
  97 // Adding empty directories required by HDL coding guidelines
  98 //
  99 //
 100
 101 // synopsys translate_off
 102 `include "timescale.v"
 103 // synopsys translate_on
 104 `include "or1200_defines.v"
 105
 106 module or1200_spram_64x22(
 107 `ifdef OR1200_BIST
 108         // RAM BIST
 109         mbist_si_i, mbist_so_o, mbist_ctrl_i,
 110 `endif
 111         // Generic synchronous single-port RAM interface
 112         clk, rst, ce, we, oe, addr, di, do
 113 );
 114
 115 //
 116 // Default address and data buses width
 117 //
 118 parameter aw = 6;
 119 parameter dw = 22;
 120
 121 `ifdef OR1200_BIST
 122 //
 123 // RAM BIST
 124 //
 125 input mbist_si_i;
 126 input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
 127 output mbist_so_o;
 128 `endif
 129
 130 //
 131 // Generic synchronous single-port RAM interface
 132 //
 133 input                   clk;    // Clock
 134 input                   rst;    // Reset
 135 input                   ce;     // Chip enable input
 136 input                   we;     // Write enable input
 137 input                   oe;     // Output enable input
 138 input   [aw-1:0]        addr;   // address bus inputs
 139 input   [dw-1:0]        di;     // input data bus
 140 output  [dw-1:0]        do;     // output data bus
 141
 142 //
 143 // Internal wires and registers
 144 //
 145 wire    [9:0]           unconnected;
 146
 147 `ifdef OR1200_ARTISAN_SSP
 148 `else
 149 `ifdef OR1200_VIRTUALSILICON_SSP
 150 `else
 151 `ifdef OR1200_BIST
 152 assign mbist_so_o = mbist_si_i;
 153 `endif
 154 `endif
 155 `endif
 156
 157 `ifdef OR1200_ARTISAN_SSP
 158
 159 //
 160 // Instantiation of ASIC memory:
 161 //
 162 // Artisan Synchronous Single-Port RAM (ra1sh)
 163 //
 164 `ifdef UNUSED
 165 art_hssp_64x22 #(dw, 1<<aw, aw) artisan_ssp(
 166 `else
 167 `ifdef OR1200_BIST
 168 art_hssp_64x22_bist artisan_ssp(
 169 `else
 170 art_hssp_64x22 artisan_ssp(
 171 `endif
 172 `endif
 173 `ifdef OR1200_BIST
 174         // RAM BIST
 175         .mbist_si_i(mbist_si_i),
 176         .mbist_so_o(mbist_so_o),
 177         .mbist_ctrl_i(mbist_ctrl_i),
 178 `endif
 179         .CLK(clk),
 180         .CEN(~ce),
 181         .WEN(~we),
 182         .A(addr),
 183         .D(di),
 184         .OEN(~oe),
 185         .Q(do)
 186 );
 187
 188 `else
 189
 190 `ifdef OR1200_AVANT_ATP
 191
 192 //
 193 // Instantiation of ASIC memory:
 194 //
 195 // Avant! Asynchronous Two-Port RAM
 196 //
 197 avant_atp avant_atp(
 198         .web(~we),
 199         .reb(),
 200         .oeb(~oe),
 201         .rcsb(),
 202         .wcsb(),
 203         .ra(addr),
 204         .wa(addr),
 205         .di(di),
 206         .do(do)
 207 );
 208
 209 `else
 210
 211 `ifdef OR1200_VIRAGE_SSP
 212
 213 //
 214 // Instantiation of ASIC memory:
 215 //
 216 // Virage Synchronous 1-port R/W RAM
 217 //
 218 virage_ssp virage_ssp(
 219         .clk(clk),
 220         .adr(addr),
 221         .d(di),
 222         .we(we),
 223         .oe(oe),
 224         .me(ce),
 225         .q(do)
 226 );
 227
 228 `else
 229
 230 `ifdef OR1200_VIRTUALSILICON_SSP
 231
 232 //
 233 // Instantiation of ASIC memory:
 234 //
 235 // Virtual Silicon Single-Port Synchronous SRAM
 236 //
 237 `ifdef UNUSED
 238 vs_hdsp_64x22 #(1<<aw, aw-1, dw-1) vs_ssp(
 239 `else
 240 `ifdef OR1200_BIST
 241 vs_hdsp_64x22_bist vs_ssp(
 242 `else
 243 vs_hdsp_64x22 vs_ssp(
 244 `endif
 245 `endif
 246 `ifdef OR1200_BIST
 247         // RAM BIST
 248         .mbist_si_i(mbist_si_i),
 249         .mbist_so_o(mbist_so_o),
 250         .mbist_ctrl_i(mbist_ctrl_i),
 251 `endif
 252         .CK(clk),
 253         .ADR(addr),
 254         .DI(di),
 255         .WEN(~we),
 256         .CEN(~ce),
 257         .OEN(~oe),
 258         .DOUT(do)
 259 );
 260
 261 `else
 262
 263 `ifdef OR1200_XILINX_RAMB4
 264
 265 //
 266 // Instantiation of FPGA memory:
 267 //
 268 // Virtex/Spartan2
 269 //
 270
 271 //
 272 // Block 0
 273 //
 274 RAMB4_S16 ramb4_s16_0(
 275         .CLK(clk),
 276         .RST(rst),
 277         .ADDR({2'b00, addr}),
 278         .DI(di[15:0]),
 279         .EN(ce),
 280         .WE(we),
 281         .DO(do[15:0])
 282 );
 283
 284 //
 285 // Block 1
 286 //
 287 RAMB4_S16 ramb4_s16_1(
 288         .CLK(clk),
 289         .RST(rst),
 290         .ADDR({2'b00, addr}),
 291         .DI({unconnected, di[21:16]}),
 292         .EN(ce),
 293         .WE(we),
 294         .DO({unconnected, do[21:16]})
 295 );
 296
 297 `else
 298
 299 `ifdef OR1200_ALTERA_LPM
 300
 301 //
 302 // Instantiation of FPGA memory:
 303 //
 304 // Altera LPM
 305 //
 306 // Added By Jamil Khatib
 307 //
 308
 309 wire    wr;
 310
 311 assign  wr = ce & we;
 312
 313 initial $display("Using Altera LPM.");
 314
 315 lpm_ram_dq lpm_ram_dq_component (
 316         .address(addr),
 317         .inclock(clk),
 318         .outclock(clk),
 319         .data(di),
 320         .we(wr),
 321         .q(do)
 322 );
 323
 324 defparam lpm_ram_dq_component.lpm_width = dw,
 325         lpm_ram_dq_component.lpm_widthad = aw,
 326         lpm_ram_dq_component.lpm_indata = "REGISTERED",
 327         lpm_ram_dq_component.lpm_address_control = "REGISTERED",
 328         lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
 329         lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
 330         // examplar attribute lpm_ram_dq_component NOOPT TRUE
 331
 332 `else
 333
 334 //
 335 // Generic single-port synchronous RAM model
 336 //
 337
 338 //
 339 // Generic RAM's registers and wires
 340 //
 341 reg     [dw-1:0]        mem [(1<<aw)-1:0];      // RAM content
 342 reg     [dw-1:0]        do_reg;                 // RAM data output register
 343
 344 //
 345 // Data output drivers
 346 //
 347 assign do = (oe) ? do_reg : {dw{1'b0}};
 348
 349 //
 350 // RAM read and write
 351 //
 352 always @(posedge clk)
 353         if (ce && !we)
 354                 do_reg <= #1 mem[addr];
 355         else if (ce && we)
 356                 mem[addr] <= #1 di;
 357
 358 `endif  // !OR1200_ALTERA_LPM
 359 `endif  // !OR1200_XILINX_RAMB4_S16
 360 `endif  // !OR1200_VIRTUALSILICON_SSP
 361 `endif  // !OR1200_VIRAGE_SSP
 362 `endif  // !OR1200_AVANT_ATP
 363 `endif  // !OR1200_ARTISAN_SSP
 364
 365 endmodule