?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
snapshot (tar.gz zip)
Fixed module name when compiling with OR1200_XILINX_RAM32X1D
treee0b095e661ea75a336c9480a069401ee1f6a2cd5
drwxr-xr-x - bench tree | history
drwxr-xr-x - doc tree | history
drwxr-xr-x - lib tree | history
drwxr-xr-x - rtl tree | history
drwxr-xr-x - sim tree | history
drwxr-xr-x - syn tree | history
32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities