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Fixed module name when compiling with OR1200_XILINX_RAM32X1D
[or1200.git] / sim / 
tree11da1a2c7038558ca8adb19a690a5855a24ef22f
drwxr-xr-x   ..
-rwxr-xr-x 355 run.sh blob | blame | history | raw
32-bit scalar RISC with Harvard microarchitecture, 5 stage integer pipeline, virtual memory support (MMU) and basic DSP capabilities