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Linux 2.6.34-rc3
[pohmelfs.git] / drivers / media / video / pxa_camera.c
blob322ac4eecf0ae0cf39b82e33baaa2ef5294a6fe4
1 /*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/io.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/errno.h>
19 #include <linux/fs.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mm.h>
23 #include <linux/moduleparam.h>
24 #include <linux/time.h>
25 #include <linux/version.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29 #include <linux/sched.h>
30
31 #include <media/v4l2-common.h>
32 #include <media/v4l2-dev.h>
33 #include <media/videobuf-dma-sg.h>
34 #include <media/soc_camera.h>
35 #include <media/soc_mediabus.h>
36
37 #include <linux/videodev2.h>
38
39 #include <mach/dma.h>
40 #include <mach/camera.h>
41
42 #define PXA_CAM_VERSION_CODE KERNEL_VERSION(0, 0, 5)
43 #define PXA_CAM_DRV_NAME "pxa27x-camera"
44
45 /* Camera Interface */
46 #define CICR0 0x0000
47 #define CICR1 0x0004
48 #define CICR2 0x0008
49 #define CICR3 0x000C
50 #define CICR4 0x0010
51 #define CISR 0x0014
52 #define CIFR 0x0018
53 #define CITOR 0x001C
54 #define CIBR0 0x0028
55 #define CIBR1 0x0030
56 #define CIBR2 0x0038
57
58 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
59 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
60 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
61 #define CICR0_ENB (1 << 28) /* Camera interface enable */
62 #define CICR0_DIS (1 << 27) /* Camera interface disable */
63 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
64 #define CICR0_TOM (1 << 9) /* Time-out mask */
65 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
66 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
67 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
68 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
69 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
70 #define CICR0_CDM (1 << 3) /* Disable-done mask */
71 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
72 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
73 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
74
75 #define CICR1_TBIT (1 << 31) /* Transparency bit */
76 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
77 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
78 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
79 #define CICR1_RGB_F (1 << 11) /* RGB format */
80 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
81 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
82 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
83 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
84 #define CICR1_DW (0x7 << 0) /* Data width mask */
85
86 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
87 wait count mask */
88 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
89 wait count mask */
90 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
91 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
92 wait count mask */
93 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
94 wait count mask */
95
96 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
97 wait count mask */
98 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
99 wait count mask */
100 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
101 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
102 wait count mask */
103 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
104
105 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
106 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
107 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
108 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
109 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
110 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
111 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
112 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
113
114 #define CISR_FTO (1 << 15) /* FIFO time-out */
115 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
116 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
117 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
118 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
119 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
120 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
121 #define CISR_EOL (1 << 8) /* End of line */
122 #define CISR_PAR_ERR (1 << 7) /* Parity error */
123 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
124 #define CISR_CDD (1 << 5) /* Camera interface disable done */
125 #define CISR_SOF (1 << 4) /* Start of frame */
126 #define CISR_EOF (1 << 3) /* End of frame */
127 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
128 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
129 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
130
131 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
132 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
133 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
134 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
135 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
136 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
137 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
138 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
139
140 #define CICR0_SIM_MP (0 << 24)
141 #define CICR0_SIM_SP (1 << 24)
142 #define CICR0_SIM_MS (2 << 24)
143 #define CICR0_SIM_EP (3 << 24)
144 #define CICR0_SIM_ES (4 << 24)
145
146 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
147 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
148 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
149 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
150 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
151
152 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
153 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
154 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
155 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
156 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
157
158 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
159 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
160 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
161 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
162
163 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
164 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
165 CICR0_EOFM | CICR0_FOM)
166
167 /*
168 * Structures
169 */
170 enum pxa_camera_active_dma {
171 DMA_Y = 0x1,
172 DMA_U = 0x2,
173 DMA_V = 0x4,
174 };
175
176 /* descriptor needed for the PXA DMA engine */
177 struct pxa_cam_dma {
178 dma_addr_t sg_dma;
179 struct pxa_dma_desc *sg_cpu;
180 size_t sg_size;
181 int sglen;
182 };
183
184 /* buffer for one video frame */
185 struct pxa_buffer {
186 /* common v4l buffer stuff -- must be first */
187 struct videobuf_buffer vb;
188 enum v4l2_mbus_pixelcode code;
189 /* our descriptor lists for Y, U and V channels */
190 struct pxa_cam_dma dmas[3];
191 int inwork;
192 enum pxa_camera_active_dma active_dma;
193 };
194
195 struct pxa_camera_dev {
196 struct soc_camera_host soc_host;
197 /*
198 * PXA27x is only supposed to handle one camera on its Quick Capture
199 * interface. If anyone ever builds hardware to enable more than
200 * one camera, they will have to modify this driver too
201 */
202 struct soc_camera_device *icd;
203 struct clk *clk;
204
205 unsigned int irq;
206 void __iomem *base;
207
208 int channels;
209 unsigned int dma_chans[3];
210
211 struct pxacamera_platform_data *pdata;
212 struct resource *res;
213 unsigned long platform_flags;
214 unsigned long ciclk;
215 unsigned long mclk;
216 u32 mclk_divisor;
217
218 struct list_head capture;
219
220 spinlock_t lock;
221
222 struct pxa_buffer *active;
223 struct pxa_dma_desc *sg_tail[3];
224
225 u32 save_cicr[5];
226 };
227
228 struct pxa_cam {
229 unsigned long flags;
230 };
231
232 static const char *pxa_cam_driver_description = "PXA_Camera";
233
234 static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
235
236 /*
237 * Videobuf operations
238 */
239 static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
240 unsigned int *size)
241 {
242 struct soc_camera_device *icd = vq->priv_data;
243 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
244 icd->current_fmt->host_fmt);
245
246 if (bytes_per_line < 0)
247 return bytes_per_line;
248
249 dev_dbg(icd->dev.parent, "count=%d, size=%d\n", *count, *size);
250
251 *size = bytes_per_line * icd->user_height;
252
253 if (0 == *count)
254 *count = 32;
255 while (*size * *count > vid_limit * 1024 * 1024)
256 (*count)--;
257
258 return 0;
259 }
260
261 static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
262 {
263 struct soc_camera_device *icd = vq->priv_data;
264 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
265 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
266 int i;
267
268 BUG_ON(in_interrupt());
269
270 dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
271 &buf->vb, buf->vb.baddr, buf->vb.bsize);
272
273 /*
274 * This waits until this buffer is out of danger, i.e., until it is no
275 * longer in STATE_QUEUED or STATE_ACTIVE
276 */
277 videobuf_waiton(&buf->vb, 0, 0);
278 videobuf_dma_unmap(vq, dma);
279 videobuf_dma_free(dma);
280
281 for (i = 0; i < ARRAY_SIZE(buf->dmas); i++) {
282 if (buf->dmas[i].sg_cpu)
283 dma_free_coherent(ici->v4l2_dev.dev,
284 buf->dmas[i].sg_size,
285 buf->dmas[i].sg_cpu,
286 buf->dmas[i].sg_dma);
287 buf->dmas[i].sg_cpu = NULL;
288 }
289
290 buf->vb.state = VIDEOBUF_NEEDS_INIT;
291 }
292
293 static int calculate_dma_sglen(struct scatterlist *sglist, int sglen,
294 int sg_first_ofs, int size)
295 {
296 int i, offset, dma_len, xfer_len;
297 struct scatterlist *sg;
298
299 offset = sg_first_ofs;
300 for_each_sg(sglist, sg, sglen, i) {
301 dma_len = sg_dma_len(sg);
302
303 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
304 xfer_len = roundup(min(dma_len - offset, size), 8);
305
306 size = max(0, size - xfer_len);
307 offset = 0;
308 if (size == 0)
309 break;
310 }
311
312 BUG_ON(size != 0);
313 return i + 1;
314 }
315
316 /**
317 * pxa_init_dma_channel - init dma descriptors
318 * @pcdev: pxa camera device
319 * @buf: pxa buffer to find pxa dma channel
320 * @dma: dma video buffer
321 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
322 * @cibr: camera Receive Buffer Register
323 * @size: bytes to transfer
324 * @sg_first: first element of sg_list
325 * @sg_first_ofs: offset in first element of sg_list
326 *
327 * Prepares the pxa dma descriptors to transfer one camera channel.
328 * Beware sg_first and sg_first_ofs are both input and output parameters.
329 *
330 * Returns 0 or -ENOMEM if no coherent memory is available
331 */
332 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
333 struct pxa_buffer *buf,
334 struct videobuf_dmabuf *dma, int channel,
335 int cibr, int size,
336 struct scatterlist **sg_first, int *sg_first_ofs)
337 {
338 struct pxa_cam_dma *pxa_dma = &buf->dmas[channel];
339 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
340 struct scatterlist *sg;
341 int i, offset, sglen;
342 int dma_len = 0, xfer_len = 0;
343
344 if (pxa_dma->sg_cpu)
345 dma_free_coherent(dev, pxa_dma->sg_size,
346 pxa_dma->sg_cpu, pxa_dma->sg_dma);
347
348 sglen = calculate_dma_sglen(*sg_first, dma->sglen,
349 *sg_first_ofs, size);
350
351 pxa_dma->sg_size = (sglen + 1) * sizeof(struct pxa_dma_desc);
352 pxa_dma->sg_cpu = dma_alloc_coherent(dev, pxa_dma->sg_size,
353 &pxa_dma->sg_dma, GFP_KERNEL);
354 if (!pxa_dma->sg_cpu)
355 return -ENOMEM;
356
357 pxa_dma->sglen = sglen;
358 offset = *sg_first_ofs;
359
360 dev_dbg(dev, "DMA: sg_first=%p, sglen=%d, ofs=%d, dma.desc=%x\n",
361 *sg_first, sglen, *sg_first_ofs, pxa_dma->sg_dma);
362
363
364 for_each_sg(*sg_first, sg, sglen, i) {
365 dma_len = sg_dma_len(sg);
366
367 /* PXA27x Developer's Manual 27.4.4.1: round up to 8 bytes */
368 xfer_len = roundup(min(dma_len - offset, size), 8);
369
370 size = max(0, size - xfer_len);
371
372 pxa_dma->sg_cpu[i].dsadr = pcdev->res->start + cibr;
373 pxa_dma->sg_cpu[i].dtadr = sg_dma_address(sg) + offset;
374 pxa_dma->sg_cpu[i].dcmd =
375 DCMD_FLOWSRC | DCMD_BURST8 | DCMD_INCTRGADDR | xfer_len;
376 #ifdef DEBUG
377 if (!i)
378 pxa_dma->sg_cpu[i].dcmd |= DCMD_STARTIRQEN;
379 #endif
380 pxa_dma->sg_cpu[i].ddadr =
381 pxa_dma->sg_dma + (i + 1) * sizeof(struct pxa_dma_desc);
382
383 dev_vdbg(dev, "DMA: desc.%08x->@phys=0x%08x, len=%d\n",
384 pxa_dma->sg_dma + i * sizeof(struct pxa_dma_desc),
385 sg_dma_address(sg) + offset, xfer_len);
386 offset = 0;
387
388 if (size == 0)
389 break;
390 }
391
392 pxa_dma->sg_cpu[sglen].ddadr = DDADR_STOP;
393 pxa_dma->sg_cpu[sglen].dcmd = DCMD_FLOWSRC | DCMD_BURST8 | DCMD_ENDIRQEN;
394
395 /*
396 * Handle 1 special case :
397 * - in 3 planes (YUV422P format), we might finish with xfer_len equal
398 * to dma_len (end on PAGE boundary). In this case, the sg element
399 * for next plane should be the next after the last used to store the
400 * last scatter gather RAM page
401 */
402 if (xfer_len >= dma_len) {
403 *sg_first_ofs = xfer_len - dma_len;
404 *sg_first = sg_next(sg);
405 } else {
406 *sg_first_ofs = xfer_len;
407 *sg_first = sg;
408 }
409
410 return 0;
411 }
412
413 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
414 struct pxa_buffer *buf)
415 {
416 buf->active_dma = DMA_Y;
417 if (pcdev->channels == 3)
418 buf->active_dma |= DMA_U | DMA_V;
419 }
420
421 /*
422 * Please check the DMA prepared buffer structure in :
423 * Documentation/video4linux/pxa_camera.txt
424 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
425 * modification while DMA chain is running will work anyway.
426 */
427 static int pxa_videobuf_prepare(struct videobuf_queue *vq,
428 struct videobuf_buffer *vb, enum v4l2_field field)
429 {
430 struct soc_camera_device *icd = vq->priv_data;
431 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
432 struct pxa_camera_dev *pcdev = ici->priv;
433 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
434 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
435 int ret;
436 int size_y, size_u = 0, size_v = 0;
437 int bytes_per_line = soc_mbus_bytes_per_line(icd->user_width,
438 icd->current_fmt->host_fmt);
439
440 if (bytes_per_line < 0)
441 return bytes_per_line;
442
443 dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
444 vb, vb->baddr, vb->bsize);
445
446 /* Added list head initialization on alloc */
447 WARN_ON(!list_empty(&vb->queue));
448
449 #ifdef DEBUG
450 /*
451 * This can be useful if you want to see if we actually fill
452 * the buffer with something
453 */
454 memset((void *)vb->baddr, 0xaa, vb->bsize);
455 #endif
456
457 BUG_ON(NULL == icd->current_fmt);
458
459 /*
460 * I think, in buf_prepare you only have to protect global data,
461 * the actual buffer is yours
462 */
463 buf->inwork = 1;
464
465 if (buf->code != icd->current_fmt->code ||
466 vb->width != icd->user_width ||
467 vb->height != icd->user_height ||
468 vb->field != field) {
469 buf->code = icd->current_fmt->code;
470 vb->width = icd->user_width;
471 vb->height = icd->user_height;
472 vb->field = field;
473 vb->state = VIDEOBUF_NEEDS_INIT;
474 }
475
476 vb->size = bytes_per_line * vb->height;
477 if (0 != vb->baddr && vb->bsize < vb->size) {
478 ret = -EINVAL;
479 goto out;
480 }
481
482 if (vb->state == VIDEOBUF_NEEDS_INIT) {
483 int size = vb->size;
484 int next_ofs = 0;
485 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
486 struct scatterlist *sg;
487
488 ret = videobuf_iolock(vq, vb, NULL);
489 if (ret)
490 goto fail;
491
492 if (pcdev->channels == 3) {
493 size_y = size / 2;
494 size_u = size_v = size / 4;
495 } else {
496 size_y = size;
497 }
498
499 sg = dma->sglist;
500
501 /* init DMA for Y channel */
502 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0, size_y,
503 &sg, &next_ofs);
504 if (ret) {
505 dev_err(dev, "DMA initialization for Y/RGB failed\n");
506 goto fail;
507 }
508
509 /* init DMA for U channel */
510 if (size_u)
511 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1,
512 size_u, &sg, &next_ofs);
513 if (ret) {
514 dev_err(dev, "DMA initialization for U failed\n");
515 goto fail_u;
516 }
517
518 /* init DMA for V channel */
519 if (size_v)
520 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2,
521 size_v, &sg, &next_ofs);
522 if (ret) {
523 dev_err(dev, "DMA initialization for V failed\n");
524 goto fail_v;
525 }
526
527 vb->state = VIDEOBUF_PREPARED;
528 }
529
530 buf->inwork = 0;
531 pxa_videobuf_set_actdma(pcdev, buf);
532
533 return 0;
534
535 fail_v:
536 dma_free_coherent(dev, buf->dmas[1].sg_size,
537 buf->dmas[1].sg_cpu, buf->dmas[1].sg_dma);
538 fail_u:
539 dma_free_coherent(dev, buf->dmas[0].sg_size,
540 buf->dmas[0].sg_cpu, buf->dmas[0].sg_dma);
541 fail:
542 free_buffer(vq, buf);
543 out:
544 buf->inwork = 0;
545 return ret;
546 }
547
548 /**
549 * pxa_dma_start_channels - start DMA channel for active buffer
550 * @pcdev: pxa camera device
551 *
552 * Initialize DMA channels to the beginning of the active video buffer, and
553 * start these channels.
554 */
555 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
556 {
557 int i;
558 struct pxa_buffer *active;
559
560 active = pcdev->active;
561
562 for (i = 0; i < pcdev->channels; i++) {
563 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
564 "%s (channel=%d) ddadr=%08x\n", __func__,
565 i, active->dmas[i].sg_dma);
566 DDADR(pcdev->dma_chans[i]) = active->dmas[i].sg_dma;
567 DCSR(pcdev->dma_chans[i]) = DCSR_RUN;
568 }
569 }
570
571 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
572 {
573 int i;
574
575 for (i = 0; i < pcdev->channels; i++) {
576 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
577 "%s (channel=%d)\n", __func__, i);
578 DCSR(pcdev->dma_chans[i]) = 0;
579 }
580 }
581
582 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
583 struct pxa_buffer *buf)
584 {
585 int i;
586 struct pxa_dma_desc *buf_last_desc;
587
588 for (i = 0; i < pcdev->channels; i++) {
589 buf_last_desc = buf->dmas[i].sg_cpu + buf->dmas[i].sglen;
590 buf_last_desc->ddadr = DDADR_STOP;
591
592 if (pcdev->sg_tail[i])
593 /* Link the new buffer to the old tail */
594 pcdev->sg_tail[i]->ddadr = buf->dmas[i].sg_dma;
595
596 /* Update the channel tail */
597 pcdev->sg_tail[i] = buf_last_desc;
598 }
599 }
600
601 /**
602 * pxa_camera_start_capture - start video capturing
603 * @pcdev: camera device
604 *
605 * Launch capturing. DMA channels should not be active yet. They should get
606 * activated at the end of frame interrupt, to capture only whole frames, and
607 * never begin the capture of a partial frame.
608 */
609 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
610 {
611 unsigned long cicr0, cifr;
612
613 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
614 /* Reset the FIFOs */
615 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
616 __raw_writel(cifr, pcdev->base + CIFR);
617 /* Enable End-Of-Frame Interrupt */
618 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
619 cicr0 &= ~CICR0_EOFM;
620 __raw_writel(cicr0, pcdev->base + CICR0);
621 }
622
623 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
624 {
625 unsigned long cicr0;
626
627 pxa_dma_stop_channels(pcdev);
628
629 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
630 __raw_writel(cicr0, pcdev->base + CICR0);
631
632 pcdev->active = NULL;
633 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
634 }
635
636 /* Called under spinlock_irqsave(&pcdev->lock, ...) */
637 static void pxa_videobuf_queue(struct videobuf_queue *vq,
638 struct videobuf_buffer *vb)
639 {
640 struct soc_camera_device *icd = vq->priv_data;
641 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
642 struct pxa_camera_dev *pcdev = ici->priv;
643 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
644
645 dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%08lx %d active=%p\n",
646 __func__, vb, vb->baddr, vb->bsize, pcdev->active);
647
648 list_add_tail(&vb->queue, &pcdev->capture);
649
650 vb->state = VIDEOBUF_ACTIVE;
651 pxa_dma_add_tail_buf(pcdev, buf);
652
653 if (!pcdev->active)
654 pxa_camera_start_capture(pcdev);
655 }
656
657 static void pxa_videobuf_release(struct videobuf_queue *vq,
658 struct videobuf_buffer *vb)
659 {
660 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
661 #ifdef DEBUG
662 struct soc_camera_device *icd = vq->priv_data;
663 struct device *dev = icd->dev.parent;
664
665 dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
666 vb, vb->baddr, vb->bsize);
667
668 switch (vb->state) {
669 case VIDEOBUF_ACTIVE:
670 dev_dbg(dev, "%s (active)\n", __func__);
671 break;
672 case VIDEOBUF_QUEUED:
673 dev_dbg(dev, "%s (queued)\n", __func__);
674 break;
675 case VIDEOBUF_PREPARED:
676 dev_dbg(dev, "%s (prepared)\n", __func__);
677 break;
678 default:
679 dev_dbg(dev, "%s (unknown)\n", __func__);
680 break;
681 }
682 #endif
683
684 free_buffer(vq, buf);
685 }
686
687 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
688 struct videobuf_buffer *vb,
689 struct pxa_buffer *buf)
690 {
691 int i;
692
693 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
694 list_del_init(&vb->queue);
695 vb->state = VIDEOBUF_DONE;
696 do_gettimeofday(&vb->ts);
697 vb->field_count++;
698 wake_up(&vb->done);
699 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s dequeud buffer (vb=0x%p)\n",
700 __func__, vb);
701
702 if (list_empty(&pcdev->capture)) {
703 pxa_camera_stop_capture(pcdev);
704 for (i = 0; i < pcdev->channels; i++)
705 pcdev->sg_tail[i] = NULL;
706 return;
707 }
708
709 pcdev->active = list_entry(pcdev->capture.next,
710 struct pxa_buffer, vb.queue);
711 }
712
713 /**
714 * pxa_camera_check_link_miss - check missed DMA linking
715 * @pcdev: camera device
716 *
717 * The DMA chaining is done with DMA running. This means a tiny temporal window
718 * remains, where a buffer is queued on the chain, while the chain is already
719 * stopped. This means the tailed buffer would never be transfered by DMA.
720 * This function restarts the capture for this corner case, where :
721 * - DADR() == DADDR_STOP
722 * - a videobuffer is queued on the pcdev->capture list
723 *
724 * Please check the "DMA hot chaining timeslice issue" in
725 * Documentation/video4linux/pxa_camera.txt
726 *
727 * Context: should only be called within the dma irq handler
728 */
729 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev)
730 {
731 int i, is_dma_stopped = 1;
732
733 for (i = 0; i < pcdev->channels; i++)
734 if (DDADR(pcdev->dma_chans[i]) != DDADR_STOP)
735 is_dma_stopped = 0;
736 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
737 "%s : top queued buffer=%p, dma_stopped=%d\n",
738 __func__, pcdev->active, is_dma_stopped);
739 if (pcdev->active && is_dma_stopped)
740 pxa_camera_start_capture(pcdev);
741 }
742
743 static void pxa_camera_dma_irq(int channel, struct pxa_camera_dev *pcdev,
744 enum pxa_camera_active_dma act_dma)
745 {
746 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
747 struct pxa_buffer *buf;
748 unsigned long flags;
749 u32 status, camera_status, overrun;
750 struct videobuf_buffer *vb;
751
752 spin_lock_irqsave(&pcdev->lock, flags);
753
754 status = DCSR(channel);
755 DCSR(channel) = status;
756
757 camera_status = __raw_readl(pcdev->base + CISR);
758 overrun = CISR_IFO_0;
759 if (pcdev->channels == 3)
760 overrun |= CISR_IFO_1 | CISR_IFO_2;
761
762 if (status & DCSR_BUSERR) {
763 dev_err(dev, "DMA Bus Error IRQ!\n");
764 goto out;
765 }
766
767 if (!(status & (DCSR_ENDINTR | DCSR_STARTINTR))) {
768 dev_err(dev, "Unknown DMA IRQ source, status: 0x%08x\n",
769 status);
770 goto out;
771 }
772
773 /*
774 * pcdev->active should not be NULL in DMA irq handler.
775 *
776 * But there is one corner case : if capture was stopped due to an
777 * overrun of channel 1, and at that same channel 2 was completed.
778 *
779 * When handling the overrun in DMA irq for channel 1, we'll stop the
780 * capture and restart it (and thus set pcdev->active to NULL). But the
781 * DMA irq handler will already be pending for channel 2. So on entering
782 * the DMA irq handler for channel 2 there will be no active buffer, yet
783 * that is normal.
784 */
785 if (!pcdev->active)
786 goto out;
787
788 vb = &pcdev->active->vb;
789 buf = container_of(vb, struct pxa_buffer, vb);
790 WARN_ON(buf->inwork || list_empty(&vb->queue));
791
792 dev_dbg(dev, "%s channel=%d %s%s(vb=0x%p) dma.desc=%x\n",
793 __func__, channel, status & DCSR_STARTINTR ? "SOF " : "",
794 status & DCSR_ENDINTR ? "EOF " : "", vb, DDADR(channel));
795
796 if (status & DCSR_ENDINTR) {
797 /*
798 * It's normal if the last frame creates an overrun, as there
799 * are no more DMA descriptors to fetch from QCI fifos
800 */
801 if (camera_status & overrun &&
802 !list_is_last(pcdev->capture.next, &pcdev->capture)) {
803 dev_dbg(dev, "FIFO overrun! CISR: %x\n",
804 camera_status);
805 pxa_camera_stop_capture(pcdev);
806 pxa_camera_start_capture(pcdev);
807 goto out;
808 }
809 buf->active_dma &= ~act_dma;
810 if (!buf->active_dma) {
811 pxa_camera_wakeup(pcdev, vb, buf);
812 pxa_camera_check_link_miss(pcdev);
813 }
814 }
815
816 out:
817 spin_unlock_irqrestore(&pcdev->lock, flags);
818 }
819
820 static void pxa_camera_dma_irq_y(int channel, void *data)
821 {
822 struct pxa_camera_dev *pcdev = data;
823 pxa_camera_dma_irq(channel, pcdev, DMA_Y);
824 }
825
826 static void pxa_camera_dma_irq_u(int channel, void *data)
827 {
828 struct pxa_camera_dev *pcdev = data;
829 pxa_camera_dma_irq(channel, pcdev, DMA_U);
830 }
831
832 static void pxa_camera_dma_irq_v(int channel, void *data)
833 {
834 struct pxa_camera_dev *pcdev = data;
835 pxa_camera_dma_irq(channel, pcdev, DMA_V);
836 }
837
838 static struct videobuf_queue_ops pxa_videobuf_ops = {
839 .buf_setup = pxa_videobuf_setup,
840 .buf_prepare = pxa_videobuf_prepare,
841 .buf_queue = pxa_videobuf_queue,
842 .buf_release = pxa_videobuf_release,
843 };
844
845 static void pxa_camera_init_videobuf(struct videobuf_queue *q,
846 struct soc_camera_device *icd)
847 {
848 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
849 struct pxa_camera_dev *pcdev = ici->priv;
850
851 /*
852 * We must pass NULL as dev pointer, then all pci_* dma operations
853 * transform to normal dma_* ones.
854 */
855 videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock,
856 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
857 sizeof(struct pxa_buffer), icd);
858 }
859
860 static u32 mclk_get_divisor(struct platform_device *pdev,
861 struct pxa_camera_dev *pcdev)
862 {
863 unsigned long mclk = pcdev->mclk;
864 struct device *dev = &pdev->dev;
865 u32 div;
866 unsigned long lcdclk;
867
868 lcdclk = clk_get_rate(pcdev->clk);
869 pcdev->ciclk = lcdclk;
870
871 /* mclk <= ciclk / 4 (27.4.2) */
872 if (mclk > lcdclk / 4) {
873 mclk = lcdclk / 4;
874 dev_warn(dev, "Limiting master clock to %lu\n", mclk);
875 }
876
877 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
878 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
879
880 /* If we're not supplying MCLK, leave it at 0 */
881 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
882 pcdev->mclk = lcdclk / (2 * (div + 1));
883
884 dev_dbg(dev, "LCD clock %luHz, target freq %luHz, divisor %u\n",
885 lcdclk, mclk, div);
886
887 return div;
888 }
889
890 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
891 unsigned long pclk)
892 {
893 /* We want a timeout > 1 pixel time, not ">=" */
894 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
895
896 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
897 }
898
899 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
900 {
901 u32 cicr4 = 0;
902
903 /* disable all interrupts */
904 __raw_writel(0x3ff, pcdev->base + CICR0);
905
906 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
907 cicr4 |= CICR4_PCLK_EN;
908 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
909 cicr4 |= CICR4_MCLK_EN;
910 if (pcdev->platform_flags & PXA_CAMERA_PCP)
911 cicr4 |= CICR4_PCP;
912 if (pcdev->platform_flags & PXA_CAMERA_HSP)
913 cicr4 |= CICR4_HSP;
914 if (pcdev->platform_flags & PXA_CAMERA_VSP)
915 cicr4 |= CICR4_VSP;
916
917 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
918
919 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
920 /* Initialise the timeout under the assumption pclk = mclk */
921 recalculate_fifo_timeout(pcdev, pcdev->mclk);
922 else
923 /* "Safe default" - 13MHz */
924 recalculate_fifo_timeout(pcdev, 13000000);
925
926 clk_enable(pcdev->clk);
927 }
928
929 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
930 {
931 clk_disable(pcdev->clk);
932 }
933
934 static irqreturn_t pxa_camera_irq(int irq, void *data)
935 {
936 struct pxa_camera_dev *pcdev = data;
937 unsigned long status, cicr0;
938 struct pxa_buffer *buf;
939 struct videobuf_buffer *vb;
940
941 status = __raw_readl(pcdev->base + CISR);
942 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
943 "Camera interrupt status 0x%lx\n", status);
944
945 if (!status)
946 return IRQ_NONE;
947
948 __raw_writel(status, pcdev->base + CISR);
949
950 if (status & CISR_EOF) {
951 pcdev->active = list_first_entry(&pcdev->capture,
952 struct pxa_buffer, vb.queue);
953 vb = &pcdev->active->vb;
954 buf = container_of(vb, struct pxa_buffer, vb);
955 pxa_videobuf_set_actdma(pcdev, buf);
956
957 pxa_dma_start_channels(pcdev);
958
959 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
960 __raw_writel(cicr0, pcdev->base + CICR0);
961 }
962
963 return IRQ_HANDLED;
964 }
965
966 /*
967 * The following two functions absolutely depend on the fact, that
968 * there can be only one camera on PXA quick capture interface
969 * Called with .video_lock held
970 */
971 static int pxa_camera_add_device(struct soc_camera_device *icd)
972 {
973 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
974 struct pxa_camera_dev *pcdev = ici->priv;
975
976 if (pcdev->icd)
977 return -EBUSY;
978
979 pxa_camera_activate(pcdev);
980
981 pcdev->icd = icd;
982
983 dev_info(icd->dev.parent, "PXA Camera driver attached to camera %d\n",
984 icd->devnum);
985
986 return 0;
987 }
988
989 /* Called with .video_lock held */
990 static void pxa_camera_remove_device(struct soc_camera_device *icd)
991 {
992 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
993 struct pxa_camera_dev *pcdev = ici->priv;
994
995 BUG_ON(icd != pcdev->icd);
996
997 dev_info(icd->dev.parent, "PXA Camera driver detached from camera %d\n",
998 icd->devnum);
999
1000 /* disable capture, disable interrupts */
1001 __raw_writel(0x3ff, pcdev->base + CICR0);
1002
1003 /* Stop DMA engine */
1004 DCSR(pcdev->dma_chans[0]) = 0;
1005 DCSR(pcdev->dma_chans[1]) = 0;
1006 DCSR(pcdev->dma_chans[2]) = 0;
1007
1008 pxa_camera_deactivate(pcdev);
1009
1010 pcdev->icd = NULL;
1011 }
1012
1013 static int test_platform_param(struct pxa_camera_dev *pcdev,
1014 unsigned char buswidth, unsigned long *flags)
1015 {
1016 /*
1017 * Platform specified synchronization and pixel clock polarities are
1018 * only a recommendation and are only used during probing. The PXA270
1019 * quick capture interface supports both.
1020 */
1021 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1022 SOCAM_MASTER : SOCAM_SLAVE) |
1023 SOCAM_HSYNC_ACTIVE_HIGH |
1024 SOCAM_HSYNC_ACTIVE_LOW |
1025 SOCAM_VSYNC_ACTIVE_HIGH |
1026 SOCAM_VSYNC_ACTIVE_LOW |
1027 SOCAM_DATA_ACTIVE_HIGH |
1028 SOCAM_PCLK_SAMPLE_RISING |
1029 SOCAM_PCLK_SAMPLE_FALLING;
1030
1031 /* If requested data width is supported by the platform, use it */
1032 switch (buswidth) {
1033 case 10:
1034 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10))
1035 return -EINVAL;
1036 *flags |= SOCAM_DATAWIDTH_10;
1037 break;
1038 case 9:
1039 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9))
1040 return -EINVAL;
1041 *flags |= SOCAM_DATAWIDTH_9;
1042 break;
1043 case 8:
1044 if (!(pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8))
1045 return -EINVAL;
1046 *flags |= SOCAM_DATAWIDTH_8;
1047 break;
1048 default:
1049 return -EINVAL;
1050 }
1051
1052 return 0;
1053 }
1054
1055 static void pxa_camera_setup_cicr(struct soc_camera_device *icd,
1056 unsigned long flags, __u32 pixfmt)
1057 {
1058 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1059 struct pxa_camera_dev *pcdev = ici->priv;
1060 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1061 unsigned long dw, bpp;
1062 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top;
1063 int ret = v4l2_subdev_call(sd, sensor, g_skip_top_lines, &y_skip_top);
1064
1065 if (ret < 0)
1066 y_skip_top = 0;
1067
1068 /*
1069 * Datawidth is now guaranteed to be equal to one of the three values.
1070 * We fix bit-per-pixel equal to data-width...
1071 */
1072 switch (flags & SOCAM_DATAWIDTH_MASK) {
1073 case SOCAM_DATAWIDTH_10:
1074 dw = 4;
1075 bpp = 0x40;
1076 break;
1077 case SOCAM_DATAWIDTH_9:
1078 dw = 3;
1079 bpp = 0x20;
1080 break;
1081 default:
1082 /*
1083 * Actually it can only be 8 now,
1084 * default is just to silence compiler warnings
1085 */
1086 case SOCAM_DATAWIDTH_8:
1087 dw = 2;
1088 bpp = 0;
1089 }
1090
1091 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1092 cicr4 |= CICR4_PCLK_EN;
1093 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1094 cicr4 |= CICR4_MCLK_EN;
1095 if (flags & SOCAM_PCLK_SAMPLE_FALLING)
1096 cicr4 |= CICR4_PCP;
1097 if (flags & SOCAM_HSYNC_ACTIVE_LOW)
1098 cicr4 |= CICR4_HSP;
1099 if (flags & SOCAM_VSYNC_ACTIVE_LOW)
1100 cicr4 |= CICR4_VSP;
1101
1102 cicr0 = __raw_readl(pcdev->base + CICR0);
1103 if (cicr0 & CICR0_ENB)
1104 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1105
1106 cicr1 = CICR1_PPL_VAL(icd->user_width - 1) | bpp | dw;
1107
1108 switch (pixfmt) {
1109 case V4L2_PIX_FMT_YUV422P:
1110 pcdev->channels = 3;
1111 cicr1 |= CICR1_YCBCR_F;
1112 /*
1113 * Normally, pxa bus wants as input UYVY format. We allow all
1114 * reorderings of the YUV422 format, as no processing is done,
1115 * and the YUV stream is just passed through without any
1116 * transformation. Note that UYVY is the only format that
1117 * should be used if pxa framebuffer Overlay2 is used.
1118 */
1119 case V4L2_PIX_FMT_UYVY:
1120 case V4L2_PIX_FMT_VYUY:
1121 case V4L2_PIX_FMT_YUYV:
1122 case V4L2_PIX_FMT_YVYU:
1123 cicr1 |= CICR1_COLOR_SP_VAL(2);
1124 break;
1125 case V4L2_PIX_FMT_RGB555:
1126 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1127 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1128 break;
1129 case V4L2_PIX_FMT_RGB565:
1130 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1131 break;
1132 }
1133
1134 cicr2 = 0;
1135 cicr3 = CICR3_LPF_VAL(icd->user_height - 1) |
1136 CICR3_BFW_VAL(min((u32)255, y_skip_top));
1137 cicr4 |= pcdev->mclk_divisor;
1138
1139 __raw_writel(cicr1, pcdev->base + CICR1);
1140 __raw_writel(cicr2, pcdev->base + CICR2);
1141 __raw_writel(cicr3, pcdev->base + CICR3);
1142 __raw_writel(cicr4, pcdev->base + CICR4);
1143
1144 /* CIF interrupts are not used, only DMA */
1145 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1146 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1147 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1148 __raw_writel(cicr0, pcdev->base + CICR0);
1149 }
1150
1151 static int pxa_camera_set_bus_param(struct soc_camera_device *icd, __u32 pixfmt)
1152 {
1153 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1154 struct pxa_camera_dev *pcdev = ici->priv;
1155 unsigned long bus_flags, camera_flags, common_flags;
1156 const struct soc_mbus_pixelfmt *fmt;
1157 int ret;
1158 struct pxa_cam *cam = icd->host_priv;
1159
1160 fmt = soc_mbus_get_fmtdesc(icd->current_fmt->code);
1161 if (!fmt)
1162 return -EINVAL;
1163
1164 ret = test_platform_param(pcdev, fmt->bits_per_sample, &bus_flags);
1165 if (ret < 0)
1166 return ret;
1167
1168 camera_flags = icd->ops->query_bus_param(icd);
1169
1170 common_flags = soc_camera_bus_param_compatible(camera_flags, bus_flags);
1171 if (!common_flags)
1172 return -EINVAL;
1173
1174 pcdev->channels = 1;
1175
1176 /* Make choises, based on platform preferences */
1177 if ((common_flags & SOCAM_HSYNC_ACTIVE_HIGH) &&
1178 (common_flags & SOCAM_HSYNC_ACTIVE_LOW)) {
1179 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1180 common_flags &= ~SOCAM_HSYNC_ACTIVE_HIGH;
1181 else
1182 common_flags &= ~SOCAM_HSYNC_ACTIVE_LOW;
1183 }
1184
1185 if ((common_flags & SOCAM_VSYNC_ACTIVE_HIGH) &&
1186 (common_flags & SOCAM_VSYNC_ACTIVE_LOW)) {
1187 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1188 common_flags &= ~SOCAM_VSYNC_ACTIVE_HIGH;
1189 else
1190 common_flags &= ~SOCAM_VSYNC_ACTIVE_LOW;
1191 }
1192
1193 if ((common_flags & SOCAM_PCLK_SAMPLE_RISING) &&
1194 (common_flags & SOCAM_PCLK_SAMPLE_FALLING)) {
1195 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1196 common_flags &= ~SOCAM_PCLK_SAMPLE_RISING;
1197 else
1198 common_flags &= ~SOCAM_PCLK_SAMPLE_FALLING;
1199 }
1200
1201 cam->flags = common_flags;
1202
1203 ret = icd->ops->set_bus_param(icd, common_flags);
1204 if (ret < 0)
1205 return ret;
1206
1207 pxa_camera_setup_cicr(icd, common_flags, pixfmt);
1208
1209 return 0;
1210 }
1211
1212 static int pxa_camera_try_bus_param(struct soc_camera_device *icd,
1213 unsigned char buswidth)
1214 {
1215 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1216 struct pxa_camera_dev *pcdev = ici->priv;
1217 unsigned long bus_flags, camera_flags;
1218 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1219
1220 if (ret < 0)
1221 return ret;
1222
1223 camera_flags = icd->ops->query_bus_param(icd);
1224
1225 return soc_camera_bus_param_compatible(camera_flags, bus_flags) ? 0 : -EINVAL;
1226 }
1227
1228 static const struct soc_mbus_pixelfmt pxa_camera_formats[] = {
1229 {
1230 .fourcc = V4L2_PIX_FMT_YUV422P,
1231 .name = "Planar YUV422 16 bit",
1232 .bits_per_sample = 8,
1233 .packing = SOC_MBUS_PACKING_2X8_PADHI,
1234 .order = SOC_MBUS_ORDER_LE,
1235 },
1236 };
1237
1238 /* This will be corrected as we get more formats */
1239 static bool pxa_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt)
1240 {
1241 return fmt->packing == SOC_MBUS_PACKING_NONE ||
1242 (fmt->bits_per_sample == 8 &&
1243 fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) ||
1244 (fmt->bits_per_sample > 8 &&
1245 fmt->packing == SOC_MBUS_PACKING_EXTEND16);
1246 }
1247
1248 static int pxa_camera_get_formats(struct soc_camera_device *icd, int idx,
1249 struct soc_camera_format_xlate *xlate)
1250 {
1251 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1252 struct device *dev = icd->dev.parent;
1253 int formats = 0, ret;
1254 struct pxa_cam *cam;
1255 enum v4l2_mbus_pixelcode code;
1256 const struct soc_mbus_pixelfmt *fmt;
1257
1258 ret = v4l2_subdev_call(sd, video, enum_mbus_fmt, idx, &code);
1259 if (ret < 0)
1260 /* No more formats */
1261 return 0;
1262
1263 fmt = soc_mbus_get_fmtdesc(code);
1264 if (!fmt) {
1265 dev_err(dev, "Invalid format code #%d: %d\n", idx, code);
1266 return 0;
1267 }
1268
1269 /* This also checks support for the requested bits-per-sample */
1270 ret = pxa_camera_try_bus_param(icd, fmt->bits_per_sample);
1271 if (ret < 0)
1272 return 0;
1273
1274 if (!icd->host_priv) {
1275 cam = kzalloc(sizeof(*cam), GFP_KERNEL);
1276 if (!cam)
1277 return -ENOMEM;
1278
1279 icd->host_priv = cam;
1280 } else {
1281 cam = icd->host_priv;
1282 }
1283
1284 switch (code) {
1285 case V4L2_MBUS_FMT_YUYV8_2X8_BE:
1286 formats++;
1287 if (xlate) {
1288 xlate->host_fmt = &pxa_camera_formats[0];
1289 xlate->code = code;
1290 xlate++;
1291 dev_dbg(dev, "Providing format %s using code %d\n",
1292 pxa_camera_formats[0].name, code);
1293 }
1294 case V4L2_MBUS_FMT_YVYU8_2X8_BE:
1295 case V4L2_MBUS_FMT_YUYV8_2X8_LE:
1296 case V4L2_MBUS_FMT_YVYU8_2X8_LE:
1297 case V4L2_MBUS_FMT_RGB565_2X8_LE:
1298 case V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE:
1299 if (xlate)
1300 dev_dbg(dev, "Providing format %s packed\n",
1301 fmt->name);
1302 break;
1303 default:
1304 if (!pxa_camera_packing_supported(fmt))
1305 return 0;
1306 if (xlate)
1307 dev_dbg(dev,
1308 "Providing format %s in pass-through mode\n",
1309 fmt->name);
1310 }
1311
1312 /* Generic pass-through */
1313 formats++;
1314 if (xlate) {
1315 xlate->host_fmt = fmt;
1316 xlate->code = code;
1317 xlate++;
1318 }
1319
1320 return formats;
1321 }
1322
1323 static void pxa_camera_put_formats(struct soc_camera_device *icd)
1324 {
1325 kfree(icd->host_priv);
1326 icd->host_priv = NULL;
1327 }
1328
1329 static int pxa_camera_check_frame(u32 width, u32 height)
1330 {
1331 /* limit to pxa hardware capabilities */
1332 return height < 32 || height > 2048 || width < 48 || width > 2048 ||
1333 (width & 0x01);
1334 }
1335
1336 static int pxa_camera_set_crop(struct soc_camera_device *icd,
1337 struct v4l2_crop *a)
1338 {
1339 struct v4l2_rect *rect = &a->c;
1340 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1341 struct pxa_camera_dev *pcdev = ici->priv;
1342 struct device *dev = icd->dev.parent;
1343 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1344 struct soc_camera_sense sense = {
1345 .master_clock = pcdev->mclk,
1346 .pixel_clock_max = pcdev->ciclk / 4,
1347 };
1348 struct v4l2_mbus_framefmt mf;
1349 struct pxa_cam *cam = icd->host_priv;
1350 u32 fourcc = icd->current_fmt->host_fmt->fourcc;
1351 int ret;
1352
1353 /* If PCLK is used to latch data from the sensor, check sense */
1354 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1355 icd->sense = &sense;
1356
1357 ret = v4l2_subdev_call(sd, video, s_crop, a);
1358
1359 icd->sense = NULL;
1360
1361 if (ret < 0) {
1362 dev_warn(dev, "Failed to crop to %ux%u@%u:%u\n",
1363 rect->width, rect->height, rect->left, rect->top);
1364 return ret;
1365 }
1366
1367 ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
1368 if (ret < 0)
1369 return ret;
1370
1371 if (pxa_camera_check_frame(mf.width, mf.height)) {
1372 /*
1373 * Camera cropping produced a frame beyond our capabilities.
1374 * FIXME: just extract a subframe, that we can process.
1375 */
1376 v4l_bound_align_image(&mf.width, 48, 2048, 1,
1377 &mf.height, 32, 2048, 0,
1378 fourcc == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1379 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
1380 if (ret < 0)
1381 return ret;
1382
1383 if (pxa_camera_check_frame(mf.width, mf.height)) {
1384 dev_warn(icd->dev.parent,
1385 "Inconsistent state. Use S_FMT to repair\n");
1386 return -EINVAL;
1387 }
1388 }
1389
1390 if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1391 if (sense.pixel_clock > sense.pixel_clock_max) {
1392 dev_err(dev,
1393 "pixel clock %lu set by the camera too high!",
1394 sense.pixel_clock);
1395 return -EIO;
1396 }
1397 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1398 }
1399
1400 icd->user_width = mf.width;
1401 icd->user_height = mf.height;
1402
1403 pxa_camera_setup_cicr(icd, cam->flags, fourcc);
1404
1405 return ret;
1406 }
1407
1408 static int pxa_camera_set_fmt(struct soc_camera_device *icd,
1409 struct v4l2_format *f)
1410 {
1411 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1412 struct pxa_camera_dev *pcdev = ici->priv;
1413 struct device *dev = icd->dev.parent;
1414 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1415 const struct soc_camera_format_xlate *xlate = NULL;
1416 struct soc_camera_sense sense = {
1417 .master_clock = pcdev->mclk,
1418 .pixel_clock_max = pcdev->ciclk / 4,
1419 };
1420 struct v4l2_pix_format *pix = &f->fmt.pix;
1421 struct v4l2_mbus_framefmt mf;
1422 int ret;
1423
1424 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1425 if (!xlate) {
1426 dev_warn(dev, "Format %x not found\n", pix->pixelformat);
1427 return -EINVAL;
1428 }
1429
1430 /* If PCLK is used to latch data from the sensor, check sense */
1431 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1432 /* The caller holds a mutex. */
1433 icd->sense = &sense;
1434
1435 mf.width = pix->width;
1436 mf.height = pix->height;
1437 mf.field = pix->field;
1438 mf.colorspace = pix->colorspace;
1439 mf.code = xlate->code;
1440
1441 ret = v4l2_subdev_call(sd, video, s_mbus_fmt, &mf);
1442
1443 if (mf.code != xlate->code)
1444 return -EINVAL;
1445
1446 icd->sense = NULL;
1447
1448 if (ret < 0) {
1449 dev_warn(dev, "Failed to configure for format %x\n",
1450 pix->pixelformat);
1451 } else if (pxa_camera_check_frame(mf.width, mf.height)) {
1452 dev_warn(dev,
1453 "Camera driver produced an unsupported frame %dx%d\n",
1454 mf.width, mf.height);
1455 ret = -EINVAL;
1456 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1457 if (sense.pixel_clock > sense.pixel_clock_max) {
1458 dev_err(dev,
1459 "pixel clock %lu set by the camera too high!",
1460 sense.pixel_clock);
1461 return -EIO;
1462 }
1463 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1464 }
1465
1466 if (ret < 0)
1467 return ret;
1468
1469 pix->width = mf.width;
1470 pix->height = mf.height;
1471 pix->field = mf.field;
1472 pix->colorspace = mf.colorspace;
1473 icd->current_fmt = xlate;
1474
1475 return ret;
1476 }
1477
1478 static int pxa_camera_try_fmt(struct soc_camera_device *icd,
1479 struct v4l2_format *f)
1480 {
1481 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1482 const struct soc_camera_format_xlate *xlate;
1483 struct v4l2_pix_format *pix = &f->fmt.pix;
1484 struct v4l2_mbus_framefmt mf;
1485 __u32 pixfmt = pix->pixelformat;
1486 int ret;
1487
1488 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1489 if (!xlate) {
1490 dev_warn(icd->dev.parent, "Format %x not found\n", pixfmt);
1491 return -EINVAL;
1492 }
1493
1494 /*
1495 * Limit to pxa hardware capabilities. YUV422P planar format requires
1496 * images size to be a multiple of 16 bytes. If not, zeros will be
1497 * inserted between Y and U planes, and U and V planes, which violates
1498 * the YUV422P standard.
1499 */
1500 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1501 &pix->height, 32, 2048, 0,
1502 pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1503
1504 pix->bytesperline = soc_mbus_bytes_per_line(pix->width,
1505 xlate->host_fmt);
1506 if (pix->bytesperline < 0)
1507 return pix->bytesperline;
1508 pix->sizeimage = pix->height * pix->bytesperline;
1509
1510 /* limit to sensor capabilities */
1511 mf.width = pix->width;
1512 mf.height = pix->height;
1513 mf.field = pix->field;
1514 mf.colorspace = pix->colorspace;
1515 mf.code = xlate->code;
1516
1517 ret = v4l2_subdev_call(sd, video, try_mbus_fmt, &mf);
1518 if (ret < 0)
1519 return ret;
1520
1521 pix->width = mf.width;
1522 pix->height = mf.height;
1523 pix->colorspace = mf.colorspace;
1524
1525 switch (mf.field) {
1526 case V4L2_FIELD_ANY:
1527 case V4L2_FIELD_NONE:
1528 pix->field = V4L2_FIELD_NONE;
1529 break;
1530 default:
1531 /* TODO: support interlaced at least in pass-through mode */
1532 dev_err(icd->dev.parent, "Field type %d unsupported.\n",
1533 mf.field);
1534 return -EINVAL;
1535 }
1536
1537 return ret;
1538 }
1539
1540 static int pxa_camera_reqbufs(struct soc_camera_file *icf,
1541 struct v4l2_requestbuffers *p)
1542 {
1543 int i;
1544
1545 /*
1546 * This is for locking debugging only. I removed spinlocks and now I
1547 * check whether .prepare is ever called on a linked buffer, or whether
1548 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
1549 * it hadn't triggered
1550 */
1551 for (i = 0; i < p->count; i++) {
1552 struct pxa_buffer *buf = container_of(icf->vb_vidq.bufs[i],
1553 struct pxa_buffer, vb);
1554 buf->inwork = 0;
1555 INIT_LIST_HEAD(&buf->vb.queue);
1556 }
1557
1558 return 0;
1559 }
1560
1561 static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
1562 {
1563 struct soc_camera_file *icf = file->private_data;
1564 struct pxa_buffer *buf;
1565
1566 buf = list_entry(icf->vb_vidq.stream.next, struct pxa_buffer,
1567 vb.stream);
1568
1569 poll_wait(file, &buf->vb.done, pt);
1570
1571 if (buf->vb.state == VIDEOBUF_DONE ||
1572 buf->vb.state == VIDEOBUF_ERROR)
1573 return POLLIN|POLLRDNORM;
1574
1575 return 0;
1576 }
1577
1578 static int pxa_camera_querycap(struct soc_camera_host *ici,
1579 struct v4l2_capability *cap)
1580 {
1581 /* cap->name is set by the firendly caller:-> */
1582 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1583 cap->version = PXA_CAM_VERSION_CODE;
1584 cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1585
1586 return 0;
1587 }
1588
1589 static int pxa_camera_suspend(struct soc_camera_device *icd, pm_message_t state)
1590 {
1591 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1592 struct pxa_camera_dev *pcdev = ici->priv;
1593 int i = 0, ret = 0;
1594
1595 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
1596 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
1597 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
1598 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
1599 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
1600
1601 if ((pcdev->icd) && (pcdev->icd->ops->suspend))
1602 ret = pcdev->icd->ops->suspend(pcdev->icd, state);
1603
1604 return ret;
1605 }
1606
1607 static int pxa_camera_resume(struct soc_camera_device *icd)
1608 {
1609 struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
1610 struct pxa_camera_dev *pcdev = ici->priv;
1611 int i = 0, ret = 0;
1612
1613 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1614 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1615 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1616
1617 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
1618 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
1619 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
1620 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
1621 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
1622
1623 if ((pcdev->icd) && (pcdev->icd->ops->resume))
1624 ret = pcdev->icd->ops->resume(pcdev->icd);
1625
1626 /* Restart frame capture if active buffer exists */
1627 if (!ret && pcdev->active)
1628 pxa_camera_start_capture(pcdev);
1629
1630 return ret;
1631 }
1632
1633 static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1634 .owner = THIS_MODULE,
1635 .add = pxa_camera_add_device,
1636 .remove = pxa_camera_remove_device,
1637 .suspend = pxa_camera_suspend,
1638 .resume = pxa_camera_resume,
1639 .set_crop = pxa_camera_set_crop,
1640 .get_formats = pxa_camera_get_formats,
1641 .put_formats = pxa_camera_put_formats,
1642 .set_fmt = pxa_camera_set_fmt,
1643 .try_fmt = pxa_camera_try_fmt,
1644 .init_videobuf = pxa_camera_init_videobuf,
1645 .reqbufs = pxa_camera_reqbufs,
1646 .poll = pxa_camera_poll,
1647 .querycap = pxa_camera_querycap,
1648 .set_bus_param = pxa_camera_set_bus_param,
1649 };
1650
1651 static int __devinit pxa_camera_probe(struct platform_device *pdev)
1652 {
1653 struct pxa_camera_dev *pcdev;
1654 struct resource *res;
1655 void __iomem *base;
1656 int irq;
1657 int err = 0;
1658
1659 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1660 irq = platform_get_irq(pdev, 0);
1661 if (!res || irq < 0) {
1662 err = -ENODEV;
1663 goto exit;
1664 }
1665
1666 pcdev = kzalloc(sizeof(*pcdev), GFP_KERNEL);
1667 if (!pcdev) {
1668 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1669 err = -ENOMEM;
1670 goto exit;
1671 }
1672
1673 pcdev->clk = clk_get(&pdev->dev, NULL);
1674 if (IS_ERR(pcdev->clk)) {
1675 err = PTR_ERR(pcdev->clk);
1676 goto exit_kfree;
1677 }
1678
1679 pcdev->res = res;
1680
1681 pcdev->pdata = pdev->dev.platform_data;
1682 pcdev->platform_flags = pcdev->pdata->flags;
1683 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1684 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
1685 /*
1686 * Platform hasn't set available data widths. This is bad.
1687 * Warn and use a default.
1688 */
1689 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1690 "data widths, using default 10 bit\n");
1691 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1692 }
1693 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
1694 if (!pcdev->mclk) {
1695 dev_warn(&pdev->dev,
1696 "mclk == 0! Please, fix your platform data. "
1697 "Using default 20MHz\n");
1698 pcdev->mclk = 20000000;
1699 }
1700
1701 pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
1702
1703 INIT_LIST_HEAD(&pcdev->capture);
1704 spin_lock_init(&pcdev->lock);
1705
1706 /*
1707 * Request the regions.
1708 */
1709 if (!request_mem_region(res->start, resource_size(res),
1710 PXA_CAM_DRV_NAME)) {
1711 err = -EBUSY;
1712 goto exit_clk;
1713 }
1714
1715 base = ioremap(res->start, resource_size(res));
1716 if (!base) {
1717 err = -ENOMEM;
1718 goto exit_release;
1719 }
1720 pcdev->irq = irq;
1721 pcdev->base = base;
1722
1723 /* request dma */
1724 err = pxa_request_dma("CI_Y", DMA_PRIO_HIGH,
1725 pxa_camera_dma_irq_y, pcdev);
1726 if (err < 0) {
1727 dev_err(&pdev->dev, "Can't request DMA for Y\n");
1728 goto exit_iounmap;
1729 }
1730 pcdev->dma_chans[0] = err;
1731 dev_dbg(&pdev->dev, "got DMA channel %d\n", pcdev->dma_chans[0]);
1732
1733 err = pxa_request_dma("CI_U", DMA_PRIO_HIGH,
1734 pxa_camera_dma_irq_u, pcdev);
1735 if (err < 0) {
1736 dev_err(&pdev->dev, "Can't request DMA for U\n");
1737 goto exit_free_dma_y;
1738 }
1739 pcdev->dma_chans[1] = err;
1740 dev_dbg(&pdev->dev, "got DMA channel (U) %d\n", pcdev->dma_chans[1]);
1741
1742 err = pxa_request_dma("CI_V", DMA_PRIO_HIGH,
1743 pxa_camera_dma_irq_v, pcdev);
1744 if (err < 0) {
1745 dev_err(&pdev->dev, "Can't request DMA for V\n");
1746 goto exit_free_dma_u;
1747 }
1748 pcdev->dma_chans[2] = err;
1749 dev_dbg(&pdev->dev, "got DMA channel (V) %d\n", pcdev->dma_chans[2]);
1750
1751 DRCMR(68) = pcdev->dma_chans[0] | DRCMR_MAPVLD;
1752 DRCMR(69) = pcdev->dma_chans[1] | DRCMR_MAPVLD;
1753 DRCMR(70) = pcdev->dma_chans[2] | DRCMR_MAPVLD;
1754
1755 /* request irq */
1756 err = request_irq(pcdev->irq, pxa_camera_irq, 0, PXA_CAM_DRV_NAME,
1757 pcdev);
1758 if (err) {
1759 dev_err(&pdev->dev, "Camera interrupt register failed \n");
1760 goto exit_free_dma;
1761 }
1762
1763 pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME;
1764 pcdev->soc_host.ops = &pxa_soc_camera_host_ops;
1765 pcdev->soc_host.priv = pcdev;
1766 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1767 pcdev->soc_host.nr = pdev->id;
1768
1769 err = soc_camera_host_register(&pcdev->soc_host);
1770 if (err)
1771 goto exit_free_irq;
1772
1773 return 0;
1774
1775 exit_free_irq:
1776 free_irq(pcdev->irq, pcdev);
1777 exit_free_dma:
1778 pxa_free_dma(pcdev->dma_chans[2]);
1779 exit_free_dma_u:
1780 pxa_free_dma(pcdev->dma_chans[1]);
1781 exit_free_dma_y:
1782 pxa_free_dma(pcdev->dma_chans[0]);
1783 exit_iounmap:
1784 iounmap(base);
1785 exit_release:
1786 release_mem_region(res->start, resource_size(res));
1787 exit_clk:
1788 clk_put(pcdev->clk);
1789 exit_kfree:
1790 kfree(pcdev);
1791 exit:
1792 return err;
1793 }
1794
1795 static int __devexit pxa_camera_remove(struct platform_device *pdev)
1796 {
1797 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1798 struct pxa_camera_dev *pcdev = container_of(soc_host,
1799 struct pxa_camera_dev, soc_host);
1800 struct resource *res;
1801
1802 clk_put(pcdev->clk);
1803
1804 pxa_free_dma(pcdev->dma_chans[0]);
1805 pxa_free_dma(pcdev->dma_chans[1]);
1806 pxa_free_dma(pcdev->dma_chans[2]);
1807 free_irq(pcdev->irq, pcdev);
1808
1809 soc_camera_host_unregister(soc_host);
1810
1811 iounmap(pcdev->base);
1812
1813 res = pcdev->res;
1814 release_mem_region(res->start, resource_size(res));
1815
1816 kfree(pcdev);
1817
1818 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
1819
1820 return 0;
1821 }
1822
1823 static struct platform_driver pxa_camera_driver = {
1824 .driver = {
1825 .name = PXA_CAM_DRV_NAME,
1826 },
1827 .probe = pxa_camera_probe,
1828 .remove = __devexit_p(pxa_camera_remove),
1829 };
1830
1831
1832 static int __init pxa_camera_init(void)
1833 {
1834 return platform_driver_register(&pxa_camera_driver);
1835 }
1836
1837 static void __exit pxa_camera_exit(void)
1838 {
1839 platform_driver_unregister(&pxa_camera_driver);
1840 }
1841
1842 module_init(pxa_camera_init);
1843 module_exit(pxa_camera_exit);
1844
1845 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1846 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1847 MODULE_LICENSE("GPL");
1848 MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);