2 * Copyright (C) 2011, 2012 glevand <geoffrey.levand@mail.ru>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/types.h>
37 #include <sys/ioctl.h>
40 #include <sys/consio.h>
44 #include "ps3gpu_ctl.h"
45 #include "ps3gpu_mth.h"
46 #include "reset_gpu_state.h"
49 #define PS3GPU_DEV_PATH "/dev/ps3gpu"
51 #define DISPLAY_WIDTH 1920
52 #define DISPLAY_HEIGHT 1080
54 #define DISPLAY_PITCH (DISPLAY_WIDTH * DISPLAY_BPP)
57 main(int argc
, char **argv
)
59 struct ps3gpu_ctl_context_allocate context_allocate
;
60 struct ps3gpu_ctl_context_free context_free
;
61 struct ps3gpu_ctl_memory_allocate memory_allocate
;
62 struct ps3gpu_ctl_setup_control setup_control
;
63 struct ps3gpu_ctl_flip flip
;
65 volatile uint32_t *control
;
66 uint32_t *fifo
, *reset_gpu
, *vram
, *gart
;
67 unsigned long fifo_handle
, vram_handle
, gart_handle
;
68 unsigned int fifo_gaddr
, reset_gpu_gaddr
, vram_gaddr
, gart_gaddr
;
76 fd
= open(PS3GPU_DEV_PATH
, O_RDWR
);
82 /* Create GPU context */
84 context_allocate
.vram_size
= 64; /* MB */
86 err
= ioctl(fd
, PS3GPU_CTL_CONTEXT_ALLOCATE
, &context_allocate
);
92 context_id
= context_allocate
.context_id
;
94 printf("context id %d\n", context_id
);
95 printf("control handle 0x%lx size %d\n",
96 context_allocate
.control_handle
, context_allocate
.control_size
);
98 /* Map control registers */
100 control
= mmap(NULL
, context_allocate
.control_size
,
101 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, context_allocate
.control_handle
);
102 if (control
== (void *) MAP_FAILED
) {
109 memory_allocate
.context_id
= context_id
;
110 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_GART
;
111 memory_allocate
.size
= 64 * 1024;
112 memory_allocate
.align
= 12;
114 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
120 fifo_handle
= memory_allocate
.handle
;
121 fifo_gaddr
= memory_allocate
.gpu_addr
;
123 printf("fifo handle 0x%lx gpu addr 0x08%x\n",
124 fifo_handle
, fifo_gaddr
);
128 fifo
= mmap(NULL
, memory_allocate
.size
,
129 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, fifo_handle
);
130 if (fifo
== (void *) MAP_FAILED
) {
137 setup_control
.context_id
= context_id
;
138 setup_control
.put
= fifo_handle
;
139 setup_control
.get
= fifo_handle
;
140 setup_control
.ref
= 0xdeadbabe;
142 err
= ioctl(fd
, PS3GPU_CTL_SETUP_CONTROL
, &setup_control
);
148 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
149 control
[0x10], control
[0x11], control
[0x12]);
151 /* Allocate FIFO for resetting GPU state */
153 memory_allocate
.context_id
= context_id
;
154 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_GART
;
155 memory_allocate
.size
= 8 * 1024;
156 memory_allocate
.align
= 12;
158 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
164 reset_gpu_gaddr
= memory_allocate
.gpu_addr
;
166 printf("reset GPU state handle 0x%lx gpu addr 0x%08x\n",
167 memory_allocate
.handle
, reset_gpu_gaddr
);
169 /* Map FIFO for resetting GPU state */
171 reset_gpu
= mmap(NULL
, memory_allocate
.size
,
172 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, memory_allocate
.handle
);
173 if (reset_gpu
== (void *) MAP_FAILED
) {
178 memcpy(reset_gpu
, reset_gpu_state_3d
, reset_gpu_state_3d_size
);
182 fifo
[0] = PS3GPU_MTH_HDR(0, 0, reset_gpu_gaddr
| PS3GPU_MTH_ADDR_CALL
);
183 fifo
[1] = PS3GPU_MTH_HDR(1, 0, PS3GPU_MTH_ADDR_REF
);
184 fifo
[2] = 0xcafef00d;
186 control
[0x10] = fifo_gaddr
+ 3 * sizeof(uint32_t);
188 while (control
[0x10] != control
[0x11])
191 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
192 control
[0x10], control
[0x11], control
[0x12]);
196 memory_allocate
.context_id
= context_id
;
197 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_VIDEO
;
198 memory_allocate
.size
= 9 * 1024 * 1024;
199 memory_allocate
.align
= 12;
201 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
207 vram_handle
= memory_allocate
.handle
;
208 vram_gaddr
= memory_allocate
.gpu_addr
;
210 printf("VRAM handle 0x%lx gpu addr 0x%08x\n",
211 vram_handle
, vram_gaddr
);
215 vram
= mmap(NULL
, memory_allocate
.size
,
216 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, vram_handle
);
217 if (vram
== (void *) MAP_FAILED
) {
222 memset(vram
, 0x40, memory_allocate
.size
);
226 flip
.context_id
= context_id
;
227 flip
.head
= PS3GPU_CTL_HEAD_A
;
228 flip
.offset
= vram_handle
;
230 err
= ioctl(fd
, PS3GPU_CTL_FLIP
, &flip
);
236 flip
.context_id
= context_id
;
237 flip
.head
= PS3GPU_CTL_HEAD_B
;
238 flip
.offset
= vram_handle
;
240 err
= ioctl(fd
, PS3GPU_CTL_FLIP
, &flip
);
250 memory_allocate
.context_id
= context_id
;
251 memory_allocate
.type
= PS3GPU_CTL_MEMORY_TYPE_GART
;
252 memory_allocate
.size
= 1024 * 1024;
253 memory_allocate
.align
= 12;
255 err
= ioctl(fd
, PS3GPU_CTL_MEMORY_ALLOCATE
, &memory_allocate
);
261 gart_handle
= memory_allocate
.handle
;
262 gart_gaddr
= memory_allocate
.gpu_addr
;
264 printf("GART handle 0x%lx gpu addr 0x%08x\n",
265 gart_handle
, gart_gaddr
);
269 gart
= mmap(NULL
, memory_allocate
.size
,
270 PROT_READ
| PROT_WRITE
, MAP_SHARED
, fd
, gart_handle
);
271 if (gart
== (void *) MAP_FAILED
) {
281 for (y
= 0; y
< h
; y
++) {
282 for (x
= 0; x
< w
; x
++) {
284 gart
[y
* w
+ x
] = 0x0000ff00;
286 gart
[y
* w
+ x
] = 0xffffff00;
290 setup_control
.context_id
= context_id
;
291 setup_control
.put
= fifo_handle
;
292 setup_control
.get
= fifo_handle
;
293 setup_control
.ref
= 0xdeadbabe;
295 err
= ioctl(fd
, PS3GPU_CTL_SETUP_CONTROL
, &setup_control
);
304 err
= transfer_data(fifo
, 0xfeed0001, 0xfeed0000,
305 vram_gaddr
+ y
* DISPLAY_PITCH
+ x
* DISPLAY_BPP
, DISPLAY_PITCH
,
306 gart_gaddr
+ 0, w
* DISPLAY_BPP
,
312 err
+= transfer_data(fifo
+ err
, 0xfeed0001, 0xfeed0000,
313 vram_gaddr
+ y
* DISPLAY_PITCH
+ x
* DISPLAY_BPP
, DISPLAY_PITCH
,
314 gart_gaddr
+ 0, w
* DISPLAY_BPP
,
317 control
[0x10] = fifo_gaddr
+ err
* sizeof(uint32_t);
319 while (control
[0x10] != control
[0x11])
322 printf("FIFO put 0x%08x get 0x%08x ref 0x%08x\n",
323 control
[0x10], control
[0x11], control
[0x12]);
326 * convert -depth 8 -size 1920x1080 rgba:image.argb \
327 * -color-matrix "0 1 0 0, 0 0 1 0, 0 0 0 1, 1 0 0 0" \
328 * -alpha off -background black -flatten image.jpg
331 save_image("image.argb", (const char *) vram
, DISPLAY_PITCH
* DISPLAY_HEIGHT
);
335 /* Destroy GPU context */
337 context_free
.context_id
= context_id
;
339 err
= ioctl(fd
, PS3GPU_CTL_CONTEXT_FREE
, &context_free
);
350 /* Restore console */
352 ioctl(0, SW_TEXT_80x25
, NULL
);