drivers/ide/pci/cy82c693.c

   1 /*
   2  * linux/drivers/ide/pci/cy82c693.c             Version 0.40    Sep. 10, 2002
   3  *
   4  *  Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
   5  *  Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
   6  *
   7  * CYPRESS CY82C693 chipset IDE controller
   8  *
   9  * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
  10  * Writing the driver was quite simple, since most of the job is
  11  * done by the generic pci-ide support.
  12  * The hard part was finding the CY82C693's datasheet on Cypress's
  13  * web page :-(. But Altavista solved this problem :-).
  14  *
  15  *
  16  * Notes:
  17  * - I recently got a 16.8G IBM DTTA, so I was able to test it with
  18  *   a large and fast disk - the results look great, so I'd say the
  19  *   driver is working fine :-)
  20  *   hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
  21  * - this is my first linux driver, so there's probably a lot  of room
  22  *   for optimizations and bug fixing, so feel free to do it.
  23  * - use idebus=xx parameter to set PCI bus speed - needed to calc
  24  *   timings for PIO modes (default will be 40)
  25  * - if using PIO mode it's a good idea to set the PIO mode and
  26  *   32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
  27  * - I had some problems with my IBM DHEA with PIO modes < 2
  28  *   (lost interrupts) ?????
  29  * - first tests with DMA look okay, they seem to work, but there is a
  30  *   problem with sound - the BusMaster IDE TimeOut should fixed this
  31  *
  32  * Ancient History:
  33  * AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
  34  * ASK@1999-01-23: v0.33 made a few minor code clean ups
  35  *                       removed DMA clock speed setting by default
  36  *                       added boot message
  37  * ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
  38  *                       added support to set DMA Controller Clock Speed
  39  * ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes
  40  *                       on some drives.
  41  * ASK@1998-10-29: v0.3 added support to set DMA modes
  42  * ASK@1998-10-28: v0.2 added support to set PIO modes
  43  * ASK@1998-10-27: v0.1 first version - chipset detection
  44  *
  45  */
  46
  47 #include <linux/module.h>
  48 #include <linux/types.h>
  49 #include <linux/pci.h>
  50 #include <linux/delay.h>
  51 #include <linux/ide.h>
  52 #include <linux/init.h>
  53
  54 #include <asm/io.h>
  55
  56 /* the current version */
  57 #define CY82_VERSION    "CY82C693U driver v0.34 99-13-12 Andreas S. Krebs (akrebs@altavista.net)"
  58
  59 /*
  60  *      The following are used to debug the driver.
  61  */
  62 #define CY82C693_DEBUG_LOGS     0
  63 #define CY82C693_DEBUG_INFO     0
  64
  65 /* define CY82C693_SETDMA_CLOCK to set DMA Controller Clock Speed to ATCLK */
  66 #undef CY82C693_SETDMA_CLOCK
  67
  68 /*
  69  *      NOTE: the value for busmaster timeout is tricky and I got it by
  70  *      trial and error!  By using a to low value will cause DMA timeouts
  71  *      and drop IDE performance, and by using a to high value will cause
  72  *      audio playback to scatter.
  73  *      If you know a better value or how to calc it, please let me know.
  74  */
  75
  76 /* twice the value written in cy82c693ub datasheet */
  77 #define BUSMASTER_TIMEOUT       0x50
  78 /*
  79  * the value above was tested on my machine and it seems to work okay
  80  */
  81
  82 /* here are the offset definitions for the registers */
  83 #define CY82_IDE_CMDREG         0x04
  84 #define CY82_IDE_ADDRSETUP      0x48
  85 #define CY82_IDE_MASTER_IOR     0x4C
  86 #define CY82_IDE_MASTER_IOW     0x4D
  87 #define CY82_IDE_SLAVE_IOR      0x4E
  88 #define CY82_IDE_SLAVE_IOW      0x4F
  89 #define CY82_IDE_MASTER_8BIT    0x50
  90 #define CY82_IDE_SLAVE_8BIT     0x51
  91
  92 #define CY82_INDEX_PORT         0x22
  93 #define CY82_DATA_PORT          0x23
  94
  95 #define CY82_INDEX_CTRLREG1     0x01
  96 #define CY82_INDEX_CHANNEL0     0x30
  97 #define CY82_INDEX_CHANNEL1     0x31
  98 #define CY82_INDEX_TIMEOUT      0x32
  99
 100 /* the min and max PCI bus speed in MHz - from datasheet */
 101 #define CY82C963_MIN_BUS_SPEED  25
 102 #define CY82C963_MAX_BUS_SPEED  33
 103
 104 /* the struct for the PIO mode timings */
 105 typedef struct pio_clocks_s {
 106         u8      address_time;   /* Address setup (clocks) */
 107         u8      time_16r;       /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
 108         u8      time_16w;       /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
 109         u8      time_8;         /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
 110 } pio_clocks_t;
 111
 112 /*
 113  * calc clocks using bus_speed
 114  * returns (rounded up) time in bus clocks for time in ns
 115  */
 116 static int calc_clk (int time, int bus_speed)
 117 {
 118         int clocks;
 119
 120         clocks = (time*bus_speed+999)/1000 -1;
 121
 122         if (clocks < 0)
 123                 clocks = 0;
 124
 125         if (clocks > 0x0F)
 126                 clocks = 0x0F;
 127
 128         return clocks;
 129 }
 130
 131 /*
 132  * compute the values for the clock registers for PIO
 133  * mode and pci_clk [MHz] speed
 134  *
 135  * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
 136  *       for mode 3 and 4 drives 8 and 16-bit timings are the same
 137  *
 138  */
 139 static void compute_clocks (u8 pio, pio_clocks_t *p_pclk)
 140 {
 141         int clk1, clk2;
 142         int bus_speed = system_bus_clock();     /* get speed of PCI bus */
 143
 144         /* we don't check against CY82C693's min and max speed,
 145          * so you can play with the idebus=xx parameter
 146          */
 147
 148         /* let's calc the address setup time clocks */
 149         p_pclk->address_time = (u8)calc_clk(ide_pio_timings[pio].setup_time, bus_speed);
 150
 151         /* let's calc the active and recovery time clocks */
 152         clk1 = calc_clk(ide_pio_timings[pio].active_time, bus_speed);
 153
 154         /* calc recovery timing */
 155         clk2 =  ide_pio_timings[pio].cycle_time -
 156                 ide_pio_timings[pio].active_time -
 157                 ide_pio_timings[pio].setup_time;
 158
 159         clk2 = calc_clk(clk2, bus_speed);
 160
 161         clk1 = (clk1<<4)|clk2;  /* combine active and recovery clocks */
 162
 163         /* note: we use the same values for 16bit IOR and IOW
 164          *      those are all the same, since I don't have other
 165          *      timings than those from ide-lib.c
 166          */
 167
 168         p_pclk->time_16r = (u8)clk1;
 169         p_pclk->time_16w = (u8)clk1;
 170
 171         /* what are good values for 8bit ?? */
 172         p_pclk->time_8 = (u8)clk1;
 173 }
 174
 175 /*
 176  * set DMA mode a specific channel for CY82C693
 177  */
 178
 179 static void cy82c693_dma_enable (ide_drive_t *drive, int mode, int single)
 180 {
 181         u8 index = 0, data = 0;
 182
 183         if (mode>2)     /* make sure we set a valid mode */
 184                 mode = 2;
 185
 186         if (mode > drive->id->tDMA)  /* to be absolutly sure we have a valid mode */
 187                 mode = drive->id->tDMA;
 188
 189         index = (HWIF(drive)->channel==0) ? CY82_INDEX_CHANNEL0 : CY82_INDEX_CHANNEL1;
 190
 191 #if CY82C693_DEBUG_LOGS
 192         /* for debug let's show the previous values */
 193
 194         outb(index, CY82_INDEX_PORT);
 195         data = inb(CY82_DATA_PORT);
 196
 197         printk (KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n",
 198                 drive->name, HWIF(drive)->channel, drive->select.b.unit,
 199                 (data&0x3), ((data>>2)&1));
 200 #endif /* CY82C693_DEBUG_LOGS */
 201
 202         data = (u8)mode|(u8)(single<<2);
 203
 204         outb(index, CY82_INDEX_PORT);
 205         outb(data, CY82_DATA_PORT);
 206
 207 #if CY82C693_DEBUG_INFO
 208         printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
 209                 drive->name, HWIF(drive)->channel, drive->select.b.unit,
 210                 mode, single);
 211 #endif /* CY82C693_DEBUG_INFO */
 212
 213         /*
 214          * note: below we set the value for Bus Master IDE TimeOut Register
 215          * I'm not absolutly sure what this does, but it solved my problem
 216          * with IDE DMA and sound, so I now can play sound and work with
 217          * my IDE driver at the same time :-)
 218          *
 219          * If you know the correct (best) value for this register please
 220          * let me know - ASK
 221          */
 222
 223         data = BUSMASTER_TIMEOUT;
 224         outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
 225         outb(data, CY82_DATA_PORT);
 226
 227 #if CY82C693_DEBUG_INFO
 228         printk (KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
 229                 drive->name, data);
 230 #endif /* CY82C693_DEBUG_INFO */
 231 }
 232
 233 /*
 234  * used to set DMA mode for CY82C693 (single and multi modes)
 235  */
 236 static int cy82c693_ide_dma_on (ide_drive_t *drive)
 237 {
 238         struct hd_driveid *id = drive->id;
 239
 240 #if CY82C693_DEBUG_INFO
 241         printk (KERN_INFO "dma_on: %s\n", drive->name);
 242 #endif /* CY82C693_DEBUG_INFO */
 243
 244         if (id != NULL) {
 245                 /* Enable DMA on any drive that has DMA
 246                  * (multi or single) enabled
 247                  */
 248                 if (id->field_valid & 2) {      /* regular DMA */
 249                         int mmode, smode;
 250
 251                         mmode = id->dma_mword & (id->dma_mword >> 8);
 252                         smode = id->dma_1word & (id->dma_1word >> 8);
 253
 254                         if (mmode != 0) {
 255                                 /* enable multi */
 256                                 cy82c693_dma_enable(drive, (mmode >> 1), 0);
 257                         } else if (smode != 0) {
 258                                 /* enable single */
 259                                 cy82c693_dma_enable(drive, (smode >> 1), 1);
 260                         }
 261                 }
 262         }
 263         return __ide_dma_on(drive);
 264 }
 265
 266 static void cy82c693_set_pio_mode(ide_drive_t *drive, const u8 pio)
 267 {
 268         ide_hwif_t *hwif = HWIF(drive);
 269         struct pci_dev *dev = hwif->pci_dev;
 270         pio_clocks_t pclk;
 271         unsigned int addrCtrl;
 272
 273         /* select primary or secondary channel */
 274         if (hwif->index > 0) {  /* drive is on the secondary channel */
 275                 dev = pci_get_slot(dev->bus, dev->devfn+1);
 276                 if (!dev) {
 277                         printk(KERN_ERR "%s: tune_drive: "
 278                                 "Cannot find secondary interface!\n",
 279                                 drive->name);
 280                         return;
 281                 }
 282         }
 283
 284 #if CY82C693_DEBUG_LOGS
 285         /* for debug let's show the register values */
 286
 287         if (drive->select.b.unit == 0) {
 288                 /*
 289                  * get master drive registers
 290                  * address setup control register
 291                  * is 32 bit !!!
 292                  */
 293                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 294                 addrCtrl &= 0x0F;
 295
 296                 /* now let's get the remaining registers */
 297                 pci_read_config_byte(dev, CY82_IDE_MASTER_IOR, &pclk.time_16r);
 298                 pci_read_config_byte(dev, CY82_IDE_MASTER_IOW, &pclk.time_16w);
 299                 pci_read_config_byte(dev, CY82_IDE_MASTER_8BIT, &pclk.time_8);
 300         } else {
 301                 /*
 302                  * set slave drive registers
 303                  * address setup control register
 304                  * is 32 bit !!!
 305                  */
 306                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 307
 308                 addrCtrl &= 0xF0;
 309                 addrCtrl >>= 4;
 310
 311                 /* now let's get the remaining registers */
 312                 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOR, &pclk.time_16r);
 313                 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOW, &pclk.time_16w);
 314                 pci_read_config_byte(dev, CY82_IDE_SLAVE_8BIT, &pclk.time_8);
 315         }
 316
 317         printk(KERN_INFO "%s (ch=%d, dev=%d): PIO timing is "
 318                 "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
 319                 drive->name, hwif->channel, drive->select.b.unit,
 320                 addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
 321 #endif /* CY82C693_DEBUG_LOGS */
 322
 323         /* let's calc the values for this PIO mode */
 324         compute_clocks(pio, &pclk);
 325
 326         /* now let's write  the clocks registers */
 327         if (drive->select.b.unit == 0) {
 328                 /*
 329                  * set master drive
 330                  * address setup control register
 331                  * is 32 bit !!!
 332                  */
 333                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 334
 335                 addrCtrl &= (~0xF);
 336                 addrCtrl |= (unsigned int)pclk.address_time;
 337                 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
 338
 339                 /* now let's set the remaining registers */
 340                 pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
 341                 pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
 342                 pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);
 343
 344                 addrCtrl &= 0xF;
 345         } else {
 346                 /*
 347                  * set slave drive
 348                  * address setup control register
 349                  * is 32 bit !!!
 350                  */
 351                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 352
 353                 addrCtrl &= (~0xF0);
 354                 addrCtrl |= ((unsigned int)pclk.address_time<<4);
 355                 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
 356
 357                 /* now let's set the remaining registers */
 358                 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
 359                 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
 360                 pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);
 361
 362                 addrCtrl >>= 4;
 363                 addrCtrl &= 0xF;
 364         }
 365
 366 #if CY82C693_DEBUG_INFO
 367         printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to "
 368                 "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
 369                 drive->name, hwif->channel, drive->select.b.unit,
 370                 addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
 371 #endif /* CY82C693_DEBUG_INFO */
 372 }
 373
 374 /*
 375  * this function is called during init and is used to setup the cy82c693 chip
 376  */
 377 static unsigned int __devinit init_chipset_cy82c693(struct pci_dev *dev, const char *name)
 378 {
 379         if (PCI_FUNC(dev->devfn) != 1)
 380                 return 0;
 381
 382 #ifdef CY82C693_SETDMA_CLOCK
 383         u8 data = 0;
 384 #endif /* CY82C693_SETDMA_CLOCK */
 385
 386         /* write info about this verion of the driver */
 387         printk(KERN_INFO CY82_VERSION "\n");
 388
 389 #ifdef CY82C693_SETDMA_CLOCK
 390        /* okay let's set the DMA clock speed */
 391
 392         outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
 393         data = inb(CY82_DATA_PORT);
 394
 395 #if CY82C693_DEBUG_INFO
 396         printk(KERN_INFO "%s: Peripheral Configuration Register: 0x%X\n",
 397                 name, data);
 398 #endif /* CY82C693_DEBUG_INFO */
 399
 400         /*
 401          * for some reason sometimes the DMA controller
 402          * speed is set to ATCLK/2 ???? - we fix this here
 403          *
 404          * note: i don't know what causes this strange behaviour,
 405          *       but even changing the dma speed doesn't solve it :-(
 406          *       the ide performance is still only half the normal speed
 407          *
 408          *       if anybody knows what goes wrong with my machine, please
 409          *       let me know - ASK
 410          */
 411
 412         data |= 0x03;
 413
 414         outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
 415         outb(data, CY82_DATA_PORT);
 416
 417 #if CY82C693_DEBUG_INFO
 418         printk (KERN_INFO "%s: New Peripheral Configuration Register: 0x%X\n",
 419                 name, data);
 420 #endif /* CY82C693_DEBUG_INFO */
 421
 422 #endif /* CY82C693_SETDMA_CLOCK */
 423         return 0;
 424 }
 425
 426 /*
 427  * the init function - called for each ide channel once
 428  */
 429 static void __devinit init_hwif_cy82c693(ide_hwif_t *hwif)
 430 {
 431         hwif->chipset = ide_cy82c693;
 432         hwif->set_pio_mode = &cy82c693_set_pio_mode;
 433
 434         if (!hwif->dma_base) {
 435                 hwif->drives[0].autotune = 1;
 436                 hwif->drives[1].autotune = 1;
 437                 return;
 438         }
 439
 440         hwif->atapi_dma = 1;
 441         hwif->mwdma_mask = 0x04;
 442         hwif->swdma_mask = 0x04;
 443
 444         hwif->ide_dma_on = &cy82c693_ide_dma_on;
 445 }
 446
 447 static __devinitdata ide_hwif_t *primary;
 448
 449 static void __devinit init_iops_cy82c693(ide_hwif_t *hwif)
 450 {
 451         if (PCI_FUNC(hwif->pci_dev->devfn) == 1)
 452                 primary = hwif;
 453         else {
 454                 hwif->mate = primary;
 455                 hwif->channel = 1;
 456         }
 457 }
 458
 459 static ide_pci_device_t cy82c693_chipset __devinitdata = {
 460         .name           = "CY82C693",
 461         .init_chipset   = init_chipset_cy82c693,
 462         .init_iops      = init_iops_cy82c693,
 463         .init_hwif      = init_hwif_cy82c693,
 464         .autodma        = AUTODMA,
 465         .bootable       = ON_BOARD,
 466         .host_flags     = IDE_HFLAG_SINGLE | IDE_HFLAG_TRUST_BIOS_FOR_DMA,
 467         .pio_mask       = ATA_PIO4,
 468 };
 469
 470 static int __devinit cy82c693_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 471 {
 472         struct pci_dev *dev2;
 473         int ret = -ENODEV;
 474
 475         /* CY82C693 is more than only a IDE controller.
 476            Function 1 is primary IDE channel, function 2 - secondary. */
 477         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
 478             PCI_FUNC(dev->devfn) == 1) {
 479                 dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
 480                 ret = ide_setup_pci_devices(dev, dev2, &cy82c693_chipset);
 481                 /* We leak pci refs here but thats ok - we can't be unloaded */
 482         }
 483         return ret;
 484 }
 485
 486 static const struct pci_device_id cy82c693_pci_tbl[] = {
 487         { PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 },
 488         { 0, },
 489 };
 490 MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);
 491
 492 static struct pci_driver driver = {
 493         .name           = "Cypress_IDE",
 494         .id_table       = cy82c693_pci_tbl,
 495         .probe          = cy82c693_init_one,
 496 };
 497
 498 static int __init cy82c693_ide_init(void)
 499 {
 500         return ide_pci_register_driver(&driver);
 501 }
 502
 503 module_init(cy82c693_ide_init);
 504
 505 MODULE_AUTHOR("Andreas Krebs, Andre Hedrick");
 506 MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
 507 MODULE_LICENSE("GPL");