drivers/ide/pci/cy82c693.c

   1 /*
   2  * linux/drivers/ide/pci/cy82c693.c             Version 0.40    Sep. 10, 2002
   3  *
   4  *  Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
   5  *  Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
   6  *
   7  * CYPRESS CY82C693 chipset IDE controller
   8  *
   9  * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
  10  * Writing the driver was quite simple, since most of the job is
  11  * done by the generic pci-ide support.
  12  * The hard part was finding the CY82C693's datasheet on Cypress's
  13  * web page :-(. But Altavista solved this problem :-).
  14  *
  15  *
  16  * Notes:
  17  * - I recently got a 16.8G IBM DTTA, so I was able to test it with
  18  *   a large and fast disk - the results look great, so I'd say the
  19  *   driver is working fine :-)
  20  *   hdparm -t reports 8.17 MB/sec at about 6% CPU usage for the DTTA
  21  * - this is my first linux driver, so there's probably a lot  of room
  22  *   for optimizations and bug fixing, so feel free to do it.
  23  * - use idebus=xx parameter to set PCI bus speed - needed to calc
  24  *   timings for PIO modes (default will be 40)
  25  * - if using PIO mode it's a good idea to set the PIO mode and
  26  *   32-bit I/O support (if possible), e.g. hdparm -p2 -c1 /dev/hda
  27  * - I had some problems with my IBM DHEA with PIO modes < 2
  28  *   (lost interrupts) ?????
  29  * - first tests with DMA look okay, they seem to work, but there is a
  30  *   problem with sound - the BusMaster IDE TimeOut should fixed this
  31  *
  32  * Ancient History:
  33  * AMH@1999-08-24: v0.34 init_cy82c693_chip moved to pci_init_cy82c693
  34  * ASK@1999-01-23: v0.33 made a few minor code clean ups
  35  *                       removed DMA clock speed setting by default
  36  *                       added boot message
  37  * ASK@1998-11-01: v0.32 added support to set BusMaster IDE TimeOut
  38  *                       added support to set DMA Controller Clock Speed
  39  * ASK@1998-10-31: v0.31 fixed problem with setting to high DMA modes
  40  *                       on some drives.
  41  * ASK@1998-10-29: v0.3 added support to set DMA modes
  42  * ASK@1998-10-28: v0.2 added support to set PIO modes
  43  * ASK@1998-10-27: v0.1 first version - chipset detection
  44  *
  45  */
  46
  47 #include <linux/module.h>
  48 #include <linux/types.h>
  49 #include <linux/pci.h>
  50 #include <linux/delay.h>
  51 #include <linux/ide.h>
  52 #include <linux/init.h>
  53
  54 #include <asm/io.h>
  55
  56 /* the current version */
  57 #define CY82_VERSION    "CY82C693U driver v0.34 99-13-12 Andreas S. Krebs (akrebs@altavista.net)"
  58
  59 /*
  60  *      The following are used to debug the driver.
  61  */
  62 #define CY82C693_DEBUG_LOGS     0
  63 #define CY82C693_DEBUG_INFO     0
  64
  65 /* define CY82C693_SETDMA_CLOCK to set DMA Controller Clock Speed to ATCLK */
  66 #undef CY82C693_SETDMA_CLOCK
  67
  68 /*
  69  *      NOTE: the value for busmaster timeout is tricky and I got it by
  70  *      trial and error!  By using a to low value will cause DMA timeouts
  71  *      and drop IDE performance, and by using a to high value will cause
  72  *      audio playback to scatter.
  73  *      If you know a better value or how to calc it, please let me know.
  74  */
  75
  76 /* twice the value written in cy82c693ub datasheet */
  77 #define BUSMASTER_TIMEOUT       0x50
  78 /*
  79  * the value above was tested on my machine and it seems to work okay
  80  */
  81
  82 /* here are the offset definitions for the registers */
  83 #define CY82_IDE_CMDREG         0x04
  84 #define CY82_IDE_ADDRSETUP      0x48
  85 #define CY82_IDE_MASTER_IOR     0x4C
  86 #define CY82_IDE_MASTER_IOW     0x4D
  87 #define CY82_IDE_SLAVE_IOR      0x4E
  88 #define CY82_IDE_SLAVE_IOW      0x4F
  89 #define CY82_IDE_MASTER_8BIT    0x50
  90 #define CY82_IDE_SLAVE_8BIT     0x51
  91
  92 #define CY82_INDEX_PORT         0x22
  93 #define CY82_DATA_PORT          0x23
  94
  95 #define CY82_INDEX_CTRLREG1     0x01
  96 #define CY82_INDEX_CHANNEL0     0x30
  97 #define CY82_INDEX_CHANNEL1     0x31
  98 #define CY82_INDEX_TIMEOUT      0x32
  99
 100 /* the max PIO mode - from datasheet */
 101 #define CY82C693_MAX_PIO        4
 102
 103 /* the min and max PCI bus speed in MHz - from datasheet */
 104 #define CY82C963_MIN_BUS_SPEED  25
 105 #define CY82C963_MAX_BUS_SPEED  33
 106
 107 /* the struct for the PIO mode timings */
 108 typedef struct pio_clocks_s {
 109         u8      address_time;   /* Address setup (clocks) */
 110         u8      time_16r;       /* clocks for 16bit IOR (0xF0=Active/data, 0x0F=Recovery) */
 111         u8      time_16w;       /* clocks for 16bit IOW (0xF0=Active/data, 0x0F=Recovery) */
 112         u8      time_8;         /* clocks for 8bit (0xF0=Active/data, 0x0F=Recovery) */
 113 } pio_clocks_t;
 114
 115 /*
 116  * calc clocks using bus_speed
 117  * returns (rounded up) time in bus clocks for time in ns
 118  */
 119 static int calc_clk (int time, int bus_speed)
 120 {
 121         int clocks;
 122
 123         clocks = (time*bus_speed+999)/1000 -1;
 124
 125         if (clocks < 0)
 126                 clocks = 0;
 127
 128         if (clocks > 0x0F)
 129                 clocks = 0x0F;
 130
 131         return clocks;
 132 }
 133
 134 /*
 135  * compute the values for the clock registers for PIO
 136  * mode and pci_clk [MHz] speed
 137  *
 138  * NOTE: for mode 0,1 and 2 drives 8-bit IDE command control registers are used
 139  *       for mode 3 and 4 drives 8 and 16-bit timings are the same
 140  *
 141  */
 142 static void compute_clocks (u8 pio, pio_clocks_t *p_pclk)
 143 {
 144         int clk1, clk2;
 145         int bus_speed = system_bus_clock();     /* get speed of PCI bus */
 146
 147         /* we don't check against CY82C693's min and max speed,
 148          * so you can play with the idebus=xx parameter
 149          */
 150
 151         if (pio > CY82C693_MAX_PIO)
 152                 pio = CY82C693_MAX_PIO;
 153
 154         /* let's calc the address setup time clocks */
 155         p_pclk->address_time = (u8)calc_clk(ide_pio_timings[pio].setup_time, bus_speed);
 156
 157         /* let's calc the active and recovery time clocks */
 158         clk1 = calc_clk(ide_pio_timings[pio].active_time, bus_speed);
 159
 160         /* calc recovery timing */
 161         clk2 =  ide_pio_timings[pio].cycle_time -
 162                 ide_pio_timings[pio].active_time -
 163                 ide_pio_timings[pio].setup_time;
 164
 165         clk2 = calc_clk(clk2, bus_speed);
 166
 167         clk1 = (clk1<<4)|clk2;  /* combine active and recovery clocks */
 168
 169         /* note: we use the same values for 16bit IOR and IOW
 170          *      those are all the same, since I don't have other
 171          *      timings than those from ide-lib.c
 172          */
 173
 174         p_pclk->time_16r = (u8)clk1;
 175         p_pclk->time_16w = (u8)clk1;
 176
 177         /* what are good values for 8bit ?? */
 178         p_pclk->time_8 = (u8)clk1;
 179 }
 180
 181 /*
 182  * set DMA mode a specific channel for CY82C693
 183  */
 184
 185 static void cy82c693_dma_enable (ide_drive_t *drive, int mode, int single)
 186 {
 187         u8 index = 0, data = 0;
 188
 189         if (mode>2)     /* make sure we set a valid mode */
 190                 mode = 2;
 191
 192         if (mode > drive->id->tDMA)  /* to be absolutly sure we have a valid mode */
 193                 mode = drive->id->tDMA;
 194
 195         index = (HWIF(drive)->channel==0) ? CY82_INDEX_CHANNEL0 : CY82_INDEX_CHANNEL1;
 196
 197 #if CY82C693_DEBUG_LOGS
 198         /* for debug let's show the previous values */
 199
 200         outb(index, CY82_INDEX_PORT);
 201         data = inb(CY82_DATA_PORT);
 202
 203         printk (KERN_INFO "%s (ch=%d, dev=%d): DMA mode is %d (single=%d)\n",
 204                 drive->name, HWIF(drive)->channel, drive->select.b.unit,
 205                 (data&0x3), ((data>>2)&1));
 206 #endif /* CY82C693_DEBUG_LOGS */
 207
 208         data = (u8)mode|(u8)(single<<2);
 209
 210         outb(index, CY82_INDEX_PORT);
 211         outb(data, CY82_DATA_PORT);
 212
 213 #if CY82C693_DEBUG_INFO
 214         printk(KERN_INFO "%s (ch=%d, dev=%d): set DMA mode to %d (single=%d)\n",
 215                 drive->name, HWIF(drive)->channel, drive->select.b.unit,
 216                 mode, single);
 217 #endif /* CY82C693_DEBUG_INFO */
 218
 219         /*
 220          * note: below we set the value for Bus Master IDE TimeOut Register
 221          * I'm not absolutly sure what this does, but it solved my problem
 222          * with IDE DMA and sound, so I now can play sound and work with
 223          * my IDE driver at the same time :-)
 224          *
 225          * If you know the correct (best) value for this register please
 226          * let me know - ASK
 227          */
 228
 229         data = BUSMASTER_TIMEOUT;
 230         outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
 231         outb(data, CY82_DATA_PORT);
 232
 233 #if CY82C693_DEBUG_INFO
 234         printk (KERN_INFO "%s: Set IDE Bus Master TimeOut Register to 0x%X\n",
 235                 drive->name, data);
 236 #endif /* CY82C693_DEBUG_INFO */
 237 }
 238
 239 /*
 240  * used to set DMA mode for CY82C693 (single and multi modes)
 241  */
 242 static int cy82c693_ide_dma_on (ide_drive_t *drive)
 243 {
 244         struct hd_driveid *id = drive->id;
 245
 246 #if CY82C693_DEBUG_INFO
 247         printk (KERN_INFO "dma_on: %s\n", drive->name);
 248 #endif /* CY82C693_DEBUG_INFO */
 249
 250         if (id != NULL) {
 251                 /* Enable DMA on any drive that has DMA
 252                  * (multi or single) enabled
 253                  */
 254                 if (id->field_valid & 2) {      /* regular DMA */
 255                         int mmode, smode;
 256
 257                         mmode = id->dma_mword & (id->dma_mword >> 8);
 258                         smode = id->dma_1word & (id->dma_1word >> 8);
 259
 260                         if (mmode != 0) {
 261                                 /* enable multi */
 262                                 cy82c693_dma_enable(drive, (mmode >> 1), 0);
 263                         } else if (smode != 0) {
 264                                 /* enable single */
 265                                 cy82c693_dma_enable(drive, (smode >> 1), 1);
 266                         }
 267                 }
 268         }
 269         return __ide_dma_on(drive);
 270 }
 271
 272 /*
 273  * tune ide drive - set PIO mode
 274  */
 275 static void cy82c693_tune_drive (ide_drive_t *drive, u8 pio)
 276 {
 277         ide_hwif_t *hwif = HWIF(drive);
 278         struct pci_dev *dev = hwif->pci_dev;
 279         pio_clocks_t pclk;
 280         unsigned int addrCtrl;
 281
 282         /* select primary or secondary channel */
 283         if (hwif->index > 0) {  /* drive is on the secondary channel */
 284                 dev = pci_get_slot(dev->bus, dev->devfn+1);
 285                 if (!dev) {
 286                         printk(KERN_ERR "%s: tune_drive: "
 287                                 "Cannot find secondary interface!\n",
 288                                 drive->name);
 289                         return;
 290                 }
 291         }
 292
 293 #if CY82C693_DEBUG_LOGS
 294         /* for debug let's show the register values */
 295
 296         if (drive->select.b.unit == 0) {
 297                 /*
 298                  * get master drive registers
 299                  * address setup control register
 300                  * is 32 bit !!!
 301                  */
 302                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 303                 addrCtrl &= 0x0F;
 304
 305                 /* now let's get the remaining registers */
 306                 pci_read_config_byte(dev, CY82_IDE_MASTER_IOR, &pclk.time_16r);
 307                 pci_read_config_byte(dev, CY82_IDE_MASTER_IOW, &pclk.time_16w);
 308                 pci_read_config_byte(dev, CY82_IDE_MASTER_8BIT, &pclk.time_8);
 309         } else {
 310                 /*
 311                  * set slave drive registers
 312                  * address setup control register
 313                  * is 32 bit !!!
 314                  */
 315                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 316
 317                 addrCtrl &= 0xF0;
 318                 addrCtrl >>= 4;
 319
 320                 /* now let's get the remaining registers */
 321                 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOR, &pclk.time_16r);
 322                 pci_read_config_byte(dev, CY82_IDE_SLAVE_IOW, &pclk.time_16w);
 323                 pci_read_config_byte(dev, CY82_IDE_SLAVE_8BIT, &pclk.time_8);
 324         }
 325
 326         printk(KERN_INFO "%s (ch=%d, dev=%d): PIO timing is "
 327                 "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
 328                 drive->name, hwif->channel, drive->select.b.unit,
 329                 addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
 330 #endif /* CY82C693_DEBUG_LOGS */
 331
 332         /* first let's calc the pio modes */
 333         pio = ide_get_best_pio_mode(drive, pio, CY82C693_MAX_PIO, NULL);
 334
 335 #if CY82C693_DEBUG_INFO
 336         printk (KERN_INFO "%s: Selected PIO mode %d\n", drive->name, pio);
 337 #endif /* CY82C693_DEBUG_INFO */
 338
 339         /* let's calc the values for this PIO mode */
 340         compute_clocks(pio, &pclk);
 341
 342         /* now let's write  the clocks registers */
 343         if (drive->select.b.unit == 0) {
 344                 /*
 345                  * set master drive
 346                  * address setup control register
 347                  * is 32 bit !!!
 348                  */
 349                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 350
 351                 addrCtrl &= (~0xF);
 352                 addrCtrl |= (unsigned int)pclk.address_time;
 353                 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
 354
 355                 /* now let's set the remaining registers */
 356                 pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, pclk.time_16r);
 357                 pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, pclk.time_16w);
 358                 pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, pclk.time_8);
 359
 360                 addrCtrl &= 0xF;
 361         } else {
 362                 /*
 363                  * set slave drive
 364                  * address setup control register
 365                  * is 32 bit !!!
 366                  */
 367                 pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
 368
 369                 addrCtrl &= (~0xF0);
 370                 addrCtrl |= ((unsigned int)pclk.address_time<<4);
 371                 pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
 372
 373                 /* now let's set the remaining registers */
 374                 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, pclk.time_16r);
 375                 pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, pclk.time_16w);
 376                 pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, pclk.time_8);
 377
 378                 addrCtrl >>= 4;
 379                 addrCtrl &= 0xF;
 380         }
 381
 382 #if CY82C693_DEBUG_INFO
 383         printk(KERN_INFO "%s (ch=%d, dev=%d): set PIO timing to "
 384                 "(addr=0x%X, ior=0x%X, iow=0x%X, 8bit=0x%X)\n",
 385                 drive->name, hwif->channel, drive->select.b.unit,
 386                 addrCtrl, pclk.time_16r, pclk.time_16w, pclk.time_8);
 387 #endif /* CY82C693_DEBUG_INFO */
 388 }
 389
 390 /*
 391  * this function is called during init and is used to setup the cy82c693 chip
 392  */
 393 static unsigned int __devinit init_chipset_cy82c693(struct pci_dev *dev, const char *name)
 394 {
 395         if (PCI_FUNC(dev->devfn) != 1)
 396                 return 0;
 397
 398 #ifdef CY82C693_SETDMA_CLOCK
 399         u8 data = 0;
 400 #endif /* CY82C693_SETDMA_CLOCK */
 401
 402         /* write info about this verion of the driver */
 403         printk(KERN_INFO CY82_VERSION "\n");
 404
 405 #ifdef CY82C693_SETDMA_CLOCK
 406        /* okay let's set the DMA clock speed */
 407
 408         outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
 409         data = inb(CY82_DATA_PORT);
 410
 411 #if CY82C693_DEBUG_INFO
 412         printk(KERN_INFO "%s: Peripheral Configuration Register: 0x%X\n",
 413                 name, data);
 414 #endif /* CY82C693_DEBUG_INFO */
 415
 416         /*
 417          * for some reason sometimes the DMA controller
 418          * speed is set to ATCLK/2 ???? - we fix this here
 419          *
 420          * note: i don't know what causes this strange behaviour,
 421          *       but even changing the dma speed doesn't solve it :-(
 422          *       the ide performance is still only half the normal speed
 423          *
 424          *       if anybody knows what goes wrong with my machine, please
 425          *       let me know - ASK
 426          */
 427
 428         data |= 0x03;
 429
 430         outb(CY82_INDEX_CTRLREG1, CY82_INDEX_PORT);
 431         outb(data, CY82_DATA_PORT);
 432
 433 #if CY82C693_DEBUG_INFO
 434         printk (KERN_INFO "%s: New Peripheral Configuration Register: 0x%X\n",
 435                 name, data);
 436 #endif /* CY82C693_DEBUG_INFO */
 437
 438 #endif /* CY82C693_SETDMA_CLOCK */
 439         return 0;
 440 }
 441
 442 /*
 443  * the init function - called for each ide channel once
 444  */
 445 static void __devinit init_hwif_cy82c693(ide_hwif_t *hwif)
 446 {
 447         hwif->autodma = 0;
 448
 449         hwif->chipset = ide_cy82c693;
 450         hwif->tuneproc = &cy82c693_tune_drive;
 451
 452         if (!hwif->dma_base) {
 453                 hwif->drives[0].autotune = 1;
 454                 hwif->drives[1].autotune = 1;
 455                 return;
 456         }
 457
 458         hwif->atapi_dma = 1;
 459         hwif->mwdma_mask = 0x04;
 460         hwif->swdma_mask = 0x04;
 461
 462         hwif->ide_dma_on = &cy82c693_ide_dma_on;
 463         if (!noautodma)
 464                 hwif->autodma = 1;
 465         hwif->drives[0].autodma = hwif->autodma;
 466         hwif->drives[1].autodma = hwif->autodma;
 467 }
 468
 469 static __devinitdata ide_hwif_t *primary;
 470
 471 static void __devinit init_iops_cy82c693(ide_hwif_t *hwif)
 472 {
 473         if (PCI_FUNC(hwif->pci_dev->devfn) == 1)
 474                 primary = hwif;
 475         else {
 476                 hwif->mate = primary;
 477                 hwif->channel = 1;
 478         }
 479 }
 480
 481 static ide_pci_device_t cy82c693_chipset __devinitdata = {
 482         .name           = "CY82C693",
 483         .init_chipset   = init_chipset_cy82c693,
 484         .init_iops      = init_iops_cy82c693,
 485         .init_hwif      = init_hwif_cy82c693,
 486         .channels       = 1,
 487         .autodma        = AUTODMA,
 488         .bootable       = ON_BOARD,
 489 };
 490
 491 static int __devinit cy82c693_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 492 {
 493         struct pci_dev *dev2;
 494         int ret = -ENODEV;
 495
 496         /* CY82C693 is more than only a IDE controller.
 497            Function 1 is primary IDE channel, function 2 - secondary. */
 498         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
 499             PCI_FUNC(dev->devfn) == 1) {
 500                 dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
 501                 ret = ide_setup_pci_devices(dev, dev2, &cy82c693_chipset);
 502                 /* We leak pci refs here but thats ok - we can't be unloaded */
 503         }
 504         return ret;
 505 }
 506
 507 static struct pci_device_id cy82c693_pci_tbl[] = {
 508         { PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 509         { 0, },
 510 };
 511 MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);
 512
 513 static struct pci_driver driver = {
 514         .name           = "Cypress_IDE",
 515         .id_table       = cy82c693_pci_tbl,
 516         .probe          = cy82c693_init_one,
 517 };
 518
 519 static int __init cy82c693_ide_init(void)
 520 {
 521         return ide_pci_register_driver(&driver);
 522 }
 523
 524 module_init(cy82c693_ide_init);
 525
 526 MODULE_AUTHOR("Andreas Krebs, Andre Hedrick");
 527 MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
 528 MODULE_LICENSE("GPL");