drivers/ide/ppc/mpc8xx.c

   1 /*
   2  *  linux/drivers/ide/ppc/ide-m8xx.c
   3  *
   4  *  Copyright (C) 2000, 2001 Wolfgang Denk, wd@denx.de
   5  *  Modified for direct IDE interface
   6  *      by Thomas Lange, thomas@corelatus.com
   7  *  Modified for direct IDE interface on 8xx without using the PCMCIA
   8  *  controller
   9  *      by Steven.Scholz@imc-berlin.de
  10  *  Moved out of arch/ppc/kernel/m8xx_setup.c, other minor cleanups
  11  *      by Mathew Locke <mattl@mvista.com>
  12  */
  13
  14 #include <linux/errno.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mm.h>
  17 #include <linux/stddef.h>
  18 #include <linux/unistd.h>
  19 #include <linux/ptrace.h>
  20 #include <linux/slab.h>
  21 #include <linux/user.h>
  22 #include <linux/a.out.h>
  23 #include <linux/tty.h>
  24 #include <linux/major.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/reboot.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/ide.h>
  30 #include <linux/bootmem.h>
  31
  32 #include <asm/mpc8xx.h>
  33 #include <asm/mmu.h>
  34 #include <asm/processor.h>
  35 #include <asm/residual.h>
  36 #include <asm/io.h>
  37 #include <asm/pgtable.h>
  38 #include <asm/ide.h>
  39 #include <asm/8xx_immap.h>
  40 #include <asm/machdep.h>
  41 #include <asm/irq.h>
  42
  43 static int identify  (volatile u8 *p);
  44 static void print_fixed (volatile u8 *p);
  45 static void print_funcid (int func);
  46 static int check_ide_device (unsigned long base);
  47
  48 static void ide_interrupt_ack (void *dev);
  49 static void m8xx_ide_tuneproc(ide_drive_t *drive, u8 pio);
  50
  51 typedef struct ide_ioport_desc {
  52         unsigned long   base_off;               /* Offset to PCMCIA memory      */
  53         unsigned long   reg_off[IDE_NR_PORTS];  /* controller register offsets  */
  54         int             irq;                    /* IRQ                          */
  55 } ide_ioport_desc_t;
  56
  57 ide_ioport_desc_t ioport_dsc[MAX_HWIFS] = {
  58 #ifdef IDE0_BASE_OFFSET
  59         { IDE0_BASE_OFFSET,
  60             {
  61                 IDE0_DATA_REG_OFFSET,
  62                 IDE0_ERROR_REG_OFFSET,
  63                 IDE0_NSECTOR_REG_OFFSET,
  64                 IDE0_SECTOR_REG_OFFSET,
  65                 IDE0_LCYL_REG_OFFSET,
  66                 IDE0_HCYL_REG_OFFSET,
  67                 IDE0_SELECT_REG_OFFSET,
  68                 IDE0_STATUS_REG_OFFSET,
  69                 IDE0_CONTROL_REG_OFFSET,
  70                 IDE0_IRQ_REG_OFFSET,
  71             },
  72             IDE0_INTERRUPT,
  73         },
  74 #ifdef IDE1_BASE_OFFSET
  75         { IDE1_BASE_OFFSET,
  76             {
  77                 IDE1_DATA_REG_OFFSET,
  78                 IDE1_ERROR_REG_OFFSET,
  79                 IDE1_NSECTOR_REG_OFFSET,
  80                 IDE1_SECTOR_REG_OFFSET,
  81                 IDE1_LCYL_REG_OFFSET,
  82                 IDE1_HCYL_REG_OFFSET,
  83                 IDE1_SELECT_REG_OFFSET,
  84                 IDE1_STATUS_REG_OFFSET,
  85                 IDE1_CONTROL_REG_OFFSET,
  86                 IDE1_IRQ_REG_OFFSET,
  87             },
  88             IDE1_INTERRUPT,
  89         },
  90 #endif /* IDE1_BASE_OFFSET */
  91 #endif  /* IDE0_BASE_OFFSET */
  92 };
  93
  94 ide_pio_timings_t ide_pio_clocks[6];
  95 int hold_time[6] =  {30, 20, 15, 10, 10, 10 };   /* PIO Mode 5 with IORDY (nonstandard) */
  96
  97 /*
  98  * Warning: only 1 (ONE) PCMCIA slot supported here,
  99  * which must be correctly initialized by the firmware (PPCBoot).
 100  */
 101 static int _slot_ = -1;                 /* will be read from PCMCIA registers   */
 102
 103 /* Make clock cycles and always round up */
 104 #define PCMCIA_MK_CLKS( t, T ) (( (t) * ((T)/1000000) + 999U ) / 1000U )
 105
 106
 107
 108 /*
 109  * IDE stuff.
 110  */
 111 static int
 112 m8xx_ide_default_irq(unsigned long base)
 113 {
 114 #ifdef CONFIG_BLK_DEV_MPC8xx_IDE
 115         if (base >= MAX_HWIFS)
 116                 return 0;
 117
 118         printk("[%d] m8xx_ide_default_irq %d\n",__LINE__,ioport_dsc[base].irq);
 119
 120         return (ioport_dsc[base].irq);
 121 #else
 122         return 9;
 123 #endif
 124 }
 125
 126 static unsigned long
 127 m8xx_ide_default_io_base(int index)
 128 {
 129         return index;
 130 }
 131
 132 #define M8XX_PCMCIA_CD2(slot)      (0x10000000 >> (slot << 4))
 133 #define M8XX_PCMCIA_CD1(slot)      (0x08000000 >> (slot << 4))
 134
 135 /*
 136  * The TQM850L hardware has two pins swapped! Grrrrgh!
 137  */
 138 #ifdef  CONFIG_TQM850L
 139 #define __MY_PCMCIA_GCRX_CXRESET        PCMCIA_GCRX_CXOE
 140 #define __MY_PCMCIA_GCRX_CXOE           PCMCIA_GCRX_CXRESET
 141 #else
 142 #define __MY_PCMCIA_GCRX_CXRESET        PCMCIA_GCRX_CXRESET
 143 #define __MY_PCMCIA_GCRX_CXOE           PCMCIA_GCRX_CXOE
 144 #endif
 145
 146 #if defined(CONFIG_BLK_DEV_MPC8xx_IDE) && defined(CONFIG_IDE_8xx_PCCARD)
 147 #define PCMCIA_SCHLVL IDE0_INTERRUPT    /* Status Change Interrupt Level        */
 148 static int pcmcia_schlvl = PCMCIA_SCHLVL;
 149 #endif
 150
 151 /*
 152  * See include/linux/ide.h for definition of hw_regs_t (p, base)
 153  */
 154
 155 /*
 156  * m8xx_ide_init_hwif_ports for a direct IDE interface _using_
 157  */
 158 #if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT)
 159 static void
 160 m8xx_ide_init_hwif_ports(hw_regs_t *hw, unsigned long data_port,
 161                 unsigned long ctrl_port, int *irq)
 162 {
 163         unsigned long *p = hw->io_ports;
 164         int i;
 165
 166         typedef struct {
 167                 ulong br;
 168                 ulong or;
 169         } pcmcia_win_t;
 170         volatile pcmcia_win_t *win;
 171         volatile pcmconf8xx_t *pcmp;
 172
 173         uint *pgcrx;
 174         u32 pcmcia_phy_base;
 175         u32 pcmcia_phy_end;
 176         static unsigned long pcmcia_base = 0;
 177         unsigned long base;
 178
 179         *p = 0;
 180         if (irq)
 181                 *irq = 0;
 182
 183         pcmp = (pcmconf8xx_t *)(&(((immap_t *)IMAP_ADDR)->im_pcmcia));
 184
 185         if (!pcmcia_base) {
 186                 /*
 187                  * Read out PCMCIA registers. Since the reset values
 188                  * are undefined, we sure hope that they have been
 189                  * set up by firmware
 190                  */
 191
 192                 /* Scan all registers for valid settings */
 193                 pcmcia_phy_base = 0xFFFFFFFF;
 194                 pcmcia_phy_end = 0;
 195                 /* br0 is start of brX and orX regs */
 196                 win = (pcmcia_win_t *) \
 197                         (&(((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pbr0));
 198                 for (i = 0; i < 8; i++) {
 199                         if (win->or & 1) {      /* This bank is marked as valid */
 200                                 if (win->br < pcmcia_phy_base) {
 201                                         pcmcia_phy_base = win->br;
 202                                 }
 203                                 if ((win->br + PCMCIA_MEM_SIZE) > pcmcia_phy_end) {
 204                                         pcmcia_phy_end  = win->br + PCMCIA_MEM_SIZE;
 205                                 }
 206                                 /* Check which slot that has been defined */
 207                                 _slot_ = (win->or >> 2) & 1;
 208
 209                         }                                       /* Valid bank */
 210                         win++;
 211                 }                                               /* for */
 212
 213                 printk ("PCMCIA slot %c: phys mem %08x...%08x (size %08x)\n",
 214                         'A' + _slot_,
 215                         pcmcia_phy_base, pcmcia_phy_end,
 216                         pcmcia_phy_end - pcmcia_phy_base);
 217
 218                 pcmcia_base=(unsigned long)ioremap(pcmcia_phy_base,
 219                                                    pcmcia_phy_end-pcmcia_phy_base);
 220
 221 #ifdef DEBUG
 222                 printk ("PCMCIA virt base: %08lx\n", pcmcia_base);
 223 #endif
 224                 /* Compute clock cycles for PIO timings */
 225                 for (i=0; i<6; ++i) {
 226                         bd_t    *binfo = (bd_t *)__res;
 227
 228                         hold_time[i]   =
 229                                 PCMCIA_MK_CLKS (hold_time[i],
 230                                                 binfo->bi_busfreq);
 231                         ide_pio_clocks[i].setup_time  =
 232                                 PCMCIA_MK_CLKS (ide_pio_timings[i].setup_time,
 233                                                 binfo->bi_busfreq);
 234                         ide_pio_clocks[i].active_time =
 235                                 PCMCIA_MK_CLKS (ide_pio_timings[i].active_time,
 236                                                 binfo->bi_busfreq);
 237                         ide_pio_clocks[i].cycle_time  =
 238                                 PCMCIA_MK_CLKS (ide_pio_timings[i].cycle_time,
 239                                                 binfo->bi_busfreq);
 240 #if 0
 241                         printk ("PIO mode %d timings: %d/%d/%d => %d/%d/%d\n",
 242                                 i,
 243                                 ide_pio_clocks[i].setup_time,
 244                                 ide_pio_clocks[i].active_time,
 245                                 ide_pio_clocks[i].hold_time,
 246                                 ide_pio_clocks[i].cycle_time,
 247                                 ide_pio_timings[i].setup_time,
 248                                 ide_pio_timings[i].active_time,
 249                                 ide_pio_timings[i].hold_time,
 250                                 ide_pio_timings[i].cycle_time);
 251 #endif
 252                 }
 253         }
 254
 255         if (data_port >= MAX_HWIFS)
 256                 return;
 257
 258         if (_slot_ == -1) {
 259                 printk ("PCMCIA slot has not been defined! Using A as default\n");
 260                 _slot_ = 0;
 261         }
 262
 263 #ifdef CONFIG_IDE_8xx_PCCARD
 264
 265 #ifdef DEBUG
 266         printk ("PIPR = 0x%08X  slot %c ==> mask = 0x%X\n",
 267                 pcmp->pcmc_pipr,
 268                 'A' + _slot_,
 269                 M8XX_PCMCIA_CD1(_slot_) | M8XX_PCMCIA_CD2(_slot_) );
 270 #endif /* DEBUG */
 271
 272         if (pcmp->pcmc_pipr & (M8XX_PCMCIA_CD1(_slot_)|M8XX_PCMCIA_CD2(_slot_))) {
 273                 printk ("No card in slot %c: PIPR=%08x\n",
 274                         'A' + _slot_, (u32) pcmp->pcmc_pipr);
 275                 return;         /* No card in slot */
 276         }
 277
 278         check_ide_device (pcmcia_base);
 279
 280 #endif  /* CONFIG_IDE_8xx_PCCARD */
 281
 282         base = pcmcia_base + ioport_dsc[data_port].base_off;
 283 #ifdef DEBUG
 284         printk ("base: %08x + %08x = %08x\n",
 285                         pcmcia_base, ioport_dsc[data_port].base_off, base);
 286 #endif
 287
 288         for (i = 0; i < IDE_NR_PORTS; ++i) {
 289 #ifdef DEBUG
 290                 printk ("port[%d]: %08x + %08x = %08x\n",
 291                         i,
 292                         base,
 293                         ioport_dsc[data_port].reg_off[i],
 294                         i, base + ioport_dsc[data_port].reg_off[i]);
 295 #endif
 296                 *p++ = base + ioport_dsc[data_port].reg_off[i];
 297         }
 298
 299         if (irq) {
 300 #ifdef CONFIG_IDE_8xx_PCCARD
 301                 unsigned int reg;
 302
 303                 *irq = ioport_dsc[data_port].irq;
 304                 if (_slot_)
 305                         pgcrx = &((immap_t *) IMAP_ADDR)->im_pcmcia.pcmc_pgcrb;
 306                 else
 307                         pgcrx = &((immap_t *) IMAP_ADDR)->im_pcmcia.pcmc_pgcra;
 308
 309                 reg = *pgcrx;
 310                 reg |= mk_int_int_mask (pcmcia_schlvl) << 24;
 311                 reg |= mk_int_int_mask (pcmcia_schlvl) << 16;
 312                 *pgcrx = reg;
 313 #else   /* direct connected IDE drive, i.e. external IRQ, not the PCMCIA irq */
 314                 *irq = ioport_dsc[data_port].irq;
 315 #endif  /* CONFIG_IDE_8xx_PCCARD */
 316         }
 317
 318         /* register routine to tune PIO mode */
 319         ide_hwifs[data_port].tuneproc = m8xx_ide_tuneproc;
 320
 321         hw->ack_intr = (ide_ack_intr_t *) ide_interrupt_ack;
 322         /* Enable Harddisk Interrupt,
 323          * and make it edge sensitive
 324          */
 325         /* (11-18) Set edge detect for irq, no wakeup from low power mode */
 326         ((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel |=
 327                                         (0x80000000 >> ioport_dsc[data_port].irq);
 328
 329 #ifdef CONFIG_IDE_8xx_PCCARD
 330         /* Make sure we don't get garbage irq */
 331         ((immap_t *) IMAP_ADDR)->im_pcmcia.pcmc_pscr = 0xFFFF;
 332
 333         /* Enable falling edge irq */
 334         pcmp->pcmc_per = 0x100000 >> (16 * _slot_);
 335 #endif  /* CONFIG_IDE_8xx_PCCARD */
 336 }       /* m8xx_ide_init_hwif_ports() using 8xx internal PCMCIA interface */
 337 #endif /* CONFIG_IDE_8xx_PCCARD || CONFIG_IDE_8xx_DIRECT */
 338
 339 /*
 340  * m8xx_ide_init_hwif_ports for a direct IDE interface _not_ using
 341  * MPC8xx's internal PCMCIA interface
 342  */
 343 #if defined(CONFIG_IDE_EXT_DIRECT)
 344 void m8xx_ide_init_hwif_ports (hw_regs_t *hw,
 345         unsigned long data_port, unsigned long ctrl_port, int *irq)
 346 {
 347         unsigned long *p = hw->io_ports;
 348         int i;
 349
 350         u32 ide_phy_base;
 351         u32 ide_phy_end;
 352         static unsigned long ide_base = 0;
 353         unsigned long base;
 354
 355         *p = 0;
 356         if (irq)
 357                 *irq = 0;
 358
 359         if (!ide_base) {
 360
 361                 /* TODO:
 362                  * - add code to read ORx, BRx
 363                  */
 364                 ide_phy_base = CFG_ATA_BASE_ADDR;
 365                 ide_phy_end  = CFG_ATA_BASE_ADDR + 0x200;
 366
 367                 printk ("IDE phys mem : %08x...%08x (size %08x)\n",
 368                         ide_phy_base, ide_phy_end,
 369                         ide_phy_end - ide_phy_base);
 370
 371                 ide_base=(unsigned long)ioremap(ide_phy_base,
 372                                                 ide_phy_end-ide_phy_base);
 373
 374 #ifdef DEBUG
 375                 printk ("IDE virt base: %08lx\n", ide_base);
 376 #endif
 377         }
 378
 379         if (data_port >= MAX_HWIFS)
 380                 return;
 381
 382         base = ide_base + ioport_dsc[data_port].base_off;
 383 #ifdef DEBUG
 384         printk ("base: %08x + %08x = %08x\n",
 385                 ide_base, ioport_dsc[data_port].base_off, base);
 386 #endif
 387
 388         for (i = 0; i < IDE_NR_PORTS; ++i) {
 389 #ifdef DEBUG
 390                 printk ("port[%d]: %08x + %08x = %08x\n",
 391                         i,
 392                         base,
 393                         ioport_dsc[data_port].reg_off[i],
 394                         i, base + ioport_dsc[data_port].reg_off[i]);
 395 #endif
 396                 *p++ = base + ioport_dsc[data_port].reg_off[i];
 397         }
 398
 399         if (irq) {
 400                 /* direct connected IDE drive, i.e. external IRQ */
 401                 *irq = ioport_dsc[data_port].irq;
 402         }
 403
 404         /* register routine to tune PIO mode */
 405         ide_hwifs[data_port].tuneproc = m8xx_ide_tuneproc;
 406
 407         hw->ack_intr = (ide_ack_intr_t *) ide_interrupt_ack;
 408         /* Enable Harddisk Interrupt,
 409          * and make it edge sensitive
 410          */
 411         /* (11-18) Set edge detect for irq, no wakeup from low power mode */
 412         ((immap_t *) IMAP_ADDR)->im_siu_conf.sc_siel |=
 413                         (0x80000000 >> ioport_dsc[data_port].irq);
 414 }       /* m8xx_ide_init_hwif_ports() for CONFIG_IDE_8xx_DIRECT */
 415
 416 #endif  /* CONFIG_IDE_8xx_DIRECT */
 417
 418
 419 /* -------------------------------------------------------------------- */
 420
 421
 422 /* PCMCIA Timing */
 423 #ifndef PCMCIA_SHT
 424 #define PCMCIA_SHT(t)   ((t & 0x0F)<<16)        /* Strobe Hold  Time    */
 425 #define PCMCIA_SST(t)   ((t & 0x0F)<<12)        /* Strobe Setup Time    */
 426 #define PCMCIA_SL(t) ((t==32) ? 0 : ((t & 0x1F)<<7)) /* Strobe Length   */
 427 #endif
 428
 429
 430 /* Calculate PIO timings */
 431 static void
 432 m8xx_ide_tuneproc(ide_drive_t *drive, u8 pio)
 433 {
 434         ide_pio_data_t d;
 435 #if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT)
 436         volatile pcmconf8xx_t   *pcmp;
 437         ulong timing, mask, reg;
 438 #endif
 439
 440         pio = ide_get_best_pio_mode(drive, pio, 4, &d);
 441
 442 #if 1
 443         printk("%s[%d] %s: best PIO mode: %d\n",
 444                 __FILE__,__LINE__,__FUNCTION__, pio);
 445 #endif
 446
 447 #if defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_DIRECT)
 448         pcmp = (pcmconf8xx_t *)(&(((immap_t *)IMAP_ADDR)->im_pcmcia));
 449
 450         mask = ~(PCMCIA_SHT(0xFF) | PCMCIA_SST(0xFF) | PCMCIA_SL(0xFF));
 451
 452         timing  = PCMCIA_SHT(hold_time[pio]  )
 453                 | PCMCIA_SST(ide_pio_clocks[pio].setup_time )
 454                 | PCMCIA_SL (ide_pio_clocks[pio].active_time)
 455                 ;
 456
 457 #if 1
 458         printk ("Setting timing bits 0x%08lx in PCMCIA controller\n", timing);
 459 #endif
 460         if ((reg = pcmp->pcmc_por0 & mask) != 0)
 461                 pcmp->pcmc_por0 = reg | timing;
 462
 463         if ((reg = pcmp->pcmc_por1 & mask) != 0)
 464                 pcmp->pcmc_por1 = reg | timing;
 465
 466         if ((reg = pcmp->pcmc_por2 & mask) != 0)
 467                 pcmp->pcmc_por2 = reg | timing;
 468
 469         if ((reg = pcmp->pcmc_por3 & mask) != 0)
 470                 pcmp->pcmc_por3 = reg | timing;
 471
 472         if ((reg = pcmp->pcmc_por4 & mask) != 0)
 473                 pcmp->pcmc_por4 = reg | timing;
 474
 475         if ((reg = pcmp->pcmc_por5 & mask) != 0)
 476                 pcmp->pcmc_por5 = reg | timing;
 477
 478         if ((reg = pcmp->pcmc_por6 & mask) != 0)
 479                 pcmp->pcmc_por6 = reg | timing;
 480
 481         if ((reg = pcmp->pcmc_por7 & mask) != 0)
 482                 pcmp->pcmc_por7 = reg | timing;
 483
 484 #elif defined(CONFIG_IDE_EXT_DIRECT)
 485
 486         printk("%s[%d] %s: not implemented yet!\n",
 487                 __FILE__,__LINE__,__FUNCTION__);
 488 #endif /* defined(CONFIG_IDE_8xx_PCCARD) || defined(CONFIG_IDE_8xx_PCMCIA */
 489 }
 490
 491 static void
 492 ide_interrupt_ack (void *dev)
 493 {
 494 #ifdef CONFIG_IDE_8xx_PCCARD
 495         u_int pscr, pipr;
 496
 497 #if (PCMCIA_SOCKETS_NO == 2)
 498         u_int _slot_;
 499 #endif
 500
 501         /* get interrupt sources */
 502
 503         pscr = ((volatile immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr;
 504         pipr = ((volatile immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pipr;
 505
 506         /*
 507          * report only if both card detect signals are the same
 508          * not too nice done,
 509          * we depend on that CD2 is the bit to the left of CD1...
 510          */
 511
 512         if(_slot_==-1){
 513           printk("PCMCIA slot has not been defined! Using A as default\n");
 514           _slot_=0;
 515         }
 516
 517         if(((pipr & M8XX_PCMCIA_CD2(_slot_)) >> 1) ^
 518            (pipr & M8XX_PCMCIA_CD1(_slot_))         ) {
 519           printk ("card detect interrupt\n");
 520         }
 521         /* clear the interrupt sources */
 522         ((immap_t *)IMAP_ADDR)->im_pcmcia.pcmc_pscr = pscr;
 523
 524 #else /* ! CONFIG_IDE_8xx_PCCARD */
 525         /*
 526          * Only CONFIG_IDE_8xx_PCCARD is using the interrupt of the
 527          * MPC8xx's PCMCIA controller, so there is nothing to be done here
 528          * for CONFIG_IDE_8xx_DIRECT and CONFIG_IDE_EXT_DIRECT.
 529          * The interrupt is handled somewhere else.     -- Steven
 530          */
 531 #endif /* CONFIG_IDE_8xx_PCCARD */
 532 }
 533
 534
 535
 536 /*
 537  * CIS Tupel codes
 538  */
 539 #define CISTPL_NULL             0x00
 540 #define CISTPL_DEVICE           0x01
 541 #define CISTPL_LONGLINK_CB      0x02
 542 #define CISTPL_INDIRECT         0x03
 543 #define CISTPL_CONFIG_CB        0x04
 544 #define CISTPL_CFTABLE_ENTRY_CB 0x05
 545 #define CISTPL_LONGLINK_MFC     0x06
 546 #define CISTPL_BAR              0x07
 547 #define CISTPL_PWR_MGMNT        0x08
 548 #define CISTPL_EXTDEVICE        0x09
 549 #define CISTPL_CHECKSUM         0x10
 550 #define CISTPL_LONGLINK_A       0x11
 551 #define CISTPL_LONGLINK_C       0x12
 552 #define CISTPL_LINKTARGET       0x13
 553 #define CISTPL_NO_LINK          0x14
 554 #define CISTPL_VERS_1           0x15
 555 #define CISTPL_ALTSTR           0x16
 556 #define CISTPL_DEVICE_A         0x17
 557 #define CISTPL_JEDEC_C          0x18
 558 #define CISTPL_JEDEC_A          0x19
 559 #define CISTPL_CONFIG           0x1a
 560 #define CISTPL_CFTABLE_ENTRY    0x1b
 561 #define CISTPL_DEVICE_OC        0x1c
 562 #define CISTPL_DEVICE_OA        0x1d
 563 #define CISTPL_DEVICE_GEO       0x1e
 564 #define CISTPL_DEVICE_GEO_A     0x1f
 565 #define CISTPL_MANFID           0x20
 566 #define CISTPL_FUNCID           0x21
 567 #define CISTPL_FUNCE            0x22
 568 #define CISTPL_SWIL             0x23
 569 #define CISTPL_END              0xff
 570
 571 /*
 572  * CIS Function ID codes
 573  */
 574 #define CISTPL_FUNCID_MULTI     0x00
 575 #define CISTPL_FUNCID_MEMORY    0x01
 576 #define CISTPL_FUNCID_SERIAL    0x02
 577 #define CISTPL_FUNCID_PARALLEL  0x03
 578 #define CISTPL_FUNCID_FIXED     0x04
 579 #define CISTPL_FUNCID_VIDEO     0x05
 580 #define CISTPL_FUNCID_NETWORK   0x06
 581 #define CISTPL_FUNCID_AIMS      0x07
 582 #define CISTPL_FUNCID_SCSI      0x08
 583
 584 /*
 585  * Fixed Disk FUNCE codes
 586  */
 587 #define CISTPL_IDE_INTERFACE    0x01
 588
 589 #define CISTPL_FUNCE_IDE_IFACE  0x01
 590 #define CISTPL_FUNCE_IDE_MASTER 0x02
 591 #define CISTPL_FUNCE_IDE_SLAVE  0x03
 592
 593 /* First feature byte */
 594 #define CISTPL_IDE_SILICON      0x04
 595 #define CISTPL_IDE_UNIQUE       0x08
 596 #define CISTPL_IDE_DUAL         0x10
 597
 598 /* Second feature byte */
 599 #define CISTPL_IDE_HAS_SLEEP    0x01
 600 #define CISTPL_IDE_HAS_STANDBY  0x02
 601 #define CISTPL_IDE_HAS_IDLE     0x04
 602 #define CISTPL_IDE_LOW_POWER    0x08
 603 #define CISTPL_IDE_REG_INHIBIT  0x10
 604 #define CISTPL_IDE_HAS_INDEX    0x20
 605 #define CISTPL_IDE_IOIS16       0x40
 606
 607
 608 /* -------------------------------------------------------------------- */
 609
 610
 611 #define MAX_TUPEL_SZ    512
 612 #define MAX_FEATURES    4
 613
 614 static int check_ide_device (unsigned long base)
 615 {
 616         volatile u8 *ident = NULL;
 617         volatile u8 *feature_p[MAX_FEATURES];
 618         volatile u8 *p, *start;
 619         int n_features = 0;
 620         u8 func_id = ~0;
 621         u8 code, len;
 622         unsigned short config_base = 0;
 623         int found = 0;
 624         int i;
 625
 626 #ifdef DEBUG
 627         printk ("PCMCIA MEM: %08lX\n", base);
 628 #endif
 629         start = p = (volatile u8 *) base;
 630
 631         while ((p - start) < MAX_TUPEL_SZ) {
 632
 633                 code = *p; p += 2;
 634
 635                 if (code == 0xFF) { /* End of chain */
 636                         break;
 637                 }
 638
 639                 len = *p; p += 2;
 640 #ifdef  DEBUG_PCMCIA
 641                 { volatile u8 *q = p;
 642                         printk ("\nTuple code %02x  length %d\n\tData:",
 643                                 code, len);
 644
 645                         for (i = 0; i < len; ++i) {
 646                                 printk (" %02x", *q);
 647                                 q+= 2;
 648                         }
 649                 }
 650 #endif  /* DEBUG_PCMCIA */
 651                 switch (code) {
 652                 case CISTPL_VERS_1:
 653                         ident = p + 4;
 654                         break;
 655                 case CISTPL_FUNCID:
 656                         func_id = *p;
 657                         break;
 658                 case CISTPL_FUNCE:
 659                         if (n_features < MAX_FEATURES)
 660                                 feature_p[n_features++] = p;
 661                         break;
 662                 case CISTPL_CONFIG:
 663                         config_base = (*(p+6) << 8) + (*(p+4));
 664                 default:
 665                         break;
 666                 }
 667                 p += 2 * len;
 668         }
 669
 670         found = identify (ident);
 671
 672         if (func_id != ((u8)~0)) {
 673                 print_funcid (func_id);
 674
 675                 if (func_id == CISTPL_FUNCID_FIXED)
 676                         found = 1;
 677                 else
 678                         return (1);     /* no disk drive */
 679         }
 680
 681         for (i=0; i<n_features; ++i) {
 682                 print_fixed (feature_p[i]);
 683         }
 684
 685         if (!found) {
 686                 printk ("unknown card type\n");
 687                 return (1);
 688         }
 689
 690         /* set level mode irq and I/O mapped device in config reg*/
 691         *((u8 *)(base + config_base)) = 0x41;
 692
 693         return (0);
 694 }
 695
 696 /* ------------------------------------------------------------------------- */
 697
 698 static void print_funcid (int func)
 699 {
 700         switch (func) {
 701         case CISTPL_FUNCID_MULTI:
 702                 printk (" Multi-Function");
 703                 break;
 704         case CISTPL_FUNCID_MEMORY:
 705                 printk (" Memory");
 706                 break;
 707         case CISTPL_FUNCID_SERIAL:
 708                 printk (" Serial Port");
 709                 break;
 710         case CISTPL_FUNCID_PARALLEL:
 711                 printk (" Parallel Port");
 712                 break;
 713         case CISTPL_FUNCID_FIXED:
 714                 printk (" Fixed Disk");
 715                 break;
 716         case CISTPL_FUNCID_VIDEO:
 717                 printk (" Video Adapter");
 718                 break;
 719         case CISTPL_FUNCID_NETWORK:
 720                 printk (" Network Adapter");
 721                 break;
 722         case CISTPL_FUNCID_AIMS:
 723                 printk (" AIMS Card");
 724                 break;
 725         case CISTPL_FUNCID_SCSI:
 726                 printk (" SCSI Adapter");
 727                 break;
 728         default:
 729                 printk (" Unknown");
 730                 break;
 731         }
 732         printk (" Card\n");
 733 }
 734
 735 /* ------------------------------------------------------------------------- */
 736
 737 static void print_fixed (volatile u8 *p)
 738 {
 739         if (p == NULL)
 740                 return;
 741
 742         switch (*p) {
 743         case CISTPL_FUNCE_IDE_IFACE:
 744             {   u8 iface = *(p+2);
 745
 746                 printk ((iface == CISTPL_IDE_INTERFACE) ? " IDE" : " unknown");
 747                 printk (" interface ");
 748                 break;
 749             }
 750         case CISTPL_FUNCE_IDE_MASTER:
 751         case CISTPL_FUNCE_IDE_SLAVE:
 752             {   u8 f1 = *(p+2);
 753                 u8 f2 = *(p+4);
 754
 755                 printk ((f1 & CISTPL_IDE_SILICON) ? " [silicon]" : " [rotating]");
 756
 757                 if (f1 & CISTPL_IDE_UNIQUE)
 758                         printk (" [unique]");
 759
 760                 printk ((f1 & CISTPL_IDE_DUAL) ? " [dual]" : " [single]");
 761
 762                 if (f2 & CISTPL_IDE_HAS_SLEEP)
 763                         printk (" [sleep]");
 764
 765                 if (f2 & CISTPL_IDE_HAS_STANDBY)
 766                         printk (" [standby]");
 767
 768                 if (f2 & CISTPL_IDE_HAS_IDLE)
 769                         printk (" [idle]");
 770
 771                 if (f2 & CISTPL_IDE_LOW_POWER)
 772                         printk (" [low power]");
 773
 774                 if (f2 & CISTPL_IDE_REG_INHIBIT)
 775                         printk (" [reg inhibit]");
 776
 777                 if (f2 & CISTPL_IDE_HAS_INDEX)
 778                         printk (" [index]");
 779
 780                 if (f2 & CISTPL_IDE_IOIS16)
 781                         printk (" [IOis16]");
 782
 783                 break;
 784             }
 785         }
 786         printk ("\n");
 787 }
 788
 789 /* ------------------------------------------------------------------------- */
 790
 791
 792 #define MAX_IDENT_CHARS         64
 793 #define MAX_IDENT_FIELDS        4
 794
 795 static u8 *known_cards[] = {
 796         "ARGOSY PnPIDE D5",
 797         NULL
 798 };
 799
 800 static int identify  (volatile u8 *p)
 801 {
 802         u8 id_str[MAX_IDENT_CHARS];
 803         u8 data;
 804         u8 *t;
 805         u8 **card;
 806         int i, done;
 807
 808         if (p == NULL)
 809                 return (0);     /* Don't know */
 810
 811         t = id_str;
 812         done =0;
 813
 814         for (i=0; i<=4 && !done; ++i, p+=2) {
 815                 while ((data = *p) != '\0') {
 816                         if (data == 0xFF) {
 817                                 done = 1;
 818                                 break;
 819                         }
 820                         *t++ = data;
 821                         if (t == &id_str[MAX_IDENT_CHARS-1]) {
 822                                 done = 1;
 823                                 break;
 824                         }
 825                         p += 2;
 826                 }
 827                 if (!done)
 828                         *t++ = ' ';
 829         }
 830         *t = '\0';
 831         while (--t > id_str) {
 832                 if (*t == ' ')
 833                         *t = '\0';
 834                 else
 835                         break;
 836         }
 837         printk ("Card ID: %s\n", id_str);
 838
 839         for (card=known_cards; *card; ++card) {
 840                 if (strcmp(*card, id_str) == 0) {       /* found! */
 841                         return (1);
 842                 }
 843         }
 844
 845         return (0);     /* don't know */
 846 }
 847
 848 void m8xx_ide_init(void)
 849 {
 850         ppc_ide_md.default_irq          = m8xx_ide_default_irq;
 851         ppc_ide_md.default_io_base      = m8xx_ide_default_io_base;
 852         ppc_ide_md.ide_init_hwif        = m8xx_ide_init_hwif_ports;
 853 }