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libata pata_via: ACPI checks for 80wire cable
[pv_ops_mirror.git] / drivers / ide / pci / pdc202xx_old.c
blobb578307fad51a3a1b1dd9320a14ccc35de015ee0
1 /*
2 * linux/drivers/ide/pci/pdc202xx_old.c Version 0.51 Jul 27, 2007
3 *
4 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2006-2007 MontaVista Software, Inc.
6 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
7 *
8 * Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
9 * compiled into the kernel if you have more than one card installed.
10 * Note that BIOS v1.29 is reported to fix the problem. Since this is
11 * safe chipset tuning, including this support is harmless
12 *
13 * Promise Ultra66 cards with BIOS v1.11 this
14 * compiled into the kernel if you have more than one card installed.
15 *
16 * Promise Ultra100 cards.
17 *
18 * The latest chipset code will support the following ::
19 * Three Ultra33 controllers and 12 drives.
20 * 8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
21 * The 8/4 ratio is a BIOS code limit by promise.
22 *
23 * UNLESS you enable "CONFIG_PDC202XX_BURST"
24 *
25 */
26
27 /*
28 * Portions Copyright (C) 1999 Promise Technology, Inc.
29 * Author: Frank Tiernan (frankt@promise.com)
30 * Released under terms of General Public License
31 */
32
33 #include <linux/types.h>
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/delay.h>
37 #include <linux/timer.h>
38 #include <linux/mm.h>
39 #include <linux/ioport.h>
40 #include <linux/blkdev.h>
41 #include <linux/hdreg.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/init.h>
45 #include <linux/ide.h>
46
47 #include <asm/io.h>
48 #include <asm/irq.h>
49
50 #define PDC202XX_DEBUG_DRIVE_INFO 0
51
52 static const char *pdc_quirk_drives[] = {
53 "QUANTUM FIREBALLlct08 08",
54 "QUANTUM FIREBALLP KA6.4",
55 "QUANTUM FIREBALLP KA9.1",
56 "QUANTUM FIREBALLP LM20.4",
57 "QUANTUM FIREBALLP KX13.6",
58 "QUANTUM FIREBALLP KX20.5",
59 "QUANTUM FIREBALLP KX27.3",
60 "QUANTUM FIREBALLP LM20.5",
61 NULL
62 };
63
64 static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
65
66 static int pdc202xx_tune_chipset(ide_drive_t *drive, const u8 speed)
67 {
68 ide_hwif_t *hwif = HWIF(drive);
69 struct pci_dev *dev = hwif->pci_dev;
70 u8 drive_pci = 0x60 + (drive->dn << 2);
71
72 u8 AP = 0, BP = 0, CP = 0;
73 u8 TA = 0, TB = 0, TC = 0;
74
75 #if PDC202XX_DEBUG_DRIVE_INFO
76 u32 drive_conf = 0;
77 pci_read_config_dword(dev, drive_pci, &drive_conf);
78 #endif
79
80 /*
81 * TODO: do this once per channel
82 */
83 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
84 pdc_old_disable_66MHz_clock(hwif);
85
86 pci_read_config_byte(dev, drive_pci, &AP);
87 pci_read_config_byte(dev, drive_pci + 1, &BP);
88 pci_read_config_byte(dev, drive_pci + 2, &CP);
89
90 switch(speed) {
91 case XFER_UDMA_5:
92 case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
93 case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
94 case XFER_UDMA_3:
95 case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
96 case XFER_UDMA_0:
97 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
98 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
99 case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
100 case XFER_SW_DMA_2: TB = 0x60; TC = 0x05; break;
101 case XFER_SW_DMA_1: TB = 0x80; TC = 0x06; break;
102 case XFER_SW_DMA_0: TB = 0xC0; TC = 0x0B; break;
103 case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
104 case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
105 case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
106 case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
107 case XFER_PIO_0:
108 default: TA = 0x09; TB = 0x13; break;
109 }
110
111 if (speed < XFER_SW_DMA_0) {
112 /*
113 * preserve SYNC_INT / ERDDY_EN bits while clearing
114 * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
115 */
116 AP &= ~0x3f;
117 if (drive->id->capability & 4)
118 AP |= 0x20; /* set IORDY_EN bit */
119 if (drive->media == ide_disk)
120 AP |= 0x10; /* set Prefetch_EN bit */
121 /* clear PB[4:0] bits of register B */
122 BP &= ~0x1f;
123 pci_write_config_byte(dev, drive_pci, AP | TA);
124 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
125 } else {
126 /* clear MB[2:0] bits of register B */
127 BP &= ~0xe0;
128 /* clear MC[3:0] bits of register C */
129 CP &= ~0x0f;
130 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
131 pci_write_config_byte(dev, drive_pci + 2, CP | TC);
132 }
133
134 #if PDC202XX_DEBUG_DRIVE_INFO
135 printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
136 drive->name, ide_xfer_verbose(speed),
137 drive->dn, drive_conf);
138 pci_read_config_dword(dev, drive_pci, &drive_conf);
139 printk("0x%08x\n", drive_conf);
140 #endif
141
142 return ide_config_drive_speed(drive, speed);
143 }
144
145 static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
146 {
147 pdc202xx_tune_chipset(drive, XFER_PIO_0 + pio);
148 }
149
150 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
151 {
152 u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
153
154 pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
155
156 return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
157 }
158
159 /*
160 * Set the control register to use the 66MHz system
161 * clock for UDMA 3/4/5 mode operation when necessary.
162 *
163 * FIXME: this register is shared by both channels, some locking is needed
164 *
165 * It may also be possible to leave the 66MHz clock on
166 * and readjust the timing parameters.
167 */
168 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
169 {
170 unsigned long clock_reg = hwif->dma_master + 0x11;
171 u8 clock = inb(clock_reg);
172
173 outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
174 }
175
176 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
177 {
178 unsigned long clock_reg = hwif->dma_master + 0x11;
179 u8 clock = inb(clock_reg);
180
181 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
182 }
183
184 static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
185 {
186 drive->init_speed = 0;
187
188 if (ide_tune_dma(drive))
189 return 0;
190
191 if (ide_use_fast_pio(drive))
192 ide_set_max_pio(drive);
193
194 return -1;
195 }
196
197 static int pdc202xx_quirkproc (ide_drive_t *drive)
198 {
199 const char **list, *model = drive->id->model;
200
201 for (list = pdc_quirk_drives; *list != NULL; list++)
202 if (strstr(model, *list) != NULL)
203 return 2;
204 return 0;
205 }
206
207 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
208 {
209 if (drive->current_speed > XFER_UDMA_2)
210 pdc_old_enable_66MHz_clock(drive->hwif);
211 if (drive->media != ide_disk || drive->addressing == 1) {
212 struct request *rq = HWGROUP(drive)->rq;
213 ide_hwif_t *hwif = HWIF(drive);
214 unsigned long high_16 = hwif->dma_master;
215 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
216 u32 word_count = 0;
217 u8 clock = inb(high_16 + 0x11);
218
219 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
220 word_count = (rq->nr_sectors << 8);
221 word_count = (rq_data_dir(rq) == READ) ?
222 word_count | 0x05000000 :
223 word_count | 0x06000000;
224 outl(word_count, atapi_reg);
225 }
226 ide_dma_start(drive);
227 }
228
229 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
230 {
231 if (drive->media != ide_disk || drive->addressing == 1) {
232 ide_hwif_t *hwif = HWIF(drive);
233 unsigned long high_16 = hwif->dma_master;
234 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
235 u8 clock = 0;
236
237 outl(0, atapi_reg); /* zero out extra */
238 clock = inb(high_16 + 0x11);
239 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
240 }
241 if (drive->current_speed > XFER_UDMA_2)
242 pdc_old_disable_66MHz_clock(drive->hwif);
243 return __ide_dma_end(drive);
244 }
245
246 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
247 {
248 ide_hwif_t *hwif = HWIF(drive);
249 unsigned long high_16 = hwif->dma_master;
250 u8 dma_stat = inb(hwif->dma_status);
251 u8 sc1d = inb(high_16 + 0x001d);
252
253 if (hwif->channel) {
254 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
255 if ((sc1d & 0x50) == 0x50)
256 goto somebody_else;
257 else if ((sc1d & 0x40) == 0x40)
258 return (dma_stat & 4) == 4;
259 } else {
260 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
261 if ((sc1d & 0x05) == 0x05)
262 goto somebody_else;
263 else if ((sc1d & 0x04) == 0x04)
264 return (dma_stat & 4) == 4;
265 }
266 somebody_else:
267 return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
268 }
269
270 static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
271 {
272 ide_hwif_t *hwif = HWIF(drive);
273
274 if (hwif->resetproc != NULL)
275 hwif->resetproc(drive);
276
277 ide_dma_lost_irq(drive);
278 }
279
280 static void pdc202xx_dma_timeout(ide_drive_t *drive)
281 {
282 ide_hwif_t *hwif = HWIF(drive);
283
284 if (hwif->resetproc != NULL)
285 hwif->resetproc(drive);
286
287 ide_dma_timeout(drive);
288 }
289
290 static void pdc202xx_reset_host (ide_hwif_t *hwif)
291 {
292 unsigned long high_16 = hwif->dma_master;
293 u8 udma_speed_flag = inb(high_16 | 0x001f);
294
295 outb(udma_speed_flag | 0x10, high_16 | 0x001f);
296 mdelay(100);
297 outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
298 mdelay(2000); /* 2 seconds ?! */
299
300 printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
301 hwif->channel ? "Secondary" : "Primary");
302 }
303
304 static void pdc202xx_reset (ide_drive_t *drive)
305 {
306 ide_hwif_t *hwif = HWIF(drive);
307 ide_hwif_t *mate = hwif->mate;
308
309 pdc202xx_reset_host(hwif);
310 pdc202xx_reset_host(mate);
311
312 ide_set_max_pio(drive);
313 }
314
315 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
316 const char *name)
317 {
318 return dev->irq;
319 }
320
321 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
322 {
323 struct pci_dev *dev = hwif->pci_dev;
324
325 /* PDC20265 has problems with large LBA48 requests */
326 if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
327 (dev->device == PCI_DEVICE_ID_PROMISE_20265))
328 hwif->rqsize = 256;
329
330 hwif->autodma = 0;
331
332 hwif->set_pio_mode = &pdc202xx_set_pio_mode;
333
334 hwif->quirkproc = &pdc202xx_quirkproc;
335
336 if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
337 hwif->resetproc = &pdc202xx_reset;
338
339 hwif->speedproc = &pdc202xx_tune_chipset;
340
341 hwif->err_stops_fifo = 1;
342
343 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
344
345 if (hwif->dma_base == 0)
346 return;
347
348 hwif->ultra_mask = hwif->cds->udma_mask;
349 hwif->mwdma_mask = 0x07;
350 hwif->swdma_mask = 0x07;
351 hwif->atapi_dma = 1;
352
353 hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
354 hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
355 hwif->dma_timeout = &pdc202xx_dma_timeout;
356
357 if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
358 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
359 hwif->cbl = pdc202xx_old_cable_detect(hwif);
360
361 hwif->dma_start = &pdc202xx_old_ide_dma_start;
362 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
363 }
364 hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
365
366 if (!noautodma)
367 hwif->autodma = 1;
368 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
369 }
370
371 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
372 {
373 u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
374
375 if (hwif->channel) {
376 ide_setup_dma(hwif, dmabase, 8);
377 return;
378 }
379
380 udma_speed_flag = inb(dmabase | 0x1f);
381 primary_mode = inb(dmabase | 0x1a);
382 secondary_mode = inb(dmabase | 0x1b);
383 printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
384 "Primary %s Mode " \
385 "Secondary %s Mode.\n", hwif->cds->name,
386 (udma_speed_flag & 1) ? "EN" : "DIS",
387 (primary_mode & 1) ? "MASTER" : "PCI",
388 (secondary_mode & 1) ? "MASTER" : "PCI" );
389
390 #ifdef CONFIG_PDC202XX_BURST
391 if (!(udma_speed_flag & 1)) {
392 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
393 hwif->cds->name, udma_speed_flag,
394 (udma_speed_flag|1));
395 outb(udma_speed_flag | 1, dmabase | 0x1f);
396 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
397 }
398 #endif /* CONFIG_PDC202XX_BURST */
399
400 ide_setup_dma(hwif, dmabase, 8);
401 }
402
403 static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
404 ide_pci_device_t *d)
405 {
406 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
407 u8 irq = 0, irq2 = 0;
408 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
409 /* 0xbc */
410 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
411 if (irq != irq2) {
412 pci_write_config_byte(dev,
413 (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
414 printk(KERN_INFO "%s: pci-config space interrupt "
415 "mirror fixed.\n", d->name);
416 }
417 }
418 return ide_setup_pci_device(dev, d);
419 }
420
421 static int __devinit init_setup_pdc20265(struct pci_dev *dev,
422 ide_pci_device_t *d)
423 {
424 if ((dev->bus->self) &&
425 (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
426 ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
427 (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
428 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
429 "attached to I2O RAID controller.\n");
430 return -ENODEV;
431 }
432 return ide_setup_pci_device(dev, d);
433 }
434
435 static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
436 ide_pci_device_t *d)
437 {
438 return ide_setup_pci_device(dev, d);
439 }
440
441 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
442 { /* 0 */
443 .name = "PDC20246",
444 .init_setup = init_setup_pdc202ata4,
445 .init_chipset = init_chipset_pdc202xx,
446 .init_hwif = init_hwif_pdc202xx,
447 .init_dma = init_dma_pdc202xx,
448 .autodma = AUTODMA,
449 .bootable = OFF_BOARD,
450 .extra = 16,
451 .pio_mask = ATA_PIO4,
452 .udma_mask = 0x07, /* udma0-2 */
453 },{ /* 1 */
454 .name = "PDC20262",
455 .init_setup = init_setup_pdc202ata4,
456 .init_chipset = init_chipset_pdc202xx,
457 .init_hwif = init_hwif_pdc202xx,
458 .init_dma = init_dma_pdc202xx,
459 .autodma = AUTODMA,
460 .bootable = OFF_BOARD,
461 .extra = 48,
462 .pio_mask = ATA_PIO4,
463 .udma_mask = 0x1f, /* udma0-4 */
464 },{ /* 2 */
465 .name = "PDC20263",
466 .init_setup = init_setup_pdc202ata4,
467 .init_chipset = init_chipset_pdc202xx,
468 .init_hwif = init_hwif_pdc202xx,
469 .init_dma = init_dma_pdc202xx,
470 .autodma = AUTODMA,
471 .bootable = OFF_BOARD,
472 .extra = 48,
473 .pio_mask = ATA_PIO4,
474 .udma_mask = 0x1f, /* udma0-4 */
475 },{ /* 3 */
476 .name = "PDC20265",
477 .init_setup = init_setup_pdc20265,
478 .init_chipset = init_chipset_pdc202xx,
479 .init_hwif = init_hwif_pdc202xx,
480 .init_dma = init_dma_pdc202xx,
481 .autodma = AUTODMA,
482 .bootable = OFF_BOARD,
483 .extra = 48,
484 .pio_mask = ATA_PIO4,
485 .udma_mask = 0x3f, /* udma0-5 */
486 },{ /* 4 */
487 .name = "PDC20267",
488 .init_setup = init_setup_pdc202xx,
489 .init_chipset = init_chipset_pdc202xx,
490 .init_hwif = init_hwif_pdc202xx,
491 .init_dma = init_dma_pdc202xx,
492 .autodma = AUTODMA,
493 .bootable = OFF_BOARD,
494 .extra = 48,
495 .pio_mask = ATA_PIO4,
496 .udma_mask = 0x3f, /* udma0-5 */
497 }
498 };
499
500 /**
501 * pdc202xx_init_one - called when a PDC202xx is found
502 * @dev: the pdc202xx device
503 * @id: the matching pci id
504 *
505 * Called when the PCI registration layer (or the IDE initialization)
506 * finds a device matching our IDE device tables.
507 */
508
509 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
510 {
511 ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
512
513 return d->init_setup(dev, d);
514 }
515
516 static struct pci_device_id pdc202xx_pci_tbl[] = {
517 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
518 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
519 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
520 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
521 { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
522 { 0, },
523 };
524 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
525
526 static struct pci_driver driver = {
527 .name = "Promise_Old_IDE",
528 .id_table = pdc202xx_pci_tbl,
529 .probe = pdc202xx_init_one,
530 };
531
532 static int __init pdc202xx_ide_init(void)
533 {
534 return ide_pci_register_driver(&driver);
535 }
536
537 module_init(pdc202xx_ide_init);
538
539 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
540 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
541 MODULE_LICENSE("GPL");
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