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[ARM] 3340/1: Fix the PCI setup for direct master access to SDRAM
[pv_ops_mirror.git] / arch / arm / plat-omap / gpio.c
blobb4d5b9e4bfce68c72805c158b4a038ebc2dc4d65
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/config.h>
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/sched.h>
18 #include <linux/interrupt.h>
19 #include <linux/ptrace.h>
20 #include <linux/sysdev.h>
21 #include <linux/err.h>
22 #include <linux/clk.h>
23
24 #include <asm/hardware.h>
25 #include <asm/irq.h>
26 #include <asm/arch/irqs.h>
27 #include <asm/arch/gpio.h>
28 #include <asm/mach/irq.h>
29
30 #include <asm/io.h>
31
32 /*
33 * OMAP1510 GPIO registers
34 */
35 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
36 #define OMAP1510_GPIO_DATA_INPUT 0x00
37 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
38 #define OMAP1510_GPIO_DIR_CONTROL 0x08
39 #define OMAP1510_GPIO_INT_CONTROL 0x0c
40 #define OMAP1510_GPIO_INT_MASK 0x10
41 #define OMAP1510_GPIO_INT_STATUS 0x14
42 #define OMAP1510_GPIO_PIN_CONTROL 0x18
43
44 #define OMAP1510_IH_GPIO_BASE 64
45
46 /*
47 * OMAP1610 specific GPIO registers
48 */
49 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
50 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
51 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
52 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
53 #define OMAP1610_GPIO_REVISION 0x0000
54 #define OMAP1610_GPIO_SYSCONFIG 0x0010
55 #define OMAP1610_GPIO_SYSSTATUS 0x0014
56 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
57 #define OMAP1610_GPIO_IRQENABLE1 0x001c
58 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
59 #define OMAP1610_GPIO_DATAIN 0x002c
60 #define OMAP1610_GPIO_DATAOUT 0x0030
61 #define OMAP1610_GPIO_DIRECTION 0x0034
62 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
63 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
64 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
65 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
66 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
67 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
68 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
69 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
70
71 /*
72 * OMAP730 specific GPIO registers
73 */
74 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
75 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
76 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
77 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
78 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
79 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
80 #define OMAP730_GPIO_DATA_INPUT 0x00
81 #define OMAP730_GPIO_DATA_OUTPUT 0x04
82 #define OMAP730_GPIO_DIR_CONTROL 0x08
83 #define OMAP730_GPIO_INT_CONTROL 0x0c
84 #define OMAP730_GPIO_INT_MASK 0x10
85 #define OMAP730_GPIO_INT_STATUS 0x14
86
87 /*
88 * omap24xx specific GPIO registers
89 */
90 #define OMAP24XX_GPIO1_BASE (void __iomem *)0x48018000
91 #define OMAP24XX_GPIO2_BASE (void __iomem *)0x4801a000
92 #define OMAP24XX_GPIO3_BASE (void __iomem *)0x4801c000
93 #define OMAP24XX_GPIO4_BASE (void __iomem *)0x4801e000
94 #define OMAP24XX_GPIO_REVISION 0x0000
95 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
96 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
97 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
98 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
99 #define OMAP24XX_GPIO_CTRL 0x0030
100 #define OMAP24XX_GPIO_OE 0x0034
101 #define OMAP24XX_GPIO_DATAIN 0x0038
102 #define OMAP24XX_GPIO_DATAOUT 0x003c
103 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
104 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
105 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
106 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
107 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
108 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
109 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
110 #define OMAP24XX_GPIO_SETWKUENA 0x0084
111 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
112 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
113
114 #define OMAP_MPUIO_MASK (~OMAP_MAX_GPIO_LINES & 0xff)
115
116 struct gpio_bank {
117 void __iomem *base;
118 u16 irq;
119 u16 virtual_irq_start;
120 int method;
121 u32 reserved_map;
122 u32 suspend_wakeup;
123 u32 saved_wakeup;
124 spinlock_t lock;
125 };
126
127 #define METHOD_MPUIO 0
128 #define METHOD_GPIO_1510 1
129 #define METHOD_GPIO_1610 2
130 #define METHOD_GPIO_730 3
131 #define METHOD_GPIO_24XX 4
132
133 #ifdef CONFIG_ARCH_OMAP16XX
134 static struct gpio_bank gpio_bank_1610[5] = {
135 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
136 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
137 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
138 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
139 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
140 };
141 #endif
142
143 #ifdef CONFIG_ARCH_OMAP15XX
144 static struct gpio_bank gpio_bank_1510[2] = {
145 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
146 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
147 };
148 #endif
149
150 #ifdef CONFIG_ARCH_OMAP730
151 static struct gpio_bank gpio_bank_730[7] = {
152 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
153 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
154 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
155 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
156 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
157 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
158 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
159 };
160 #endif
161
162 #ifdef CONFIG_ARCH_OMAP24XX
163 static struct gpio_bank gpio_bank_24xx[4] = {
164 { OMAP24XX_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
165 { OMAP24XX_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
166 { OMAP24XX_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
167 { OMAP24XX_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
168 };
169 #endif
170
171 static struct gpio_bank *gpio_bank;
172 static int gpio_bank_count;
173
174 static inline struct gpio_bank *get_gpio_bank(int gpio)
175 {
176 #ifdef CONFIG_ARCH_OMAP15XX
177 if (cpu_is_omap1510()) {
178 if (OMAP_GPIO_IS_MPUIO(gpio))
179 return &gpio_bank[0];
180 return &gpio_bank[1];
181 }
182 #endif
183 #if defined(CONFIG_ARCH_OMAP16XX)
184 if (cpu_is_omap16xx()) {
185 if (OMAP_GPIO_IS_MPUIO(gpio))
186 return &gpio_bank[0];
187 return &gpio_bank[1 + (gpio >> 4)];
188 }
189 #endif
190 #ifdef CONFIG_ARCH_OMAP730
191 if (cpu_is_omap730()) {
192 if (OMAP_GPIO_IS_MPUIO(gpio))
193 return &gpio_bank[0];
194 return &gpio_bank[1 + (gpio >> 5)];
195 }
196 #endif
197 #ifdef CONFIG_ARCH_OMAP24XX
198 if (cpu_is_omap24xx())
199 return &gpio_bank[gpio >> 5];
200 #endif
201 }
202
203 static inline int get_gpio_index(int gpio)
204 {
205 #ifdef CONFIG_ARCH_OMAP730
206 if (cpu_is_omap730())
207 return gpio & 0x1f;
208 #endif
209 #ifdef CONFIG_ARCH_OMAP24XX
210 if (cpu_is_omap24xx())
211 return gpio & 0x1f;
212 #endif
213 return gpio & 0x0f;
214 }
215
216 static inline int gpio_valid(int gpio)
217 {
218 if (gpio < 0)
219 return -1;
220 if (OMAP_GPIO_IS_MPUIO(gpio)) {
221 if ((gpio & OMAP_MPUIO_MASK) > 16)
222 return -1;
223 return 0;
224 }
225 #ifdef CONFIG_ARCH_OMAP15XX
226 if (cpu_is_omap1510() && gpio < 16)
227 return 0;
228 #endif
229 #if defined(CONFIG_ARCH_OMAP16XX)
230 if ((cpu_is_omap16xx()) && gpio < 64)
231 return 0;
232 #endif
233 #ifdef CONFIG_ARCH_OMAP730
234 if (cpu_is_omap730() && gpio < 192)
235 return 0;
236 #endif
237 #ifdef CONFIG_ARCH_OMAP24XX
238 if (cpu_is_omap24xx() && gpio < 128)
239 return 0;
240 #endif
241 return -1;
242 }
243
244 static int check_gpio(int gpio)
245 {
246 if (unlikely(gpio_valid(gpio)) < 0) {
247 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
248 dump_stack();
249 return -1;
250 }
251 return 0;
252 }
253
254 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
255 {
256 void __iomem *reg = bank->base;
257 u32 l;
258
259 switch (bank->method) {
260 case METHOD_MPUIO:
261 reg += OMAP_MPUIO_IO_CNTL;
262 break;
263 case METHOD_GPIO_1510:
264 reg += OMAP1510_GPIO_DIR_CONTROL;
265 break;
266 case METHOD_GPIO_1610:
267 reg += OMAP1610_GPIO_DIRECTION;
268 break;
269 case METHOD_GPIO_730:
270 reg += OMAP730_GPIO_DIR_CONTROL;
271 break;
272 case METHOD_GPIO_24XX:
273 reg += OMAP24XX_GPIO_OE;
274 break;
275 }
276 l = __raw_readl(reg);
277 if (is_input)
278 l |= 1 << gpio;
279 else
280 l &= ~(1 << gpio);
281 __raw_writel(l, reg);
282 }
283
284 void omap_set_gpio_direction(int gpio, int is_input)
285 {
286 struct gpio_bank *bank;
287
288 if (check_gpio(gpio) < 0)
289 return;
290 bank = get_gpio_bank(gpio);
291 spin_lock(&bank->lock);
292 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
293 spin_unlock(&bank->lock);
294 }
295
296 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
297 {
298 void __iomem *reg = bank->base;
299 u32 l = 0;
300
301 switch (bank->method) {
302 case METHOD_MPUIO:
303 reg += OMAP_MPUIO_OUTPUT;
304 l = __raw_readl(reg);
305 if (enable)
306 l |= 1 << gpio;
307 else
308 l &= ~(1 << gpio);
309 break;
310 case METHOD_GPIO_1510:
311 reg += OMAP1510_GPIO_DATA_OUTPUT;
312 l = __raw_readl(reg);
313 if (enable)
314 l |= 1 << gpio;
315 else
316 l &= ~(1 << gpio);
317 break;
318 case METHOD_GPIO_1610:
319 if (enable)
320 reg += OMAP1610_GPIO_SET_DATAOUT;
321 else
322 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
323 l = 1 << gpio;
324 break;
325 case METHOD_GPIO_730:
326 reg += OMAP730_GPIO_DATA_OUTPUT;
327 l = __raw_readl(reg);
328 if (enable)
329 l |= 1 << gpio;
330 else
331 l &= ~(1 << gpio);
332 break;
333 case METHOD_GPIO_24XX:
334 if (enable)
335 reg += OMAP24XX_GPIO_SETDATAOUT;
336 else
337 reg += OMAP24XX_GPIO_CLEARDATAOUT;
338 l = 1 << gpio;
339 break;
340 default:
341 BUG();
342 return;
343 }
344 __raw_writel(l, reg);
345 }
346
347 void omap_set_gpio_dataout(int gpio, int enable)
348 {
349 struct gpio_bank *bank;
350
351 if (check_gpio(gpio) < 0)
352 return;
353 bank = get_gpio_bank(gpio);
354 spin_lock(&bank->lock);
355 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
356 spin_unlock(&bank->lock);
357 }
358
359 int omap_get_gpio_datain(int gpio)
360 {
361 struct gpio_bank *bank;
362 void __iomem *reg;
363
364 if (check_gpio(gpio) < 0)
365 return -1;
366 bank = get_gpio_bank(gpio);
367 reg = bank->base;
368 switch (bank->method) {
369 case METHOD_MPUIO:
370 reg += OMAP_MPUIO_INPUT_LATCH;
371 break;
372 case METHOD_GPIO_1510:
373 reg += OMAP1510_GPIO_DATA_INPUT;
374 break;
375 case METHOD_GPIO_1610:
376 reg += OMAP1610_GPIO_DATAIN;
377 break;
378 case METHOD_GPIO_730:
379 reg += OMAP730_GPIO_DATA_INPUT;
380 break;
381 case METHOD_GPIO_24XX:
382 reg += OMAP24XX_GPIO_DATAIN;
383 break;
384 default:
385 BUG();
386 return -1;
387 }
388 return (__raw_readl(reg)
389 & (1 << get_gpio_index(gpio))) != 0;
390 }
391
392 #define MOD_REG_BIT(reg, bit_mask, set) \
393 do { \
394 int l = __raw_readl(base + reg); \
395 if (set) l |= bit_mask; \
396 else l &= ~bit_mask; \
397 __raw_writel(l, base + reg); \
398 } while(0)
399
400 static inline void set_24xx_gpio_triggering(void __iomem *base, int gpio, int trigger)
401 {
402 u32 gpio_bit = 1 << gpio;
403
404 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
405 trigger & IRQT_LOW);
406 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
407 trigger & IRQT_HIGH);
408 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
409 trigger & IRQT_RISING);
410 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
411 trigger & IRQT_FALLING);
412 /* FIXME: Possibly do 'set_irq_handler(j, do_level_IRQ)' if only level
413 * triggering requested. */
414 }
415
416 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
417 {
418 void __iomem *reg = bank->base;
419 u32 l = 0;
420
421 switch (bank->method) {
422 case METHOD_MPUIO:
423 reg += OMAP_MPUIO_GPIO_INT_EDGE;
424 l = __raw_readl(reg);
425 if (trigger == IRQT_RISING)
426 l |= 1 << gpio;
427 else if (trigger == IRQT_FALLING)
428 l &= ~(1 << gpio);
429 else
430 goto bad;
431 break;
432 case METHOD_GPIO_1510:
433 reg += OMAP1510_GPIO_INT_CONTROL;
434 l = __raw_readl(reg);
435 if (trigger == IRQT_RISING)
436 l |= 1 << gpio;
437 else if (trigger == IRQT_FALLING)
438 l &= ~(1 << gpio);
439 else
440 goto bad;
441 break;
442 case METHOD_GPIO_1610:
443 if (gpio & 0x08)
444 reg += OMAP1610_GPIO_EDGE_CTRL2;
445 else
446 reg += OMAP1610_GPIO_EDGE_CTRL1;
447 gpio &= 0x07;
448 /* We allow only edge triggering, i.e. two lowest bits */
449 if (trigger & ~IRQT_BOTHEDGE)
450 BUG();
451 /* NOTE: knows __IRQT_{FAL,RIS}EDGE match OMAP hardware */
452 trigger &= 0x03;
453 l = __raw_readl(reg);
454 l &= ~(3 << (gpio << 1));
455 l |= trigger << (gpio << 1);
456 break;
457 case METHOD_GPIO_730:
458 reg += OMAP730_GPIO_INT_CONTROL;
459 l = __raw_readl(reg);
460 if (trigger == IRQT_RISING)
461 l |= 1 << gpio;
462 else if (trigger == IRQT_FALLING)
463 l &= ~(1 << gpio);
464 else
465 goto bad;
466 break;
467 case METHOD_GPIO_24XX:
468 set_24xx_gpio_triggering(reg, gpio, trigger);
469 break;
470 default:
471 BUG();
472 goto bad;
473 }
474 __raw_writel(l, reg);
475 return 0;
476 bad:
477 return -EINVAL;
478 }
479
480 static int gpio_irq_type(unsigned irq, unsigned type)
481 {
482 struct gpio_bank *bank;
483 unsigned gpio;
484 int retval;
485
486 if (irq > IH_MPUIO_BASE)
487 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
488 else
489 gpio = irq - IH_GPIO_BASE;
490
491 if (check_gpio(gpio) < 0)
492 return -EINVAL;
493
494 if (type & (__IRQT_LOWLVL|__IRQT_HIGHLVL|IRQT_PROBE))
495 return -EINVAL;
496
497 bank = get_gpio_bank(gpio);
498 spin_lock(&bank->lock);
499 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
500 spin_unlock(&bank->lock);
501 return retval;
502 }
503
504 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
505 {
506 void __iomem *reg = bank->base;
507
508 switch (bank->method) {
509 case METHOD_MPUIO:
510 /* MPUIO irqstatus is reset by reading the status register,
511 * so do nothing here */
512 return;
513 case METHOD_GPIO_1510:
514 reg += OMAP1510_GPIO_INT_STATUS;
515 break;
516 case METHOD_GPIO_1610:
517 reg += OMAP1610_GPIO_IRQSTATUS1;
518 break;
519 case METHOD_GPIO_730:
520 reg += OMAP730_GPIO_INT_STATUS;
521 break;
522 case METHOD_GPIO_24XX:
523 reg += OMAP24XX_GPIO_IRQSTATUS1;
524 break;
525 default:
526 BUG();
527 return;
528 }
529 __raw_writel(gpio_mask, reg);
530 }
531
532 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
533 {
534 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
535 }
536
537 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
538 {
539 void __iomem *reg = bank->base;
540 u32 l;
541
542 switch (bank->method) {
543 case METHOD_MPUIO:
544 reg += OMAP_MPUIO_GPIO_MASKIT;
545 l = __raw_readl(reg);
546 if (enable)
547 l &= ~(gpio_mask);
548 else
549 l |= gpio_mask;
550 break;
551 case METHOD_GPIO_1510:
552 reg += OMAP1510_GPIO_INT_MASK;
553 l = __raw_readl(reg);
554 if (enable)
555 l &= ~(gpio_mask);
556 else
557 l |= gpio_mask;
558 break;
559 case METHOD_GPIO_1610:
560 if (enable)
561 reg += OMAP1610_GPIO_SET_IRQENABLE1;
562 else
563 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
564 l = gpio_mask;
565 break;
566 case METHOD_GPIO_730:
567 reg += OMAP730_GPIO_INT_MASK;
568 l = __raw_readl(reg);
569 if (enable)
570 l &= ~(gpio_mask);
571 else
572 l |= gpio_mask;
573 break;
574 case METHOD_GPIO_24XX:
575 if (enable)
576 reg += OMAP24XX_GPIO_SETIRQENABLE1;
577 else
578 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
579 l = gpio_mask;
580 break;
581 default:
582 BUG();
583 return;
584 }
585 __raw_writel(l, reg);
586 }
587
588 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
589 {
590 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
591 }
592
593 /*
594 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
595 * 1510 does not seem to have a wake-up register. If JTAG is connected
596 * to the target, system will wake up always on GPIO events. While
597 * system is running all registered GPIO interrupts need to have wake-up
598 * enabled. When system is suspended, only selected GPIO interrupts need
599 * to have wake-up enabled.
600 */
601 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
602 {
603 switch (bank->method) {
604 case METHOD_GPIO_1610:
605 case METHOD_GPIO_24XX:
606 spin_lock(&bank->lock);
607 if (enable)
608 bank->suspend_wakeup |= (1 << gpio);
609 else
610 bank->suspend_wakeup &= ~(1 << gpio);
611 spin_unlock(&bank->lock);
612 return 0;
613 default:
614 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
615 bank->method);
616 return -EINVAL;
617 }
618 }
619
620 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
621 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
622 {
623 unsigned int gpio = irq - IH_GPIO_BASE;
624 struct gpio_bank *bank;
625 int retval;
626
627 if (check_gpio(gpio) < 0)
628 return -ENODEV;
629 bank = get_gpio_bank(gpio);
630 spin_lock(&bank->lock);
631 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
632 spin_unlock(&bank->lock);
633
634 return retval;
635 }
636
637 int omap_request_gpio(int gpio)
638 {
639 struct gpio_bank *bank;
640
641 if (check_gpio(gpio) < 0)
642 return -EINVAL;
643
644 bank = get_gpio_bank(gpio);
645 spin_lock(&bank->lock);
646 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
647 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
648 dump_stack();
649 spin_unlock(&bank->lock);
650 return -1;
651 }
652 bank->reserved_map |= (1 << get_gpio_index(gpio));
653
654 /* Set trigger to none. You need to enable the trigger after request_irq */
655 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
656
657 #ifdef CONFIG_ARCH_OMAP15XX
658 if (bank->method == METHOD_GPIO_1510) {
659 void __iomem *reg;
660
661 /* Claim the pin for MPU */
662 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
663 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
664 }
665 #endif
666 #ifdef CONFIG_ARCH_OMAP16XX
667 if (bank->method == METHOD_GPIO_1610) {
668 /* Enable wake-up during idle for dynamic tick */
669 void __iomem *reg = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
670 __raw_writel(1 << get_gpio_index(gpio), reg);
671 }
672 #endif
673 #ifdef CONFIG_ARCH_OMAP24XX
674 if (bank->method == METHOD_GPIO_24XX) {
675 /* Enable wake-up during idle for dynamic tick */
676 void __iomem *reg = bank->base + OMAP24XX_GPIO_SETWKUENA;
677 __raw_writel(1 << get_gpio_index(gpio), reg);
678 }
679 #endif
680 spin_unlock(&bank->lock);
681
682 return 0;
683 }
684
685 void omap_free_gpio(int gpio)
686 {
687 struct gpio_bank *bank;
688
689 if (check_gpio(gpio) < 0)
690 return;
691 bank = get_gpio_bank(gpio);
692 spin_lock(&bank->lock);
693 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
694 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
695 dump_stack();
696 spin_unlock(&bank->lock);
697 return;
698 }
699 #ifdef CONFIG_ARCH_OMAP16XX
700 if (bank->method == METHOD_GPIO_1610) {
701 /* Disable wake-up during idle for dynamic tick */
702 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
703 __raw_writel(1 << get_gpio_index(gpio), reg);
704 }
705 #endif
706 #ifdef CONFIG_ARCH_OMAP24XX
707 if (bank->method == METHOD_GPIO_24XX) {
708 /* Disable wake-up during idle for dynamic tick */
709 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
710 __raw_writel(1 << get_gpio_index(gpio), reg);
711 }
712 #endif
713 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
714 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
715 _set_gpio_irqenable(bank, gpio, 0);
716 _clear_gpio_irqstatus(bank, gpio);
717 spin_unlock(&bank->lock);
718 }
719
720 /*
721 * We need to unmask the GPIO bank interrupt as soon as possible to
722 * avoid missing GPIO interrupts for other lines in the bank.
723 * Then we need to mask-read-clear-unmask the triggered GPIO lines
724 * in the bank to avoid missing nested interrupts for a GPIO line.
725 * If we wait to unmask individual GPIO lines in the bank after the
726 * line's interrupt handler has been run, we may miss some nested
727 * interrupts.
728 */
729 static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc,
730 struct pt_regs *regs)
731 {
732 void __iomem *isr_reg = NULL;
733 u32 isr;
734 unsigned int gpio_irq;
735 struct gpio_bank *bank;
736
737 desc->chip->ack(irq);
738
739 bank = (struct gpio_bank *) desc->data;
740 if (bank->method == METHOD_MPUIO)
741 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
742 #ifdef CONFIG_ARCH_OMAP15XX
743 if (bank->method == METHOD_GPIO_1510)
744 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
745 #endif
746 #if defined(CONFIG_ARCH_OMAP16XX)
747 if (bank->method == METHOD_GPIO_1610)
748 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
749 #endif
750 #ifdef CONFIG_ARCH_OMAP730
751 if (bank->method == METHOD_GPIO_730)
752 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
753 #endif
754 #ifdef CONFIG_ARCH_OMAP24XX
755 if (bank->method == METHOD_GPIO_24XX)
756 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
757 #endif
758
759 while(1) {
760 isr = __raw_readl(isr_reg);
761 _enable_gpio_irqbank(bank, isr, 0);
762 _clear_gpio_irqbank(bank, isr);
763 _enable_gpio_irqbank(bank, isr, 1);
764 desc->chip->unmask(irq);
765
766 if (!isr)
767 break;
768
769 gpio_irq = bank->virtual_irq_start;
770 for (; isr != 0; isr >>= 1, gpio_irq++) {
771 struct irqdesc *d;
772 if (!(isr & 1))
773 continue;
774 d = irq_desc + gpio_irq;
775 desc_handle_irq(gpio_irq, d, regs);
776 }
777 }
778 }
779
780 static void gpio_ack_irq(unsigned int irq)
781 {
782 unsigned int gpio = irq - IH_GPIO_BASE;
783 struct gpio_bank *bank = get_gpio_bank(gpio);
784
785 _clear_gpio_irqstatus(bank, gpio);
786 }
787
788 static void gpio_mask_irq(unsigned int irq)
789 {
790 unsigned int gpio = irq - IH_GPIO_BASE;
791 struct gpio_bank *bank = get_gpio_bank(gpio);
792
793 _set_gpio_irqenable(bank, gpio, 0);
794 }
795
796 static void gpio_unmask_irq(unsigned int irq)
797 {
798 unsigned int gpio = irq - IH_GPIO_BASE;
799 unsigned int gpio_idx = get_gpio_index(gpio);
800 struct gpio_bank *bank = get_gpio_bank(gpio);
801
802 _set_gpio_irqenable(bank, gpio_idx, 1);
803 }
804
805 static void mpuio_ack_irq(unsigned int irq)
806 {
807 /* The ISR is reset automatically, so do nothing here. */
808 }
809
810 static void mpuio_mask_irq(unsigned int irq)
811 {
812 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
813 struct gpio_bank *bank = get_gpio_bank(gpio);
814
815 _set_gpio_irqenable(bank, gpio, 0);
816 }
817
818 static void mpuio_unmask_irq(unsigned int irq)
819 {
820 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
821 struct gpio_bank *bank = get_gpio_bank(gpio);
822
823 _set_gpio_irqenable(bank, gpio, 1);
824 }
825
826 static struct irqchip gpio_irq_chip = {
827 .ack = gpio_ack_irq,
828 .mask = gpio_mask_irq,
829 .unmask = gpio_unmask_irq,
830 .set_type = gpio_irq_type,
831 .set_wake = gpio_wake_enable,
832 };
833
834 static struct irqchip mpuio_irq_chip = {
835 .ack = mpuio_ack_irq,
836 .mask = mpuio_mask_irq,
837 .unmask = mpuio_unmask_irq
838 };
839
840 static int initialized;
841 static struct clk * gpio_ick;
842 static struct clk * gpio_fck;
843
844 static int __init _omap_gpio_init(void)
845 {
846 int i;
847 struct gpio_bank *bank;
848
849 initialized = 1;
850
851 if (cpu_is_omap1510()) {
852 gpio_ick = clk_get(NULL, "arm_gpio_ck");
853 if (IS_ERR(gpio_ick))
854 printk("Could not get arm_gpio_ck\n");
855 else
856 clk_enable(gpio_ick);
857 }
858 if (cpu_is_omap24xx()) {
859 gpio_ick = clk_get(NULL, "gpios_ick");
860 if (IS_ERR(gpio_ick))
861 printk("Could not get gpios_ick\n");
862 else
863 clk_enable(gpio_ick);
864 gpio_fck = clk_get(NULL, "gpios_fck");
865 if (IS_ERR(gpio_ick))
866 printk("Could not get gpios_fck\n");
867 else
868 clk_enable(gpio_fck);
869 }
870
871 #ifdef CONFIG_ARCH_OMAP15XX
872 if (cpu_is_omap1510()) {
873 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
874 gpio_bank_count = 2;
875 gpio_bank = gpio_bank_1510;
876 }
877 #endif
878 #if defined(CONFIG_ARCH_OMAP16XX)
879 if (cpu_is_omap16xx()) {
880 u32 rev;
881
882 gpio_bank_count = 5;
883 gpio_bank = gpio_bank_1610;
884 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
885 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
886 (rev >> 4) & 0x0f, rev & 0x0f);
887 }
888 #endif
889 #ifdef CONFIG_ARCH_OMAP730
890 if (cpu_is_omap730()) {
891 printk(KERN_INFO "OMAP730 GPIO hardware\n");
892 gpio_bank_count = 7;
893 gpio_bank = gpio_bank_730;
894 }
895 #endif
896 #ifdef CONFIG_ARCH_OMAP24XX
897 if (cpu_is_omap24xx()) {
898 int rev;
899
900 gpio_bank_count = 4;
901 gpio_bank = gpio_bank_24xx;
902 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
903 printk(KERN_INFO "OMAP24xx GPIO hardware version %d.%d\n",
904 (rev >> 4) & 0x0f, rev & 0x0f);
905 }
906 #endif
907 for (i = 0; i < gpio_bank_count; i++) {
908 int j, gpio_count = 16;
909
910 bank = &gpio_bank[i];
911 bank->reserved_map = 0;
912 bank->base = IO_ADDRESS(bank->base);
913 spin_lock_init(&bank->lock);
914 if (bank->method == METHOD_MPUIO) {
915 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
916 }
917 #ifdef CONFIG_ARCH_OMAP15XX
918 if (bank->method == METHOD_GPIO_1510) {
919 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
920 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
921 }
922 #endif
923 #if defined(CONFIG_ARCH_OMAP16XX)
924 if (bank->method == METHOD_GPIO_1610) {
925 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
926 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
927 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
928 }
929 #endif
930 #ifdef CONFIG_ARCH_OMAP730
931 if (bank->method == METHOD_GPIO_730) {
932 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
933 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
934
935 gpio_count = 32; /* 730 has 32-bit GPIOs */
936 }
937 #endif
938 #ifdef CONFIG_ARCH_OMAP24XX
939 if (bank->method == METHOD_GPIO_24XX) {
940 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
941 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
942
943 gpio_count = 32;
944 }
945 #endif
946 for (j = bank->virtual_irq_start;
947 j < bank->virtual_irq_start + gpio_count; j++) {
948 if (bank->method == METHOD_MPUIO)
949 set_irq_chip(j, &mpuio_irq_chip);
950 else
951 set_irq_chip(j, &gpio_irq_chip);
952 set_irq_handler(j, do_simple_IRQ);
953 set_irq_flags(j, IRQF_VALID);
954 }
955 set_irq_chained_handler(bank->irq, gpio_irq_handler);
956 set_irq_data(bank->irq, bank);
957 }
958
959 /* Enable system clock for GPIO module.
960 * The CAM_CLK_CTRL *is* really the right place. */
961 if (cpu_is_omap16xx())
962 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
963
964 return 0;
965 }
966
967 #if defined (CONFIG_ARCH_OMAP16XX) || defined (CONFIG_ARCH_OMAP24XX)
968 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
969 {
970 int i;
971
972 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
973 return 0;
974
975 for (i = 0; i < gpio_bank_count; i++) {
976 struct gpio_bank *bank = &gpio_bank[i];
977 void __iomem *wake_status;
978 void __iomem *wake_clear;
979 void __iomem *wake_set;
980
981 switch (bank->method) {
982 case METHOD_GPIO_1610:
983 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
984 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
985 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
986 break;
987 case METHOD_GPIO_24XX:
988 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
989 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
990 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
991 break;
992 default:
993 continue;
994 }
995
996 spin_lock(&bank->lock);
997 bank->saved_wakeup = __raw_readl(wake_status);
998 __raw_writel(0xffffffff, wake_clear);
999 __raw_writel(bank->suspend_wakeup, wake_set);
1000 spin_unlock(&bank->lock);
1001 }
1002
1003 return 0;
1004 }
1005
1006 static int omap_gpio_resume(struct sys_device *dev)
1007 {
1008 int i;
1009
1010 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1011 return 0;
1012
1013 for (i = 0; i < gpio_bank_count; i++) {
1014 struct gpio_bank *bank = &gpio_bank[i];
1015 void __iomem *wake_clear;
1016 void __iomem *wake_set;
1017
1018 switch (bank->method) {
1019 case METHOD_GPIO_1610:
1020 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1021 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1022 break;
1023 case METHOD_GPIO_24XX:
1024 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1025 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1026 break;
1027 default:
1028 continue;
1029 }
1030
1031 spin_lock(&bank->lock);
1032 __raw_writel(0xffffffff, wake_clear);
1033 __raw_writel(bank->saved_wakeup, wake_set);
1034 spin_unlock(&bank->lock);
1035 }
1036
1037 return 0;
1038 }
1039
1040 static struct sysdev_class omap_gpio_sysclass = {
1041 set_kset_name("gpio"),
1042 .suspend = omap_gpio_suspend,
1043 .resume = omap_gpio_resume,
1044 };
1045
1046 static struct sys_device omap_gpio_device = {
1047 .id = 0,
1048 .cls = &omap_gpio_sysclass,
1049 };
1050 #endif
1051
1052 /*
1053 * This may get called early from board specific init
1054 * for boards that have interrupts routed via FPGA.
1055 */
1056 int omap_gpio_init(void)
1057 {
1058 if (!initialized)
1059 return _omap_gpio_init();
1060 else
1061 return 0;
1062 }
1063
1064 static int __init omap_gpio_sysinit(void)
1065 {
1066 int ret = 0;
1067
1068 if (!initialized)
1069 ret = _omap_gpio_init();
1070
1071 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX)
1072 if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
1073 if (ret == 0) {
1074 ret = sysdev_class_register(&omap_gpio_sysclass);
1075 if (ret == 0)
1076 ret = sysdev_register(&omap_gpio_device);
1077 }
1078 }
1079 #endif
1080
1081 return ret;
1082 }
1083
1084 EXPORT_SYMBOL(omap_request_gpio);
1085 EXPORT_SYMBOL(omap_free_gpio);
1086 EXPORT_SYMBOL(omap_set_gpio_direction);
1087 EXPORT_SYMBOL(omap_set_gpio_dataout);
1088 EXPORT_SYMBOL(omap_get_gpio_datain);
1089
1090 arch_initcall(omap_gpio_sysinit);
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