qemu-kvm-x86.c

   1 /*
   2  * qemu/kvm integration, x86 specific code
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  *
   6  * Licensed under the terms of the GNU GPL version 2 or higher.
   7  */
   8
   9 #include "config.h"
  10 #include "config-host.h"
  11
  12 #include <string.h>
  13 #include "hw/hw.h"
  14 #include "gdbstub.h"
  15 #include <sys/io.h>
  16
  17 #include "qemu-kvm.h"
  18 #include "libkvm-all.h"
  19 #include <pthread.h>
  20 #include <sys/utsname.h>
  21 #include <linux/kvm_para.h>
  22
  23 #define MSR_IA32_TSC            0x10
  24
  25 static struct kvm_msr_list *kvm_msr_list;
  26 extern unsigned int kvm_shadow_memory;
  27 static int kvm_has_msr_star;
  28 static int kvm_has_vm_hsave_pa;
  29
  30 static int lm_capable_kernel;
  31
  32 int kvm_qemu_create_memory_alias(uint64_t phys_start,
  33                                  uint64_t len,
  34                                  uint64_t target_phys)
  35 {
  36     return kvm_create_memory_alias(kvm_context, phys_start, len, target_phys);
  37 }
  38
  39 int kvm_qemu_destroy_memory_alias(uint64_t phys_start)
  40 {
  41         return kvm_destroy_memory_alias(kvm_context, phys_start);
  42 }
  43
  44 int kvm_arch_qemu_create_context(void)
  45 {
  46     int i;
  47     struct utsname utsname;
  48
  49     uname(&utsname);
  50     lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
  51
  52     if (kvm_shadow_memory)
  53         kvm_set_shadow_pages(kvm_context, kvm_shadow_memory);
  54
  55     kvm_msr_list = kvm_get_msr_list(kvm_context);
  56     if (!kvm_msr_list)
  57                 return -1;
  58     for (i = 0; i < kvm_msr_list->nmsrs; ++i) {
  59         if (kvm_msr_list->indices[i] == MSR_STAR)
  60             kvm_has_msr_star = 1;
  61         if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA)
  62             kvm_has_vm_hsave_pa = 1;
  63     }
  64
  65     return 0;
  66 }
  67
  68 static void set_msr_entry(struct kvm_msr_entry *entry, uint32_t index,
  69                           uint64_t data)
  70 {
  71     entry->index = index;
  72     entry->data  = data;
  73 }
  74
  75 /* returns 0 on success, non-0 on failure */
  76 static int get_msr_entry(struct kvm_msr_entry *entry, CPUState *env)
  77 {
  78         switch (entry->index) {
  79         case MSR_IA32_SYSENTER_CS:
  80             env->sysenter_cs  = entry->data;
  81             break;
  82         case MSR_IA32_SYSENTER_ESP:
  83             env->sysenter_esp = entry->data;
  84             break;
  85         case MSR_IA32_SYSENTER_EIP:
  86             env->sysenter_eip = entry->data;
  87             break;
  88         case MSR_STAR:
  89             env->star         = entry->data;
  90             break;
  91 #ifdef TARGET_X86_64
  92         case MSR_CSTAR:
  93             env->cstar        = entry->data;
  94             break;
  95         case MSR_KERNELGSBASE:
  96             env->kernelgsbase = entry->data;
  97             break;
  98         case MSR_FMASK:
  99             env->fmask        = entry->data;
 100             break;
 101         case MSR_LSTAR:
 102             env->lstar        = entry->data;
 103             break;
 104 #endif
 105         case MSR_IA32_TSC:
 106             env->tsc          = entry->data;
 107             break;
 108         case MSR_VM_HSAVE_PA:
 109             env->vm_hsave     = entry->data;
 110             break;
 111         default:
 112             printf("Warning unknown msr index 0x%x\n", entry->index);
 113             return 1;
 114         }
 115         return 0;
 116 }
 117
 118 #ifdef TARGET_X86_64
 119 #define MSR_COUNT 9
 120 #else
 121 #define MSR_COUNT 5
 122 #endif
 123
 124 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 125 {
 126     lhs->selector = rhs->selector;
 127     lhs->base = rhs->base;
 128     lhs->limit = rhs->limit;
 129     lhs->type = 3;
 130     lhs->present = 1;
 131     lhs->dpl = 3;
 132     lhs->db = 0;
 133     lhs->s = 1;
 134     lhs->l = 0;
 135     lhs->g = 0;
 136     lhs->avl = 0;
 137     lhs->unusable = 0;
 138 }
 139
 140 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 141 {
 142     unsigned flags = rhs->flags;
 143     lhs->selector = rhs->selector;
 144     lhs->base = rhs->base;
 145     lhs->limit = rhs->limit;
 146     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 147     lhs->present = (flags & DESC_P_MASK) != 0;
 148     lhs->dpl = rhs->selector & 3;
 149     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 150     lhs->s = (flags & DESC_S_MASK) != 0;
 151     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 152     lhs->g = (flags & DESC_G_MASK) != 0;
 153     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 154     lhs->unusable = 0;
 155 }
 156
 157 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 158 {
 159     lhs->selector = rhs->selector;
 160     lhs->base = rhs->base;
 161     lhs->limit = rhs->limit;
 162     lhs->flags =
 163         (rhs->type << DESC_TYPE_SHIFT)
 164         | (rhs->present * DESC_P_MASK)
 165         | (rhs->dpl << DESC_DPL_SHIFT)
 166         | (rhs->db << DESC_B_SHIFT)
 167         | (rhs->s * DESC_S_MASK)
 168         | (rhs->l << DESC_L_SHIFT)
 169         | (rhs->g * DESC_G_MASK)
 170         | (rhs->avl * DESC_AVL_MASK);
 171 }
 172
 173 void kvm_arch_load_regs(CPUState *env)
 174 {
 175     struct kvm_regs regs;
 176     struct kvm_fpu fpu;
 177     struct kvm_sregs sregs;
 178     struct kvm_msr_entry msrs[MSR_COUNT];
 179     int rc, n, i;
 180
 181     regs.rax = env->regs[R_EAX];
 182     regs.rbx = env->regs[R_EBX];
 183     regs.rcx = env->regs[R_ECX];
 184     regs.rdx = env->regs[R_EDX];
 185     regs.rsi = env->regs[R_ESI];
 186     regs.rdi = env->regs[R_EDI];
 187     regs.rsp = env->regs[R_ESP];
 188     regs.rbp = env->regs[R_EBP];
 189 #ifdef TARGET_X86_64
 190     regs.r8 = env->regs[8];
 191     regs.r9 = env->regs[9];
 192     regs.r10 = env->regs[10];
 193     regs.r11 = env->regs[11];
 194     regs.r12 = env->regs[12];
 195     regs.r13 = env->regs[13];
 196     regs.r14 = env->regs[14];
 197     regs.r15 = env->regs[15];
 198 #endif
 199
 200     regs.rflags = env->eflags;
 201     regs.rip = env->eip;
 202
 203     kvm_set_regs(kvm_context, env->cpu_index, &regs);
 204
 205     memset(&fpu, 0, sizeof fpu);
 206     fpu.fsw = env->fpus & ~(7 << 11);
 207     fpu.fsw |= (env->fpstt & 7) << 11;
 208     fpu.fcw = env->fpuc;
 209     for (i = 0; i < 8; ++i)
 210         fpu.ftwx |= (!env->fptags[i]) << i;
 211     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 212     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 213     fpu.mxcsr = env->mxcsr;
 214     kvm_set_fpu(kvm_context, env->cpu_index, &fpu);
 215
 216     memcpy(sregs.interrupt_bitmap, env->interrupt_bitmap, sizeof(sregs.interrupt_bitmap));
 217
 218     if ((env->eflags & VM_MASK)) {
 219             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 220             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 221             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 222             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 223             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 224             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 225     } else {
 226             set_seg(&sregs.cs, &env->segs[R_CS]);
 227             set_seg(&sregs.ds, &env->segs[R_DS]);
 228             set_seg(&sregs.es, &env->segs[R_ES]);
 229             set_seg(&sregs.fs, &env->segs[R_FS]);
 230             set_seg(&sregs.gs, &env->segs[R_GS]);
 231             set_seg(&sregs.ss, &env->segs[R_SS]);
 232
 233             if (env->cr[0] & CR0_PE_MASK) {
 234                 /* force ss cpl to cs cpl */
 235                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 236                         (sregs.cs.selector & 3);
 237                 sregs.ss.dpl = sregs.ss.selector & 3;
 238             }
 239     }
 240
 241     set_seg(&sregs.tr, &env->tr);
 242     set_seg(&sregs.ldt, &env->ldt);
 243
 244     sregs.idt.limit = env->idt.limit;
 245     sregs.idt.base = env->idt.base;
 246     sregs.gdt.limit = env->gdt.limit;
 247     sregs.gdt.base = env->gdt.base;
 248
 249     sregs.cr0 = env->cr[0];
 250     sregs.cr2 = env->cr[2];
 251     sregs.cr3 = env->cr[3];
 252     sregs.cr4 = env->cr[4];
 253
 254     sregs.cr8 = cpu_get_apic_tpr(env);
 255     sregs.apic_base = cpu_get_apic_base(env);
 256
 257     sregs.efer = env->efer;
 258
 259     kvm_set_sregs(kvm_context, env->cpu_index, &sregs);
 260
 261     /* msrs */
 262     n = 0;
 263     set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_CS,  env->sysenter_cs);
 264     set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 265     set_msr_entry(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 266     if (kvm_has_msr_star)
 267         set_msr_entry(&msrs[n++], MSR_STAR,              env->star);
 268     if (kvm_has_vm_hsave_pa)
 269         set_msr_entry(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 270 #ifdef TARGET_X86_64
 271     if (lm_capable_kernel) {
 272         set_msr_entry(&msrs[n++], MSR_CSTAR,             env->cstar);
 273         set_msr_entry(&msrs[n++], MSR_KERNELGSBASE,      env->kernelgsbase);
 274         set_msr_entry(&msrs[n++], MSR_FMASK,             env->fmask);
 275         set_msr_entry(&msrs[n++], MSR_LSTAR  ,           env->lstar);
 276     }
 277 #endif
 278
 279     rc = kvm_set_msrs(kvm_context, env->cpu_index, msrs, n);
 280     if (rc == -1)
 281         perror("kvm_set_msrs FAILED");
 282 }
 283
 284 void kvm_load_tsc(CPUState *env)
 285 {
 286     int rc;
 287     struct kvm_msr_entry msr;
 288
 289     set_msr_entry(&msr, MSR_IA32_TSC, env->tsc);
 290
 291     rc = kvm_set_msrs(kvm_context, env->cpu_index, &msr, 1);
 292     if (rc == -1)
 293         perror("kvm_set_tsc FAILED.\n");
 294 }
 295
 296 void kvm_save_mpstate(CPUState *env)
 297 {
 298 #ifdef KVM_CAP_MP_STATE
 299     int r;
 300     struct kvm_mp_state mp_state;
 301
 302     r = kvm_get_mpstate(kvm_context, env->cpu_index, &mp_state);
 303     if (r < 0)
 304         env->mp_state = -1;
 305     else
 306         env->mp_state = mp_state.mp_state;
 307 #endif
 308 }
 309
 310 void kvm_load_mpstate(CPUState *env)
 311 {
 312 #ifdef KVM_CAP_MP_STATE
 313     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
 314
 315     /*
 316      * -1 indicates that the host did not support GET_MP_STATE ioctl,
 317      *  so don't touch it.
 318      */
 319     if (env->mp_state != -1)
 320         kvm_set_mpstate(kvm_context, env->cpu_index, &mp_state);
 321 #endif
 322 }
 323
 324 void kvm_arch_save_regs(CPUState *env)
 325 {
 326     struct kvm_regs regs;
 327     struct kvm_fpu fpu;
 328     struct kvm_sregs sregs;
 329     struct kvm_msr_entry msrs[MSR_COUNT];
 330     uint32_t hflags;
 331     uint32_t i, n, rc;
 332
 333     kvm_get_regs(kvm_context, env->cpu_index, &regs);
 334
 335     env->regs[R_EAX] = regs.rax;
 336     env->regs[R_EBX] = regs.rbx;
 337     env->regs[R_ECX] = regs.rcx;
 338     env->regs[R_EDX] = regs.rdx;
 339     env->regs[R_ESI] = regs.rsi;
 340     env->regs[R_EDI] = regs.rdi;
 341     env->regs[R_ESP] = regs.rsp;
 342     env->regs[R_EBP] = regs.rbp;
 343 #ifdef TARGET_X86_64
 344     env->regs[8] = regs.r8;
 345     env->regs[9] = regs.r9;
 346     env->regs[10] = regs.r10;
 347     env->regs[11] = regs.r11;
 348     env->regs[12] = regs.r12;
 349     env->regs[13] = regs.r13;
 350     env->regs[14] = regs.r14;
 351     env->regs[15] = regs.r15;
 352 #endif
 353
 354     env->eflags = regs.rflags;
 355     env->eip = regs.rip;
 356
 357     kvm_get_fpu(kvm_context, env->cpu_index, &fpu);
 358     env->fpstt = (fpu.fsw >> 11) & 7;
 359     env->fpus = fpu.fsw;
 360     env->fpuc = fpu.fcw;
 361     for (i = 0; i < 8; ++i)
 362         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 363     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 364     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 365     env->mxcsr = fpu.mxcsr;
 366
 367     kvm_get_sregs(kvm_context, env->cpu_index, &sregs);
 368
 369     memcpy(env->interrupt_bitmap, sregs.interrupt_bitmap, sizeof(env->interrupt_bitmap));
 370
 371     get_seg(&env->segs[R_CS], &sregs.cs);
 372     get_seg(&env->segs[R_DS], &sregs.ds);
 373     get_seg(&env->segs[R_ES], &sregs.es);
 374     get_seg(&env->segs[R_FS], &sregs.fs);
 375     get_seg(&env->segs[R_GS], &sregs.gs);
 376     get_seg(&env->segs[R_SS], &sregs.ss);
 377
 378     get_seg(&env->tr, &sregs.tr);
 379     get_seg(&env->ldt, &sregs.ldt);
 380
 381     env->idt.limit = sregs.idt.limit;
 382     env->idt.base = sregs.idt.base;
 383     env->gdt.limit = sregs.gdt.limit;
 384     env->gdt.base = sregs.gdt.base;
 385
 386     env->cr[0] = sregs.cr0;
 387     env->cr[2] = sregs.cr2;
 388     env->cr[3] = sregs.cr3;
 389     env->cr[4] = sregs.cr4;
 390
 391     cpu_set_apic_base(env, sregs.apic_base);
 392
 393     env->efer = sregs.efer;
 394     //cpu_set_apic_tpr(env, sregs.cr8);
 395
 396 #define HFLAG_COPY_MASK ~( \
 397                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 398                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 399                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 400                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 401
 402
 403
 404     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 405     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 406     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 407             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 408     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 409     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 410             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 411
 412     if (env->efer & MSR_EFER_LMA) {
 413         hflags |= HF_LMA_MASK;
 414     }
 415
 416     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 417         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 418     } else {
 419         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 420                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 421         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 422                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 423         if (!(env->cr[0] & CR0_PE_MASK) ||
 424                    (env->eflags & VM_MASK) ||
 425                    !(hflags & HF_CS32_MASK)) {
 426                 hflags |= HF_ADDSEG_MASK;
 427             } else {
 428                 hflags |= ((env->segs[R_DS].base |
 429                                 env->segs[R_ES].base |
 430                                 env->segs[R_SS].base) != 0) <<
 431                     HF_ADDSEG_SHIFT;
 432             }
 433     }
 434     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 435
 436     /* msrs */
 437     n = 0;
 438     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 439     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 440     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 441     if (kvm_has_msr_star)
 442         msrs[n++].index = MSR_STAR;
 443     msrs[n++].index = MSR_IA32_TSC;
 444     if (kvm_has_vm_hsave_pa)
 445         msrs[n++].index = MSR_VM_HSAVE_PA;
 446 #ifdef TARGET_X86_64
 447     if (lm_capable_kernel) {
 448         msrs[n++].index = MSR_CSTAR;
 449         msrs[n++].index = MSR_KERNELGSBASE;
 450         msrs[n++].index = MSR_FMASK;
 451         msrs[n++].index = MSR_LSTAR;
 452     }
 453 #endif
 454     rc = kvm_get_msrs(kvm_context, env->cpu_index, msrs, n);
 455     if (rc == -1) {
 456         perror("kvm_get_msrs FAILED");
 457     }
 458     else {
 459         n = rc; /* actual number of MSRs */
 460         for (i=0 ; i<n; i++) {
 461             if (get_msr_entry(&msrs[i], env))
 462                 return;
 463         }
 464     }
 465 }
 466
 467 static void do_cpuid_ent(struct kvm_cpuid_entry2 *e, uint32_t function,
 468                          uint32_t count, CPUState *env)
 469 {
 470     env->regs[R_EAX] = function;
 471     env->regs[R_ECX] = count;
 472     qemu_kvm_cpuid_on_env(env);
 473     e->function = function;
 474     e->flags = 0;
 475     e->index = 0;
 476     e->eax = env->regs[R_EAX];
 477     e->ebx = env->regs[R_EBX];
 478     e->ecx = env->regs[R_ECX];
 479     e->edx = env->regs[R_EDX];
 480 }
 481
 482 struct kvm_para_features {
 483         int cap;
 484         int feature;
 485 } para_features[] = {
 486 #ifdef KVM_CAP_CLOCKSOURCE
 487         { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 488 #endif
 489 #ifdef KVM_CAP_NOP_IO_DELAY
 490         { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 491 #endif
 492 #ifdef KVM_CAP_PV_MMU
 493         { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 494 #endif
 495 #ifdef KVM_CAP_CR3_CACHE
 496         { KVM_CAP_CR3_CACHE, KVM_FEATURE_CR3_CACHE },
 497 #endif
 498         { -1, -1 }
 499 };
 500
 501 static int get_para_features(kvm_context_t kvm_context)
 502 {
 503         int i, features = 0;
 504
 505         for (i = 0; i < ARRAY_SIZE(para_features)-1; i++) {
 506                 if (kvm_check_extension(kvm_context, para_features[i].cap))
 507                         features |= (1 << para_features[i].feature);
 508         }
 509
 510         return features;
 511 }
 512
 513 static void kvm_trim_features(uint32_t *features, uint32_t supported)
 514 {
 515     int i;
 516     uint32_t mask;
 517
 518     for (i = 0; i < 32; ++i) {
 519         mask = 1U << i;
 520         if ((*features & mask) && !(supported & mask)) {
 521             *features &= ~mask;
 522         }
 523     }
 524 }
 525
 526 int kvm_arch_qemu_init_env(CPUState *cenv)
 527 {
 528     struct kvm_cpuid_entry2 cpuid_ent[100];
 529 #ifdef KVM_CPUID_SIGNATURE
 530     struct kvm_cpuid_entry2 *pv_ent;
 531     uint32_t signature[3];
 532 #endif
 533     int cpuid_nent = 0;
 534     CPUState copy;
 535     uint32_t i, j, limit;
 536
 537     qemu_kvm_load_lapic(cenv);
 538
 539     copy = *cenv;
 540
 541 #ifdef KVM_CPUID_SIGNATURE
 542     /* Paravirtualization CPUIDs */
 543     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 544     pv_ent = &cpuid_ent[cpuid_nent++];
 545     memset(pv_ent, 0, sizeof(*pv_ent));
 546     pv_ent->function = KVM_CPUID_SIGNATURE;
 547     pv_ent->eax = 0;
 548     pv_ent->ebx = signature[0];
 549     pv_ent->ecx = signature[1];
 550     pv_ent->edx = signature[2];
 551
 552     pv_ent = &cpuid_ent[cpuid_nent++];
 553     memset(pv_ent, 0, sizeof(*pv_ent));
 554     pv_ent->function = KVM_CPUID_FEATURES;
 555     pv_ent->eax = get_para_features(kvm_context);
 556 #endif
 557
 558     copy.regs[R_EAX] = 0;
 559     qemu_kvm_cpuid_on_env(&copy);
 560     limit = copy.regs[R_EAX];
 561
 562     for (i = 0; i <= limit; ++i) {
 563         if (i == 4 || i == 0xb || i == 0xd) {
 564             for (j = 0; ; ++j) {
 565                 do_cpuid_ent(&cpuid_ent[cpuid_nent], i, j, &copy);
 566
 567                 cpuid_ent[cpuid_nent].flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 568                 cpuid_ent[cpuid_nent].index = j;
 569
 570                 cpuid_nent++;
 571
 572                 if (i == 4 && copy.regs[R_EAX] == 0)
 573                     break;
 574                 if (i == 0xb && !(copy.regs[R_ECX] & 0xff00))
 575                     break;
 576                 if (i == 0xd && copy.regs[R_EAX] == 0)
 577                     break;
 578             }
 579         } else
 580             do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
 581     }
 582
 583     copy.regs[R_EAX] = 0x80000000;
 584     qemu_kvm_cpuid_on_env(&copy);
 585     limit = copy.regs[R_EAX];
 586
 587     for (i = 0x80000000; i <= limit; ++i)
 588         do_cpuid_ent(&cpuid_ent[cpuid_nent++], i, 0, &copy);
 589
 590     kvm_setup_cpuid2(kvm_context, cenv->cpu_index, cpuid_nent, cpuid_ent);
 591
 592     kvm_trim_features(&cenv->cpuid_features,
 593                       kvm_arch_get_supported_cpuid(cenv, 1, R_EDX));
 594     kvm_trim_features(&cenv->cpuid_ext_features,
 595                       kvm_arch_get_supported_cpuid(cenv, 1, R_ECX));
 596     kvm_trim_features(&cenv->cpuid_ext2_features,
 597                       kvm_arch_get_supported_cpuid(cenv, 0x80000001, R_EDX));
 598     kvm_trim_features(&cenv->cpuid_ext3_features,
 599                       kvm_arch_get_supported_cpuid(cenv, 0x80000001, R_ECX));
 600
 601     return 0;
 602 }
 603
 604 int kvm_arch_halt(void *opaque, int vcpu)
 605 {
 606     CPUState *env = cpu_single_env;
 607
 608     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 609           (env->eflags & IF_MASK)) &&
 610         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
 611             env->halted = 1;
 612             env->exception_index = EXCP_HLT;
 613     }
 614     return 1;
 615 }
 616
 617 void kvm_arch_pre_kvm_run(void *opaque, CPUState *env)
 618 {
 619     if (!kvm_irqchip_in_kernel(kvm_context))
 620         kvm_set_cr8(kvm_context, env->cpu_index, cpu_get_apic_tpr(env));
 621 }
 622
 623 void kvm_arch_post_kvm_run(void *opaque, CPUState *env)
 624 {
 625     int vcpu = env->cpu_index;
 626
 627     cpu_single_env = env;
 628
 629     env->eflags = kvm_get_interrupt_flag(kvm_context, vcpu)
 630         ? env->eflags | IF_MASK : env->eflags & ~IF_MASK;
 631
 632     cpu_set_apic_tpr(env, kvm_get_cr8(kvm_context, vcpu));
 633     cpu_set_apic_base(env, kvm_get_apic_base(kvm_context, vcpu));
 634 }
 635
 636 int kvm_arch_has_work(CPUState *env)
 637 {
 638     if (env->exit_request ||
 639         ((env->interrupt_request & CPU_INTERRUPT_HARD) &&
 640          (env->eflags & IF_MASK)) ||
 641         (env->interrupt_request & CPU_INTERRUPT_NMI))
 642         return 1;
 643     return 0;
 644 }
 645
 646 int kvm_arch_try_push_interrupts(void *opaque)
 647 {
 648     CPUState *env = cpu_single_env;
 649     int r, irq;
 650
 651     if (kvm_is_ready_for_interrupt_injection(kvm_context, env->cpu_index) &&
 652         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
 653         (env->eflags & IF_MASK)) {
 654             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 655             irq = cpu_get_pic_interrupt(env);
 656             if (irq >= 0) {
 657                 r = kvm_inject_irq(kvm_context, env->cpu_index, irq);
 658                 if (r < 0)
 659                     printf("cpu %d fail inject %x\n", env->cpu_index, irq);
 660             }
 661     }
 662
 663     return (env->interrupt_request & CPU_INTERRUPT_HARD) != 0;
 664 }
 665
 666 #ifdef KVM_CAP_USER_NMI
 667 void kvm_arch_push_nmi(void *opaque)
 668 {
 669     CPUState *env = cpu_single_env;
 670     int r;
 671
 672     if (likely(!(env->interrupt_request & CPU_INTERRUPT_NMI)))
 673         return;
 674
 675     env->interrupt_request &= ~CPU_INTERRUPT_NMI;
 676     r = kvm_inject_nmi(kvm_context, env->cpu_index);
 677     if (r < 0)
 678         printf("cpu %d fail inject NMI\n", env->cpu_index);
 679 }
 680 #endif /* KVM_CAP_USER_NMI */
 681
 682 void kvm_arch_update_regs_for_sipi(CPUState *env)
 683 {
 684     SegmentCache cs = env->segs[R_CS];
 685
 686     kvm_arch_save_regs(env);
 687     env->segs[R_CS] = cs;
 688     env->eip = 0;
 689     kvm_arch_load_regs(env);
 690 }
 691
 692 int handle_tpr_access(void *opaque, int vcpu,
 693                              uint64_t rip, int is_write)
 694 {
 695     kvm_tpr_access_report(cpu_single_env, rip, is_write);
 696     return 0;
 697 }
 698
 699 void kvm_arch_cpu_reset(CPUState *env)
 700 {
 701     kvm_arch_load_regs(env);
 702     if (env->cpu_index != 0) {
 703         if (kvm_irqchip_in_kernel(kvm_context)) {
 704 #ifdef KVM_CAP_MP_STATE
 705             kvm_reset_mpstate(kvm_context, env->cpu_index);
 706 #endif
 707         } else {
 708             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 709             env->halted = 1;
 710             env->exception_index = EXCP_HLT;
 711         }
 712     }
 713 }
 714
 715 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 716 {
 717     uint8_t int3 = 0xcc;
 718
 719     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
 720         cpu_memory_rw_debug(env, bp->pc, &int3, 1, 1))
 721         return -EINVAL;
 722     return 0;
 723 }
 724
 725 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
 726 {
 727     uint8_t int3;
 728
 729     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
 730         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
 731         return -EINVAL;
 732     return 0;
 733 }
 734
 735 #ifdef KVM_CAP_SET_GUEST_DEBUG
 736 static struct {
 737     target_ulong addr;
 738     int len;
 739     int type;
 740 } hw_breakpoint[4];
 741
 742 static int nb_hw_breakpoint;
 743
 744 static int find_hw_breakpoint(target_ulong addr, int len, int type)
 745 {
 746     int n;
 747
 748     for (n = 0; n < nb_hw_breakpoint; n++)
 749         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
 750             (hw_breakpoint[n].len == len || len == -1))
 751             return n;
 752     return -1;
 753 }
 754
 755 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
 756                                   target_ulong len, int type)
 757 {
 758     switch (type) {
 759     case GDB_BREAKPOINT_HW:
 760         len = 1;
 761         break;
 762     case GDB_WATCHPOINT_WRITE:
 763     case GDB_WATCHPOINT_ACCESS:
 764         switch (len) {
 765         case 1:
 766             break;
 767         case 2:
 768         case 4:
 769         case 8:
 770             if (addr & (len - 1))
 771                 return -EINVAL;
 772             break;
 773         default:
 774             return -EINVAL;
 775         }
 776         break;
 777     default:
 778         return -ENOSYS;
 779     }
 780
 781     if (nb_hw_breakpoint == 4)
 782         return -ENOBUFS;
 783
 784     if (find_hw_breakpoint(addr, len, type) >= 0)
 785         return -EEXIST;
 786
 787     hw_breakpoint[nb_hw_breakpoint].addr = addr;
 788     hw_breakpoint[nb_hw_breakpoint].len = len;
 789     hw_breakpoint[nb_hw_breakpoint].type = type;
 790     nb_hw_breakpoint++;
 791
 792     return 0;
 793 }
 794
 795 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
 796                                   target_ulong len, int type)
 797 {
 798     int n;
 799
 800     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
 801     if (n < 0)
 802         return -ENOENT;
 803
 804     nb_hw_breakpoint--;
 805     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
 806
 807     return 0;
 808 }
 809
 810 void kvm_arch_remove_all_hw_breakpoints(void)
 811 {
 812     nb_hw_breakpoint = 0;
 813 }
 814
 815 static CPUWatchpoint hw_watchpoint;
 816
 817 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
 818 {
 819     int handle = 0;
 820     int n;
 821
 822     if (arch_info->exception == 1) {
 823         if (arch_info->dr6 & (1 << 14)) {
 824             if (cpu_single_env->singlestep_enabled)
 825                 handle = 1;
 826         } else {
 827             for (n = 0; n < 4; n++)
 828                 if (arch_info->dr6 & (1 << n))
 829                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
 830                     case 0x0:
 831                         handle = 1;
 832                         break;
 833                     case 0x1:
 834                         handle = 1;
 835                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
 836                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
 837                         hw_watchpoint.flags = BP_MEM_WRITE;
 838                         break;
 839                     case 0x3:
 840                         handle = 1;
 841                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
 842                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
 843                         hw_watchpoint.flags = BP_MEM_ACCESS;
 844                         break;
 845                     }
 846         }
 847     } else if (kvm_find_sw_breakpoint(arch_info->pc))
 848         handle = 1;
 849
 850     if (!handle)
 851         kvm_update_guest_debug(cpu_single_env,
 852                         (arch_info->exception == 1) ?
 853                         KVM_GUESTDBG_INJECT_DB : KVM_GUESTDBG_INJECT_BP);
 854
 855     return handle;
 856 }
 857
 858 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
 859 {
 860     const uint8_t type_code[] = {
 861         [GDB_BREAKPOINT_HW] = 0x0,
 862         [GDB_WATCHPOINT_WRITE] = 0x1,
 863         [GDB_WATCHPOINT_ACCESS] = 0x3
 864     };
 865     const uint8_t len_code[] = {
 866         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
 867     };
 868     int n;
 869
 870     if (!TAILQ_EMPTY(&kvm_sw_breakpoints))
 871         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
 872
 873     if (nb_hw_breakpoint > 0) {
 874         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
 875         dbg->arch.debugreg[7] = 0x0600;
 876         for (n = 0; n < nb_hw_breakpoint; n++) {
 877             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
 878             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
 879                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
 880                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
 881         }
 882     }
 883 }
 884 #endif
 885
 886 void kvm_arch_do_ioperm(void *_data)
 887 {
 888     struct ioperm_data *data = _data;
 889     ioperm(data->start_port, data->num, data->turn_on);
 890 }
 891
 892 /*
 893  * Setup x86 specific IRQ routing
 894  */
 895 int kvm_arch_init_irq_routing(void)
 896 {
 897     int i, r;
 898
 899     if (kvm_irqchip && kvm_has_gsi_routing(kvm_context)) {
 900         kvm_clear_gsi_routes(kvm_context);
 901         for (i = 0; i < 8; ++i) {
 902             if (i == 2)
 903                 continue;
 904             r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_PIC_MASTER, i);
 905             if (r < 0)
 906                 return r;
 907         }
 908         for (i = 8; i < 16; ++i) {
 909             r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
 910             if (r < 0)
 911                 return r;
 912         }
 913         for (i = 0; i < 24; ++i) {
 914             r = kvm_add_irq_route(kvm_context, i, KVM_IRQCHIP_IOAPIC, i);
 915             if (r < 0)
 916                 return r;
 917         }
 918         kvm_commit_irq_routes(kvm_context);
 919     }
 920     return 0;
 921 }
 922
 923 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
 924                                       int reg)
 925 {
 926     return kvm_get_supported_cpuid(kvm_context, function, reg);
 927 }