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qapi/error: Check format string argument in error_*prepend()
[qemu/armbru.git] / hw / block / fdc.c
blobe9ed3eef45527e4ed8505ebe58b0679aa8ef1fcc
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "qemu/osdep.h"
31 #include "hw/block/fdc.h"
32 #include "qapi/error.h"
33 #include "qemu/error-report.h"
34 #include "qemu/timer.h"
35 #include "hw/acpi/aml-build.h"
36 #include "hw/irq.h"
37 #include "hw/isa/isa.h"
38 #include "hw/qdev-properties.h"
39 #include "hw/sysbus.h"
40 #include "migration/vmstate.h"
41 #include "hw/block/block.h"
42 #include "sysemu/block-backend.h"
43 #include "sysemu/blockdev.h"
44 #include "sysemu/sysemu.h"
45 #include "qemu/log.h"
46 #include "qemu/main-loop.h"
47 #include "qemu/module.h"
48 #include "trace.h"
49
50 /********************************************************/
51 /* debug Floppy devices */
52
53 #define DEBUG_FLOPPY 0
54
55 #define FLOPPY_DPRINTF(fmt, ...) \
56 do { \
57 if (DEBUG_FLOPPY) { \
58 fprintf(stderr, "FLOPPY: " fmt , ## __VA_ARGS__); \
59 } \
60 } while (0)
61
62
63 /********************************************************/
64 /* qdev floppy bus */
65
66 #define TYPE_FLOPPY_BUS "floppy-bus"
67 #define FLOPPY_BUS(obj) OBJECT_CHECK(FloppyBus, (obj), TYPE_FLOPPY_BUS)
68
69 typedef struct FDCtrl FDCtrl;
70 typedef struct FDrive FDrive;
71 static FDrive *get_drv(FDCtrl *fdctrl, int unit);
72
73 typedef struct FloppyBus {
74 BusState bus;
75 FDCtrl *fdc;
76 } FloppyBus;
77
78 static const TypeInfo floppy_bus_info = {
79 .name = TYPE_FLOPPY_BUS,
80 .parent = TYPE_BUS,
81 .instance_size = sizeof(FloppyBus),
82 };
83
84 static void floppy_bus_create(FDCtrl *fdc, FloppyBus *bus, DeviceState *dev)
85 {
86 qbus_create_inplace(bus, sizeof(FloppyBus), TYPE_FLOPPY_BUS, dev, NULL);
87 bus->fdc = fdc;
88 }
89
90
91 /********************************************************/
92 /* Floppy drive emulation */
93
94 typedef enum FDriveRate {
95 FDRIVE_RATE_500K = 0x00, /* 500 Kbps */
96 FDRIVE_RATE_300K = 0x01, /* 300 Kbps */
97 FDRIVE_RATE_250K = 0x02, /* 250 Kbps */
98 FDRIVE_RATE_1M = 0x03, /* 1 Mbps */
99 } FDriveRate;
100
101 typedef enum FDriveSize {
102 FDRIVE_SIZE_UNKNOWN,
103 FDRIVE_SIZE_350,
104 FDRIVE_SIZE_525,
105 } FDriveSize;
106
107 typedef struct FDFormat {
108 FloppyDriveType drive;
109 uint8_t last_sect;
110 uint8_t max_track;
111 uint8_t max_head;
112 FDriveRate rate;
113 } FDFormat;
114
115 /* In many cases, the total sector size of a format is enough to uniquely
116 * identify it. However, there are some total sector collisions between
117 * formats of different physical size, and these are noted below by
118 * highlighting the total sector size for entries with collisions. */
119 static const FDFormat fd_formats[] = {
120 /* First entry is default format */
121 /* 1.44 MB 3"1/2 floppy disks */
122 { FLOPPY_DRIVE_TYPE_144, 18, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 2880 */
123 { FLOPPY_DRIVE_TYPE_144, 20, 80, 1, FDRIVE_RATE_500K, }, /* 3.5" 3200 */
124 { FLOPPY_DRIVE_TYPE_144, 21, 80, 1, FDRIVE_RATE_500K, },
125 { FLOPPY_DRIVE_TYPE_144, 21, 82, 1, FDRIVE_RATE_500K, },
126 { FLOPPY_DRIVE_TYPE_144, 21, 83, 1, FDRIVE_RATE_500K, },
127 { FLOPPY_DRIVE_TYPE_144, 22, 80, 1, FDRIVE_RATE_500K, },
128 { FLOPPY_DRIVE_TYPE_144, 23, 80, 1, FDRIVE_RATE_500K, },
129 { FLOPPY_DRIVE_TYPE_144, 24, 80, 1, FDRIVE_RATE_500K, },
130 /* 2.88 MB 3"1/2 floppy disks */
131 { FLOPPY_DRIVE_TYPE_288, 36, 80, 1, FDRIVE_RATE_1M, },
132 { FLOPPY_DRIVE_TYPE_288, 39, 80, 1, FDRIVE_RATE_1M, },
133 { FLOPPY_DRIVE_TYPE_288, 40, 80, 1, FDRIVE_RATE_1M, },
134 { FLOPPY_DRIVE_TYPE_288, 44, 80, 1, FDRIVE_RATE_1M, },
135 { FLOPPY_DRIVE_TYPE_288, 48, 80, 1, FDRIVE_RATE_1M, },
136 /* 720 kB 3"1/2 floppy disks */
137 { FLOPPY_DRIVE_TYPE_144, 9, 80, 1, FDRIVE_RATE_250K, }, /* 3.5" 1440 */
138 { FLOPPY_DRIVE_TYPE_144, 10, 80, 1, FDRIVE_RATE_250K, },
139 { FLOPPY_DRIVE_TYPE_144, 10, 82, 1, FDRIVE_RATE_250K, },
140 { FLOPPY_DRIVE_TYPE_144, 10, 83, 1, FDRIVE_RATE_250K, },
141 { FLOPPY_DRIVE_TYPE_144, 13, 80, 1, FDRIVE_RATE_250K, },
142 { FLOPPY_DRIVE_TYPE_144, 14, 80, 1, FDRIVE_RATE_250K, },
143 /* 1.2 MB 5"1/4 floppy disks */
144 { FLOPPY_DRIVE_TYPE_120, 15, 80, 1, FDRIVE_RATE_500K, },
145 { FLOPPY_DRIVE_TYPE_120, 18, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 2880 */
146 { FLOPPY_DRIVE_TYPE_120, 18, 82, 1, FDRIVE_RATE_500K, },
147 { FLOPPY_DRIVE_TYPE_120, 18, 83, 1, FDRIVE_RATE_500K, },
148 { FLOPPY_DRIVE_TYPE_120, 20, 80, 1, FDRIVE_RATE_500K, }, /* 5.25" 3200 */
149 /* 720 kB 5"1/4 floppy disks */
150 { FLOPPY_DRIVE_TYPE_120, 9, 80, 1, FDRIVE_RATE_250K, }, /* 5.25" 1440 */
151 { FLOPPY_DRIVE_TYPE_120, 11, 80, 1, FDRIVE_RATE_250K, },
152 /* 360 kB 5"1/4 floppy disks */
153 { FLOPPY_DRIVE_TYPE_120, 9, 40, 1, FDRIVE_RATE_300K, }, /* 5.25" 720 */
154 { FLOPPY_DRIVE_TYPE_120, 9, 40, 0, FDRIVE_RATE_300K, },
155 { FLOPPY_DRIVE_TYPE_120, 10, 41, 1, FDRIVE_RATE_300K, },
156 { FLOPPY_DRIVE_TYPE_120, 10, 42, 1, FDRIVE_RATE_300K, },
157 /* 320 kB 5"1/4 floppy disks */
158 { FLOPPY_DRIVE_TYPE_120, 8, 40, 1, FDRIVE_RATE_250K, },
159 { FLOPPY_DRIVE_TYPE_120, 8, 40, 0, FDRIVE_RATE_250K, },
160 /* 360 kB must match 5"1/4 better than 3"1/2... */
161 { FLOPPY_DRIVE_TYPE_144, 9, 80, 0, FDRIVE_RATE_250K, }, /* 3.5" 720 */
162 /* end */
163 { FLOPPY_DRIVE_TYPE_NONE, -1, -1, 0, 0, },
164 };
165
166 static FDriveSize drive_size(FloppyDriveType drive)
167 {
168 switch (drive) {
169 case FLOPPY_DRIVE_TYPE_120:
170 return FDRIVE_SIZE_525;
171 case FLOPPY_DRIVE_TYPE_144:
172 case FLOPPY_DRIVE_TYPE_288:
173 return FDRIVE_SIZE_350;
174 default:
175 return FDRIVE_SIZE_UNKNOWN;
176 }
177 }
178
179 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
180 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
181
182 /* Will always be a fixed parameter for us */
183 #define FD_SECTOR_LEN 512
184 #define FD_SECTOR_SC 2 /* Sector size code */
185 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
186
187 /* Floppy disk drive emulation */
188 typedef enum FDiskFlags {
189 FDISK_DBL_SIDES = 0x01,
190 } FDiskFlags;
191
192 struct FDrive {
193 FDCtrl *fdctrl;
194 BlockBackend *blk;
195 BlockConf *conf;
196 /* Drive status */
197 FloppyDriveType drive; /* CMOS drive type */
198 uint8_t perpendicular; /* 2.88 MB access mode */
199 /* Position */
200 uint8_t head;
201 uint8_t track;
202 uint8_t sect;
203 /* Media */
204 FloppyDriveType disk; /* Current disk type */
205 FDiskFlags flags;
206 uint8_t last_sect; /* Nb sector per track */
207 uint8_t max_track; /* Nb of tracks */
208 uint16_t bps; /* Bytes per sector */
209 uint8_t ro; /* Is read-only */
210 uint8_t media_changed; /* Is media changed */
211 uint8_t media_rate; /* Data rate of medium */
212
213 bool media_validated; /* Have we validated the media? */
214 };
215
216
217 static FloppyDriveType get_fallback_drive_type(FDrive *drv);
218
219 /* Hack: FD_SEEK is expected to work on empty drives. However, QEMU
220 * currently goes through some pains to keep seeks within the bounds
221 * established by last_sect and max_track. Correcting this is difficult,
222 * as refactoring FDC code tends to expose nasty bugs in the Linux kernel.
223 *
224 * For now: allow empty drives to have large bounds so we can seek around,
225 * with the understanding that when a diskette is inserted, the bounds will
226 * properly tighten to match the geometry of that inserted medium.
227 */
228 static void fd_empty_seek_hack(FDrive *drv)
229 {
230 drv->last_sect = 0xFF;
231 drv->max_track = 0xFF;
232 }
233
234 static void fd_init(FDrive *drv)
235 {
236 /* Drive */
237 drv->perpendicular = 0;
238 /* Disk */
239 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
240 drv->last_sect = 0;
241 drv->max_track = 0;
242 drv->ro = true;
243 drv->media_changed = 1;
244 }
245
246 #define NUM_SIDES(drv) ((drv)->flags & FDISK_DBL_SIDES ? 2 : 1)
247
248 static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,
249 uint8_t last_sect, uint8_t num_sides)
250 {
251 return (((track * num_sides) + head) * last_sect) + sect - 1;
252 }
253
254 /* Returns current position, in sectors, for given drive */
255 static int fd_sector(FDrive *drv)
256 {
257 return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect,
258 NUM_SIDES(drv));
259 }
260
261 /* Returns current position, in bytes, for given drive */
262 static int fd_offset(FDrive *drv)
263 {
264 g_assert(fd_sector(drv) < INT_MAX >> BDRV_SECTOR_BITS);
265 return fd_sector(drv) << BDRV_SECTOR_BITS;
266 }
267
268 /* Seek to a new position:
269 * returns 0 if already on right track
270 * returns 1 if track changed
271 * returns 2 if track is invalid
272 * returns 3 if sector is invalid
273 * returns 4 if seek is disabled
274 */
275 static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,
276 int enable_seek)
277 {
278 uint32_t sector;
279 int ret;
280
281 if (track > drv->max_track ||
282 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
283 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
284 head, track, sect, 1,
285 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
286 drv->max_track, drv->last_sect);
287 return 2;
288 }
289 if (sect > drv->last_sect) {
290 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
291 head, track, sect, 1,
292 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
293 drv->max_track, drv->last_sect);
294 return 3;
295 }
296 sector = fd_sector_calc(head, track, sect, drv->last_sect, NUM_SIDES(drv));
297 ret = 0;
298 if (sector != fd_sector(drv)) {
299 #if 0
300 if (!enable_seek) {
301 FLOPPY_DPRINTF("error: no implicit seek %d %02x %02x"
302 " (max=%d %02x %02x)\n",
303 head, track, sect, 1, drv->max_track,
304 drv->last_sect);
305 return 4;
306 }
307 #endif
308 drv->head = head;
309 if (drv->track != track) {
310 if (drv->blk != NULL && blk_is_inserted(drv->blk)) {
311 drv->media_changed = 0;
312 }
313 ret = 1;
314 }
315 drv->track = track;
316 drv->sect = sect;
317 }
318
319 if (drv->blk == NULL || !blk_is_inserted(drv->blk)) {
320 ret = 2;
321 }
322
323 return ret;
324 }
325
326 /* Set drive back to track 0 */
327 static void fd_recalibrate(FDrive *drv)
328 {
329 FLOPPY_DPRINTF("recalibrate\n");
330 fd_seek(drv, 0, 0, 1, 1);
331 }
332
333 /**
334 * Determine geometry based on inserted diskette.
335 * Will not operate on an empty drive.
336 *
337 * @return: 0 on success, -1 if the drive is empty.
338 */
339 static int pick_geometry(FDrive *drv)
340 {
341 BlockBackend *blk = drv->blk;
342 const FDFormat *parse;
343 uint64_t nb_sectors, size;
344 int i;
345 int match, size_match, type_match;
346 bool magic = drv->drive == FLOPPY_DRIVE_TYPE_AUTO;
347
348 /* We can only pick a geometry if we have a diskette. */
349 if (!drv->blk || !blk_is_inserted(drv->blk) ||
350 drv->drive == FLOPPY_DRIVE_TYPE_NONE)
351 {
352 return -1;
353 }
354
355 /* We need to determine the likely geometry of the inserted medium.
356 * In order of preference, we look for:
357 * (1) The same drive type and number of sectors,
358 * (2) The same diskette size and number of sectors,
359 * (3) The same drive type.
360 *
361 * In all cases, matches that occur higher in the drive table will take
362 * precedence over matches that occur later in the table.
363 */
364 blk_get_geometry(blk, &nb_sectors);
365 match = size_match = type_match = -1;
366 for (i = 0; ; i++) {
367 parse = &fd_formats[i];
368 if (parse->drive == FLOPPY_DRIVE_TYPE_NONE) {
369 break;
370 }
371 size = (parse->max_head + 1) * parse->max_track * parse->last_sect;
372 if (nb_sectors == size) {
373 if (magic || parse->drive == drv->drive) {
374 /* (1) perfect match -- nb_sectors and drive type */
375 goto out;
376 } else if (drive_size(parse->drive) == drive_size(drv->drive)) {
377 /* (2) size match -- nb_sectors and physical medium size */
378 match = (match == -1) ? i : match;
379 } else {
380 /* This is suspicious -- Did the user misconfigure? */
381 size_match = (size_match == -1) ? i : size_match;
382 }
383 } else if (type_match == -1) {
384 if ((parse->drive == drv->drive) ||
385 (magic && (parse->drive == get_fallback_drive_type(drv)))) {
386 /* (3) type match -- nb_sectors mismatch, but matches the type
387 * specified explicitly by the user, or matches the fallback
388 * default type when using the drive autodetect mechanism */
389 type_match = i;
390 }
391 }
392 }
393
394 /* No exact match found */
395 if (match == -1) {
396 if (size_match != -1) {
397 parse = &fd_formats[size_match];
398 FLOPPY_DPRINTF("User requested floppy drive type '%s', "
399 "but inserted medium appears to be a "
400 "%"PRId64" sector '%s' type\n",
401 FloppyDriveType_str(drv->drive),
402 nb_sectors,
403 FloppyDriveType_str(parse->drive));
404 }
405 assert(type_match != -1 && "misconfigured fd_format");
406 match = type_match;
407 }
408 parse = &(fd_formats[match]);
409
410 out:
411 if (parse->max_head == 0) {
412 drv->flags &= ~FDISK_DBL_SIDES;
413 } else {
414 drv->flags |= FDISK_DBL_SIDES;
415 }
416 drv->max_track = parse->max_track;
417 drv->last_sect = parse->last_sect;
418 drv->disk = parse->drive;
419 drv->media_rate = parse->rate;
420 return 0;
421 }
422
423 static void pick_drive_type(FDrive *drv)
424 {
425 if (drv->drive != FLOPPY_DRIVE_TYPE_AUTO) {
426 return;
427 }
428
429 if (pick_geometry(drv) == 0) {
430 drv->drive = drv->disk;
431 } else {
432 drv->drive = get_fallback_drive_type(drv);
433 }
434
435 g_assert(drv->drive != FLOPPY_DRIVE_TYPE_AUTO);
436 }
437
438 /* Revalidate a disk drive after a disk change */
439 static void fd_revalidate(FDrive *drv)
440 {
441 int rc;
442
443 FLOPPY_DPRINTF("revalidate\n");
444 if (drv->blk != NULL) {
445 drv->ro = blk_is_read_only(drv->blk);
446 if (!blk_is_inserted(drv->blk)) {
447 FLOPPY_DPRINTF("No disk in drive\n");
448 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
449 fd_empty_seek_hack(drv);
450 } else if (!drv->media_validated) {
451 rc = pick_geometry(drv);
452 if (rc) {
453 FLOPPY_DPRINTF("Could not validate floppy drive media");
454 } else {
455 drv->media_validated = true;
456 FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n",
457 (drv->flags & FDISK_DBL_SIDES) ? 2 : 1,
458 drv->max_track, drv->last_sect,
459 drv->ro ? "ro" : "rw");
460 }
461 }
462 } else {
463 FLOPPY_DPRINTF("No drive connected\n");
464 drv->last_sect = 0;
465 drv->max_track = 0;
466 drv->flags &= ~FDISK_DBL_SIDES;
467 drv->drive = FLOPPY_DRIVE_TYPE_NONE;
468 drv->disk = FLOPPY_DRIVE_TYPE_NONE;
469 }
470 }
471
472 static void fd_change_cb(void *opaque, bool load, Error **errp)
473 {
474 FDrive *drive = opaque;
475
476 if (!load) {
477 blk_set_perm(drive->blk, 0, BLK_PERM_ALL, &error_abort);
478 } else {
479 if (!blkconf_apply_backend_options(drive->conf,
480 blk_is_read_only(drive->blk), false,
481 errp)) {
482 return;
483 }
484 }
485
486 drive->media_changed = 1;
487 drive->media_validated = false;
488 fd_revalidate(drive);
489 }
490
491 static const BlockDevOps fd_block_ops = {
492 .change_media_cb = fd_change_cb,
493 };
494
495
496 #define TYPE_FLOPPY_DRIVE "floppy"
497 #define FLOPPY_DRIVE(obj) \
498 OBJECT_CHECK(FloppyDrive, (obj), TYPE_FLOPPY_DRIVE)
499
500 typedef struct FloppyDrive {
501 DeviceState qdev;
502 uint32_t unit;
503 BlockConf conf;
504 FloppyDriveType type;
505 } FloppyDrive;
506
507 static Property floppy_drive_properties[] = {
508 DEFINE_PROP_UINT32("unit", FloppyDrive, unit, -1),
509 DEFINE_BLOCK_PROPERTIES(FloppyDrive, conf),
510 DEFINE_PROP_SIGNED("drive-type", FloppyDrive, type,
511 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
512 FloppyDriveType),
513 DEFINE_PROP_END_OF_LIST(),
514 };
515
516 static void floppy_drive_realize(DeviceState *qdev, Error **errp)
517 {
518 FloppyDrive *dev = FLOPPY_DRIVE(qdev);
519 FloppyBus *bus = FLOPPY_BUS(qdev->parent_bus);
520 FDrive *drive;
521 bool read_only;
522 int ret;
523
524 if (dev->unit == -1) {
525 for (dev->unit = 0; dev->unit < MAX_FD; dev->unit++) {
526 drive = get_drv(bus->fdc, dev->unit);
527 if (!drive->blk) {
528 break;
529 }
530 }
531 }
532
533 if (dev->unit >= MAX_FD) {
534 error_setg(errp, "Can't create floppy unit %d, bus supports "
535 "only %d units", dev->unit, MAX_FD);
536 return;
537 }
538
539 drive = get_drv(bus->fdc, dev->unit);
540 if (drive->blk) {
541 error_setg(errp, "Floppy unit %d is in use", dev->unit);
542 return;
543 }
544
545 if (!dev->conf.blk) {
546 /* Anonymous BlockBackend for an empty drive */
547 dev->conf.blk = blk_new(qemu_get_aio_context(), 0, BLK_PERM_ALL);
548 ret = blk_attach_dev(dev->conf.blk, qdev);
549 assert(ret == 0);
550
551 /* Don't take write permissions on an empty drive to allow attaching a
552 * read-only node later */
553 read_only = true;
554 } else {
555 read_only = !blk_bs(dev->conf.blk) || blk_is_read_only(dev->conf.blk);
556 }
557
558 if (!blkconf_blocksizes(&dev->conf, errp)) {
559 return;
560 }
561
562 if (dev->conf.logical_block_size != 512 ||
563 dev->conf.physical_block_size != 512)
564 {
565 error_setg(errp, "Physical and logical block size must "
566 "be 512 for floppy");
567 return;
568 }
569
570 /* rerror/werror aren't supported by fdc and therefore not even registered
571 * with qdev. So set the defaults manually before they are used in
572 * blkconf_apply_backend_options(). */
573 dev->conf.rerror = BLOCKDEV_ON_ERROR_AUTO;
574 dev->conf.werror = BLOCKDEV_ON_ERROR_AUTO;
575
576 if (!blkconf_apply_backend_options(&dev->conf, read_only, false, errp)) {
577 return;
578 }
579
580 /* 'enospc' is the default for -drive, 'report' is what blk_new() gives us
581 * for empty drives. */
582 if (blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_ENOSPC &&
583 blk_get_on_error(dev->conf.blk, 0) != BLOCKDEV_ON_ERROR_REPORT) {
584 error_setg(errp, "fdc doesn't support drive option werror");
585 return;
586 }
587 if (blk_get_on_error(dev->conf.blk, 1) != BLOCKDEV_ON_ERROR_REPORT) {
588 error_setg(errp, "fdc doesn't support drive option rerror");
589 return;
590 }
591
592 drive->conf = &dev->conf;
593 drive->blk = dev->conf.blk;
594 drive->fdctrl = bus->fdc;
595
596 fd_init(drive);
597 blk_set_dev_ops(drive->blk, &fd_block_ops, drive);
598
599 /* Keep 'type' qdev property and FDrive->drive in sync */
600 drive->drive = dev->type;
601 pick_drive_type(drive);
602 dev->type = drive->drive;
603
604 fd_revalidate(drive);
605 }
606
607 static void floppy_drive_class_init(ObjectClass *klass, void *data)
608 {
609 DeviceClass *k = DEVICE_CLASS(klass);
610 k->realize = floppy_drive_realize;
611 set_bit(DEVICE_CATEGORY_STORAGE, k->categories);
612 k->bus_type = TYPE_FLOPPY_BUS;
613 device_class_set_props(k, floppy_drive_properties);
614 k->desc = "virtual floppy drive";
615 }
616
617 static const TypeInfo floppy_drive_info = {
618 .name = TYPE_FLOPPY_DRIVE,
619 .parent = TYPE_DEVICE,
620 .instance_size = sizeof(FloppyDrive),
621 .class_init = floppy_drive_class_init,
622 };
623
624 /********************************************************/
625 /* Intel 82078 floppy disk controller emulation */
626
627 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);
628 static void fdctrl_to_command_phase(FDCtrl *fdctrl);
629 static int fdctrl_transfer_handler (void *opaque, int nchan,
630 int dma_pos, int dma_len);
631 static void fdctrl_raise_irq(FDCtrl *fdctrl);
632 static FDrive *get_cur_drv(FDCtrl *fdctrl);
633
634 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);
635 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);
636 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);
637 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);
638 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);
639 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);
640 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);
641 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);
642 static uint32_t fdctrl_read_data(FDCtrl *fdctrl);
643 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);
644 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);
645 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value);
646
647 enum {
648 FD_DIR_WRITE = 0,
649 FD_DIR_READ = 1,
650 FD_DIR_SCANE = 2,
651 FD_DIR_SCANL = 3,
652 FD_DIR_SCANH = 4,
653 FD_DIR_VERIFY = 5,
654 };
655
656 enum {
657 FD_STATE_MULTI = 0x01, /* multi track flag */
658 FD_STATE_FORMAT = 0x02, /* format flag */
659 };
660
661 enum {
662 FD_REG_SRA = 0x00,
663 FD_REG_SRB = 0x01,
664 FD_REG_DOR = 0x02,
665 FD_REG_TDR = 0x03,
666 FD_REG_MSR = 0x04,
667 FD_REG_DSR = 0x04,
668 FD_REG_FIFO = 0x05,
669 FD_REG_DIR = 0x07,
670 FD_REG_CCR = 0x07,
671 };
672
673 enum {
674 FD_CMD_READ_TRACK = 0x02,
675 FD_CMD_SPECIFY = 0x03,
676 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
677 FD_CMD_WRITE = 0x05,
678 FD_CMD_READ = 0x06,
679 FD_CMD_RECALIBRATE = 0x07,
680 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
681 FD_CMD_WRITE_DELETED = 0x09,
682 FD_CMD_READ_ID = 0x0a,
683 FD_CMD_READ_DELETED = 0x0c,
684 FD_CMD_FORMAT_TRACK = 0x0d,
685 FD_CMD_DUMPREG = 0x0e,
686 FD_CMD_SEEK = 0x0f,
687 FD_CMD_VERSION = 0x10,
688 FD_CMD_SCAN_EQUAL = 0x11,
689 FD_CMD_PERPENDICULAR_MODE = 0x12,
690 FD_CMD_CONFIGURE = 0x13,
691 FD_CMD_LOCK = 0x14,
692 FD_CMD_VERIFY = 0x16,
693 FD_CMD_POWERDOWN_MODE = 0x17,
694 FD_CMD_PART_ID = 0x18,
695 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
696 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
697 FD_CMD_SAVE = 0x2e,
698 FD_CMD_OPTION = 0x33,
699 FD_CMD_RESTORE = 0x4e,
700 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
701 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
702 FD_CMD_FORMAT_AND_WRITE = 0xcd,
703 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
704 };
705
706 enum {
707 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
708 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
709 FD_CONFIG_POLL = 0x10, /* Poll enabled */
710 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
711 FD_CONFIG_EIS = 0x40, /* No implied seeks */
712 };
713
714 enum {
715 FD_SR0_DS0 = 0x01,
716 FD_SR0_DS1 = 0x02,
717 FD_SR0_HEAD = 0x04,
718 FD_SR0_EQPMT = 0x10,
719 FD_SR0_SEEK = 0x20,
720 FD_SR0_ABNTERM = 0x40,
721 FD_SR0_INVCMD = 0x80,
722 FD_SR0_RDYCHG = 0xc0,
723 };
724
725 enum {
726 FD_SR1_MA = 0x01, /* Missing address mark */
727 FD_SR1_NW = 0x02, /* Not writable */
728 FD_SR1_EC = 0x80, /* End of cylinder */
729 };
730
731 enum {
732 FD_SR2_SNS = 0x04, /* Scan not satisfied */
733 FD_SR2_SEH = 0x08, /* Scan equal hit */
734 };
735
736 enum {
737 FD_SRA_DIR = 0x01,
738 FD_SRA_nWP = 0x02,
739 FD_SRA_nINDX = 0x04,
740 FD_SRA_HDSEL = 0x08,
741 FD_SRA_nTRK0 = 0x10,
742 FD_SRA_STEP = 0x20,
743 FD_SRA_nDRV2 = 0x40,
744 FD_SRA_INTPEND = 0x80,
745 };
746
747 enum {
748 FD_SRB_MTR0 = 0x01,
749 FD_SRB_MTR1 = 0x02,
750 FD_SRB_WGATE = 0x04,
751 FD_SRB_RDATA = 0x08,
752 FD_SRB_WDATA = 0x10,
753 FD_SRB_DR0 = 0x20,
754 };
755
756 enum {
757 #if MAX_FD == 4
758 FD_DOR_SELMASK = 0x03,
759 #else
760 FD_DOR_SELMASK = 0x01,
761 #endif
762 FD_DOR_nRESET = 0x04,
763 FD_DOR_DMAEN = 0x08,
764 FD_DOR_MOTEN0 = 0x10,
765 FD_DOR_MOTEN1 = 0x20,
766 FD_DOR_MOTEN2 = 0x40,
767 FD_DOR_MOTEN3 = 0x80,
768 };
769
770 enum {
771 #if MAX_FD == 4
772 FD_TDR_BOOTSEL = 0x0c,
773 #else
774 FD_TDR_BOOTSEL = 0x04,
775 #endif
776 };
777
778 enum {
779 FD_DSR_DRATEMASK= 0x03,
780 FD_DSR_PWRDOWN = 0x40,
781 FD_DSR_SWRESET = 0x80,
782 };
783
784 enum {
785 FD_MSR_DRV0BUSY = 0x01,
786 FD_MSR_DRV1BUSY = 0x02,
787 FD_MSR_DRV2BUSY = 0x04,
788 FD_MSR_DRV3BUSY = 0x08,
789 FD_MSR_CMDBUSY = 0x10,
790 FD_MSR_NONDMA = 0x20,
791 FD_MSR_DIO = 0x40,
792 FD_MSR_RQM = 0x80,
793 };
794
795 enum {
796 FD_DIR_DSKCHG = 0x80,
797 };
798
799 /*
800 * See chapter 5.0 "Controller phases" of the spec:
801 *
802 * Command phase:
803 * The host writes a command and its parameters into the FIFO. The command
804 * phase is completed when all parameters for the command have been supplied,
805 * and execution phase is entered.
806 *
807 * Execution phase:
808 * Data transfers, either DMA or non-DMA. For non-DMA transfers, the FIFO
809 * contains the payload now, otherwise it's unused. When all bytes of the
810 * required data have been transferred, the state is switched to either result
811 * phase (if the command produces status bytes) or directly back into the
812 * command phase for the next command.
813 *
814 * Result phase:
815 * The host reads out the FIFO, which contains one or more result bytes now.
816 */
817 enum {
818 /* Only for migration: reconstruct phase from registers like qemu 2.3 */
819 FD_PHASE_RECONSTRUCT = 0,
820
821 FD_PHASE_COMMAND = 1,
822 FD_PHASE_EXECUTION = 2,
823 FD_PHASE_RESULT = 3,
824 };
825
826 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
827 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
828
829 struct FDCtrl {
830 MemoryRegion iomem;
831 qemu_irq irq;
832 /* Controller state */
833 QEMUTimer *result_timer;
834 int dma_chann;
835 uint8_t phase;
836 IsaDma *dma;
837 /* Controller's identification */
838 uint8_t version;
839 /* HW */
840 uint8_t sra;
841 uint8_t srb;
842 uint8_t dor;
843 uint8_t dor_vmstate; /* only used as temp during vmstate */
844 uint8_t tdr;
845 uint8_t dsr;
846 uint8_t msr;
847 uint8_t cur_drv;
848 uint8_t status0;
849 uint8_t status1;
850 uint8_t status2;
851 /* Command FIFO */
852 uint8_t *fifo;
853 int32_t fifo_size;
854 uint32_t data_pos;
855 uint32_t data_len;
856 uint8_t data_state;
857 uint8_t data_dir;
858 uint8_t eot; /* last wanted sector */
859 /* States kept only to be returned back */
860 /* precompensation */
861 uint8_t precomp_trk;
862 uint8_t config;
863 uint8_t lock;
864 /* Power down config (also with status regB access mode */
865 uint8_t pwrd;
866 /* Floppy drives */
867 FloppyBus bus;
868 uint8_t num_floppies;
869 FDrive drives[MAX_FD];
870 struct {
871 BlockBackend *blk;
872 FloppyDriveType type;
873 } qdev_for_drives[MAX_FD];
874 int reset_sensei;
875 uint32_t check_media_rate;
876 FloppyDriveType fallback; /* type=auto failure fallback */
877 /* Timers state */
878 uint8_t timer0;
879 uint8_t timer1;
880 PortioList portio_list;
881 };
882
883 static FloppyDriveType get_fallback_drive_type(FDrive *drv)
884 {
885 return drv->fdctrl->fallback;
886 }
887
888 #define TYPE_SYSBUS_FDC "base-sysbus-fdc"
889 #define SYSBUS_FDC(obj) OBJECT_CHECK(FDCtrlSysBus, (obj), TYPE_SYSBUS_FDC)
890
891 typedef struct FDCtrlSysBus {
892 /*< private >*/
893 SysBusDevice parent_obj;
894 /*< public >*/
895
896 struct FDCtrl state;
897 } FDCtrlSysBus;
898
899 #define ISA_FDC(obj) OBJECT_CHECK(FDCtrlISABus, (obj), TYPE_ISA_FDC)
900
901 typedef struct FDCtrlISABus {
902 ISADevice parent_obj;
903
904 uint32_t iobase;
905 uint32_t irq;
906 uint32_t dma;
907 struct FDCtrl state;
908 int32_t bootindexA;
909 int32_t bootindexB;
910 } FDCtrlISABus;
911
912 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
913 {
914 FDCtrl *fdctrl = opaque;
915 uint32_t retval;
916
917 reg &= 7;
918 switch (reg) {
919 case FD_REG_SRA:
920 retval = fdctrl_read_statusA(fdctrl);
921 break;
922 case FD_REG_SRB:
923 retval = fdctrl_read_statusB(fdctrl);
924 break;
925 case FD_REG_DOR:
926 retval = fdctrl_read_dor(fdctrl);
927 break;
928 case FD_REG_TDR:
929 retval = fdctrl_read_tape(fdctrl);
930 break;
931 case FD_REG_MSR:
932 retval = fdctrl_read_main_status(fdctrl);
933 break;
934 case FD_REG_FIFO:
935 retval = fdctrl_read_data(fdctrl);
936 break;
937 case FD_REG_DIR:
938 retval = fdctrl_read_dir(fdctrl);
939 break;
940 default:
941 retval = (uint32_t)(-1);
942 break;
943 }
944 trace_fdc_ioport_read(reg, retval);
945
946 return retval;
947 }
948
949 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
950 {
951 FDCtrl *fdctrl = opaque;
952
953 reg &= 7;
954 trace_fdc_ioport_write(reg, value);
955 switch (reg) {
956 case FD_REG_DOR:
957 fdctrl_write_dor(fdctrl, value);
958 break;
959 case FD_REG_TDR:
960 fdctrl_write_tape(fdctrl, value);
961 break;
962 case FD_REG_DSR:
963 fdctrl_write_rate(fdctrl, value);
964 break;
965 case FD_REG_FIFO:
966 fdctrl_write_data(fdctrl, value);
967 break;
968 case FD_REG_CCR:
969 fdctrl_write_ccr(fdctrl, value);
970 break;
971 default:
972 break;
973 }
974 }
975
976 static uint64_t fdctrl_read_mem (void *opaque, hwaddr reg,
977 unsigned ize)
978 {
979 return fdctrl_read(opaque, (uint32_t)reg);
980 }
981
982 static void fdctrl_write_mem (void *opaque, hwaddr reg,
983 uint64_t value, unsigned size)
984 {
985 fdctrl_write(opaque, (uint32_t)reg, value);
986 }
987
988 static const MemoryRegionOps fdctrl_mem_ops = {
989 .read = fdctrl_read_mem,
990 .write = fdctrl_write_mem,
991 .endianness = DEVICE_NATIVE_ENDIAN,
992 };
993
994 static const MemoryRegionOps fdctrl_mem_strict_ops = {
995 .read = fdctrl_read_mem,
996 .write = fdctrl_write_mem,
997 .endianness = DEVICE_NATIVE_ENDIAN,
998 .valid = {
999 .min_access_size = 1,
1000 .max_access_size = 1,
1001 },
1002 };
1003
1004 static bool fdrive_media_changed_needed(void *opaque)
1005 {
1006 FDrive *drive = opaque;
1007
1008 return (drive->blk != NULL && drive->media_changed != 1);
1009 }
1010
1011 static const VMStateDescription vmstate_fdrive_media_changed = {
1012 .name = "fdrive/media_changed",
1013 .version_id = 1,
1014 .minimum_version_id = 1,
1015 .needed = fdrive_media_changed_needed,
1016 .fields = (VMStateField[]) {
1017 VMSTATE_UINT8(media_changed, FDrive),
1018 VMSTATE_END_OF_LIST()
1019 }
1020 };
1021
1022 static bool fdrive_media_rate_needed(void *opaque)
1023 {
1024 FDrive *drive = opaque;
1025
1026 return drive->fdctrl->check_media_rate;
1027 }
1028
1029 static const VMStateDescription vmstate_fdrive_media_rate = {
1030 .name = "fdrive/media_rate",
1031 .version_id = 1,
1032 .minimum_version_id = 1,
1033 .needed = fdrive_media_rate_needed,
1034 .fields = (VMStateField[]) {
1035 VMSTATE_UINT8(media_rate, FDrive),
1036 VMSTATE_END_OF_LIST()
1037 }
1038 };
1039
1040 static bool fdrive_perpendicular_needed(void *opaque)
1041 {
1042 FDrive *drive = opaque;
1043
1044 return drive->perpendicular != 0;
1045 }
1046
1047 static const VMStateDescription vmstate_fdrive_perpendicular = {
1048 .name = "fdrive/perpendicular",
1049 .version_id = 1,
1050 .minimum_version_id = 1,
1051 .needed = fdrive_perpendicular_needed,
1052 .fields = (VMStateField[]) {
1053 VMSTATE_UINT8(perpendicular, FDrive),
1054 VMSTATE_END_OF_LIST()
1055 }
1056 };
1057
1058 static int fdrive_post_load(void *opaque, int version_id)
1059 {
1060 fd_revalidate(opaque);
1061 return 0;
1062 }
1063
1064 static const VMStateDescription vmstate_fdrive = {
1065 .name = "fdrive",
1066 .version_id = 1,
1067 .minimum_version_id = 1,
1068 .post_load = fdrive_post_load,
1069 .fields = (VMStateField[]) {
1070 VMSTATE_UINT8(head, FDrive),
1071 VMSTATE_UINT8(track, FDrive),
1072 VMSTATE_UINT8(sect, FDrive),
1073 VMSTATE_END_OF_LIST()
1074 },
1075 .subsections = (const VMStateDescription*[]) {
1076 &vmstate_fdrive_media_changed,
1077 &vmstate_fdrive_media_rate,
1078 &vmstate_fdrive_perpendicular,
1079 NULL
1080 }
1081 };
1082
1083 /*
1084 * Reconstructs the phase from register values according to the logic that was
1085 * implemented in qemu 2.3. This is the default value that is used if the phase
1086 * subsection is not present on migration.
1087 *
1088 * Don't change this function to reflect newer qemu versions, it is part of
1089 * the migration ABI.
1090 */
1091 static int reconstruct_phase(FDCtrl *fdctrl)
1092 {
1093 if (fdctrl->msr & FD_MSR_NONDMA) {
1094 return FD_PHASE_EXECUTION;
1095 } else if ((fdctrl->msr & FD_MSR_RQM) == 0) {
1096 /* qemu 2.3 disabled RQM only during DMA transfers */
1097 return FD_PHASE_EXECUTION;
1098 } else if (fdctrl->msr & FD_MSR_DIO) {
1099 return FD_PHASE_RESULT;
1100 } else {
1101 return FD_PHASE_COMMAND;
1102 }
1103 }
1104
1105 static int fdc_pre_save(void *opaque)
1106 {
1107 FDCtrl *s = opaque;
1108
1109 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
1110
1111 return 0;
1112 }
1113
1114 static int fdc_pre_load(void *opaque)
1115 {
1116 FDCtrl *s = opaque;
1117 s->phase = FD_PHASE_RECONSTRUCT;
1118 return 0;
1119 }
1120
1121 static int fdc_post_load(void *opaque, int version_id)
1122 {
1123 FDCtrl *s = opaque;
1124
1125 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
1126 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
1127
1128 if (s->phase == FD_PHASE_RECONSTRUCT) {
1129 s->phase = reconstruct_phase(s);
1130 }
1131
1132 return 0;
1133 }
1134
1135 static bool fdc_reset_sensei_needed(void *opaque)
1136 {
1137 FDCtrl *s = opaque;
1138
1139 return s->reset_sensei != 0;
1140 }
1141
1142 static const VMStateDescription vmstate_fdc_reset_sensei = {
1143 .name = "fdc/reset_sensei",
1144 .version_id = 1,
1145 .minimum_version_id = 1,
1146 .needed = fdc_reset_sensei_needed,
1147 .fields = (VMStateField[]) {
1148 VMSTATE_INT32(reset_sensei, FDCtrl),
1149 VMSTATE_END_OF_LIST()
1150 }
1151 };
1152
1153 static bool fdc_result_timer_needed(void *opaque)
1154 {
1155 FDCtrl *s = opaque;
1156
1157 return timer_pending(s->result_timer);
1158 }
1159
1160 static const VMStateDescription vmstate_fdc_result_timer = {
1161 .name = "fdc/result_timer",
1162 .version_id = 1,
1163 .minimum_version_id = 1,
1164 .needed = fdc_result_timer_needed,
1165 .fields = (VMStateField[]) {
1166 VMSTATE_TIMER_PTR(result_timer, FDCtrl),
1167 VMSTATE_END_OF_LIST()
1168 }
1169 };
1170
1171 static bool fdc_phase_needed(void *opaque)
1172 {
1173 FDCtrl *fdctrl = opaque;
1174
1175 return reconstruct_phase(fdctrl) != fdctrl->phase;
1176 }
1177
1178 static const VMStateDescription vmstate_fdc_phase = {
1179 .name = "fdc/phase",
1180 .version_id = 1,
1181 .minimum_version_id = 1,
1182 .needed = fdc_phase_needed,
1183 .fields = (VMStateField[]) {
1184 VMSTATE_UINT8(phase, FDCtrl),
1185 VMSTATE_END_OF_LIST()
1186 }
1187 };
1188
1189 static const VMStateDescription vmstate_fdc = {
1190 .name = "fdc",
1191 .version_id = 2,
1192 .minimum_version_id = 2,
1193 .pre_save = fdc_pre_save,
1194 .pre_load = fdc_pre_load,
1195 .post_load = fdc_post_load,
1196 .fields = (VMStateField[]) {
1197 /* Controller State */
1198 VMSTATE_UINT8(sra, FDCtrl),
1199 VMSTATE_UINT8(srb, FDCtrl),
1200 VMSTATE_UINT8(dor_vmstate, FDCtrl),
1201 VMSTATE_UINT8(tdr, FDCtrl),
1202 VMSTATE_UINT8(dsr, FDCtrl),
1203 VMSTATE_UINT8(msr, FDCtrl),
1204 VMSTATE_UINT8(status0, FDCtrl),
1205 VMSTATE_UINT8(status1, FDCtrl),
1206 VMSTATE_UINT8(status2, FDCtrl),
1207 /* Command FIFO */
1208 VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,
1209 uint8_t),
1210 VMSTATE_UINT32(data_pos, FDCtrl),
1211 VMSTATE_UINT32(data_len, FDCtrl),
1212 VMSTATE_UINT8(data_state, FDCtrl),
1213 VMSTATE_UINT8(data_dir, FDCtrl),
1214 VMSTATE_UINT8(eot, FDCtrl),
1215 /* States kept only to be returned back */
1216 VMSTATE_UINT8(timer0, FDCtrl),
1217 VMSTATE_UINT8(timer1, FDCtrl),
1218 VMSTATE_UINT8(precomp_trk, FDCtrl),
1219 VMSTATE_UINT8(config, FDCtrl),
1220 VMSTATE_UINT8(lock, FDCtrl),
1221 VMSTATE_UINT8(pwrd, FDCtrl),
1222 VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl, NULL),
1223 VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,
1224 vmstate_fdrive, FDrive),
1225 VMSTATE_END_OF_LIST()
1226 },
1227 .subsections = (const VMStateDescription*[]) {
1228 &vmstate_fdc_reset_sensei,
1229 &vmstate_fdc_result_timer,
1230 &vmstate_fdc_phase,
1231 NULL
1232 }
1233 };
1234
1235 static void fdctrl_external_reset_sysbus(DeviceState *d)
1236 {
1237 FDCtrlSysBus *sys = SYSBUS_FDC(d);
1238 FDCtrl *s = &sys->state;
1239
1240 fdctrl_reset(s, 0);
1241 }
1242
1243 static void fdctrl_external_reset_isa(DeviceState *d)
1244 {
1245 FDCtrlISABus *isa = ISA_FDC(d);
1246 FDCtrl *s = &isa->state;
1247
1248 fdctrl_reset(s, 0);
1249 }
1250
1251 static void fdctrl_handle_tc(void *opaque, int irq, int level)
1252 {
1253 //FDCtrl *s = opaque;
1254
1255 if (level) {
1256 // XXX
1257 FLOPPY_DPRINTF("TC pulsed\n");
1258 }
1259 }
1260
1261 /* Change IRQ state */
1262 static void fdctrl_reset_irq(FDCtrl *fdctrl)
1263 {
1264 fdctrl->status0 = 0;
1265 if (!(fdctrl->sra & FD_SRA_INTPEND))
1266 return;
1267 FLOPPY_DPRINTF("Reset interrupt\n");
1268 qemu_set_irq(fdctrl->irq, 0);
1269 fdctrl->sra &= ~FD_SRA_INTPEND;
1270 }
1271
1272 static void fdctrl_raise_irq(FDCtrl *fdctrl)
1273 {
1274 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
1275 qemu_set_irq(fdctrl->irq, 1);
1276 fdctrl->sra |= FD_SRA_INTPEND;
1277 }
1278
1279 fdctrl->reset_sensei = 0;
1280 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
1281 }
1282
1283 /* Reset controller */
1284 static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)
1285 {
1286 int i;
1287
1288 FLOPPY_DPRINTF("reset controller\n");
1289 fdctrl_reset_irq(fdctrl);
1290 /* Initialise controller */
1291 fdctrl->sra = 0;
1292 fdctrl->srb = 0xc0;
1293 if (!fdctrl->drives[1].blk) {
1294 fdctrl->sra |= FD_SRA_nDRV2;
1295 }
1296 fdctrl->cur_drv = 0;
1297 fdctrl->dor = FD_DOR_nRESET;
1298 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
1299 fdctrl->msr = FD_MSR_RQM;
1300 fdctrl->reset_sensei = 0;
1301 timer_del(fdctrl->result_timer);
1302 /* FIFO state */
1303 fdctrl->data_pos = 0;
1304 fdctrl->data_len = 0;
1305 fdctrl->data_state = 0;
1306 fdctrl->data_dir = FD_DIR_WRITE;
1307 for (i = 0; i < MAX_FD; i++)
1308 fd_recalibrate(&fdctrl->drives[i]);
1309 fdctrl_to_command_phase(fdctrl);
1310 if (do_irq) {
1311 fdctrl->status0 |= FD_SR0_RDYCHG;
1312 fdctrl_raise_irq(fdctrl);
1313 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
1314 }
1315 }
1316
1317 static inline FDrive *drv0(FDCtrl *fdctrl)
1318 {
1319 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
1320 }
1321
1322 static inline FDrive *drv1(FDCtrl *fdctrl)
1323 {
1324 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
1325 return &fdctrl->drives[1];
1326 else
1327 return &fdctrl->drives[0];
1328 }
1329
1330 #if MAX_FD == 4
1331 static inline FDrive *drv2(FDCtrl *fdctrl)
1332 {
1333 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
1334 return &fdctrl->drives[2];
1335 else
1336 return &fdctrl->drives[1];
1337 }
1338
1339 static inline FDrive *drv3(FDCtrl *fdctrl)
1340 {
1341 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
1342 return &fdctrl->drives[3];
1343 else
1344 return &fdctrl->drives[2];
1345 }
1346 #endif
1347
1348 static FDrive *get_drv(FDCtrl *fdctrl, int unit)
1349 {
1350 switch (unit) {
1351 case 0: return drv0(fdctrl);
1352 case 1: return drv1(fdctrl);
1353 #if MAX_FD == 4
1354 case 2: return drv2(fdctrl);
1355 case 3: return drv3(fdctrl);
1356 #endif
1357 default: return NULL;
1358 }
1359 }
1360
1361 static FDrive *get_cur_drv(FDCtrl *fdctrl)
1362 {
1363 return get_drv(fdctrl, fdctrl->cur_drv);
1364 }
1365
1366 /* Status A register : 0x00 (read-only) */
1367 static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)
1368 {
1369 uint32_t retval = fdctrl->sra;
1370
1371 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
1372
1373 return retval;
1374 }
1375
1376 /* Status B register : 0x01 (read-only) */
1377 static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)
1378 {
1379 uint32_t retval = fdctrl->srb;
1380
1381 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
1382
1383 return retval;
1384 }
1385
1386 /* Digital output register : 0x02 */
1387 static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)
1388 {
1389 uint32_t retval = fdctrl->dor;
1390
1391 /* Selected drive */
1392 retval |= fdctrl->cur_drv;
1393 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
1394
1395 return retval;
1396 }
1397
1398 static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)
1399 {
1400 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
1401
1402 /* Motors */
1403 if (value & FD_DOR_MOTEN0)
1404 fdctrl->srb |= FD_SRB_MTR0;
1405 else
1406 fdctrl->srb &= ~FD_SRB_MTR0;
1407 if (value & FD_DOR_MOTEN1)
1408 fdctrl->srb |= FD_SRB_MTR1;
1409 else
1410 fdctrl->srb &= ~FD_SRB_MTR1;
1411
1412 /* Drive */
1413 if (value & 1)
1414 fdctrl->srb |= FD_SRB_DR0;
1415 else
1416 fdctrl->srb &= ~FD_SRB_DR0;
1417
1418 /* Reset */
1419 if (!(value & FD_DOR_nRESET)) {
1420 if (fdctrl->dor & FD_DOR_nRESET) {
1421 FLOPPY_DPRINTF("controller enter RESET state\n");
1422 }
1423 } else {
1424 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1425 FLOPPY_DPRINTF("controller out of RESET state\n");
1426 fdctrl_reset(fdctrl, 1);
1427 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1428 }
1429 }
1430 /* Selected drive */
1431 fdctrl->cur_drv = value & FD_DOR_SELMASK;
1432
1433 fdctrl->dor = value;
1434 }
1435
1436 /* Tape drive register : 0x03 */
1437 static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)
1438 {
1439 uint32_t retval = fdctrl->tdr;
1440
1441 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
1442
1443 return retval;
1444 }
1445
1446 static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)
1447 {
1448 /* Reset mode */
1449 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1450 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1451 return;
1452 }
1453 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
1454 /* Disk boot selection indicator */
1455 fdctrl->tdr = value & FD_TDR_BOOTSEL;
1456 /* Tape indicators: never allow */
1457 }
1458
1459 /* Main status register : 0x04 (read) */
1460 static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)
1461 {
1462 uint32_t retval = fdctrl->msr;
1463
1464 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1465 fdctrl->dor |= FD_DOR_nRESET;
1466
1467 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
1468
1469 return retval;
1470 }
1471
1472 /* Data select rate register : 0x04 (write) */
1473 static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)
1474 {
1475 /* Reset mode */
1476 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1477 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1478 return;
1479 }
1480 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
1481 /* Reset: autoclear */
1482 if (value & FD_DSR_SWRESET) {
1483 fdctrl->dor &= ~FD_DOR_nRESET;
1484 fdctrl_reset(fdctrl, 1);
1485 fdctrl->dor |= FD_DOR_nRESET;
1486 }
1487 if (value & FD_DSR_PWRDOWN) {
1488 fdctrl_reset(fdctrl, 1);
1489 }
1490 fdctrl->dsr = value;
1491 }
1492
1493 /* Configuration control register: 0x07 (write) */
1494 static void fdctrl_write_ccr(FDCtrl *fdctrl, uint32_t value)
1495 {
1496 /* Reset mode */
1497 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1498 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1499 return;
1500 }
1501 FLOPPY_DPRINTF("configuration control register set to 0x%02x\n", value);
1502
1503 /* Only the rate selection bits used in AT mode, and we
1504 * store those in the DSR.
1505 */
1506 fdctrl->dsr = (fdctrl->dsr & ~FD_DSR_DRATEMASK) |
1507 (value & FD_DSR_DRATEMASK);
1508 }
1509
1510 static int fdctrl_media_changed(FDrive *drv)
1511 {
1512 return drv->media_changed;
1513 }
1514
1515 /* Digital input register : 0x07 (read-only) */
1516 static uint32_t fdctrl_read_dir(FDCtrl *fdctrl)
1517 {
1518 uint32_t retval = 0;
1519
1520 if (fdctrl_media_changed(get_cur_drv(fdctrl))) {
1521 retval |= FD_DIR_DSKCHG;
1522 }
1523 if (retval != 0) {
1524 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
1525 }
1526
1527 return retval;
1528 }
1529
1530 /* Clear the FIFO and update the state for receiving the next command */
1531 static void fdctrl_to_command_phase(FDCtrl *fdctrl)
1532 {
1533 fdctrl->phase = FD_PHASE_COMMAND;
1534 fdctrl->data_dir = FD_DIR_WRITE;
1535 fdctrl->data_pos = 0;
1536 fdctrl->data_len = 1; /* Accept command byte, adjust for params later */
1537 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1538 fdctrl->msr |= FD_MSR_RQM;
1539 }
1540
1541 /* Update the state to allow the guest to read out the command status.
1542 * @fifo_len is the number of result bytes to be read out. */
1543 static void fdctrl_to_result_phase(FDCtrl *fdctrl, int fifo_len)
1544 {
1545 fdctrl->phase = FD_PHASE_RESULT;
1546 fdctrl->data_dir = FD_DIR_READ;
1547 fdctrl->data_len = fifo_len;
1548 fdctrl->data_pos = 0;
1549 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1550 }
1551
1552 /* Set an error: unimplemented/unknown command */
1553 static void fdctrl_unimplemented(FDCtrl *fdctrl, int direction)
1554 {
1555 qemu_log_mask(LOG_UNIMP, "fdc: unimplemented command 0x%02x\n",
1556 fdctrl->fifo[0]);
1557 fdctrl->fifo[0] = FD_SR0_INVCMD;
1558 fdctrl_to_result_phase(fdctrl, 1);
1559 }
1560
1561 /* Seek to next sector
1562 * returns 0 when end of track reached (for DBL_SIDES on head 1)
1563 * otherwise returns 1
1564 */
1565 static int fdctrl_seek_to_next_sect(FDCtrl *fdctrl, FDrive *cur_drv)
1566 {
1567 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1568 cur_drv->head, cur_drv->track, cur_drv->sect,
1569 fd_sector(cur_drv));
1570 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1571 error in fact */
1572 uint8_t new_head = cur_drv->head;
1573 uint8_t new_track = cur_drv->track;
1574 uint8_t new_sect = cur_drv->sect;
1575
1576 int ret = 1;
1577
1578 if (new_sect >= cur_drv->last_sect ||
1579 new_sect == fdctrl->eot) {
1580 new_sect = 1;
1581 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1582 if (new_head == 0 &&
1583 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1584 new_head = 1;
1585 } else {
1586 new_head = 0;
1587 new_track++;
1588 fdctrl->status0 |= FD_SR0_SEEK;
1589 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0) {
1590 ret = 0;
1591 }
1592 }
1593 } else {
1594 fdctrl->status0 |= FD_SR0_SEEK;
1595 new_track++;
1596 ret = 0;
1597 }
1598 if (ret == 1) {
1599 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1600 new_head, new_track, new_sect, fd_sector(cur_drv));
1601 }
1602 } else {
1603 new_sect++;
1604 }
1605 fd_seek(cur_drv, new_head, new_track, new_sect, 1);
1606 return ret;
1607 }
1608
1609 /* Callback for transfer end (stop or abort) */
1610 static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
1611 uint8_t status1, uint8_t status2)
1612 {
1613 FDrive *cur_drv;
1614 cur_drv = get_cur_drv(fdctrl);
1615
1616 fdctrl->status0 &= ~(FD_SR0_DS0 | FD_SR0_DS1 | FD_SR0_HEAD);
1617 fdctrl->status0 |= GET_CUR_DRV(fdctrl);
1618 if (cur_drv->head) {
1619 fdctrl->status0 |= FD_SR0_HEAD;
1620 }
1621 fdctrl->status0 |= status0;
1622
1623 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1624 status0, status1, status2, fdctrl->status0);
1625 fdctrl->fifo[0] = fdctrl->status0;
1626 fdctrl->fifo[1] = status1;
1627 fdctrl->fifo[2] = status2;
1628 fdctrl->fifo[3] = cur_drv->track;
1629 fdctrl->fifo[4] = cur_drv->head;
1630 fdctrl->fifo[5] = cur_drv->sect;
1631 fdctrl->fifo[6] = FD_SECTOR_SC;
1632 fdctrl->data_dir = FD_DIR_READ;
1633 if (fdctrl->dma_chann != -1 && !(fdctrl->msr & FD_MSR_NONDMA)) {
1634 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
1635 k->release_DREQ(fdctrl->dma, fdctrl->dma_chann);
1636 }
1637 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1638 fdctrl->msr &= ~FD_MSR_NONDMA;
1639
1640 fdctrl_to_result_phase(fdctrl, 7);
1641 fdctrl_raise_irq(fdctrl);
1642 }
1643
1644 /* Prepare a data transfer (either DMA or FIFO) */
1645 static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
1646 {
1647 FDrive *cur_drv;
1648 uint8_t kh, kt, ks;
1649
1650 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1651 cur_drv = get_cur_drv(fdctrl);
1652 kt = fdctrl->fifo[2];
1653 kh = fdctrl->fifo[3];
1654 ks = fdctrl->fifo[4];
1655 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1656 GET_CUR_DRV(fdctrl), kh, kt, ks,
1657 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1658 NUM_SIDES(cur_drv)));
1659 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1660 case 2:
1661 /* sect too big */
1662 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1663 fdctrl->fifo[3] = kt;
1664 fdctrl->fifo[4] = kh;
1665 fdctrl->fifo[5] = ks;
1666 return;
1667 case 3:
1668 /* track too big */
1669 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1670 fdctrl->fifo[3] = kt;
1671 fdctrl->fifo[4] = kh;
1672 fdctrl->fifo[5] = ks;
1673 return;
1674 case 4:
1675 /* No seek enabled */
1676 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1677 fdctrl->fifo[3] = kt;
1678 fdctrl->fifo[4] = kh;
1679 fdctrl->fifo[5] = ks;
1680 return;
1681 case 1:
1682 fdctrl->status0 |= FD_SR0_SEEK;
1683 break;
1684 default:
1685 break;
1686 }
1687
1688 /* Check the data rate. If the programmed data rate does not match
1689 * the currently inserted medium, the operation has to fail. */
1690 if (fdctrl->check_media_rate &&
1691 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
1692 FLOPPY_DPRINTF("data rate mismatch (fdc=%d, media=%d)\n",
1693 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
1694 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
1695 fdctrl->fifo[3] = kt;
1696 fdctrl->fifo[4] = kh;
1697 fdctrl->fifo[5] = ks;
1698 return;
1699 }
1700
1701 /* Set the FIFO state */
1702 fdctrl->data_dir = direction;
1703 fdctrl->data_pos = 0;
1704 assert(fdctrl->msr & FD_MSR_CMDBUSY);
1705 if (fdctrl->fifo[0] & 0x80)
1706 fdctrl->data_state |= FD_STATE_MULTI;
1707 else
1708 fdctrl->data_state &= ~FD_STATE_MULTI;
1709 if (fdctrl->fifo[5] == 0) {
1710 fdctrl->data_len = fdctrl->fifo[8];
1711 } else {
1712 int tmp;
1713 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1714 tmp = (fdctrl->fifo[6] - ks + 1);
1715 if (fdctrl->fifo[0] & 0x80)
1716 tmp += fdctrl->fifo[6];
1717 fdctrl->data_len *= tmp;
1718 }
1719 fdctrl->eot = fdctrl->fifo[6];
1720 if (fdctrl->dor & FD_DOR_DMAEN) {
1721 /* DMA transfer is enabled. */
1722 IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
1723
1724 FLOPPY_DPRINTF("direction=%d (%d - %d)\n",
1725 direction, (128 << fdctrl->fifo[5]) *
1726 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1727
1728 /* No access is allowed until DMA transfer has completed */
1729 fdctrl->msr &= ~FD_MSR_RQM;
1730 if (direction != FD_DIR_VERIFY) {
1731 /*
1732 * Now, we just have to wait for the DMA controller to
1733 * recall us...
1734 */
1735 k->hold_DREQ(fdctrl->dma, fdctrl->dma_chann);
1736 k->schedule(fdctrl->dma);
1737 } else {
1738 /* Start transfer */
1739 fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0,
1740 fdctrl->data_len);
1741 }
1742 return;
1743 }
1744 FLOPPY_DPRINTF("start non-DMA transfer\n");
1745 fdctrl->msr |= FD_MSR_NONDMA | FD_MSR_RQM;
1746 if (direction != FD_DIR_WRITE)
1747 fdctrl->msr |= FD_MSR_DIO;
1748 /* IO based transfer: calculate len */
1749 fdctrl_raise_irq(fdctrl);
1750 }
1751
1752 /* Prepare a transfer of deleted data */
1753 static void fdctrl_start_transfer_del(FDCtrl *fdctrl, int direction)
1754 {
1755 qemu_log_mask(LOG_UNIMP, "fdctrl_start_transfer_del() unimplemented\n");
1756
1757 /* We don't handle deleted data,
1758 * so we don't return *ANYTHING*
1759 */
1760 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1761 }
1762
1763 /* handlers for DMA transfers */
1764 static int fdctrl_transfer_handler (void *opaque, int nchan,
1765 int dma_pos, int dma_len)
1766 {
1767 FDCtrl *fdctrl;
1768 FDrive *cur_drv;
1769 int len, start_pos, rel_pos;
1770 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1771 IsaDmaClass *k;
1772
1773 fdctrl = opaque;
1774 if (fdctrl->msr & FD_MSR_RQM) {
1775 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1776 return 0;
1777 }
1778 k = ISADMA_GET_CLASS(fdctrl->dma);
1779 cur_drv = get_cur_drv(fdctrl);
1780 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1781 fdctrl->data_dir == FD_DIR_SCANH)
1782 status2 = FD_SR2_SNS;
1783 if (dma_len > fdctrl->data_len)
1784 dma_len = fdctrl->data_len;
1785 if (cur_drv->blk == NULL) {
1786 if (fdctrl->data_dir == FD_DIR_WRITE)
1787 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1788 else
1789 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1790 len = 0;
1791 goto transfer_error;
1792 }
1793 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1794 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1795 len = dma_len - fdctrl->data_pos;
1796 if (len + rel_pos > FD_SECTOR_LEN)
1797 len = FD_SECTOR_LEN - rel_pos;
1798 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1799 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1800 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1801 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1802 fd_sector(cur_drv) * FD_SECTOR_LEN);
1803 if (fdctrl->data_dir != FD_DIR_WRITE ||
1804 len < FD_SECTOR_LEN || rel_pos != 0) {
1805 /* READ & SCAN commands and realign to a sector for WRITE */
1806 if (blk_pread(cur_drv->blk, fd_offset(cur_drv),
1807 fdctrl->fifo, BDRV_SECTOR_SIZE) < 0) {
1808 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1809 fd_sector(cur_drv));
1810 /* Sure, image size is too small... */
1811 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1812 }
1813 }
1814 switch (fdctrl->data_dir) {
1815 case FD_DIR_READ:
1816 /* READ commands */
1817 k->write_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
1818 fdctrl->data_pos, len);
1819 break;
1820 case FD_DIR_WRITE:
1821 /* WRITE commands */
1822 if (cur_drv->ro) {
1823 /* Handle readonly medium early, no need to do DMA, touch the
1824 * LED or attempt any writes. A real floppy doesn't attempt
1825 * to write to readonly media either. */
1826 fdctrl_stop_transfer(fdctrl,
1827 FD_SR0_ABNTERM | FD_SR0_SEEK, FD_SR1_NW,
1828 0x00);
1829 goto transfer_error;
1830 }
1831
1832 k->read_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
1833 fdctrl->data_pos, len);
1834 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv),
1835 fdctrl->fifo, BDRV_SECTOR_SIZE, 0) < 0) {
1836 FLOPPY_DPRINTF("error writing sector %d\n",
1837 fd_sector(cur_drv));
1838 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1839 goto transfer_error;
1840 }
1841 break;
1842 case FD_DIR_VERIFY:
1843 /* VERIFY commands */
1844 break;
1845 default:
1846 /* SCAN commands */
1847 {
1848 uint8_t tmpbuf[FD_SECTOR_LEN];
1849 int ret;
1850 k->read_memory(fdctrl->dma, nchan, tmpbuf, fdctrl->data_pos,
1851 len);
1852 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1853 if (ret == 0) {
1854 status2 = FD_SR2_SEH;
1855 goto end_transfer;
1856 }
1857 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1858 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1859 status2 = 0x00;
1860 goto end_transfer;
1861 }
1862 }
1863 break;
1864 }
1865 fdctrl->data_pos += len;
1866 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1867 if (rel_pos == 0) {
1868 /* Seek to next sector */
1869 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1870 break;
1871 }
1872 }
1873 end_transfer:
1874 len = fdctrl->data_pos - start_pos;
1875 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1876 fdctrl->data_pos, len, fdctrl->data_len);
1877 if (fdctrl->data_dir == FD_DIR_SCANE ||
1878 fdctrl->data_dir == FD_DIR_SCANL ||
1879 fdctrl->data_dir == FD_DIR_SCANH)
1880 status2 = FD_SR2_SEH;
1881 fdctrl->data_len -= len;
1882 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1883 transfer_error:
1884
1885 return len;
1886 }
1887
1888 /* Data register : 0x05 */
1889 static uint32_t fdctrl_read_data(FDCtrl *fdctrl)
1890 {
1891 FDrive *cur_drv;
1892 uint32_t retval = 0;
1893 uint32_t pos;
1894
1895 cur_drv = get_cur_drv(fdctrl);
1896 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1897 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1898 FLOPPY_DPRINTF("error: controller not ready for reading\n");
1899 return 0;
1900 }
1901
1902 /* If data_len spans multiple sectors, the current position in the FIFO
1903 * wraps around while fdctrl->data_pos is the real position in the whole
1904 * request. */
1905 pos = fdctrl->data_pos;
1906 pos %= FD_SECTOR_LEN;
1907
1908 switch (fdctrl->phase) {
1909 case FD_PHASE_EXECUTION:
1910 assert(fdctrl->msr & FD_MSR_NONDMA);
1911 if (pos == 0) {
1912 if (fdctrl->data_pos != 0)
1913 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1914 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1915 fd_sector(cur_drv));
1916 return 0;
1917 }
1918 if (blk_pread(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
1919 BDRV_SECTOR_SIZE)
1920 < 0) {
1921 FLOPPY_DPRINTF("error getting sector %d\n",
1922 fd_sector(cur_drv));
1923 /* Sure, image size is too small... */
1924 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1925 }
1926 }
1927
1928 if (++fdctrl->data_pos == fdctrl->data_len) {
1929 fdctrl->msr &= ~FD_MSR_RQM;
1930 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1931 }
1932 break;
1933
1934 case FD_PHASE_RESULT:
1935 assert(!(fdctrl->msr & FD_MSR_NONDMA));
1936 if (++fdctrl->data_pos == fdctrl->data_len) {
1937 fdctrl->msr &= ~FD_MSR_RQM;
1938 fdctrl_to_command_phase(fdctrl);
1939 fdctrl_reset_irq(fdctrl);
1940 }
1941 break;
1942
1943 case FD_PHASE_COMMAND:
1944 default:
1945 abort();
1946 }
1947
1948 retval = fdctrl->fifo[pos];
1949 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1950
1951 return retval;
1952 }
1953
1954 static void fdctrl_format_sector(FDCtrl *fdctrl)
1955 {
1956 FDrive *cur_drv;
1957 uint8_t kh, kt, ks;
1958
1959 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1960 cur_drv = get_cur_drv(fdctrl);
1961 kt = fdctrl->fifo[6];
1962 kh = fdctrl->fifo[7];
1963 ks = fdctrl->fifo[8];
1964 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1965 GET_CUR_DRV(fdctrl), kh, kt, ks,
1966 fd_sector_calc(kh, kt, ks, cur_drv->last_sect,
1967 NUM_SIDES(cur_drv)));
1968 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1969 case 2:
1970 /* sect too big */
1971 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1972 fdctrl->fifo[3] = kt;
1973 fdctrl->fifo[4] = kh;
1974 fdctrl->fifo[5] = ks;
1975 return;
1976 case 3:
1977 /* track too big */
1978 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1979 fdctrl->fifo[3] = kt;
1980 fdctrl->fifo[4] = kh;
1981 fdctrl->fifo[5] = ks;
1982 return;
1983 case 4:
1984 /* No seek enabled */
1985 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1986 fdctrl->fifo[3] = kt;
1987 fdctrl->fifo[4] = kh;
1988 fdctrl->fifo[5] = ks;
1989 return;
1990 case 1:
1991 fdctrl->status0 |= FD_SR0_SEEK;
1992 break;
1993 default:
1994 break;
1995 }
1996 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1997 if (cur_drv->blk == NULL ||
1998 blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
1999 BDRV_SECTOR_SIZE, 0) < 0) {
2000 FLOPPY_DPRINTF("error formatting sector %d\n", fd_sector(cur_drv));
2001 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
2002 } else {
2003 if (cur_drv->sect == cur_drv->last_sect) {
2004 fdctrl->data_state &= ~FD_STATE_FORMAT;
2005 /* Last sector done */
2006 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2007 } else {
2008 /* More to do */
2009 fdctrl->data_pos = 0;
2010 fdctrl->data_len = 4;
2011 }
2012 }
2013 }
2014
2015 static void fdctrl_handle_lock(FDCtrl *fdctrl, int direction)
2016 {
2017 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
2018 fdctrl->fifo[0] = fdctrl->lock << 4;
2019 fdctrl_to_result_phase(fdctrl, 1);
2020 }
2021
2022 static void fdctrl_handle_dumpreg(FDCtrl *fdctrl, int direction)
2023 {
2024 FDrive *cur_drv = get_cur_drv(fdctrl);
2025
2026 /* Drives position */
2027 fdctrl->fifo[0] = drv0(fdctrl)->track;
2028 fdctrl->fifo[1] = drv1(fdctrl)->track;
2029 #if MAX_FD == 4
2030 fdctrl->fifo[2] = drv2(fdctrl)->track;
2031 fdctrl->fifo[3] = drv3(fdctrl)->track;
2032 #else
2033 fdctrl->fifo[2] = 0;
2034 fdctrl->fifo[3] = 0;
2035 #endif
2036 /* timers */
2037 fdctrl->fifo[4] = fdctrl->timer0;
2038 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
2039 fdctrl->fifo[6] = cur_drv->last_sect;
2040 fdctrl->fifo[7] = (fdctrl->lock << 7) |
2041 (cur_drv->perpendicular << 2);
2042 fdctrl->fifo[8] = fdctrl->config;
2043 fdctrl->fifo[9] = fdctrl->precomp_trk;
2044 fdctrl_to_result_phase(fdctrl, 10);
2045 }
2046
2047 static void fdctrl_handle_version(FDCtrl *fdctrl, int direction)
2048 {
2049 /* Controller's version */
2050 fdctrl->fifo[0] = fdctrl->version;
2051 fdctrl_to_result_phase(fdctrl, 1);
2052 }
2053
2054 static void fdctrl_handle_partid(FDCtrl *fdctrl, int direction)
2055 {
2056 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
2057 fdctrl_to_result_phase(fdctrl, 1);
2058 }
2059
2060 static void fdctrl_handle_restore(FDCtrl *fdctrl, int direction)
2061 {
2062 FDrive *cur_drv = get_cur_drv(fdctrl);
2063
2064 /* Drives position */
2065 drv0(fdctrl)->track = fdctrl->fifo[3];
2066 drv1(fdctrl)->track = fdctrl->fifo[4];
2067 #if MAX_FD == 4
2068 drv2(fdctrl)->track = fdctrl->fifo[5];
2069 drv3(fdctrl)->track = fdctrl->fifo[6];
2070 #endif
2071 /* timers */
2072 fdctrl->timer0 = fdctrl->fifo[7];
2073 fdctrl->timer1 = fdctrl->fifo[8];
2074 cur_drv->last_sect = fdctrl->fifo[9];
2075 fdctrl->lock = fdctrl->fifo[10] >> 7;
2076 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
2077 fdctrl->config = fdctrl->fifo[11];
2078 fdctrl->precomp_trk = fdctrl->fifo[12];
2079 fdctrl->pwrd = fdctrl->fifo[13];
2080 fdctrl_to_command_phase(fdctrl);
2081 }
2082
2083 static void fdctrl_handle_save(FDCtrl *fdctrl, int direction)
2084 {
2085 FDrive *cur_drv = get_cur_drv(fdctrl);
2086
2087 fdctrl->fifo[0] = 0;
2088 fdctrl->fifo[1] = 0;
2089 /* Drives position */
2090 fdctrl->fifo[2] = drv0(fdctrl)->track;
2091 fdctrl->fifo[3] = drv1(fdctrl)->track;
2092 #if MAX_FD == 4
2093 fdctrl->fifo[4] = drv2(fdctrl)->track;
2094 fdctrl->fifo[5] = drv3(fdctrl)->track;
2095 #else
2096 fdctrl->fifo[4] = 0;
2097 fdctrl->fifo[5] = 0;
2098 #endif
2099 /* timers */
2100 fdctrl->fifo[6] = fdctrl->timer0;
2101 fdctrl->fifo[7] = fdctrl->timer1;
2102 fdctrl->fifo[8] = cur_drv->last_sect;
2103 fdctrl->fifo[9] = (fdctrl->lock << 7) |
2104 (cur_drv->perpendicular << 2);
2105 fdctrl->fifo[10] = fdctrl->config;
2106 fdctrl->fifo[11] = fdctrl->precomp_trk;
2107 fdctrl->fifo[12] = fdctrl->pwrd;
2108 fdctrl->fifo[13] = 0;
2109 fdctrl->fifo[14] = 0;
2110 fdctrl_to_result_phase(fdctrl, 15);
2111 }
2112
2113 static void fdctrl_handle_readid(FDCtrl *fdctrl, int direction)
2114 {
2115 FDrive *cur_drv = get_cur_drv(fdctrl);
2116
2117 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
2118 timer_mod(fdctrl->result_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
2119 (NANOSECONDS_PER_SECOND / 50));
2120 }
2121
2122 static void fdctrl_handle_format_track(FDCtrl *fdctrl, int direction)
2123 {
2124 FDrive *cur_drv;
2125
2126 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2127 cur_drv = get_cur_drv(fdctrl);
2128 fdctrl->data_state |= FD_STATE_FORMAT;
2129 if (fdctrl->fifo[0] & 0x80)
2130 fdctrl->data_state |= FD_STATE_MULTI;
2131 else
2132 fdctrl->data_state &= ~FD_STATE_MULTI;
2133 cur_drv->bps =
2134 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
2135 #if 0
2136 cur_drv->last_sect =
2137 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
2138 fdctrl->fifo[3] / 2;
2139 #else
2140 cur_drv->last_sect = fdctrl->fifo[3];
2141 #endif
2142 /* TODO: implement format using DMA expected by the Bochs BIOS
2143 * and Linux fdformat (read 3 bytes per sector via DMA and fill
2144 * the sector with the specified fill byte
2145 */
2146 fdctrl->data_state &= ~FD_STATE_FORMAT;
2147 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2148 }
2149
2150 static void fdctrl_handle_specify(FDCtrl *fdctrl, int direction)
2151 {
2152 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
2153 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
2154 if (fdctrl->fifo[2] & 1)
2155 fdctrl->dor &= ~FD_DOR_DMAEN;
2156 else
2157 fdctrl->dor |= FD_DOR_DMAEN;
2158 /* No result back */
2159 fdctrl_to_command_phase(fdctrl);
2160 }
2161
2162 static void fdctrl_handle_sense_drive_status(FDCtrl *fdctrl, int direction)
2163 {
2164 FDrive *cur_drv;
2165
2166 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2167 cur_drv = get_cur_drv(fdctrl);
2168 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
2169 /* 1 Byte status back */
2170 fdctrl->fifo[0] = (cur_drv->ro << 6) |
2171 (cur_drv->track == 0 ? 0x10 : 0x00) |
2172 (cur_drv->head << 2) |
2173 GET_CUR_DRV(fdctrl) |
2174 0x28;
2175 fdctrl_to_result_phase(fdctrl, 1);
2176 }
2177
2178 static void fdctrl_handle_recalibrate(FDCtrl *fdctrl, int direction)
2179 {
2180 FDrive *cur_drv;
2181
2182 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2183 cur_drv = get_cur_drv(fdctrl);
2184 fd_recalibrate(cur_drv);
2185 fdctrl_to_command_phase(fdctrl);
2186 /* Raise Interrupt */
2187 fdctrl->status0 |= FD_SR0_SEEK;
2188 fdctrl_raise_irq(fdctrl);
2189 }
2190
2191 static void fdctrl_handle_sense_interrupt_status(FDCtrl *fdctrl, int direction)
2192 {
2193 FDrive *cur_drv = get_cur_drv(fdctrl);
2194
2195 if (fdctrl->reset_sensei > 0) {
2196 fdctrl->fifo[0] =
2197 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
2198 fdctrl->reset_sensei--;
2199 } else if (!(fdctrl->sra & FD_SRA_INTPEND)) {
2200 fdctrl->fifo[0] = FD_SR0_INVCMD;
2201 fdctrl_to_result_phase(fdctrl, 1);
2202 return;
2203 } else {
2204 fdctrl->fifo[0] =
2205 (fdctrl->status0 & ~(FD_SR0_HEAD | FD_SR0_DS1 | FD_SR0_DS0))
2206 | GET_CUR_DRV(fdctrl);
2207 }
2208
2209 fdctrl->fifo[1] = cur_drv->track;
2210 fdctrl_to_result_phase(fdctrl, 2);
2211 fdctrl_reset_irq(fdctrl);
2212 fdctrl->status0 = FD_SR0_RDYCHG;
2213 }
2214
2215 static void fdctrl_handle_seek(FDCtrl *fdctrl, int direction)
2216 {
2217 FDrive *cur_drv;
2218
2219 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2220 cur_drv = get_cur_drv(fdctrl);
2221 fdctrl_to_command_phase(fdctrl);
2222 /* The seek command just sends step pulses to the drive and doesn't care if
2223 * there is a medium inserted of if it's banging the head against the drive.
2224 */
2225 fd_seek(cur_drv, cur_drv->head, fdctrl->fifo[2], cur_drv->sect, 1);
2226 /* Raise Interrupt */
2227 fdctrl->status0 |= FD_SR0_SEEK;
2228 fdctrl_raise_irq(fdctrl);
2229 }
2230
2231 static void fdctrl_handle_perpendicular_mode(FDCtrl *fdctrl, int direction)
2232 {
2233 FDrive *cur_drv = get_cur_drv(fdctrl);
2234
2235 if (fdctrl->fifo[1] & 0x80)
2236 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
2237 /* No result back */
2238 fdctrl_to_command_phase(fdctrl);
2239 }
2240
2241 static void fdctrl_handle_configure(FDCtrl *fdctrl, int direction)
2242 {
2243 fdctrl->config = fdctrl->fifo[2];
2244 fdctrl->precomp_trk = fdctrl->fifo[3];
2245 /* No result back */
2246 fdctrl_to_command_phase(fdctrl);
2247 }
2248
2249 static void fdctrl_handle_powerdown_mode(FDCtrl *fdctrl, int direction)
2250 {
2251 fdctrl->pwrd = fdctrl->fifo[1];
2252 fdctrl->fifo[0] = fdctrl->fifo[1];
2253 fdctrl_to_result_phase(fdctrl, 1);
2254 }
2255
2256 static void fdctrl_handle_option(FDCtrl *fdctrl, int direction)
2257 {
2258 /* No result back */
2259 fdctrl_to_command_phase(fdctrl);
2260 }
2261
2262 static void fdctrl_handle_drive_specification_command(FDCtrl *fdctrl, int direction)
2263 {
2264 FDrive *cur_drv = get_cur_drv(fdctrl);
2265 uint32_t pos;
2266
2267 pos = fdctrl->data_pos - 1;
2268 pos %= FD_SECTOR_LEN;
2269 if (fdctrl->fifo[pos] & 0x80) {
2270 /* Command parameters done */
2271 if (fdctrl->fifo[pos] & 0x40) {
2272 fdctrl->fifo[0] = fdctrl->fifo[1];
2273 fdctrl->fifo[2] = 0;
2274 fdctrl->fifo[3] = 0;
2275 fdctrl_to_result_phase(fdctrl, 4);
2276 } else {
2277 fdctrl_to_command_phase(fdctrl);
2278 }
2279 } else if (fdctrl->data_len > 7) {
2280 /* ERROR */
2281 fdctrl->fifo[0] = 0x80 |
2282 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
2283 fdctrl_to_result_phase(fdctrl, 1);
2284 }
2285 }
2286
2287 static void fdctrl_handle_relative_seek_in(FDCtrl *fdctrl, int direction)
2288 {
2289 FDrive *cur_drv;
2290
2291 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2292 cur_drv = get_cur_drv(fdctrl);
2293 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
2294 fd_seek(cur_drv, cur_drv->head, cur_drv->max_track - 1,
2295 cur_drv->sect, 1);
2296 } else {
2297 fd_seek(cur_drv, cur_drv->head,
2298 cur_drv->track + fdctrl->fifo[2], cur_drv->sect, 1);
2299 }
2300 fdctrl_to_command_phase(fdctrl);
2301 /* Raise Interrupt */
2302 fdctrl->status0 |= FD_SR0_SEEK;
2303 fdctrl_raise_irq(fdctrl);
2304 }
2305
2306 static void fdctrl_handle_relative_seek_out(FDCtrl *fdctrl, int direction)
2307 {
2308 FDrive *cur_drv;
2309
2310 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
2311 cur_drv = get_cur_drv(fdctrl);
2312 if (fdctrl->fifo[2] > cur_drv->track) {
2313 fd_seek(cur_drv, cur_drv->head, 0, cur_drv->sect, 1);
2314 } else {
2315 fd_seek(cur_drv, cur_drv->head,
2316 cur_drv->track - fdctrl->fifo[2], cur_drv->sect, 1);
2317 }
2318 fdctrl_to_command_phase(fdctrl);
2319 /* Raise Interrupt */
2320 fdctrl->status0 |= FD_SR0_SEEK;
2321 fdctrl_raise_irq(fdctrl);
2322 }
2323
2324 /*
2325 * Handlers for the execution phase of each command
2326 */
2327 typedef struct FDCtrlCommand {
2328 uint8_t value;
2329 uint8_t mask;
2330 const char* name;
2331 int parameters;
2332 void (*handler)(FDCtrl *fdctrl, int direction);
2333 int direction;
2334 } FDCtrlCommand;
2335
2336 static const FDCtrlCommand handlers[] = {
2337 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
2338 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
2339 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
2340 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
2341 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
2342 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
2343 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
2344 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
2345 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
2346 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
2347 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
2348 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_start_transfer, FD_DIR_VERIFY },
2349 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
2350 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
2351 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
2352 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
2353 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
2354 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
2355 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
2356 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
2357 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
2358 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
2359 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
2360 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
2361 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
2362 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
2363 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
2364 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
2365 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
2366 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
2367 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
2368 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
2369 };
2370 /* Associate command to an index in the 'handlers' array */
2371 static uint8_t command_to_handler[256];
2372
2373 static const FDCtrlCommand *get_command(uint8_t cmd)
2374 {
2375 int idx;
2376
2377 idx = command_to_handler[cmd];
2378 FLOPPY_DPRINTF("%s command\n", handlers[idx].name);
2379 return &handlers[idx];
2380 }
2381
2382 static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value)
2383 {
2384 FDrive *cur_drv;
2385 const FDCtrlCommand *cmd;
2386 uint32_t pos;
2387
2388 /* Reset mode */
2389 if (!(fdctrl->dor & FD_DOR_nRESET)) {
2390 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
2391 return;
2392 }
2393 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
2394 FLOPPY_DPRINTF("error: controller not ready for writing\n");
2395 return;
2396 }
2397 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
2398
2399 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
2400
2401 /* If data_len spans multiple sectors, the current position in the FIFO
2402 * wraps around while fdctrl->data_pos is the real position in the whole
2403 * request. */
2404 pos = fdctrl->data_pos++;
2405 pos %= FD_SECTOR_LEN;
2406 fdctrl->fifo[pos] = value;
2407
2408 if (fdctrl->data_pos == fdctrl->data_len) {
2409 fdctrl->msr &= ~FD_MSR_RQM;
2410 }
2411
2412 switch (fdctrl->phase) {
2413 case FD_PHASE_EXECUTION:
2414 /* For DMA requests, RQM should be cleared during execution phase, so
2415 * we would have errored out above. */
2416 assert(fdctrl->msr & FD_MSR_NONDMA);
2417
2418 /* FIFO data write */
2419 if (pos == FD_SECTOR_LEN - 1 ||
2420 fdctrl->data_pos == fdctrl->data_len) {
2421 cur_drv = get_cur_drv(fdctrl);
2422 if (blk_pwrite(cur_drv->blk, fd_offset(cur_drv), fdctrl->fifo,
2423 BDRV_SECTOR_SIZE, 0) < 0) {
2424 FLOPPY_DPRINTF("error writing sector %d\n",
2425 fd_sector(cur_drv));
2426 break;
2427 }
2428 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
2429 FLOPPY_DPRINTF("error seeking to next sector %d\n",
2430 fd_sector(cur_drv));
2431 break;
2432 }
2433 }
2434
2435 /* Switch to result phase when done with the transfer */
2436 if (fdctrl->data_pos == fdctrl->data_len) {
2437 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2438 }
2439 break;
2440
2441 case FD_PHASE_COMMAND:
2442 assert(!(fdctrl->msr & FD_MSR_NONDMA));
2443 assert(fdctrl->data_pos < FD_SECTOR_LEN);
2444
2445 if (pos == 0) {
2446 /* The first byte specifies the command. Now we start reading
2447 * as many parameters as this command requires. */
2448 cmd = get_command(value);
2449 fdctrl->data_len = cmd->parameters + 1;
2450 if (cmd->parameters) {
2451 fdctrl->msr |= FD_MSR_RQM;
2452 }
2453 fdctrl->msr |= FD_MSR_CMDBUSY;
2454 }
2455
2456 if (fdctrl->data_pos == fdctrl->data_len) {
2457 /* We have all parameters now, execute the command */
2458 fdctrl->phase = FD_PHASE_EXECUTION;
2459
2460 if (fdctrl->data_state & FD_STATE_FORMAT) {
2461 fdctrl_format_sector(fdctrl);
2462 break;
2463 }
2464
2465 cmd = get_command(fdctrl->fifo[0]);
2466 FLOPPY_DPRINTF("Calling handler for '%s'\n", cmd->name);
2467 cmd->handler(fdctrl, cmd->direction);
2468 }
2469 break;
2470
2471 case FD_PHASE_RESULT:
2472 default:
2473 abort();
2474 }
2475 }
2476
2477 static void fdctrl_result_timer(void *opaque)
2478 {
2479 FDCtrl *fdctrl = opaque;
2480 FDrive *cur_drv = get_cur_drv(fdctrl);
2481
2482 /* Pretend we are spinning.
2483 * This is needed for Coherent, which uses READ ID to check for
2484 * sector interleaving.
2485 */
2486 if (cur_drv->last_sect != 0) {
2487 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
2488 }
2489 /* READ_ID can't automatically succeed! */
2490 if (fdctrl->check_media_rate &&
2491 (fdctrl->dsr & FD_DSR_DRATEMASK) != cur_drv->media_rate) {
2492 FLOPPY_DPRINTF("read id rate mismatch (fdc=%d, media=%d)\n",
2493 fdctrl->dsr & FD_DSR_DRATEMASK, cur_drv->media_rate);
2494 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_MA, 0x00);
2495 } else {
2496 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
2497 }
2498 }
2499
2500 /* Init functions */
2501
2502 static void fdctrl_init_drives(FloppyBus *bus, DriveInfo **fds)
2503 {
2504 DeviceState *dev;
2505 int i;
2506
2507 for (i = 0; i < MAX_FD; i++) {
2508 if (fds[i]) {
2509 dev = qdev_new("floppy");
2510 qdev_prop_set_uint32(dev, "unit", i);
2511 qdev_prop_set_enum(dev, "drive-type", FLOPPY_DRIVE_TYPE_AUTO);
2512 qdev_prop_set_drive_err(dev, "drive", blk_by_legacy_dinfo(fds[i]),
2513 &error_fatal);
2514 qdev_realize_and_unref(dev, &bus->bus, &error_fatal);
2515 }
2516 }
2517 }
2518
2519 void isa_fdc_init_drives(ISADevice *fdc, DriveInfo **fds)
2520 {
2521 fdctrl_init_drives(&ISA_FDC(fdc)->state.bus, fds);
2522 }
2523
2524 static void fdctrl_connect_drives(FDCtrl *fdctrl, DeviceState *fdc_dev,
2525 Error **errp)
2526 {
2527 unsigned int i;
2528 FDrive *drive;
2529 DeviceState *dev;
2530 BlockBackend *blk;
2531 bool ok;
2532 const char *fdc_name, *drive_suffix;
2533
2534 for (i = 0; i < MAX_FD; i++) {
2535 drive = &fdctrl->drives[i];
2536 drive->fdctrl = fdctrl;
2537
2538 /* If the drive is not present, we skip creating the qdev device, but
2539 * still have to initialise the controller. */
2540 blk = fdctrl->qdev_for_drives[i].blk;
2541 if (!blk) {
2542 fd_init(drive);
2543 fd_revalidate(drive);
2544 continue;
2545 }
2546
2547 fdc_name = object_get_typename(OBJECT(fdc_dev));
2548 drive_suffix = !strcmp(fdc_name, "SUNW,fdtwo") ? "" : i ? "B" : "A";
2549 warn_report("warning: property %s.drive%s is deprecated",
2550 fdc_name, drive_suffix);
2551 error_printf("Use -device floppy,unit=%d,drive=... instead.\n", i);
2552
2553 dev = qdev_new("floppy");
2554 qdev_prop_set_uint32(dev, "unit", i);
2555 qdev_prop_set_enum(dev, "drive-type", fdctrl->qdev_for_drives[i].type);
2556
2557 /*
2558 * Hack alert: we move the backend from the floppy controller
2559 * device to the floppy device. We first need to detach the
2560 * controller, or else floppy_create()'s qdev_prop_set_drive()
2561 * will die when it attaches floppy device. We also need to
2562 * take another reference so that blk_detach_dev() doesn't
2563 * free blk while we still need it.
2564 *
2565 * The hack is probably a bad idea.
2566 */
2567 blk_ref(blk);
2568 blk_detach_dev(blk, fdc_dev);
2569 fdctrl->qdev_for_drives[i].blk = NULL;
2570 ok = qdev_prop_set_drive_err(dev, "drive", blk, errp);
2571 blk_unref(blk);
2572 if (!ok) {
2573 return;
2574 }
2575
2576 if (!qdev_realize_and_unref(dev, &fdctrl->bus.bus, errp)) {
2577 return;
2578 }
2579 }
2580 }
2581
2582 void fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
2583 hwaddr mmio_base, DriveInfo **fds)
2584 {
2585 FDCtrl *fdctrl;
2586 DeviceState *dev;
2587 SysBusDevice *sbd;
2588 FDCtrlSysBus *sys;
2589
2590 dev = qdev_new("sysbus-fdc");
2591 sys = SYSBUS_FDC(dev);
2592 fdctrl = &sys->state;
2593 fdctrl->dma_chann = dma_chann; /* FIXME */
2594 sbd = SYS_BUS_DEVICE(dev);
2595 sysbus_realize_and_unref(sbd, &error_fatal);
2596 sysbus_connect_irq(sbd, 0, irq);
2597 sysbus_mmio_map(sbd, 0, mmio_base);
2598
2599 fdctrl_init_drives(&sys->state.bus, fds);
2600 }
2601
2602 void sun4m_fdctrl_init(qemu_irq irq, hwaddr io_base,
2603 DriveInfo **fds, qemu_irq *fdc_tc)
2604 {
2605 DeviceState *dev;
2606 FDCtrlSysBus *sys;
2607
2608 dev = qdev_new("SUNW,fdtwo");
2609 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
2610 sys = SYSBUS_FDC(dev);
2611 sysbus_connect_irq(SYS_BUS_DEVICE(sys), 0, irq);
2612 sysbus_mmio_map(SYS_BUS_DEVICE(sys), 0, io_base);
2613 *fdc_tc = qdev_get_gpio_in(dev, 0);
2614
2615 fdctrl_init_drives(&sys->state.bus, fds);
2616 }
2617
2618 static void fdctrl_realize_common(DeviceState *dev, FDCtrl *fdctrl,
2619 Error **errp)
2620 {
2621 int i, j;
2622 static int command_tables_inited = 0;
2623
2624 if (fdctrl->fallback == FLOPPY_DRIVE_TYPE_AUTO) {
2625 error_setg(errp, "Cannot choose a fallback FDrive type of 'auto'");
2626 return;
2627 }
2628
2629 /* Fill 'command_to_handler' lookup table */
2630 if (!command_tables_inited) {
2631 command_tables_inited = 1;
2632 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
2633 for (j = 0; j < sizeof(command_to_handler); j++) {
2634 if ((j & handlers[i].mask) == handlers[i].value) {
2635 command_to_handler[j] = i;
2636 }
2637 }
2638 }
2639 }
2640
2641 FLOPPY_DPRINTF("init controller\n");
2642 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
2643 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
2644 fdctrl->fifo_size = 512;
2645 fdctrl->result_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2646 fdctrl_result_timer, fdctrl);
2647
2648 fdctrl->version = 0x90; /* Intel 82078 controller */
2649 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
2650 fdctrl->num_floppies = MAX_FD;
2651
2652 if (fdctrl->dma_chann != -1) {
2653 IsaDmaClass *k;
2654 assert(fdctrl->dma);
2655 k = ISADMA_GET_CLASS(fdctrl->dma);
2656 k->register_channel(fdctrl->dma, fdctrl->dma_chann,
2657 &fdctrl_transfer_handler, fdctrl);
2658 }
2659
2660 floppy_bus_create(fdctrl, &fdctrl->bus, dev);
2661 fdctrl_connect_drives(fdctrl, dev, errp);
2662 }
2663
2664 static const MemoryRegionPortio fdc_portio_list[] = {
2665 { 1, 5, 1, .read = fdctrl_read, .write = fdctrl_write },
2666 { 7, 1, 1, .read = fdctrl_read, .write = fdctrl_write },
2667 PORTIO_END_OF_LIST(),
2668 };
2669
2670 static void isabus_fdc_realize(DeviceState *dev, Error **errp)
2671 {
2672 ISADevice *isadev = ISA_DEVICE(dev);
2673 FDCtrlISABus *isa = ISA_FDC(dev);
2674 FDCtrl *fdctrl = &isa->state;
2675 Error *err = NULL;
2676
2677 isa_register_portio_list(isadev, &fdctrl->portio_list,
2678 isa->iobase, fdc_portio_list, fdctrl,
2679 "fdc");
2680
2681 isa_init_irq(isadev, &fdctrl->irq, isa->irq);
2682 fdctrl->dma_chann = isa->dma;
2683 if (fdctrl->dma_chann != -1) {
2684 fdctrl->dma = isa_get_dma(isa_bus_from_device(isadev), isa->dma);
2685 if (!fdctrl->dma) {
2686 error_setg(errp, "ISA controller does not support DMA");
2687 return;
2688 }
2689 }
2690
2691 qdev_set_legacy_instance_id(dev, isa->iobase, 2);
2692 fdctrl_realize_common(dev, fdctrl, &err);
2693 if (err != NULL) {
2694 error_propagate(errp, err);
2695 return;
2696 }
2697 }
2698
2699 static void sysbus_fdc_initfn(Object *obj)
2700 {
2701 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2702 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2703 FDCtrl *fdctrl = &sys->state;
2704
2705 fdctrl->dma_chann = -1;
2706
2707 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_ops, fdctrl,
2708 "fdc", 0x08);
2709 sysbus_init_mmio(sbd, &fdctrl->iomem);
2710 }
2711
2712 static void sun4m_fdc_initfn(Object *obj)
2713 {
2714 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
2715 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2716 FDCtrl *fdctrl = &sys->state;
2717
2718 fdctrl->dma_chann = -1;
2719
2720 memory_region_init_io(&fdctrl->iomem, obj, &fdctrl_mem_strict_ops,
2721 fdctrl, "fdctrl", 0x08);
2722 sysbus_init_mmio(sbd, &fdctrl->iomem);
2723 }
2724
2725 static void sysbus_fdc_common_initfn(Object *obj)
2726 {
2727 DeviceState *dev = DEVICE(obj);
2728 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
2729 FDCtrlSysBus *sys = SYSBUS_FDC(obj);
2730 FDCtrl *fdctrl = &sys->state;
2731
2732 qdev_set_legacy_instance_id(dev, 0 /* io */, 2); /* FIXME */
2733
2734 sysbus_init_irq(sbd, &fdctrl->irq);
2735 qdev_init_gpio_in(dev, fdctrl_handle_tc, 1);
2736 }
2737
2738 static void sysbus_fdc_common_realize(DeviceState *dev, Error **errp)
2739 {
2740 FDCtrlSysBus *sys = SYSBUS_FDC(dev);
2741 FDCtrl *fdctrl = &sys->state;
2742
2743 fdctrl_realize_common(dev, fdctrl, errp);
2744 }
2745
2746 FloppyDriveType isa_fdc_get_drive_type(ISADevice *fdc, int i)
2747 {
2748 FDCtrlISABus *isa = ISA_FDC(fdc);
2749
2750 return isa->state.drives[i].drive;
2751 }
2752
2753 static void isa_fdc_get_drive_max_chs(FloppyDriveType type, uint8_t *maxc,
2754 uint8_t *maxh, uint8_t *maxs)
2755 {
2756 const FDFormat *fdf;
2757
2758 *maxc = *maxh = *maxs = 0;
2759 for (fdf = fd_formats; fdf->drive != FLOPPY_DRIVE_TYPE_NONE; fdf++) {
2760 if (fdf->drive != type) {
2761 continue;
2762 }
2763 if (*maxc < fdf->max_track) {
2764 *maxc = fdf->max_track;
2765 }
2766 if (*maxh < fdf->max_head) {
2767 *maxh = fdf->max_head;
2768 }
2769 if (*maxs < fdf->last_sect) {
2770 *maxs = fdf->last_sect;
2771 }
2772 }
2773 (*maxc)--;
2774 }
2775
2776 static Aml *build_fdinfo_aml(int idx, FloppyDriveType type)
2777 {
2778 Aml *dev, *fdi;
2779 uint8_t maxc, maxh, maxs;
2780
2781 isa_fdc_get_drive_max_chs(type, &maxc, &maxh, &maxs);
2782
2783 dev = aml_device("FLP%c", 'A' + idx);
2784
2785 aml_append(dev, aml_name_decl("_ADR", aml_int(idx)));
2786
2787 fdi = aml_package(16);
2788 aml_append(fdi, aml_int(idx)); /* Drive Number */
2789 aml_append(fdi,
2790 aml_int(cmos_get_fd_drive_type(type))); /* Device Type */
2791 /*
2792 * the values below are the limits of the drive, and are thus independent
2793 * of the inserted media
2794 */
2795 aml_append(fdi, aml_int(maxc)); /* Maximum Cylinder Number */
2796 aml_append(fdi, aml_int(maxs)); /* Maximum Sector Number */
2797 aml_append(fdi, aml_int(maxh)); /* Maximum Head Number */
2798 /*
2799 * SeaBIOS returns the below values for int 0x13 func 0x08 regardless of
2800 * the drive type, so shall we
2801 */
2802 aml_append(fdi, aml_int(0xAF)); /* disk_specify_1 */
2803 aml_append(fdi, aml_int(0x02)); /* disk_specify_2 */
2804 aml_append(fdi, aml_int(0x25)); /* disk_motor_wait */
2805 aml_append(fdi, aml_int(0x02)); /* disk_sector_siz */
2806 aml_append(fdi, aml_int(0x12)); /* disk_eot */
2807 aml_append(fdi, aml_int(0x1B)); /* disk_rw_gap */
2808 aml_append(fdi, aml_int(0xFF)); /* disk_dtl */
2809 aml_append(fdi, aml_int(0x6C)); /* disk_formt_gap */
2810 aml_append(fdi, aml_int(0xF6)); /* disk_fill */
2811 aml_append(fdi, aml_int(0x0F)); /* disk_head_sttl */
2812 aml_append(fdi, aml_int(0x08)); /* disk_motor_strt */
2813
2814 aml_append(dev, aml_name_decl("_FDI", fdi));
2815 return dev;
2816 }
2817
2818 int cmos_get_fd_drive_type(FloppyDriveType fd0)
2819 {
2820 int val;
2821
2822 switch (fd0) {
2823 case FLOPPY_DRIVE_TYPE_144:
2824 /* 1.44 Mb 3"5 drive */
2825 val = 4;
2826 break;
2827 case FLOPPY_DRIVE_TYPE_288:
2828 /* 2.88 Mb 3"5 drive */
2829 val = 5;
2830 break;
2831 case FLOPPY_DRIVE_TYPE_120:
2832 /* 1.2 Mb 5"5 drive */
2833 val = 2;
2834 break;
2835 case FLOPPY_DRIVE_TYPE_NONE:
2836 default:
2837 val = 0;
2838 break;
2839 }
2840 return val;
2841 }
2842
2843 static void fdc_isa_build_aml(ISADevice *isadev, Aml *scope)
2844 {
2845 Aml *dev;
2846 Aml *crs;
2847 int i;
2848
2849 #define ACPI_FDE_MAX_FD 4
2850 uint32_t fde_buf[5] = {
2851 0, 0, 0, 0, /* presence of floppy drives #0 - #3 */
2852 cpu_to_le32(2) /* tape presence (2 == never present) */
2853 };
2854
2855 crs = aml_resource_template();
2856 aml_append(crs, aml_io(AML_DECODE16, 0x03F2, 0x03F2, 0x00, 0x04));
2857 aml_append(crs, aml_io(AML_DECODE16, 0x03F7, 0x03F7, 0x00, 0x01));
2858 aml_append(crs, aml_irq_no_flags(6));
2859 aml_append(crs,
2860 aml_dma(AML_COMPATIBILITY, AML_NOTBUSMASTER, AML_TRANSFER8, 2));
2861
2862 dev = aml_device("FDC0");
2863 aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0700")));
2864 aml_append(dev, aml_name_decl("_CRS", crs));
2865
2866 for (i = 0; i < MIN(MAX_FD, ACPI_FDE_MAX_FD); i++) {
2867 FloppyDriveType type = isa_fdc_get_drive_type(isadev, i);
2868
2869 if (type < FLOPPY_DRIVE_TYPE_NONE) {
2870 fde_buf[i] = cpu_to_le32(1); /* drive present */
2871 aml_append(dev, build_fdinfo_aml(i, type));
2872 }
2873 }
2874 aml_append(dev, aml_name_decl("_FDE",
2875 aml_buffer(sizeof(fde_buf), (uint8_t *)fde_buf)));
2876
2877 aml_append(scope, dev);
2878 }
2879
2880 static const VMStateDescription vmstate_isa_fdc ={
2881 .name = "fdc",
2882 .version_id = 2,
2883 .minimum_version_id = 2,
2884 .fields = (VMStateField[]) {
2885 VMSTATE_STRUCT(state, FDCtrlISABus, 0, vmstate_fdc, FDCtrl),
2886 VMSTATE_END_OF_LIST()
2887 }
2888 };
2889
2890 static Property isa_fdc_properties[] = {
2891 DEFINE_PROP_UINT32("iobase", FDCtrlISABus, iobase, 0x3f0),
2892 DEFINE_PROP_UINT32("irq", FDCtrlISABus, irq, 6),
2893 DEFINE_PROP_UINT32("dma", FDCtrlISABus, dma, 2),
2894 DEFINE_PROP_DRIVE("driveA", FDCtrlISABus, state.qdev_for_drives[0].blk),
2895 DEFINE_PROP_DRIVE("driveB", FDCtrlISABus, state.qdev_for_drives[1].blk),
2896 DEFINE_PROP_BIT("check_media_rate", FDCtrlISABus, state.check_media_rate,
2897 0, true),
2898 DEFINE_PROP_SIGNED("fdtypeA", FDCtrlISABus, state.qdev_for_drives[0].type,
2899 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2900 FloppyDriveType),
2901 DEFINE_PROP_SIGNED("fdtypeB", FDCtrlISABus, state.qdev_for_drives[1].type,
2902 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2903 FloppyDriveType),
2904 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback,
2905 FLOPPY_DRIVE_TYPE_288, qdev_prop_fdc_drive_type,
2906 FloppyDriveType),
2907 DEFINE_PROP_END_OF_LIST(),
2908 };
2909
2910 static void isabus_fdc_class_init(ObjectClass *klass, void *data)
2911 {
2912 DeviceClass *dc = DEVICE_CLASS(klass);
2913 ISADeviceClass *isa = ISA_DEVICE_CLASS(klass);
2914
2915 dc->realize = isabus_fdc_realize;
2916 dc->fw_name = "fdc";
2917 dc->reset = fdctrl_external_reset_isa;
2918 dc->vmsd = &vmstate_isa_fdc;
2919 isa->build_aml = fdc_isa_build_aml;
2920 device_class_set_props(dc, isa_fdc_properties);
2921 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2922 }
2923
2924 static void isabus_fdc_instance_init(Object *obj)
2925 {
2926 FDCtrlISABus *isa = ISA_FDC(obj);
2927
2928 device_add_bootindex_property(obj, &isa->bootindexA,
2929 "bootindexA", "/floppy@0",
2930 DEVICE(obj));
2931 device_add_bootindex_property(obj, &isa->bootindexB,
2932 "bootindexB", "/floppy@1",
2933 DEVICE(obj));
2934 }
2935
2936 static const TypeInfo isa_fdc_info = {
2937 .name = TYPE_ISA_FDC,
2938 .parent = TYPE_ISA_DEVICE,
2939 .instance_size = sizeof(FDCtrlISABus),
2940 .class_init = isabus_fdc_class_init,
2941 .instance_init = isabus_fdc_instance_init,
2942 };
2943
2944 static const VMStateDescription vmstate_sysbus_fdc ={
2945 .name = "fdc",
2946 .version_id = 2,
2947 .minimum_version_id = 2,
2948 .fields = (VMStateField[]) {
2949 VMSTATE_STRUCT(state, FDCtrlSysBus, 0, vmstate_fdc, FDCtrl),
2950 VMSTATE_END_OF_LIST()
2951 }
2952 };
2953
2954 static Property sysbus_fdc_properties[] = {
2955 DEFINE_PROP_DRIVE("driveA", FDCtrlSysBus, state.qdev_for_drives[0].blk),
2956 DEFINE_PROP_DRIVE("driveB", FDCtrlSysBus, state.qdev_for_drives[1].blk),
2957 DEFINE_PROP_SIGNED("fdtypeA", FDCtrlSysBus, state.qdev_for_drives[0].type,
2958 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2959 FloppyDriveType),
2960 DEFINE_PROP_SIGNED("fdtypeB", FDCtrlSysBus, state.qdev_for_drives[1].type,
2961 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2962 FloppyDriveType),
2963 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback,
2964 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2965 FloppyDriveType),
2966 DEFINE_PROP_END_OF_LIST(),
2967 };
2968
2969 static void sysbus_fdc_class_init(ObjectClass *klass, void *data)
2970 {
2971 DeviceClass *dc = DEVICE_CLASS(klass);
2972
2973 device_class_set_props(dc, sysbus_fdc_properties);
2974 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
2975 }
2976
2977 static const TypeInfo sysbus_fdc_info = {
2978 .name = "sysbus-fdc",
2979 .parent = TYPE_SYSBUS_FDC,
2980 .instance_init = sysbus_fdc_initfn,
2981 .class_init = sysbus_fdc_class_init,
2982 };
2983
2984 static Property sun4m_fdc_properties[] = {
2985 DEFINE_PROP_DRIVE("drive", FDCtrlSysBus, state.qdev_for_drives[0].blk),
2986 DEFINE_PROP_SIGNED("fdtype", FDCtrlSysBus, state.qdev_for_drives[0].type,
2987 FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type,
2988 FloppyDriveType),
2989 DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback,
2990 FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type,
2991 FloppyDriveType),
2992 DEFINE_PROP_END_OF_LIST(),
2993 };
2994
2995 static void sun4m_fdc_class_init(ObjectClass *klass, void *data)
2996 {
2997 DeviceClass *dc = DEVICE_CLASS(klass);
2998
2999 device_class_set_props(dc, sun4m_fdc_properties);
3000 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
3001 }
3002
3003 static const TypeInfo sun4m_fdc_info = {
3004 .name = "SUNW,fdtwo",
3005 .parent = TYPE_SYSBUS_FDC,
3006 .instance_init = sun4m_fdc_initfn,
3007 .class_init = sun4m_fdc_class_init,
3008 };
3009
3010 static void sysbus_fdc_common_class_init(ObjectClass *klass, void *data)
3011 {
3012 DeviceClass *dc = DEVICE_CLASS(klass);
3013
3014 dc->realize = sysbus_fdc_common_realize;
3015 dc->reset = fdctrl_external_reset_sysbus;
3016 dc->vmsd = &vmstate_sysbus_fdc;
3017 }
3018
3019 static const TypeInfo sysbus_fdc_type_info = {
3020 .name = TYPE_SYSBUS_FDC,
3021 .parent = TYPE_SYS_BUS_DEVICE,
3022 .instance_size = sizeof(FDCtrlSysBus),
3023 .instance_init = sysbus_fdc_common_initfn,
3024 .abstract = true,
3025 .class_init = sysbus_fdc_common_class_init,
3026 };
3027
3028 static void fdc_register_types(void)
3029 {
3030 type_register_static(&isa_fdc_info);
3031 type_register_static(&sysbus_fdc_type_info);
3032 type_register_static(&sysbus_fdc_info);
3033 type_register_static(&sun4m_fdc_info);
3034 type_register_static(&floppy_bus_info);
3035 type_register_static(&floppy_drive_info);
3036 }
3037
3038 type_init(fdc_register_types)
armbru's QEMU hackery