hw/misc/zynq_slcr.c

   1 /*
   2  * Status and system control registers for Xilinx Zynq Platform
   3  *
   4  * Copyright (c) 2011 Michal Simek <monstr@monstr.eu>
   5  * Copyright (c) 2012 PetaLogix Pty Ltd.
   6  * Based on hw/arm_sysctl.c, written by Paul Brook
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version
  11  * 2 of the License, or (at your option) any later version.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include "qemu/osdep.h"
  18 #include "qemu/timer.h"
  19 #include "sysemu/runstate.h"
  20 #include "hw/sysbus.h"
  21 #include "migration/vmstate.h"
  22 #include "qemu/log.h"
  23 #include "qemu/module.h"
  24 #include "hw/registerfields.h"
  25 #include "hw/qdev-clock.h"
  26
  27 #ifndef ZYNQ_SLCR_ERR_DEBUG
  28 #define ZYNQ_SLCR_ERR_DEBUG 0
  29 #endif
  30
  31 #define DB_PRINT(...) do { \
  32         if (ZYNQ_SLCR_ERR_DEBUG) { \
  33             fprintf(stderr,  ": %s: ", __func__); \
  34             fprintf(stderr, ## __VA_ARGS__); \
  35         } \
  36     } while (0)
  37
  38 #define XILINX_LOCK_KEY 0x767b
  39 #define XILINX_UNLOCK_KEY 0xdf0d
  40
  41 REG32(SCL, 0x000)
  42 REG32(LOCK, 0x004)
  43 REG32(UNLOCK, 0x008)
  44 REG32(LOCKSTA, 0x00c)
  45
  46 REG32(ARM_PLL_CTRL, 0x100)
  47 REG32(DDR_PLL_CTRL, 0x104)
  48 REG32(IO_PLL_CTRL, 0x108)
  49 /* fields for [ARM|DDR|IO]_PLL_CTRL registers */
  50     FIELD(xxx_PLL_CTRL, PLL_RESET, 0, 1)
  51     FIELD(xxx_PLL_CTRL, PLL_PWRDWN, 1, 1)
  52     FIELD(xxx_PLL_CTRL, PLL_BYPASS_QUAL, 3, 1)
  53     FIELD(xxx_PLL_CTRL, PLL_BYPASS_FORCE, 4, 1)
  54     FIELD(xxx_PLL_CTRL, PLL_FPDIV, 12, 7)
  55 REG32(PLL_STATUS, 0x10c)
  56 REG32(ARM_PLL_CFG, 0x110)
  57 REG32(DDR_PLL_CFG, 0x114)
  58 REG32(IO_PLL_CFG, 0x118)
  59
  60 REG32(ARM_CLK_CTRL, 0x120)
  61 REG32(DDR_CLK_CTRL, 0x124)
  62 REG32(DCI_CLK_CTRL, 0x128)
  63 REG32(APER_CLK_CTRL, 0x12c)
  64 REG32(USB0_CLK_CTRL, 0x130)
  65 REG32(USB1_CLK_CTRL, 0x134)
  66 REG32(GEM0_RCLK_CTRL, 0x138)
  67 REG32(GEM1_RCLK_CTRL, 0x13c)
  68 REG32(GEM0_CLK_CTRL, 0x140)
  69 REG32(GEM1_CLK_CTRL, 0x144)
  70 REG32(SMC_CLK_CTRL, 0x148)
  71 REG32(LQSPI_CLK_CTRL, 0x14c)
  72 REG32(SDIO_CLK_CTRL, 0x150)
  73 REG32(UART_CLK_CTRL, 0x154)
  74     FIELD(UART_CLK_CTRL, CLKACT0, 0, 1)
  75     FIELD(UART_CLK_CTRL, CLKACT1, 1, 1)
  76     FIELD(UART_CLK_CTRL, SRCSEL,  4, 2)
  77     FIELD(UART_CLK_CTRL, DIVISOR, 8, 6)
  78 REG32(SPI_CLK_CTRL, 0x158)
  79 REG32(CAN_CLK_CTRL, 0x15c)
  80 REG32(CAN_MIOCLK_CTRL, 0x160)
  81 REG32(DBG_CLK_CTRL, 0x164)
  82 REG32(PCAP_CLK_CTRL, 0x168)
  83 REG32(TOPSW_CLK_CTRL, 0x16c)
  84
  85 #define FPGA_CTRL_REGS(n, start) \
  86     REG32(FPGA ## n ## _CLK_CTRL, (start)) \
  87     REG32(FPGA ## n ## _THR_CTRL, (start) + 0x4)\
  88     REG32(FPGA ## n ## _THR_CNT,  (start) + 0x8)\
  89     REG32(FPGA ## n ## _THR_STA,  (start) + 0xc)
  90 FPGA_CTRL_REGS(0, 0x170)
  91 FPGA_CTRL_REGS(1, 0x180)
  92 FPGA_CTRL_REGS(2, 0x190)
  93 FPGA_CTRL_REGS(3, 0x1a0)
  94
  95 REG32(BANDGAP_TRIP, 0x1b8)
  96 REG32(PLL_PREDIVISOR, 0x1c0)
  97 REG32(CLK_621_TRUE, 0x1c4)
  98
  99 REG32(PSS_RST_CTRL, 0x200)
 100     FIELD(PSS_RST_CTRL, SOFT_RST, 0, 1)
 101 REG32(DDR_RST_CTRL, 0x204)
 102 REG32(TOPSW_RESET_CTRL, 0x208)
 103 REG32(DMAC_RST_CTRL, 0x20c)
 104 REG32(USB_RST_CTRL, 0x210)
 105 REG32(GEM_RST_CTRL, 0x214)
 106 REG32(SDIO_RST_CTRL, 0x218)
 107 REG32(SPI_RST_CTRL, 0x21c)
 108 REG32(CAN_RST_CTRL, 0x220)
 109 REG32(I2C_RST_CTRL, 0x224)
 110 REG32(UART_RST_CTRL, 0x228)
 111 REG32(GPIO_RST_CTRL, 0x22c)
 112 REG32(LQSPI_RST_CTRL, 0x230)
 113 REG32(SMC_RST_CTRL, 0x234)
 114 REG32(OCM_RST_CTRL, 0x238)
 115 REG32(FPGA_RST_CTRL, 0x240)
 116 REG32(A9_CPU_RST_CTRL, 0x244)
 117
 118 REG32(RS_AWDT_CTRL, 0x24c)
 119 REG32(RST_REASON, 0x250)
 120
 121 REG32(REBOOT_STATUS, 0x258)
 122 REG32(BOOT_MODE, 0x25c)
 123
 124 REG32(APU_CTRL, 0x300)
 125 REG32(WDT_CLK_SEL, 0x304)
 126
 127 REG32(TZ_DMA_NS, 0x440)
 128 REG32(TZ_DMA_IRQ_NS, 0x444)
 129 REG32(TZ_DMA_PERIPH_NS, 0x448)
 130
 131 REG32(PSS_IDCODE, 0x530)
 132
 133 REG32(DDR_URGENT, 0x600)
 134 REG32(DDR_CAL_START, 0x60c)
 135 REG32(DDR_REF_START, 0x614)
 136 REG32(DDR_CMD_STA, 0x618)
 137 REG32(DDR_URGENT_SEL, 0x61c)
 138 REG32(DDR_DFI_STATUS, 0x620)
 139
 140 REG32(MIO, 0x700)
 141 #define MIO_LENGTH 54
 142
 143 REG32(MIO_LOOPBACK, 0x804)
 144 REG32(MIO_MST_TRI0, 0x808)
 145 REG32(MIO_MST_TRI1, 0x80c)
 146
 147 REG32(SD0_WP_CD_SEL, 0x830)
 148 REG32(SD1_WP_CD_SEL, 0x834)
 149
 150 REG32(LVL_SHFTR_EN, 0x900)
 151 REG32(OCM_CFG, 0x910)
 152
 153 REG32(CPU_RAM, 0xa00)
 154
 155 REG32(IOU, 0xa30)
 156
 157 REG32(DMAC_RAM, 0xa50)
 158
 159 REG32(AFI0, 0xa60)
 160 REG32(AFI1, 0xa6c)
 161 REG32(AFI2, 0xa78)
 162 REG32(AFI3, 0xa84)
 163 #define AFI_LENGTH 3
 164
 165 REG32(OCM, 0xa90)
 166
 167 REG32(DEVCI_RAM, 0xaa0)
 168
 169 REG32(CSG_RAM, 0xab0)
 170
 171 REG32(GPIOB_CTRL, 0xb00)
 172 REG32(GPIOB_CFG_CMOS18, 0xb04)
 173 REG32(GPIOB_CFG_CMOS25, 0xb08)
 174 REG32(GPIOB_CFG_CMOS33, 0xb0c)
 175 REG32(GPIOB_CFG_HSTL, 0xb14)
 176 REG32(GPIOB_DRVR_BIAS_CTRL, 0xb18)
 177
 178 REG32(DDRIOB, 0xb40)
 179 #define DDRIOB_LENGTH 14
 180
 181 #define ZYNQ_SLCR_MMIO_SIZE     0x1000
 182 #define ZYNQ_SLCR_NUM_REGS      (ZYNQ_SLCR_MMIO_SIZE / 4)
 183
 184 #define TYPE_ZYNQ_SLCR "xilinx,zynq_slcr"
 185 #define ZYNQ_SLCR(obj) OBJECT_CHECK(ZynqSLCRState, (obj), TYPE_ZYNQ_SLCR)
 186
 187 typedef struct ZynqSLCRState {
 188     SysBusDevice parent_obj;
 189
 190     MemoryRegion iomem;
 191
 192     uint32_t regs[ZYNQ_SLCR_NUM_REGS];
 193
 194     Clock *ps_clk;
 195     Clock *uart0_ref_clk;
 196     Clock *uart1_ref_clk;
 197 } ZynqSLCRState;
 198
 199 /*
 200  * return the output frequency of ARM/DDR/IO pll
 201  * using input frequency and PLL_CTRL register
 202  */
 203 static uint64_t zynq_slcr_compute_pll(uint64_t input, uint32_t ctrl_reg)
 204 {
 205     uint32_t mult = ((ctrl_reg & R_xxx_PLL_CTRL_PLL_FPDIV_MASK) >>
 206             R_xxx_PLL_CTRL_PLL_FPDIV_SHIFT);
 207
 208     /* first, check if pll is bypassed */
 209     if (ctrl_reg & R_xxx_PLL_CTRL_PLL_BYPASS_FORCE_MASK) {
 210         return input;
 211     }
 212
 213     /* is pll disabled ? */
 214     if (ctrl_reg & (R_xxx_PLL_CTRL_PLL_RESET_MASK |
 215                     R_xxx_PLL_CTRL_PLL_PWRDWN_MASK)) {
 216         return 0;
 217     }
 218
 219     /* frequency multiplier -> period division */
 220     return input / mult;
 221 }
 222
 223 /*
 224  * return the output period of a clock given:
 225  * + the periods in an array corresponding to input mux selector
 226  * + the register xxx_CLK_CTRL value
 227  * + enable bit index in ctrl register
 228  *
 229  * This function makes the assumption that the ctrl_reg value is organized as
 230  * follows:
 231  * + bits[13:8]  clock frequency divisor
 232  * + bits[5:4]   clock mux selector (index in array)
 233  * + bits[index] clock enable
 234  */
 235 static uint64_t zynq_slcr_compute_clock(const uint64_t periods[],
 236                                         uint32_t ctrl_reg,
 237                                         unsigned index)
 238 {
 239     uint32_t srcsel = extract32(ctrl_reg, 4, 2); /* bits [5:4] */
 240     uint32_t divisor = extract32(ctrl_reg, 8, 6); /* bits [13:8] */
 241
 242     /* first, check if clock is disabled */
 243     if (((ctrl_reg >> index) & 1u) == 0) {
 244         return 0;
 245     }
 246
 247     /*
 248      * according to the Zynq technical ref. manual UG585 v1.12.2 in
 249      * Clocks chapter, section 25.10.1 page 705:
 250      * "The 6-bit divider provides a divide range of 1 to 63"
 251      * We follow here what is implemented in linux kernel and consider
 252      * the 0 value as a bypass (no division).
 253      */
 254     /* frequency divisor -> period multiplication */
 255     return periods[srcsel] * (divisor ? divisor : 1u);
 256 }
 257
 258 /*
 259  * macro helper around zynq_slcr_compute_clock to avoid repeating
 260  * the register name.
 261  */
 262 #define ZYNQ_COMPUTE_CLK(state, plls, reg, enable_field) \
 263     zynq_slcr_compute_clock((plls), (state)->regs[reg], \
 264                             reg ## _ ## enable_field ## _SHIFT)
 265
 266 /**
 267  * Compute and set the ouputs clocks periods.
 268  * But do not propagate them further. Connected clocks
 269  * will not receive any updates (See zynq_slcr_compute_clocks())
 270  */
 271 static void zynq_slcr_compute_clocks(ZynqSLCRState *s)
 272 {
 273     uint64_t ps_clk = clock_get(s->ps_clk);
 274
 275     /* consider outputs clocks are disabled while in reset */
 276     if (device_is_in_reset(DEVICE(s))) {
 277         ps_clk = 0;
 278     }
 279
 280     uint64_t io_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTRL]);
 281     uint64_t arm_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_CTRL]);
 282     uint64_t ddr_pll = zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_CTRL]);
 283
 284     uint64_t uart_mux[4] = {io_pll, io_pll, arm_pll, ddr_pll};
 285
 286     /* compute uartX reference clocks */
 287     clock_set(s->uart0_ref_clk,
 288               ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0));
 289     clock_set(s->uart1_ref_clk,
 290               ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1));
 291 }
 292
 293 /**
 294  * Propagate the outputs clocks.
 295  * zynq_slcr_compute_clocks() should have been called before
 296  * to configure them.
 297  */
 298 static void zynq_slcr_propagate_clocks(ZynqSLCRState *s)
 299 {
 300     clock_propagate(s->uart0_ref_clk);
 301     clock_propagate(s->uart1_ref_clk);
 302 }
 303
 304 static void zynq_slcr_ps_clk_callback(void *opaque)
 305 {
 306     ZynqSLCRState *s = (ZynqSLCRState *) opaque;
 307     zynq_slcr_compute_clocks(s);
 308     zynq_slcr_propagate_clocks(s);
 309 }
 310
 311 static void zynq_slcr_reset_init(Object *obj, ResetType type)
 312 {
 313     ZynqSLCRState *s = ZYNQ_SLCR(obj);
 314     int i;
 315
 316     DB_PRINT("RESET\n");
 317
 318     s->regs[R_LOCKSTA] = 1;
 319     /* 0x100 - 0x11C */
 320     s->regs[R_ARM_PLL_CTRL]   = 0x0001A008;
 321     s->regs[R_DDR_PLL_CTRL]   = 0x0001A008;
 322     s->regs[R_IO_PLL_CTRL]    = 0x0001A008;
 323     s->regs[R_PLL_STATUS]     = 0x0000003F;
 324     s->regs[R_ARM_PLL_CFG]    = 0x00014000;
 325     s->regs[R_DDR_PLL_CFG]    = 0x00014000;
 326     s->regs[R_IO_PLL_CFG]     = 0x00014000;
 327
 328     /* 0x120 - 0x16C */
 329     s->regs[R_ARM_CLK_CTRL]   = 0x1F000400;
 330     s->regs[R_DDR_CLK_CTRL]   = 0x18400003;
 331     s->regs[R_DCI_CLK_CTRL]   = 0x01E03201;
 332     s->regs[R_APER_CLK_CTRL]  = 0x01FFCCCD;
 333     s->regs[R_USB0_CLK_CTRL]  = s->regs[R_USB1_CLK_CTRL]  = 0x00101941;
 334     s->regs[R_GEM0_RCLK_CTRL] = s->regs[R_GEM1_RCLK_CTRL] = 0x00000001;
 335     s->regs[R_GEM0_CLK_CTRL]  = s->regs[R_GEM1_CLK_CTRL]  = 0x00003C01;
 336     s->regs[R_SMC_CLK_CTRL]   = 0x00003C01;
 337     s->regs[R_LQSPI_CLK_CTRL] = 0x00002821;
 338     s->regs[R_SDIO_CLK_CTRL]  = 0x00001E03;
 339     s->regs[R_UART_CLK_CTRL]  = 0x00003F03;
 340     s->regs[R_SPI_CLK_CTRL]   = 0x00003F03;
 341     s->regs[R_CAN_CLK_CTRL]   = 0x00501903;
 342     s->regs[R_DBG_CLK_CTRL]   = 0x00000F03;
 343     s->regs[R_PCAP_CLK_CTRL]  = 0x00000F01;
 344
 345     /* 0x170 - 0x1AC */
 346     s->regs[R_FPGA0_CLK_CTRL] = s->regs[R_FPGA1_CLK_CTRL]
 347                               = s->regs[R_FPGA2_CLK_CTRL]
 348                               = s->regs[R_FPGA3_CLK_CTRL] = 0x00101800;
 349     s->regs[R_FPGA0_THR_STA] = s->regs[R_FPGA1_THR_STA]
 350                              = s->regs[R_FPGA2_THR_STA]
 351                              = s->regs[R_FPGA3_THR_STA] = 0x00010000;
 352
 353     /* 0x1B0 - 0x1D8 */
 354     s->regs[R_BANDGAP_TRIP]   = 0x0000001F;
 355     s->regs[R_PLL_PREDIVISOR] = 0x00000001;
 356     s->regs[R_CLK_621_TRUE]   = 0x00000001;
 357
 358     /* 0x200 - 0x25C */
 359     s->regs[R_FPGA_RST_CTRL]  = 0x01F33F0F;
 360     s->regs[R_RST_REASON]     = 0x00000040;
 361
 362     s->regs[R_BOOT_MODE]      = 0x00000001;
 363
 364     /* 0x700 - 0x7D4 */
 365     for (i = 0; i < 54; i++) {
 366         s->regs[R_MIO + i] = 0x00001601;
 367     }
 368     for (i = 2; i <= 8; i++) {
 369         s->regs[R_MIO + i] = 0x00000601;
 370     }
 371
 372     s->regs[R_MIO_MST_TRI0] = s->regs[R_MIO_MST_TRI1] = 0xFFFFFFFF;
 373
 374     s->regs[R_CPU_RAM + 0] = s->regs[R_CPU_RAM + 1] = s->regs[R_CPU_RAM + 3]
 375                            = s->regs[R_CPU_RAM + 4] = s->regs[R_CPU_RAM + 7]
 376                            = 0x00010101;
 377     s->regs[R_CPU_RAM + 2] = s->regs[R_CPU_RAM + 5] = 0x01010101;
 378     s->regs[R_CPU_RAM + 6] = 0x00000001;
 379
 380     s->regs[R_IOU + 0] = s->regs[R_IOU + 1] = s->regs[R_IOU + 2]
 381                        = s->regs[R_IOU + 3] = 0x09090909;
 382     s->regs[R_IOU + 4] = s->regs[R_IOU + 5] = 0x00090909;
 383     s->regs[R_IOU + 6] = 0x00000909;
 384
 385     s->regs[R_DMAC_RAM] = 0x00000009;
 386
 387     s->regs[R_AFI0 + 0] = s->regs[R_AFI0 + 1] = 0x09090909;
 388     s->regs[R_AFI1 + 0] = s->regs[R_AFI1 + 1] = 0x09090909;
 389     s->regs[R_AFI2 + 0] = s->regs[R_AFI2 + 1] = 0x09090909;
 390     s->regs[R_AFI3 + 0] = s->regs[R_AFI3 + 1] = 0x09090909;
 391     s->regs[R_AFI0 + 2] = s->regs[R_AFI1 + 2] = s->regs[R_AFI2 + 2]
 392                         = s->regs[R_AFI3 + 2] = 0x00000909;
 393
 394     s->regs[R_OCM + 0] = 0x01010101;
 395     s->regs[R_OCM + 1] = s->regs[R_OCM + 2] = 0x09090909;
 396
 397     s->regs[R_DEVCI_RAM] = 0x00000909;
 398     s->regs[R_CSG_RAM]   = 0x00000001;
 399
 400     s->regs[R_DDRIOB + 0] = s->regs[R_DDRIOB + 1] = s->regs[R_DDRIOB + 2]
 401                           = s->regs[R_DDRIOB + 3] = 0x00000e00;
 402     s->regs[R_DDRIOB + 4] = s->regs[R_DDRIOB + 5] = s->regs[R_DDRIOB + 6]
 403                           = 0x00000e00;
 404     s->regs[R_DDRIOB + 12] = 0x00000021;
 405 }
 406
 407 static void zynq_slcr_reset_hold(Object *obj)
 408 {
 409     ZynqSLCRState *s = ZYNQ_SLCR(obj);
 410
 411     /* will disable all output clocks */
 412     zynq_slcr_compute_clocks(s);
 413     zynq_slcr_propagate_clocks(s);
 414 }
 415
 416 static void zynq_slcr_reset_exit(Object *obj)
 417 {
 418     ZynqSLCRState *s = ZYNQ_SLCR(obj);
 419
 420     /* will compute output clocks according to ps_clk and registers */
 421     zynq_slcr_compute_clocks(s);
 422     zynq_slcr_propagate_clocks(s);
 423 }
 424
 425 static bool zynq_slcr_check_offset(hwaddr offset, bool rnw)
 426 {
 427     switch (offset) {
 428     case R_LOCK:
 429     case R_UNLOCK:
 430     case R_DDR_CAL_START:
 431     case R_DDR_REF_START:
 432         return !rnw; /* Write only */
 433     case R_LOCKSTA:
 434     case R_FPGA0_THR_STA:
 435     case R_FPGA1_THR_STA:
 436     case R_FPGA2_THR_STA:
 437     case R_FPGA3_THR_STA:
 438     case R_BOOT_MODE:
 439     case R_PSS_IDCODE:
 440     case R_DDR_CMD_STA:
 441     case R_DDR_DFI_STATUS:
 442     case R_PLL_STATUS:
 443         return rnw;/* read only */
 444     case R_SCL:
 445     case R_ARM_PLL_CTRL ... R_IO_PLL_CTRL:
 446     case R_ARM_PLL_CFG ... R_IO_PLL_CFG:
 447     case R_ARM_CLK_CTRL ... R_TOPSW_CLK_CTRL:
 448     case R_FPGA0_CLK_CTRL ... R_FPGA0_THR_CNT:
 449     case R_FPGA1_CLK_CTRL ... R_FPGA1_THR_CNT:
 450     case R_FPGA2_CLK_CTRL ... R_FPGA2_THR_CNT:
 451     case R_FPGA3_CLK_CTRL ... R_FPGA3_THR_CNT:
 452     case R_BANDGAP_TRIP:
 453     case R_PLL_PREDIVISOR:
 454     case R_CLK_621_TRUE:
 455     case R_PSS_RST_CTRL ... R_A9_CPU_RST_CTRL:
 456     case R_RS_AWDT_CTRL:
 457     case R_RST_REASON:
 458     case R_REBOOT_STATUS:
 459     case R_APU_CTRL:
 460     case R_WDT_CLK_SEL:
 461     case R_TZ_DMA_NS ... R_TZ_DMA_PERIPH_NS:
 462     case R_DDR_URGENT:
 463     case R_DDR_URGENT_SEL:
 464     case R_MIO ... R_MIO + MIO_LENGTH - 1:
 465     case R_MIO_LOOPBACK ... R_MIO_MST_TRI1:
 466     case R_SD0_WP_CD_SEL:
 467     case R_SD1_WP_CD_SEL:
 468     case R_LVL_SHFTR_EN:
 469     case R_OCM_CFG:
 470     case R_CPU_RAM:
 471     case R_IOU:
 472     case R_DMAC_RAM:
 473     case R_AFI0 ... R_AFI3 + AFI_LENGTH - 1:
 474     case R_OCM:
 475     case R_DEVCI_RAM:
 476     case R_CSG_RAM:
 477     case R_GPIOB_CTRL ... R_GPIOB_CFG_CMOS33:
 478     case R_GPIOB_CFG_HSTL:
 479     case R_GPIOB_DRVR_BIAS_CTRL:
 480     case R_DDRIOB ... R_DDRIOB + DDRIOB_LENGTH - 1:
 481         return true;
 482     default:
 483         return false;
 484     }
 485 }
 486
 487 static uint64_t zynq_slcr_read(void *opaque, hwaddr offset,
 488     unsigned size)
 489 {
 490     ZynqSLCRState *s = opaque;
 491     offset /= 4;
 492     uint32_t ret = s->regs[offset];
 493
 494     if (!zynq_slcr_check_offset(offset, true)) {
 495         qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid read access to "
 496                       " addr %" HWADDR_PRIx "\n", offset * 4);
 497     }
 498
 499     DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx32 "\n", offset * 4, ret);
 500     return ret;
 501 }
 502
 503 static void zynq_slcr_write(void *opaque, hwaddr offset,
 504                           uint64_t val, unsigned size)
 505 {
 506     ZynqSLCRState *s = (ZynqSLCRState *)opaque;
 507     offset /= 4;
 508
 509     DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx64 "\n", offset * 4, val);
 510
 511     if (!zynq_slcr_check_offset(offset, false)) {
 512         qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid write access to "
 513                       "addr %" HWADDR_PRIx "\n", offset * 4);
 514         return;
 515     }
 516
 517     switch (offset) {
 518     case R_SCL:
 519         s->regs[R_SCL] = val & 0x1;
 520         return;
 521     case R_LOCK:
 522         if ((val & 0xFFFF) == XILINX_LOCK_KEY) {
 523             DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
 524                 (unsigned)val & 0xFFFF);
 525             s->regs[R_LOCKSTA] = 1;
 526         } else {
 527             DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
 528                 (int)offset, (unsigned)val & 0xFFFF);
 529         }
 530         return;
 531     case R_UNLOCK:
 532         if ((val & 0xFFFF) == XILINX_UNLOCK_KEY) {
 533             DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
 534                 (unsigned)val & 0xFFFF);
 535             s->regs[R_LOCKSTA] = 0;
 536         } else {
 537             DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
 538                 (int)offset, (unsigned)val & 0xFFFF);
 539         }
 540         return;
 541     }
 542
 543     if (s->regs[R_LOCKSTA]) {
 544         qemu_log_mask(LOG_GUEST_ERROR,
 545                       "SCLR registers are locked. Unlock them first\n");
 546         return;
 547     }
 548     s->regs[offset] = val;
 549
 550     switch (offset) {
 551     case R_PSS_RST_CTRL:
 552         if (FIELD_EX32(val, PSS_RST_CTRL, SOFT_RST)) {
 553             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 554         }
 555         break;
 556     case R_IO_PLL_CTRL:
 557     case R_ARM_PLL_CTRL:
 558     case R_DDR_PLL_CTRL:
 559     case R_UART_CLK_CTRL:
 560         zynq_slcr_compute_clocks(s);
 561         zynq_slcr_propagate_clocks(s);
 562         break;
 563     }
 564 }
 565
 566 static const MemoryRegionOps slcr_ops = {
 567     .read = zynq_slcr_read,
 568     .write = zynq_slcr_write,
 569     .endianness = DEVICE_NATIVE_ENDIAN,
 570 };
 571
 572 static const ClockPortInitArray zynq_slcr_clocks = {
 573     QDEV_CLOCK_IN(ZynqSLCRState, ps_clk, zynq_slcr_ps_clk_callback),
 574     QDEV_CLOCK_OUT(ZynqSLCRState, uart0_ref_clk),
 575     QDEV_CLOCK_OUT(ZynqSLCRState, uart1_ref_clk),
 576     QDEV_CLOCK_END
 577 };
 578
 579 static void zynq_slcr_init(Object *obj)
 580 {
 581     ZynqSLCRState *s = ZYNQ_SLCR(obj);
 582
 583     memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr",
 584                           ZYNQ_SLCR_MMIO_SIZE);
 585     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
 586
 587     qdev_init_clocks(DEVICE(obj), zynq_slcr_clocks);
 588 }
 589
 590 static const VMStateDescription vmstate_zynq_slcr = {
 591     .name = "zynq_slcr",
 592     .version_id = 3,
 593     .minimum_version_id = 2,
 594     .fields = (VMStateField[]) {
 595         VMSTATE_UINT32_ARRAY(regs, ZynqSLCRState, ZYNQ_SLCR_NUM_REGS),
 596         VMSTATE_CLOCK_V(ps_clk, ZynqSLCRState, 3),
 597         VMSTATE_END_OF_LIST()
 598     }
 599 };
 600
 601 static void zynq_slcr_class_init(ObjectClass *klass, void *data)
 602 {
 603     DeviceClass *dc = DEVICE_CLASS(klass);
 604     ResettableClass *rc = RESETTABLE_CLASS(klass);
 605
 606     dc->vmsd = &vmstate_zynq_slcr;
 607     rc->phases.enter = zynq_slcr_reset_init;
 608     rc->phases.hold  = zynq_slcr_reset_hold;
 609     rc->phases.exit  = zynq_slcr_reset_exit;
 610 }
 611
 612 static const TypeInfo zynq_slcr_info = {
 613     .class_init = zynq_slcr_class_init,
 614     .name  = TYPE_ZYNQ_SLCR,
 615     .parent = TYPE_SYS_BUS_DEVICE,
 616     .instance_size  = sizeof(ZynqSLCRState),
 617     .instance_init = zynq_slcr_init,
 618 };
 619
 620 static void zynq_slcr_register_types(void)
 621 {
 622     type_register_static(&zynq_slcr_info);
 623 }
 624
 625 type_init(zynq_slcr_register_types)