hw/ppc/spapr_cpu_core.c

   1 /*
   2  * sPAPR CPU core device, acts as container of CPU thread devices.
   3  *
   4  * Copyright (C) 2016 Bharata B Rao <bharata@linux.vnet.ibm.com>
   5  *
   6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
   7  * See the COPYING file in the top-level directory.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "hw/cpu/core.h"
  12 #include "hw/ppc/spapr_cpu_core.h"
  13 #include "hw/qdev-properties.h"
  14 #include "migration/vmstate.h"
  15 #include "target/ppc/cpu.h"
  16 #include "hw/ppc/spapr.h"
  17 #include "qapi/error.h"
  18 #include "sysemu/cpus.h"
  19 #include "sysemu/kvm.h"
  20 #include "target/ppc/kvm_ppc.h"
  21 #include "hw/ppc/ppc.h"
  22 #include "target/ppc/mmu-hash64.h"
  23 #include "sysemu/numa.h"
  24 #include "sysemu/reset.h"
  25 #include "sysemu/hw_accel.h"
  26 #include "qemu/error-report.h"
  27
  28 static void spapr_reset_vcpu(PowerPCCPU *cpu)
  29 {
  30     CPUState *cs = CPU(cpu);
  31     CPUPPCState *env = &cpu->env;
  32     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
  33     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
  34     target_ulong lpcr;
  35     SpaprMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
  36
  37     cpu_reset(cs);
  38
  39     /* All CPUs start halted.  CPU0 is unhalted from the machine level
  40      * reset code and the rest are explicitly started up by the guest
  41      * using an RTAS call */
  42     cs->halted = 1;
  43
  44     env->spr[SPR_HIOR] = 0;
  45
  46     lpcr = env->spr[SPR_LPCR];
  47
  48     /* Set emulated LPCR to not send interrupts to hypervisor. Note that
  49      * under KVM, the actual HW LPCR will be set differently by KVM itself,
  50      * the settings below ensure proper operations with TCG in absence of
  51      * a real hypervisor.
  52      *
  53      * Disable Power-saving mode Exit Cause exceptions for the CPU, so
  54      * we don't get spurious wakups before an RTAS start-cpu call.
  55      * For the same reason, set PSSCR_EC.
  56      */
  57     lpcr &= ~(LPCR_VPM1 | LPCR_ISL | LPCR_KBV | pcc->lpcr_pm);
  58     lpcr |= LPCR_LPES0 | LPCR_LPES1;
  59     env->spr[SPR_PSSCR] |= PSSCR_EC;
  60
  61     ppc_store_lpcr(cpu, lpcr);
  62
  63     /* Set a full AMOR so guest can use the AMR as it sees fit */
  64     env->spr[SPR_AMOR] = 0xffffffffffffffffull;
  65
  66     spapr_cpu->vpa_addr = 0;
  67     spapr_cpu->slb_shadow_addr = 0;
  68     spapr_cpu->slb_shadow_size = 0;
  69     spapr_cpu->dtl_addr = 0;
  70     spapr_cpu->dtl_size = 0;
  71
  72     spapr_caps_cpu_apply(spapr, cpu);
  73
  74     kvm_check_mmu(cpu, &error_fatal);
  75
  76     spapr_irq_cpu_intc_reset(spapr, cpu);
  77 }
  78
  79 void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ulong nip,
  80                                target_ulong r1, target_ulong r3,
  81                                target_ulong r4)
  82 {
  83     PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
  84     CPUPPCState *env = &cpu->env;
  85
  86     env->nip = nip;
  87     env->gpr[1] = r1;
  88     env->gpr[3] = r3;
  89     env->gpr[4] = r4;
  90     kvmppc_set_reg_ppc_online(cpu, 1);
  91     CPU(cpu)->halted = 0;
  92     /* Enable Power-saving mode Exit Cause exceptions */
  93     ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm);
  94 }
  95
  96 /*
  97  * Return the sPAPR CPU core type for @model which essentially is the CPU
  98  * model specified with -cpu cmdline option.
  99  */
 100 const char *spapr_get_cpu_core_type(const char *cpu_type)
 101 {
 102     int len = strlen(cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
 103     char *core_type = g_strdup_printf(SPAPR_CPU_CORE_TYPE_NAME("%.*s"),
 104                                       len, cpu_type);
 105     ObjectClass *oc = object_class_by_name(core_type);
 106
 107     g_free(core_type);
 108     if (!oc) {
 109         return NULL;
 110     }
 111
 112     return object_class_get_name(oc);
 113 }
 114
 115 static bool slb_shadow_needed(void *opaque)
 116 {
 117     SpaprCpuState *spapr_cpu = opaque;
 118
 119     return spapr_cpu->slb_shadow_addr != 0;
 120 }
 121
 122 static const VMStateDescription vmstate_spapr_cpu_slb_shadow = {
 123     .name = "spapr_cpu/vpa/slb_shadow",
 124     .version_id = 1,
 125     .minimum_version_id = 1,
 126     .needed = slb_shadow_needed,
 127     .fields = (VMStateField[]) {
 128         VMSTATE_UINT64(slb_shadow_addr, SpaprCpuState),
 129         VMSTATE_UINT64(slb_shadow_size, SpaprCpuState),
 130         VMSTATE_END_OF_LIST()
 131     }
 132 };
 133
 134 static bool dtl_needed(void *opaque)
 135 {
 136     SpaprCpuState *spapr_cpu = opaque;
 137
 138     return spapr_cpu->dtl_addr != 0;
 139 }
 140
 141 static const VMStateDescription vmstate_spapr_cpu_dtl = {
 142     .name = "spapr_cpu/vpa/dtl",
 143     .version_id = 1,
 144     .minimum_version_id = 1,
 145     .needed = dtl_needed,
 146     .fields = (VMStateField[]) {
 147         VMSTATE_UINT64(dtl_addr, SpaprCpuState),
 148         VMSTATE_UINT64(dtl_size, SpaprCpuState),
 149         VMSTATE_END_OF_LIST()
 150     }
 151 };
 152
 153 static bool vpa_needed(void *opaque)
 154 {
 155     SpaprCpuState *spapr_cpu = opaque;
 156
 157     return spapr_cpu->vpa_addr != 0;
 158 }
 159
 160 static const VMStateDescription vmstate_spapr_cpu_vpa = {
 161     .name = "spapr_cpu/vpa",
 162     .version_id = 1,
 163     .minimum_version_id = 1,
 164     .needed = vpa_needed,
 165     .fields = (VMStateField[]) {
 166         VMSTATE_UINT64(vpa_addr, SpaprCpuState),
 167         VMSTATE_END_OF_LIST()
 168     },
 169     .subsections = (const VMStateDescription * []) {
 170         &vmstate_spapr_cpu_slb_shadow,
 171         &vmstate_spapr_cpu_dtl,
 172         NULL
 173     }
 174 };
 175
 176 static const VMStateDescription vmstate_spapr_cpu_state = {
 177     .name = "spapr_cpu",
 178     .version_id = 1,
 179     .minimum_version_id = 1,
 180     .fields = (VMStateField[]) {
 181         VMSTATE_END_OF_LIST()
 182     },
 183     .subsections = (const VMStateDescription * []) {
 184         &vmstate_spapr_cpu_vpa,
 185         NULL
 186     }
 187 };
 188
 189 static void spapr_unrealize_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc)
 190 {
 191     if (!sc->pre_3_0_migration) {
 192         vmstate_unregister(NULL, &vmstate_spapr_cpu_state, cpu->machine_data);
 193     }
 194     spapr_irq_cpu_intc_destroy(SPAPR_MACHINE(qdev_get_machine()), cpu);
 195     cpu_remove_sync(CPU(cpu));
 196     object_unparent(OBJECT(cpu));
 197 }
 198
 199 /*
 200  * Called when CPUs are hot-plugged.
 201  */
 202 static void spapr_cpu_core_reset(DeviceState *dev)
 203 {
 204     CPUCore *cc = CPU_CORE(dev);
 205     SpaprCpuCore *sc = SPAPR_CPU_CORE(dev);
 206     int i;
 207
 208     for (i = 0; i < cc->nr_threads; i++) {
 209         spapr_reset_vcpu(sc->threads[i]);
 210     }
 211 }
 212
 213 /*
 214  * Called by the machine reset.
 215  */
 216 static void spapr_cpu_core_reset_handler(void *opaque)
 217 {
 218     spapr_cpu_core_reset(opaque);
 219 }
 220
 221 static void spapr_cpu_core_unrealize(DeviceState *dev)
 222 {
 223     SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
 224     CPUCore *cc = CPU_CORE(dev);
 225     int i;
 226
 227     qemu_unregister_reset(spapr_cpu_core_reset_handler, sc);
 228
 229     for (i = 0; i < cc->nr_threads; i++) {
 230         spapr_unrealize_vcpu(sc->threads[i], sc);
 231     }
 232     g_free(sc->threads);
 233 }
 234
 235 static void spapr_realize_vcpu(PowerPCCPU *cpu, SpaprMachineState *spapr,
 236                                SpaprCpuCore *sc, Error **errp)
 237 {
 238     CPUPPCState *env = &cpu->env;
 239     CPUState *cs = CPU(cpu);
 240     Error *local_err = NULL;
 241
 242     if (!qdev_realize(DEVICE(cpu), NULL, errp)) {
 243         return;
 244     }
 245
 246     /* Set time-base frequency to 512 MHz */
 247     cpu_ppc_tb_init(env, SPAPR_TIMEBASE_FREQ);
 248
 249     cpu_ppc_set_vhyp(cpu, PPC_VIRTUAL_HYPERVISOR(spapr));
 250     kvmppc_set_papr(cpu);
 251
 252     if (spapr_irq_cpu_intc_create(spapr, cpu, &local_err) < 0) {
 253         cpu_remove_sync(CPU(cpu));
 254         return;
 255     }
 256
 257     if (!sc->pre_3_0_migration) {
 258         vmstate_register(NULL, cs->cpu_index, &vmstate_spapr_cpu_state,
 259                          cpu->machine_data);
 260     }
 261 }
 262
 263 static PowerPCCPU *spapr_create_vcpu(SpaprCpuCore *sc, int i, Error **errp)
 264 {
 265     SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_GET_CLASS(sc);
 266     CPUCore *cc = CPU_CORE(sc);
 267     Object *obj;
 268     char *id;
 269     CPUState *cs;
 270     PowerPCCPU *cpu;
 271     Error *local_err = NULL;
 272
 273     obj = object_new(scc->cpu_type);
 274
 275     cs = CPU(obj);
 276     cpu = POWERPC_CPU(obj);
 277     cs->cpu_index = cc->core_id + i;
 278     spapr_set_vcpu_id(cpu, cs->cpu_index, &local_err);
 279     if (local_err) {
 280         goto err;
 281     }
 282
 283     cpu->node_id = sc->node_id;
 284
 285     id = g_strdup_printf("thread[%d]", i);
 286     object_property_add_child(OBJECT(sc), id, obj);
 287     g_free(id);
 288
 289     cpu->machine_data = g_new0(SpaprCpuState, 1);
 290
 291     object_unref(obj);
 292     return cpu;
 293
 294 err:
 295     object_unref(obj);
 296     error_propagate(errp, local_err);
 297     return NULL;
 298 }
 299
 300 static void spapr_delete_vcpu(PowerPCCPU *cpu, SpaprCpuCore *sc)
 301 {
 302     SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu);
 303
 304     cpu->machine_data = NULL;
 305     g_free(spapr_cpu);
 306     object_unparent(OBJECT(cpu));
 307 }
 308
 309 static void spapr_cpu_core_realize(DeviceState *dev, Error **errp)
 310 {
 311     /* We don't use SPAPR_MACHINE() in order to exit gracefully if the user
 312      * tries to add a sPAPR CPU core to a non-pseries machine.
 313      */
 314     SpaprMachineState *spapr =
 315         (SpaprMachineState *) object_dynamic_cast(qdev_get_machine(),
 316                                                   TYPE_SPAPR_MACHINE);
 317     SpaprCpuCore *sc = SPAPR_CPU_CORE(OBJECT(dev));
 318     CPUCore *cc = CPU_CORE(OBJECT(dev));
 319     Error *local_err = NULL;
 320     int i, j;
 321
 322     if (!spapr) {
 323         error_setg(errp, TYPE_SPAPR_CPU_CORE " needs a pseries machine");
 324         return;
 325     }
 326
 327     sc->threads = g_new(PowerPCCPU *, cc->nr_threads);
 328     for (i = 0; i < cc->nr_threads; i++) {
 329         sc->threads[i] = spapr_create_vcpu(sc, i, &local_err);
 330         if (local_err) {
 331             goto err;
 332         }
 333     }
 334
 335     for (j = 0; j < cc->nr_threads; j++) {
 336         spapr_realize_vcpu(sc->threads[j], spapr, sc, &local_err);
 337         if (local_err) {
 338             goto err_unrealize;
 339         }
 340     }
 341
 342     qemu_register_reset(spapr_cpu_core_reset_handler, sc);
 343     return;
 344
 345 err_unrealize:
 346     while (--j >= 0) {
 347         spapr_unrealize_vcpu(sc->threads[j], sc);
 348     }
 349 err:
 350     while (--i >= 0) {
 351         spapr_delete_vcpu(sc->threads[i], sc);
 352     }
 353     g_free(sc->threads);
 354     error_propagate(errp, local_err);
 355 }
 356
 357 static Property spapr_cpu_core_properties[] = {
 358     DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID),
 359     DEFINE_PROP_BOOL("pre-3.0-migration", SpaprCpuCore, pre_3_0_migration,
 360                      false),
 361     DEFINE_PROP_END_OF_LIST()
 362 };
 363
 364 static void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
 365 {
 366     DeviceClass *dc = DEVICE_CLASS(oc);
 367     SpaprCpuCoreClass *scc = SPAPR_CPU_CORE_CLASS(oc);
 368
 369     dc->realize = spapr_cpu_core_realize;
 370     dc->unrealize = spapr_cpu_core_unrealize;
 371     dc->reset = spapr_cpu_core_reset;
 372     device_class_set_props(dc, spapr_cpu_core_properties);
 373     scc->cpu_type = data;
 374 }
 375
 376 #define DEFINE_SPAPR_CPU_CORE_TYPE(cpu_model) \
 377     {                                                   \
 378         .parent = TYPE_SPAPR_CPU_CORE,                  \
 379         .class_data = (void *) POWERPC_CPU_TYPE_NAME(cpu_model), \
 380         .class_init = spapr_cpu_core_class_init,        \
 381         .name = SPAPR_CPU_CORE_TYPE_NAME(cpu_model),    \
 382     }
 383
 384 static const TypeInfo spapr_cpu_core_type_infos[] = {
 385     {
 386         .name = TYPE_SPAPR_CPU_CORE,
 387         .parent = TYPE_CPU_CORE,
 388         .abstract = true,
 389         .instance_size = sizeof(SpaprCpuCore),
 390         .class_size = sizeof(SpaprCpuCoreClass),
 391     },
 392     DEFINE_SPAPR_CPU_CORE_TYPE("970_v2.2"),
 393     DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.0"),
 394     DEFINE_SPAPR_CPU_CORE_TYPE("970mp_v1.1"),
 395     DEFINE_SPAPR_CPU_CORE_TYPE("power5+_v2.1"),
 396     DEFINE_SPAPR_CPU_CORE_TYPE("power7_v2.3"),
 397     DEFINE_SPAPR_CPU_CORE_TYPE("power7+_v2.1"),
 398     DEFINE_SPAPR_CPU_CORE_TYPE("power8_v2.0"),
 399     DEFINE_SPAPR_CPU_CORE_TYPE("power8e_v2.1"),
 400     DEFINE_SPAPR_CPU_CORE_TYPE("power8nvl_v1.0"),
 401     DEFINE_SPAPR_CPU_CORE_TYPE("power9_v1.0"),
 402     DEFINE_SPAPR_CPU_CORE_TYPE("power9_v2.0"),
 403     DEFINE_SPAPR_CPU_CORE_TYPE("power10_v1.0"),
 404 #ifdef CONFIG_KVM
 405     DEFINE_SPAPR_CPU_CORE_TYPE("host"),
 406 #endif
 407 };
 408
 409 DEFINE_TYPES(spapr_cpu_core_type_infos)