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qapi: Fix code generated for optional conditional struct member
[qemu/armbru.git] / hw / arm / virt-acpi-build.c
blob4af0de8b24166ba0a5ce6d297d31224d4851860c
1 /* Support for generating ACPI tables and passing them to Guests
2 *
3 * ARM virt ACPI generation
4 *
5 * Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
6 * Copyright (C) 2006 Fabrice Bellard
7 * Copyright (C) 2013 Red Hat Inc
8 *
9 * Author: Michael S. Tsirkin <mst@redhat.com>
10 *
11 * Copyright (c) 2015 HUAWEI TECHNOLOGIES CO.,LTD.
12 *
13 * Author: Shannon Zhao <zhaoshenglong@huawei.com>
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License as published by
17 * the Free Software Foundation; either version 2 of the License, or
18 * (at your option) any later version.
19
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, see <http://www.gnu.org/licenses/>.
27 */
28
29 #include "qemu/osdep.h"
30 #include "qapi/error.h"
31 #include "qemu/bitmap.h"
32 #include "trace.h"
33 #include "hw/core/cpu.h"
34 #include "target/arm/cpu.h"
35 #include "hw/acpi/acpi-defs.h"
36 #include "hw/acpi/acpi.h"
37 #include "hw/nvram/fw_cfg.h"
38 #include "hw/acpi/bios-linker-loader.h"
39 #include "hw/acpi/aml-build.h"
40 #include "hw/acpi/utils.h"
41 #include "hw/acpi/pci.h"
42 #include "hw/acpi/memory_hotplug.h"
43 #include "hw/acpi/generic_event_device.h"
44 #include "hw/acpi/tpm.h"
45 #include "hw/acpi/hmat.h"
46 #include "hw/pci/pcie_host.h"
47 #include "hw/pci/pci.h"
48 #include "hw/pci/pci_bus.h"
49 #include "hw/pci-host/gpex.h"
50 #include "hw/arm/virt.h"
51 #include "hw/mem/nvdimm.h"
52 #include "hw/platform-bus.h"
53 #include "sysemu/numa.h"
54 #include "sysemu/reset.h"
55 #include "sysemu/tpm.h"
56 #include "kvm_arm.h"
57 #include "migration/vmstate.h"
58 #include "hw/acpi/ghes.h"
59 #include "hw/acpi/viot.h"
60
61 #define ARM_SPI_BASE 32
62
63 #define ACPI_BUILD_TABLE_SIZE 0x20000
64
65 static void acpi_dsdt_add_cpus(Aml *scope, VirtMachineState *vms)
66 {
67 MachineState *ms = MACHINE(vms);
68 uint16_t i;
69
70 for (i = 0; i < ms->smp.cpus; i++) {
71 Aml *dev = aml_device("C%.03X", i);
72 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0007")));
73 aml_append(dev, aml_name_decl("_UID", aml_int(i)));
74 aml_append(scope, dev);
75 }
76 }
77
78 static void acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap,
79 uint32_t uart_irq)
80 {
81 Aml *dev = aml_device("COM0");
82 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0011")));
83 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
84
85 Aml *crs = aml_resource_template();
86 aml_append(crs, aml_memory32_fixed(uart_memmap->base,
87 uart_memmap->size, AML_READ_WRITE));
88 aml_append(crs,
89 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
90 AML_EXCLUSIVE, &uart_irq, 1));
91 aml_append(dev, aml_name_decl("_CRS", crs));
92
93 aml_append(scope, dev);
94 }
95
96 static void acpi_dsdt_add_fw_cfg(Aml *scope, const MemMapEntry *fw_cfg_memmap)
97 {
98 Aml *dev = aml_device("FWCF");
99 aml_append(dev, aml_name_decl("_HID", aml_string("QEMU0002")));
100 /* device present, functioning, decoding, not shown in UI */
101 aml_append(dev, aml_name_decl("_STA", aml_int(0xB)));
102 aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
103
104 Aml *crs = aml_resource_template();
105 aml_append(crs, aml_memory32_fixed(fw_cfg_memmap->base,
106 fw_cfg_memmap->size, AML_READ_WRITE));
107 aml_append(dev, aml_name_decl("_CRS", crs));
108 aml_append(scope, dev);
109 }
110
111 static void acpi_dsdt_add_flash(Aml *scope, const MemMapEntry *flash_memmap)
112 {
113 Aml *dev, *crs;
114 hwaddr base = flash_memmap->base;
115 hwaddr size = flash_memmap->size / 2;
116
117 dev = aml_device("FLS0");
118 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
119 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
120
121 crs = aml_resource_template();
122 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
123 aml_append(dev, aml_name_decl("_CRS", crs));
124 aml_append(scope, dev);
125
126 dev = aml_device("FLS1");
127 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015")));
128 aml_append(dev, aml_name_decl("_UID", aml_int(1)));
129 crs = aml_resource_template();
130 aml_append(crs, aml_memory32_fixed(base + size, size, AML_READ_WRITE));
131 aml_append(dev, aml_name_decl("_CRS", crs));
132 aml_append(scope, dev);
133 }
134
135 static void acpi_dsdt_add_virtio(Aml *scope,
136 const MemMapEntry *virtio_mmio_memmap,
137 uint32_t mmio_irq, int num)
138 {
139 hwaddr base = virtio_mmio_memmap->base;
140 hwaddr size = virtio_mmio_memmap->size;
141 int i;
142
143 for (i = 0; i < num; i++) {
144 uint32_t irq = mmio_irq + i;
145 Aml *dev = aml_device("VR%02u", i);
146 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0005")));
147 aml_append(dev, aml_name_decl("_UID", aml_int(i)));
148 aml_append(dev, aml_name_decl("_CCA", aml_int(1)));
149
150 Aml *crs = aml_resource_template();
151 aml_append(crs, aml_memory32_fixed(base, size, AML_READ_WRITE));
152 aml_append(crs,
153 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
154 AML_EXCLUSIVE, &irq, 1));
155 aml_append(dev, aml_name_decl("_CRS", crs));
156 aml_append(scope, dev);
157 base += size;
158 }
159 }
160
161 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
162 uint32_t irq, VirtMachineState *vms)
163 {
164 int ecam_id = VIRT_ECAM_ID(vms->highmem_ecam);
165 struct GPEXConfig cfg = {
166 .mmio32 = memmap[VIRT_PCIE_MMIO],
167 .pio = memmap[VIRT_PCIE_PIO],
168 .ecam = memmap[ecam_id],
169 .irq = irq,
170 .bus = vms->bus,
171 };
172
173 if (vms->highmem_mmio) {
174 cfg.mmio64 = memmap[VIRT_HIGH_PCIE_MMIO];
175 }
176
177 acpi_dsdt_add_gpex(scope, &cfg);
178 }
179
180 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap,
181 uint32_t gpio_irq)
182 {
183 Aml *dev = aml_device("GPO0");
184 aml_append(dev, aml_name_decl("_HID", aml_string("ARMH0061")));
185 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
186
187 Aml *crs = aml_resource_template();
188 aml_append(crs, aml_memory32_fixed(gpio_memmap->base, gpio_memmap->size,
189 AML_READ_WRITE));
190 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH,
191 AML_EXCLUSIVE, &gpio_irq, 1));
192 aml_append(dev, aml_name_decl("_CRS", crs));
193
194 Aml *aei = aml_resource_template();
195 /* Pin 3 for power button */
196 const uint32_t pin_list[1] = {3};
197 aml_append(aei, aml_gpio_int(AML_CONSUMER, AML_EDGE, AML_ACTIVE_HIGH,
198 AML_EXCLUSIVE, AML_PULL_UP, 0, pin_list, 1,
199 "GPO0", NULL, 0));
200 aml_append(dev, aml_name_decl("_AEI", aei));
201
202 /* _E03 is handle for power button */
203 Aml *method = aml_method("_E03", 0, AML_NOTSERIALIZED);
204 aml_append(method, aml_notify(aml_name(ACPI_POWER_BUTTON_DEVICE),
205 aml_int(0x80)));
206 aml_append(dev, method);
207 aml_append(scope, dev);
208 }
209
210 #ifdef CONFIG_TPM
211 static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineState *vms)
212 {
213 PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev);
214 hwaddr pbus_base = vms->memmap[VIRT_PLATFORM_BUS].base;
215 SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find());
216 MemoryRegion *sbdev_mr;
217 hwaddr tpm_base;
218
219 if (!sbdev) {
220 return;
221 }
222
223 tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0);
224 assert(tpm_base != -1);
225
226 tpm_base += pbus_base;
227
228 sbdev_mr = sysbus_mmio_get_region(sbdev, 0);
229
230 Aml *dev = aml_device("TPM0");
231 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101")));
232 aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device")));
233 aml_append(dev, aml_name_decl("_UID", aml_int(0)));
234
235 Aml *crs = aml_resource_template();
236 aml_append(crs,
237 aml_memory32_fixed(tpm_base,
238 (uint32_t)memory_region_size(sbdev_mr),
239 AML_READ_WRITE));
240 aml_append(dev, aml_name_decl("_CRS", crs));
241 aml_append(scope, dev);
242 }
243 #endif
244
245 #define ID_MAPPING_ENTRY_SIZE 20
246 #define SMMU_V3_ENTRY_SIZE 68
247 #define ROOT_COMPLEX_ENTRY_SIZE 36
248 #define IORT_NODE_OFFSET 48
249
250 static void build_iort_id_mapping(GArray *table_data, uint32_t input_base,
251 uint32_t id_count, uint32_t out_ref)
252 {
253 /* Table 4 ID mapping format */
254 build_append_int_noprefix(table_data, input_base, 4); /* Input base */
255 build_append_int_noprefix(table_data, id_count, 4); /* Number of IDs */
256 build_append_int_noprefix(table_data, input_base, 4); /* Output base */
257 build_append_int_noprefix(table_data, out_ref, 4); /* Output Reference */
258 /* Flags */
259 build_append_int_noprefix(table_data, 0 /* Single mapping (disabled) */, 4);
260 }
261
262 struct AcpiIortIdMapping {
263 uint32_t input_base;
264 uint32_t id_count;
265 };
266 typedef struct AcpiIortIdMapping AcpiIortIdMapping;
267
268 /* Build the iort ID mapping to SMMUv3 for a given PCI host bridge */
269 static int
270 iort_host_bridges(Object *obj, void *opaque)
271 {
272 GArray *idmap_blob = opaque;
273
274 if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) {
275 PCIBus *bus = PCI_HOST_BRIDGE(obj)->bus;
276
277 if (bus && !pci_bus_bypass_iommu(bus)) {
278 int min_bus, max_bus;
279
280 pci_bus_range(bus, &min_bus, &max_bus);
281
282 AcpiIortIdMapping idmap = {
283 .input_base = min_bus << 8,
284 .id_count = (max_bus - min_bus + 1) << 8,
285 };
286 g_array_append_val(idmap_blob, idmap);
287 }
288 }
289
290 return 0;
291 }
292
293 static int iort_idmap_compare(gconstpointer a, gconstpointer b)
294 {
295 AcpiIortIdMapping *idmap_a = (AcpiIortIdMapping *)a;
296 AcpiIortIdMapping *idmap_b = (AcpiIortIdMapping *)b;
297
298 return idmap_a->input_base - idmap_b->input_base;
299 }
300
301 /*
302 * Input Output Remapping Table (IORT)
303 * Conforms to "IO Remapping Table System Software on ARM Platforms",
304 * Document number: ARM DEN 0049E.b, Feb 2021
305 */
306 static void
307 build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
308 {
309 int i, nb_nodes, rc_mapping_count;
310 const uint32_t iort_node_offset = IORT_NODE_OFFSET;
311 size_t node_size, smmu_offset = 0;
312 AcpiIortIdMapping *idmap;
313 uint32_t id = 0;
314 GArray *smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
315 GArray *its_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
316
317 AcpiTable table = { .sig = "IORT", .rev = 3, .oem_id = vms->oem_id,
318 .oem_table_id = vms->oem_table_id };
319 /* Table 2 The IORT */
320 acpi_table_begin(&table, table_data);
321
322 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
323 AcpiIortIdMapping next_range = {0};
324
325 object_child_foreach_recursive(object_get_root(),
326 iort_host_bridges, smmu_idmaps);
327
328 /* Sort the smmu idmap by input_base */
329 g_array_sort(smmu_idmaps, iort_idmap_compare);
330
331 /*
332 * Split the whole RIDs by mapping from RC to SMMU,
333 * build the ID mapping from RC to ITS directly.
334 */
335 for (i = 0; i < smmu_idmaps->len; i++) {
336 idmap = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i);
337
338 if (next_range.input_base < idmap->input_base) {
339 next_range.id_count = idmap->input_base - next_range.input_base;
340 g_array_append_val(its_idmaps, next_range);
341 }
342
343 next_range.input_base = idmap->input_base + idmap->id_count;
344 }
345
346 /* Append the last RC -> ITS ID mapping */
347 if (next_range.input_base < 0xFFFF) {
348 next_range.id_count = 0xFFFF - next_range.input_base;
349 g_array_append_val(its_idmaps, next_range);
350 }
351
352 nb_nodes = 3; /* RC, ITS, SMMUv3 */
353 rc_mapping_count = smmu_idmaps->len + its_idmaps->len;
354 } else {
355 nb_nodes = 2; /* RC, ITS */
356 rc_mapping_count = 1;
357 }
358 /* Number of IORT Nodes */
359 build_append_int_noprefix(table_data, nb_nodes, 4);
360
361 /* Offset to Array of IORT Nodes */
362 build_append_int_noprefix(table_data, IORT_NODE_OFFSET, 4);
363 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
364
365 /* Table 12 ITS Group Format */
366 build_append_int_noprefix(table_data, 0 /* ITS Group */, 1); /* Type */
367 node_size = 20 /* fixed header size */ + 4 /* 1 GIC ITS Identifier */;
368 build_append_int_noprefix(table_data, node_size, 2); /* Length */
369 build_append_int_noprefix(table_data, 1, 1); /* Revision */
370 build_append_int_noprefix(table_data, id++, 4); /* Identifier */
371 build_append_int_noprefix(table_data, 0, 4); /* Number of ID mappings */
372 build_append_int_noprefix(table_data, 0, 4); /* Reference to ID Array */
373 build_append_int_noprefix(table_data, 1, 4); /* Number of ITSs */
374 /* GIC ITS Identifier Array */
375 build_append_int_noprefix(table_data, 0 /* MADT translation_id */, 4);
376
377 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
378 int irq = vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE;
379
380 smmu_offset = table_data->len - table.table_offset;
381 /* Table 9 SMMUv3 Format */
382 build_append_int_noprefix(table_data, 4 /* SMMUv3 */, 1); /* Type */
383 node_size = SMMU_V3_ENTRY_SIZE + ID_MAPPING_ENTRY_SIZE;
384 build_append_int_noprefix(table_data, node_size, 2); /* Length */
385 build_append_int_noprefix(table_data, 4, 1); /* Revision */
386 build_append_int_noprefix(table_data, id++, 4); /* Identifier */
387 build_append_int_noprefix(table_data, 1, 4); /* Number of ID mappings */
388 /* Reference to ID Array */
389 build_append_int_noprefix(table_data, SMMU_V3_ENTRY_SIZE, 4);
390 /* Base address */
391 build_append_int_noprefix(table_data, vms->memmap[VIRT_SMMU].base, 8);
392 /* Flags */
393 build_append_int_noprefix(table_data, 1 /* COHACC Override */, 4);
394 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
395 build_append_int_noprefix(table_data, 0, 8); /* VATOS address */
396 /* Model */
397 build_append_int_noprefix(table_data, 0 /* Generic SMMU-v3 */, 4);
398 build_append_int_noprefix(table_data, irq, 4); /* Event */
399 build_append_int_noprefix(table_data, irq + 1, 4); /* PRI */
400 build_append_int_noprefix(table_data, irq + 3, 4); /* GERR */
401 build_append_int_noprefix(table_data, irq + 2, 4); /* Sync */
402 build_append_int_noprefix(table_data, 0, 4); /* Proximity domain */
403 /* DeviceID mapping index (ignored since interrupts are GSIV based) */
404 build_append_int_noprefix(table_data, 0, 4);
405
406 /* output IORT node is the ITS group node (the first node) */
407 build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET);
408 }
409
410 /* Table 17 Root Complex Node */
411 build_append_int_noprefix(table_data, 2 /* Root complex */, 1); /* Type */
412 node_size = ROOT_COMPLEX_ENTRY_SIZE +
413 ID_MAPPING_ENTRY_SIZE * rc_mapping_count;
414 build_append_int_noprefix(table_data, node_size, 2); /* Length */
415 build_append_int_noprefix(table_data, 3, 1); /* Revision */
416 build_append_int_noprefix(table_data, id++, 4); /* Identifier */
417 /* Number of ID mappings */
418 build_append_int_noprefix(table_data, rc_mapping_count, 4);
419 /* Reference to ID Array */
420 build_append_int_noprefix(table_data, ROOT_COMPLEX_ENTRY_SIZE, 4);
421
422 /* Table 14 Memory access properties */
423 /* CCA: Cache Coherent Attribute */
424 build_append_int_noprefix(table_data, 1 /* fully coherent */, 4);
425 build_append_int_noprefix(table_data, 0, 1); /* AH: Note Allocation Hints */
426 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
427 /* Table 15 Memory Access Flags */
428 build_append_int_noprefix(table_data, 0x3 /* CCA = CPM = DACS = 1 */, 1);
429
430 build_append_int_noprefix(table_data, 0, 4); /* ATS Attribute */
431 /* MCFG pci_segment */
432 build_append_int_noprefix(table_data, 0, 4); /* PCI Segment number */
433
434 /* Memory address size limit */
435 build_append_int_noprefix(table_data, 64, 1);
436
437 build_append_int_noprefix(table_data, 0, 3); /* Reserved */
438
439 /* Output Reference */
440 if (vms->iommu == VIRT_IOMMU_SMMUV3) {
441 AcpiIortIdMapping *range;
442
443 /* translated RIDs connect to SMMUv3 node: RC -> SMMUv3 -> ITS */
444 for (i = 0; i < smmu_idmaps->len; i++) {
445 range = &g_array_index(smmu_idmaps, AcpiIortIdMapping, i);
446 /* output IORT node is the smmuv3 node */
447 build_iort_id_mapping(table_data, range->input_base,
448 range->id_count, smmu_offset);
449 }
450
451 /* bypassed RIDs connect to ITS group node directly: RC -> ITS */
452 for (i = 0; i < its_idmaps->len; i++) {
453 range = &g_array_index(its_idmaps, AcpiIortIdMapping, i);
454 /* output IORT node is the ITS group node (the first node) */
455 build_iort_id_mapping(table_data, range->input_base,
456 range->id_count, iort_node_offset);
457 }
458 } else {
459 /* output IORT node is the ITS group node (the first node) */
460 build_iort_id_mapping(table_data, 0, 0xFFFF, IORT_NODE_OFFSET);
461 }
462
463 acpi_table_end(linker, &table);
464 g_array_free(smmu_idmaps, true);
465 g_array_free(its_idmaps, true);
466 }
467
468 /*
469 * Serial Port Console Redirection Table (SPCR)
470 * Rev: 1.07
471 */
472 static void
473 build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
474 {
475 AcpiTable table = { .sig = "SPCR", .rev = 2, .oem_id = vms->oem_id,
476 .oem_table_id = vms->oem_table_id };
477
478 acpi_table_begin(&table, table_data);
479
480 /* Interface Type */
481 build_append_int_noprefix(table_data, 3, 1); /* ARM PL011 UART */
482 build_append_int_noprefix(table_data, 0, 3); /* Reserved */
483 /* Base Address */
484 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 8, 0, 1,
485 vms->memmap[VIRT_UART].base);
486 /* Interrupt Type */
487 build_append_int_noprefix(table_data,
488 (1 << 3) /* Bit[3] ARMH GIC interrupt */, 1);
489 build_append_int_noprefix(table_data, 0, 1); /* IRQ */
490 /* Global System Interrupt */
491 build_append_int_noprefix(table_data,
492 vms->irqmap[VIRT_UART] + ARM_SPI_BASE, 4);
493 build_append_int_noprefix(table_data, 3 /* 9600 */, 1); /* Baud Rate */
494 build_append_int_noprefix(table_data, 0 /* No Parity */, 1); /* Parity */
495 /* Stop Bits */
496 build_append_int_noprefix(table_data, 1 /* 1 Stop bit */, 1);
497 /* Flow Control */
498 build_append_int_noprefix(table_data,
499 (1 << 1) /* RTS/CTS hardware flow control */, 1);
500 /* Terminal Type */
501 build_append_int_noprefix(table_data, 0 /* VT100 */, 1);
502 build_append_int_noprefix(table_data, 0, 1); /* Language */
503 /* PCI Device ID */
504 build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2);
505 /* PCI Vendor ID */
506 build_append_int_noprefix(table_data, 0xffff /* not a PCI device*/, 2);
507 build_append_int_noprefix(table_data, 0, 1); /* PCI Bus Number */
508 build_append_int_noprefix(table_data, 0, 1); /* PCI Device Number */
509 build_append_int_noprefix(table_data, 0, 1); /* PCI Function Number */
510 build_append_int_noprefix(table_data, 0, 4); /* PCI Flags */
511 build_append_int_noprefix(table_data, 0, 1); /* PCI Segment */
512 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
513
514 acpi_table_end(linker, &table);
515 }
516
517 /*
518 * ACPI spec, Revision 5.1
519 * 5.2.16 System Resource Affinity Table (SRAT)
520 */
521 static void
522 build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
523 {
524 int i;
525 uint64_t mem_base;
526 MachineClass *mc = MACHINE_GET_CLASS(vms);
527 MachineState *ms = MACHINE(vms);
528 const CPUArchIdList *cpu_list = mc->possible_cpu_arch_ids(ms);
529 AcpiTable table = { .sig = "SRAT", .rev = 3, .oem_id = vms->oem_id,
530 .oem_table_id = vms->oem_table_id };
531
532 acpi_table_begin(&table, table_data);
533 build_append_int_noprefix(table_data, 1, 4); /* Reserved */
534 build_append_int_noprefix(table_data, 0, 8); /* Reserved */
535
536 for (i = 0; i < cpu_list->len; ++i) {
537 uint32_t nodeid = cpu_list->cpus[i].props.node_id;
538 /*
539 * 5.2.16.4 GICC Affinity Structure
540 */
541 build_append_int_noprefix(table_data, 3, 1); /* Type */
542 build_append_int_noprefix(table_data, 18, 1); /* Length */
543 build_append_int_noprefix(table_data, nodeid, 4); /* Proximity Domain */
544 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
545 /* Flags, Table 5-76 */
546 build_append_int_noprefix(table_data, 1 /* Enabled */, 4);
547 build_append_int_noprefix(table_data, 0, 4); /* Clock Domain */
548 }
549
550 mem_base = vms->memmap[VIRT_MEM].base;
551 for (i = 0; i < ms->numa_state->num_nodes; ++i) {
552 if (ms->numa_state->nodes[i].node_mem > 0) {
553 build_srat_memory(table_data, mem_base,
554 ms->numa_state->nodes[i].node_mem, i,
555 MEM_AFFINITY_ENABLED);
556 mem_base += ms->numa_state->nodes[i].node_mem;
557 }
558 }
559
560 if (ms->nvdimms_state->is_enabled) {
561 nvdimm_build_srat(table_data);
562 }
563
564 if (ms->device_memory) {
565 build_srat_memory(table_data, ms->device_memory->base,
566 memory_region_size(&ms->device_memory->mr),
567 ms->numa_state->num_nodes - 1,
568 MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED);
569 }
570
571 acpi_table_end(linker, &table);
572 }
573
574 /*
575 * ACPI spec, Revision 5.1
576 * 5.2.24 Generic Timer Description Table (GTDT)
577 */
578 static void
579 build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
580 {
581 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
582 /*
583 * Table 5-117 Flag Definitions
584 * set only "Timer interrupt Mode" and assume "Timer Interrupt
585 * polarity" bit as '0: Interrupt is Active high'
586 */
587 uint32_t irqflags = vmc->claim_edge_triggered_timers ?
588 1 : /* Interrupt is Edge triggered */
589 0; /* Interrupt is Level triggered */
590 AcpiTable table = { .sig = "GTDT", .rev = 2, .oem_id = vms->oem_id,
591 .oem_table_id = vms->oem_table_id };
592
593 acpi_table_begin(&table, table_data);
594
595 /* CntControlBase Physical Address */
596 build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8);
597 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
598 /*
599 * FIXME: clarify comment:
600 * The interrupt values are the same with the device tree when adding 16
601 */
602 /* Secure EL1 timer GSIV */
603 build_append_int_noprefix(table_data, ARCH_TIMER_S_EL1_IRQ + 16, 4);
604 /* Secure EL1 timer Flags */
605 build_append_int_noprefix(table_data, irqflags, 4);
606 /* Non-Secure EL1 timer GSIV */
607 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL1_IRQ + 16, 4);
608 /* Non-Secure EL1 timer Flags */
609 build_append_int_noprefix(table_data, irqflags |
610 1UL << 2, /* Always-on Capability */
611 4);
612 /* Virtual timer GSIV */
613 build_append_int_noprefix(table_data, ARCH_TIMER_VIRT_IRQ + 16, 4);
614 /* Virtual Timer Flags */
615 build_append_int_noprefix(table_data, irqflags, 4);
616 /* Non-Secure EL2 timer GSIV */
617 build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_IRQ + 16, 4);
618 /* Non-Secure EL2 timer Flags */
619 build_append_int_noprefix(table_data, irqflags, 4);
620 /* CntReadBase Physical address */
621 build_append_int_noprefix(table_data, 0xFFFFFFFFFFFFFFFF, 8);
622 /* Platform Timer Count */
623 build_append_int_noprefix(table_data, 0, 4);
624 /* Platform Timer Offset */
625 build_append_int_noprefix(table_data, 0, 4);
626
627 acpi_table_end(linker, &table);
628 }
629
630 /* Debug Port Table 2 (DBG2) */
631 static void
632 build_dbg2(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
633 {
634 AcpiTable table = { .sig = "DBG2", .rev = 0, .oem_id = vms->oem_id,
635 .oem_table_id = vms->oem_table_id };
636 int dbg2devicelength;
637 const char name[] = "COM0";
638 const int namespace_length = sizeof(name);
639
640 acpi_table_begin(&table, table_data);
641
642 dbg2devicelength = 22 + /* BaseAddressRegister[] offset */
643 12 + /* BaseAddressRegister[] */
644 4 + /* AddressSize[] */
645 namespace_length /* NamespaceString[] */;
646
647 /* OffsetDbgDeviceInfo */
648 build_append_int_noprefix(table_data, 44, 4);
649 /* NumberDbgDeviceInfo */
650 build_append_int_noprefix(table_data, 1, 4);
651
652 /* Table 2. Debug Device Information structure format */
653 build_append_int_noprefix(table_data, 0, 1); /* Revision */
654 build_append_int_noprefix(table_data, dbg2devicelength, 2); /* Length */
655 /* NumberofGenericAddressRegisters */
656 build_append_int_noprefix(table_data, 1, 1);
657 /* NameSpaceStringLength */
658 build_append_int_noprefix(table_data, namespace_length, 2);
659 build_append_int_noprefix(table_data, 38, 2); /* NameSpaceStringOffset */
660 build_append_int_noprefix(table_data, 0, 2); /* OemDataLength */
661 /* OemDataOffset (0 means no OEM data) */
662 build_append_int_noprefix(table_data, 0, 2);
663
664 /* Port Type */
665 build_append_int_noprefix(table_data, 0x8000 /* Serial */, 2);
666 /* Port Subtype */
667 build_append_int_noprefix(table_data, 0x3 /* ARM PL011 UART */, 2);
668 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
669 /* BaseAddressRegisterOffset */
670 build_append_int_noprefix(table_data, 22, 2);
671 /* AddressSizeOffset */
672 build_append_int_noprefix(table_data, 34, 2);
673
674 /* BaseAddressRegister[] */
675 build_append_gas(table_data, AML_AS_SYSTEM_MEMORY, 8, 0, 1,
676 vms->memmap[VIRT_UART].base);
677
678 /* AddressSize[] */
679 build_append_int_noprefix(table_data,
680 vms->memmap[VIRT_UART].size, 4);
681
682 /* NamespaceString[] */
683 g_array_append_vals(table_data, name, namespace_length);
684
685 acpi_table_end(linker, &table);
686 };
687
688 /*
689 * ACPI spec, Revision 6.0 Errata A
690 * 5.2.12 Multiple APIC Description Table (MADT)
691 */
692 static void build_append_gicr(GArray *table_data, uint64_t base, uint32_t size)
693 {
694 build_append_int_noprefix(table_data, 0xE, 1); /* Type */
695 build_append_int_noprefix(table_data, 16, 1); /* Length */
696 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
697 /* Discovery Range Base Address */
698 build_append_int_noprefix(table_data, base, 8);
699 build_append_int_noprefix(table_data, size, 4); /* Discovery Range Length */
700 }
701
702 static void
703 build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
704 {
705 int i;
706 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
707 const MemMapEntry *memmap = vms->memmap;
708 AcpiTable table = { .sig = "APIC", .rev = 4, .oem_id = vms->oem_id,
709 .oem_table_id = vms->oem_table_id };
710
711 acpi_table_begin(&table, table_data);
712 /* Local Interrupt Controller Address */
713 build_append_int_noprefix(table_data, 0, 4);
714 build_append_int_noprefix(table_data, 0, 4); /* Flags */
715
716 /* 5.2.12.15 GIC Distributor Structure */
717 build_append_int_noprefix(table_data, 0xC, 1); /* Type */
718 build_append_int_noprefix(table_data, 24, 1); /* Length */
719 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
720 build_append_int_noprefix(table_data, 0, 4); /* GIC ID */
721 /* Physical Base Address */
722 build_append_int_noprefix(table_data, memmap[VIRT_GIC_DIST].base, 8);
723 build_append_int_noprefix(table_data, 0, 4); /* System Vector Base */
724 /* GIC version */
725 build_append_int_noprefix(table_data, vms->gic_version, 1);
726 build_append_int_noprefix(table_data, 0, 3); /* Reserved */
727
728 for (i = 0; i < MACHINE(vms)->smp.cpus; i++) {
729 ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(i));
730 uint64_t physical_base_address = 0, gich = 0, gicv = 0;
731 uint32_t vgic_interrupt = vms->virt ? PPI(ARCH_GIC_MAINT_IRQ) : 0;
732 uint32_t pmu_interrupt = arm_feature(&armcpu->env, ARM_FEATURE_PMU) ?
733 PPI(VIRTUAL_PMU_IRQ) : 0;
734
735 if (vms->gic_version == VIRT_GIC_VERSION_2) {
736 physical_base_address = memmap[VIRT_GIC_CPU].base;
737 gicv = memmap[VIRT_GIC_VCPU].base;
738 gich = memmap[VIRT_GIC_HYP].base;
739 }
740
741 /* 5.2.12.14 GIC Structure */
742 build_append_int_noprefix(table_data, 0xB, 1); /* Type */
743 build_append_int_noprefix(table_data, 80, 1); /* Length */
744 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
745 build_append_int_noprefix(table_data, i, 4); /* GIC ID */
746 build_append_int_noprefix(table_data, i, 4); /* ACPI Processor UID */
747 /* Flags */
748 build_append_int_noprefix(table_data, 1, 4); /* Enabled */
749 /* Parking Protocol Version */
750 build_append_int_noprefix(table_data, 0, 4);
751 /* Performance Interrupt GSIV */
752 build_append_int_noprefix(table_data, pmu_interrupt, 4);
753 build_append_int_noprefix(table_data, 0, 8); /* Parked Address */
754 /* Physical Base Address */
755 build_append_int_noprefix(table_data, physical_base_address, 8);
756 build_append_int_noprefix(table_data, gicv, 8); /* GICV */
757 build_append_int_noprefix(table_data, gich, 8); /* GICH */
758 /* VGIC Maintenance interrupt */
759 build_append_int_noprefix(table_data, vgic_interrupt, 4);
760 build_append_int_noprefix(table_data, 0, 8); /* GICR Base Address*/
761 /* MPIDR */
762 build_append_int_noprefix(table_data, armcpu->mp_affinity, 8);
763 /* Processor Power Efficiency Class */
764 build_append_int_noprefix(table_data, 0, 1);
765 /* Reserved */
766 build_append_int_noprefix(table_data, 0, 3);
767 }
768
769 if (vms->gic_version != VIRT_GIC_VERSION_2) {
770 build_append_gicr(table_data, memmap[VIRT_GIC_REDIST].base,
771 memmap[VIRT_GIC_REDIST].size);
772 if (virt_gicv3_redist_region_count(vms) == 2) {
773 build_append_gicr(table_data, memmap[VIRT_HIGH_GIC_REDIST2].base,
774 memmap[VIRT_HIGH_GIC_REDIST2].size);
775 }
776
777 if (its_class_name() && !vmc->no_its) {
778 /*
779 * ACPI spec, Revision 6.0 Errata A
780 * (original 6.0 definition has invalid Length)
781 * 5.2.12.18 GIC ITS Structure
782 */
783 build_append_int_noprefix(table_data, 0xF, 1); /* Type */
784 build_append_int_noprefix(table_data, 20, 1); /* Length */
785 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
786 build_append_int_noprefix(table_data, 0, 4); /* GIC ITS ID */
787 /* Physical Base Address */
788 build_append_int_noprefix(table_data, memmap[VIRT_GIC_ITS].base, 8);
789 build_append_int_noprefix(table_data, 0, 4); /* Reserved */
790 }
791 } else {
792 const uint16_t spi_base = vms->irqmap[VIRT_GIC_V2M] + ARM_SPI_BASE;
793
794 /* 5.2.12.16 GIC MSI Frame Structure */
795 build_append_int_noprefix(table_data, 0xD, 1); /* Type */
796 build_append_int_noprefix(table_data, 24, 1); /* Length */
797 build_append_int_noprefix(table_data, 0, 2); /* Reserved */
798 build_append_int_noprefix(table_data, 0, 4); /* GIC MSI Frame ID */
799 /* Physical Base Address */
800 build_append_int_noprefix(table_data, memmap[VIRT_GIC_V2M].base, 8);
801 build_append_int_noprefix(table_data, 1, 4); /* Flags */
802 /* SPI Count */
803 build_append_int_noprefix(table_data, NUM_GICV2M_SPIS, 2);
804 build_append_int_noprefix(table_data, spi_base, 2); /* SPI Base */
805 }
806 acpi_table_end(linker, &table);
807 }
808
809 /* FADT */
810 static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker,
811 VirtMachineState *vms, unsigned dsdt_tbl_offset)
812 {
813 /* ACPI v6.0 */
814 AcpiFadtData fadt = {
815 .rev = 6,
816 .minor_ver = 0,
817 .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI,
818 .xdsdt_tbl_offset = &dsdt_tbl_offset,
819 };
820
821 switch (vms->psci_conduit) {
822 case QEMU_PSCI_CONDUIT_DISABLED:
823 fadt.arm_boot_arch = 0;
824 break;
825 case QEMU_PSCI_CONDUIT_HVC:
826 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT |
827 ACPI_FADT_ARM_PSCI_USE_HVC;
828 break;
829 case QEMU_PSCI_CONDUIT_SMC:
830 fadt.arm_boot_arch = ACPI_FADT_ARM_PSCI_COMPLIANT;
831 break;
832 default:
833 g_assert_not_reached();
834 }
835
836 build_fadt(table_data, linker, &fadt, vms->oem_id, vms->oem_table_id);
837 }
838
839 /* DSDT */
840 static void
841 build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
842 {
843 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
844 Aml *scope, *dsdt;
845 MachineState *ms = MACHINE(vms);
846 const MemMapEntry *memmap = vms->memmap;
847 const int *irqmap = vms->irqmap;
848 AcpiTable table = { .sig = "DSDT", .rev = 2, .oem_id = vms->oem_id,
849 .oem_table_id = vms->oem_table_id };
850
851 acpi_table_begin(&table, table_data);
852 dsdt = init_aml_allocator();
853
854 /* When booting the VM with UEFI, UEFI takes ownership of the RTC hardware.
855 * While UEFI can use libfdt to disable the RTC device node in the DTB that
856 * it passes to the OS, it cannot modify AML. Therefore, we won't generate
857 * the RTC ACPI device at all when using UEFI.
858 */
859 scope = aml_scope("\\_SB");
860 acpi_dsdt_add_cpus(scope, vms);
861 acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
862 (irqmap[VIRT_UART] + ARM_SPI_BASE));
863 if (vmc->acpi_expose_flash) {
864 acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
865 }
866 acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
867 acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
868 (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
869 acpi_dsdt_add_pci(scope, memmap, irqmap[VIRT_PCIE] + ARM_SPI_BASE, vms);
870 if (vms->acpi_dev) {
871 build_ged_aml(scope, "\\_SB."GED_DEVICE,
872 HOTPLUG_HANDLER(vms->acpi_dev),
873 irqmap[VIRT_ACPI_GED] + ARM_SPI_BASE, AML_SYSTEM_MEMORY,
874 memmap[VIRT_ACPI_GED].base);
875 } else {
876 acpi_dsdt_add_gpio(scope, &memmap[VIRT_GPIO],
877 (irqmap[VIRT_GPIO] + ARM_SPI_BASE));
878 }
879
880 if (vms->acpi_dev) {
881 uint32_t event = object_property_get_uint(OBJECT(vms->acpi_dev),
882 "ged-event", &error_abort);
883
884 if (event & ACPI_GED_MEM_HOTPLUG_EVT) {
885 build_memory_hotplug_aml(scope, ms->ram_slots, "\\_SB", NULL,
886 AML_SYSTEM_MEMORY,
887 memmap[VIRT_PCDIMM_ACPI].base);
888 }
889 }
890
891 acpi_dsdt_add_power_button(scope);
892 #ifdef CONFIG_TPM
893 acpi_dsdt_add_tpm(scope, vms);
894 #endif
895
896 aml_append(dsdt, scope);
897
898 /* copy AML table into ACPI tables blob */
899 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len);
900
901 acpi_table_end(linker, &table);
902 free_aml_allocator();
903 }
904
905 typedef
906 struct AcpiBuildState {
907 /* Copy of table in RAM (for patching). */
908 MemoryRegion *table_mr;
909 MemoryRegion *rsdp_mr;
910 MemoryRegion *linker_mr;
911 /* Is table patched? */
912 bool patched;
913 } AcpiBuildState;
914
915 static void acpi_align_size(GArray *blob, unsigned align)
916 {
917 /*
918 * Align size to multiple of given size. This reduces the chance
919 * we need to change size in the future (breaking cross version migration).
920 */
921 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
922 }
923
924 static
925 void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables)
926 {
927 VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
928 GArray *table_offsets;
929 unsigned dsdt, xsdt;
930 GArray *tables_blob = tables->table_data;
931 MachineState *ms = MACHINE(vms);
932
933 table_offsets = g_array_new(false, true /* clear */,
934 sizeof(uint32_t));
935
936 bios_linker_loader_alloc(tables->linker,
937 ACPI_BUILD_TABLE_FILE, tables_blob,
938 64, false /* high memory */);
939
940 /* DSDT is pointed to by FADT */
941 dsdt = tables_blob->len;
942 build_dsdt(tables_blob, tables->linker, vms);
943
944 /* FADT MADT PPTT GTDT MCFG SPCR DBG2 pointed to by RSDT */
945 acpi_add_table(table_offsets, tables_blob);
946 build_fadt_rev6(tables_blob, tables->linker, vms, dsdt);
947
948 acpi_add_table(table_offsets, tables_blob);
949 build_madt(tables_blob, tables->linker, vms);
950
951 if (!vmc->no_cpu_topology) {
952 acpi_add_table(table_offsets, tables_blob);
953 build_pptt(tables_blob, tables->linker, ms,
954 vms->oem_id, vms->oem_table_id);
955 }
956
957 acpi_add_table(table_offsets, tables_blob);
958 build_gtdt(tables_blob, tables->linker, vms);
959
960 acpi_add_table(table_offsets, tables_blob);
961 {
962 AcpiMcfgInfo mcfg = {
963 .base = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base,
964 .size = vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size,
965 };
966 build_mcfg(tables_blob, tables->linker, &mcfg, vms->oem_id,
967 vms->oem_table_id);
968 }
969
970 acpi_add_table(table_offsets, tables_blob);
971 build_spcr(tables_blob, tables->linker, vms);
972
973 acpi_add_table(table_offsets, tables_blob);
974 build_dbg2(tables_blob, tables->linker, vms);
975
976 if (vms->ras) {
977 build_ghes_error_table(tables->hardware_errors, tables->linker);
978 acpi_add_table(table_offsets, tables_blob);
979 acpi_build_hest(tables_blob, tables->linker, vms->oem_id,
980 vms->oem_table_id);
981 }
982
983 if (ms->numa_state->num_nodes > 0) {
984 acpi_add_table(table_offsets, tables_blob);
985 build_srat(tables_blob, tables->linker, vms);
986 if (ms->numa_state->have_numa_distance) {
987 acpi_add_table(table_offsets, tables_blob);
988 build_slit(tables_blob, tables->linker, ms, vms->oem_id,
989 vms->oem_table_id);
990 }
991
992 if (ms->numa_state->hmat_enabled) {
993 acpi_add_table(table_offsets, tables_blob);
994 build_hmat(tables_blob, tables->linker, ms->numa_state,
995 vms->oem_id, vms->oem_table_id);
996 }
997 }
998
999 if (ms->nvdimms_state->is_enabled) {
1000 nvdimm_build_acpi(table_offsets, tables_blob, tables->linker,
1001 ms->nvdimms_state, ms->ram_slots, vms->oem_id,
1002 vms->oem_table_id);
1003 }
1004
1005 if (its_class_name() && !vmc->no_its) {
1006 acpi_add_table(table_offsets, tables_blob);
1007 build_iort(tables_blob, tables->linker, vms);
1008 }
1009
1010 #ifdef CONFIG_TPM
1011 if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) {
1012 acpi_add_table(table_offsets, tables_blob);
1013 build_tpm2(tables_blob, tables->linker, tables->tcpalog, vms->oem_id,
1014 vms->oem_table_id);
1015 }
1016 #endif
1017
1018 if (vms->iommu == VIRT_IOMMU_VIRTIO) {
1019 acpi_add_table(table_offsets, tables_blob);
1020 build_viot(ms, tables_blob, tables->linker, vms->virtio_iommu_bdf,
1021 vms->oem_id, vms->oem_table_id);
1022 }
1023
1024 /* XSDT is pointed to by RSDP */
1025 xsdt = tables_blob->len;
1026 build_xsdt(tables_blob, tables->linker, table_offsets, vms->oem_id,
1027 vms->oem_table_id);
1028
1029 /* RSDP is in FSEG memory, so allocate it separately */
1030 {
1031 AcpiRsdpData rsdp_data = {
1032 .revision = 2,
1033 .oem_id = vms->oem_id,
1034 .xsdt_tbl_offset = &xsdt,
1035 .rsdt_tbl_offset = NULL,
1036 };
1037 build_rsdp(tables->rsdp, tables->linker, &rsdp_data);
1038 }
1039
1040 /*
1041 * The align size is 128, warn if 64k is not enough therefore
1042 * the align size could be resized.
1043 */
1044 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) {
1045 warn_report("ACPI table size %u exceeds %d bytes,"
1046 " migration may not work",
1047 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2);
1048 error_printf("Try removing CPUs, NUMA nodes, memory slots"
1049 " or PCI bridges.");
1050 }
1051 acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE);
1052
1053
1054 /* Cleanup memory that's no longer used. */
1055 g_array_free(table_offsets, true);
1056 }
1057
1058 static void acpi_ram_update(MemoryRegion *mr, GArray *data)
1059 {
1060 uint32_t size = acpi_data_len(data);
1061
1062 /* Make sure RAM size is correct - in case it got changed
1063 * e.g. by migration */
1064 memory_region_ram_resize(mr, size, &error_abort);
1065
1066 memcpy(memory_region_get_ram_ptr(mr), data->data, size);
1067 memory_region_set_dirty(mr, 0, size);
1068 }
1069
1070 static void virt_acpi_build_update(void *build_opaque)
1071 {
1072 AcpiBuildState *build_state = build_opaque;
1073 AcpiBuildTables tables;
1074
1075 /* No state to update or already patched? Nothing to do. */
1076 if (!build_state || build_state->patched) {
1077 return;
1078 }
1079 build_state->patched = true;
1080
1081 acpi_build_tables_init(&tables);
1082
1083 virt_acpi_build(VIRT_MACHINE(qdev_get_machine()), &tables);
1084
1085 acpi_ram_update(build_state->table_mr, tables.table_data);
1086 acpi_ram_update(build_state->rsdp_mr, tables.rsdp);
1087 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob);
1088
1089 acpi_build_tables_cleanup(&tables, true);
1090 }
1091
1092 static void virt_acpi_build_reset(void *build_opaque)
1093 {
1094 AcpiBuildState *build_state = build_opaque;
1095 build_state->patched = false;
1096 }
1097
1098 static const VMStateDescription vmstate_virt_acpi_build = {
1099 .name = "virt_acpi_build",
1100 .version_id = 1,
1101 .minimum_version_id = 1,
1102 .fields = (VMStateField[]) {
1103 VMSTATE_BOOL(patched, AcpiBuildState),
1104 VMSTATE_END_OF_LIST()
1105 },
1106 };
1107
1108 void virt_acpi_setup(VirtMachineState *vms)
1109 {
1110 AcpiBuildTables tables;
1111 AcpiBuildState *build_state;
1112 AcpiGedState *acpi_ged_state;
1113
1114 if (!vms->fw_cfg) {
1115 trace_virt_acpi_setup();
1116 return;
1117 }
1118
1119 if (!virt_is_acpi_enabled(vms)) {
1120 trace_virt_acpi_setup();
1121 return;
1122 }
1123
1124 build_state = g_malloc0(sizeof *build_state);
1125
1126 acpi_build_tables_init(&tables);
1127 virt_acpi_build(vms, &tables);
1128
1129 /* Now expose it all to Guest */
1130 build_state->table_mr = acpi_add_rom_blob(virt_acpi_build_update,
1131 build_state, tables.table_data,
1132 ACPI_BUILD_TABLE_FILE);
1133 assert(build_state->table_mr != NULL);
1134
1135 build_state->linker_mr = acpi_add_rom_blob(virt_acpi_build_update,
1136 build_state,
1137 tables.linker->cmd_blob,
1138 ACPI_BUILD_LOADER_FILE);
1139
1140 fw_cfg_add_file(vms->fw_cfg, ACPI_BUILD_TPMLOG_FILE, tables.tcpalog->data,
1141 acpi_data_len(tables.tcpalog));
1142
1143 if (vms->ras) {
1144 assert(vms->acpi_dev);
1145 acpi_ged_state = ACPI_GED(vms->acpi_dev);
1146 acpi_ghes_add_fw_cfg(&acpi_ged_state->ghes_state,
1147 vms->fw_cfg, tables.hardware_errors);
1148 }
1149
1150 build_state->rsdp_mr = acpi_add_rom_blob(virt_acpi_build_update,
1151 build_state, tables.rsdp,
1152 ACPI_BUILD_RSDP_FILE);
1153
1154 qemu_register_reset(virt_acpi_build_reset, build_state);
1155 virt_acpi_build_reset(build_state);
1156 vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state);
1157
1158 /* Cleanup tables but don't free the memory: we track it
1159 * in build_state.
1160 */
1161 acpi_build_tables_cleanup(&tables, false);
1162 }
armbru's QEMU hackery