hw/arm/strongarm.c

   1 /*
   2  * StrongARM SA-1100/SA-1110 emulation
   3  *
   4  * Copyright (C) 2011 Dmitry Eremin-Solenikov
   5  *
   6  * Largely based on StrongARM emulation:
   7  * Copyright (c) 2006 Openedhand Ltd.
   8  * Written by Andrzej Zaborowski <balrog@zabor.org>
   9  *
  10  * UART code based on QEMU 16550A UART emulation
  11  * Copyright (c) 2003-2004 Fabrice Bellard
  12  * Copyright (c) 2008 Citrix Systems, Inc.
  13  *
  14  *  This program is free software; you can redistribute it and/or modify
  15  *  it under the terms of the GNU General Public License version 2 as
  16  *  published by the Free Software Foundation.
  17  *
  18  *  This program is distributed in the hope that it will be useful,
  19  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *  GNU General Public License for more details.
  22  *
  23  *  You should have received a copy of the GNU General Public License along
  24  *  with this program; if not, see <http://www.gnu.org/licenses/>.
  25  *
  26  *  Contributions after 2012-01-13 are licensed under the terms of the
  27  *  GNU GPL, version 2 or (at your option) any later version.
  28  */
  29
  30 #include "qemu/osdep.h"
  31 #include "qemu-common.h"
  32 #include "cpu.h"
  33 #include "hw/boards.h"
  34 #include "hw/irq.h"
  35 #include "hw/qdev-properties.h"
  36 #include "hw/sysbus.h"
  37 #include "migration/vmstate.h"
  38 #include "strongarm.h"
  39 #include "qemu/error-report.h"
  40 #include "hw/arm/boot.h"
  41 #include "chardev/char-fe.h"
  42 #include "chardev/char-serial.h"
  43 #include "sysemu/sysemu.h"
  44 #include "hw/ssi/ssi.h"
  45 #include "qapi/error.h"
  46 #include "qemu/cutils.h"
  47 #include "qemu/log.h"
  48
  49 //#define DEBUG
  50
  51 /*
  52  TODO
  53  - Implement cp15, c14 ?
  54  - Implement cp15, c15 !!! (idle used in L)
  55  - Implement idle mode handling/DIM
  56  - Implement sleep mode/Wake sources
  57  - Implement reset control
  58  - Implement memory control regs
  59  - PCMCIA handling
  60  - Maybe support MBGNT/MBREQ
  61  - DMA channels
  62  - GPCLK
  63  - IrDA
  64  - MCP
  65  - Enhance UART with modem signals
  66  */
  67
  68 #ifdef DEBUG
  69 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
  70 #else
  71 # define DPRINTF(format, ...) do { } while (0)
  72 #endif
  73
  74 static struct {
  75     hwaddr io_base;
  76     int irq;
  77 } sa_serial[] = {
  78     { 0x80010000, SA_PIC_UART1 },
  79     { 0x80030000, SA_PIC_UART2 },
  80     { 0x80050000, SA_PIC_UART3 },
  81     { 0, 0 }
  82 };
  83
  84 /* Interrupt Controller */
  85
  86 #define TYPE_STRONGARM_PIC "strongarm_pic"
  87 #define STRONGARM_PIC(obj) \
  88     OBJECT_CHECK(StrongARMPICState, (obj), TYPE_STRONGARM_PIC)
  89
  90 typedef struct StrongARMPICState {
  91     SysBusDevice parent_obj;
  92
  93     MemoryRegion iomem;
  94     qemu_irq    irq;
  95     qemu_irq    fiq;
  96
  97     uint32_t pending;
  98     uint32_t enabled;
  99     uint32_t is_fiq;
 100     uint32_t int_idle;
 101 } StrongARMPICState;
 102
 103 #define ICIP    0x00
 104 #define ICMR    0x04
 105 #define ICLR    0x08
 106 #define ICFP    0x10
 107 #define ICPR    0x20
 108 #define ICCR    0x0c
 109
 110 #define SA_PIC_SRCS     32
 111
 112
 113 static void strongarm_pic_update(void *opaque)
 114 {
 115     StrongARMPICState *s = opaque;
 116
 117     /* FIXME: reflect DIM */
 118     qemu_set_irq(s->fiq, s->pending & s->enabled &  s->is_fiq);
 119     qemu_set_irq(s->irq, s->pending & s->enabled & ~s->is_fiq);
 120 }
 121
 122 static void strongarm_pic_set_irq(void *opaque, int irq, int level)
 123 {
 124     StrongARMPICState *s = opaque;
 125
 126     if (level) {
 127         s->pending |= 1 << irq;
 128     } else {
 129         s->pending &= ~(1 << irq);
 130     }
 131
 132     strongarm_pic_update(s);
 133 }
 134
 135 static uint64_t strongarm_pic_mem_read(void *opaque, hwaddr offset,
 136                                        unsigned size)
 137 {
 138     StrongARMPICState *s = opaque;
 139
 140     switch (offset) {
 141     case ICIP:
 142         return s->pending & ~s->is_fiq & s->enabled;
 143     case ICMR:
 144         return s->enabled;
 145     case ICLR:
 146         return s->is_fiq;
 147     case ICCR:
 148         return s->int_idle == 0;
 149     case ICFP:
 150         return s->pending & s->is_fiq & s->enabled;
 151     case ICPR:
 152         return s->pending;
 153     default:
 154         printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
 155                         __func__, offset);
 156         return 0;
 157     }
 158 }
 159
 160 static void strongarm_pic_mem_write(void *opaque, hwaddr offset,
 161                                     uint64_t value, unsigned size)
 162 {
 163     StrongARMPICState *s = opaque;
 164
 165     switch (offset) {
 166     case ICMR:
 167         s->enabled = value;
 168         break;
 169     case ICLR:
 170         s->is_fiq = value;
 171         break;
 172     case ICCR:
 173         s->int_idle = (value & 1) ? 0 : ~0;
 174         break;
 175     default:
 176         printf("%s: Bad register offset 0x" TARGET_FMT_plx "\n",
 177                         __func__, offset);
 178         break;
 179     }
 180     strongarm_pic_update(s);
 181 }
 182
 183 static const MemoryRegionOps strongarm_pic_ops = {
 184     .read = strongarm_pic_mem_read,
 185     .write = strongarm_pic_mem_write,
 186     .endianness = DEVICE_NATIVE_ENDIAN,
 187 };
 188
 189 static void strongarm_pic_initfn(Object *obj)
 190 {
 191     DeviceState *dev = DEVICE(obj);
 192     StrongARMPICState *s = STRONGARM_PIC(obj);
 193     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 194
 195     qdev_init_gpio_in(dev, strongarm_pic_set_irq, SA_PIC_SRCS);
 196     memory_region_init_io(&s->iomem, obj, &strongarm_pic_ops, s,
 197                           "pic", 0x1000);
 198     sysbus_init_mmio(sbd, &s->iomem);
 199     sysbus_init_irq(sbd, &s->irq);
 200     sysbus_init_irq(sbd, &s->fiq);
 201 }
 202
 203 static int strongarm_pic_post_load(void *opaque, int version_id)
 204 {
 205     strongarm_pic_update(opaque);
 206     return 0;
 207 }
 208
 209 static VMStateDescription vmstate_strongarm_pic_regs = {
 210     .name = "strongarm_pic",
 211     .version_id = 0,
 212     .minimum_version_id = 0,
 213     .post_load = strongarm_pic_post_load,
 214     .fields = (VMStateField[]) {
 215         VMSTATE_UINT32(pending, StrongARMPICState),
 216         VMSTATE_UINT32(enabled, StrongARMPICState),
 217         VMSTATE_UINT32(is_fiq, StrongARMPICState),
 218         VMSTATE_UINT32(int_idle, StrongARMPICState),
 219         VMSTATE_END_OF_LIST(),
 220     },
 221 };
 222
 223 static void strongarm_pic_class_init(ObjectClass *klass, void *data)
 224 {
 225     DeviceClass *dc = DEVICE_CLASS(klass);
 226
 227     dc->desc = "StrongARM PIC";
 228     dc->vmsd = &vmstate_strongarm_pic_regs;
 229 }
 230
 231 static const TypeInfo strongarm_pic_info = {
 232     .name          = TYPE_STRONGARM_PIC,
 233     .parent        = TYPE_SYS_BUS_DEVICE,
 234     .instance_size = sizeof(StrongARMPICState),
 235     .instance_init = strongarm_pic_initfn,
 236     .class_init    = strongarm_pic_class_init,
 237 };
 238
 239 /* Real-Time Clock */
 240 #define RTAR 0x00 /* RTC Alarm register */
 241 #define RCNR 0x04 /* RTC Counter register */
 242 #define RTTR 0x08 /* RTC Timer Trim register */
 243 #define RTSR 0x10 /* RTC Status register */
 244
 245 #define RTSR_AL (1 << 0) /* RTC Alarm detected */
 246 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */
 247 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */
 248 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */
 249
 250 /* 16 LSB of RTTR are clockdiv for internal trim logic,
 251  * trim delete isn't emulated, so
 252  * f = 32 768 / (RTTR_trim + 1) */
 253
 254 #define TYPE_STRONGARM_RTC "strongarm-rtc"
 255 #define STRONGARM_RTC(obj) \
 256     OBJECT_CHECK(StrongARMRTCState, (obj), TYPE_STRONGARM_RTC)
 257
 258 typedef struct StrongARMRTCState {
 259     SysBusDevice parent_obj;
 260
 261     MemoryRegion iomem;
 262     uint32_t rttr;
 263     uint32_t rtsr;
 264     uint32_t rtar;
 265     uint32_t last_rcnr;
 266     int64_t last_hz;
 267     QEMUTimer *rtc_alarm;
 268     QEMUTimer *rtc_hz;
 269     qemu_irq rtc_irq;
 270     qemu_irq rtc_hz_irq;
 271 } StrongARMRTCState;
 272
 273 static inline void strongarm_rtc_int_update(StrongARMRTCState *s)
 274 {
 275     qemu_set_irq(s->rtc_irq, s->rtsr & RTSR_AL);
 276     qemu_set_irq(s->rtc_hz_irq, s->rtsr & RTSR_HZ);
 277 }
 278
 279 static void strongarm_rtc_hzupdate(StrongARMRTCState *s)
 280 {
 281     int64_t rt = qemu_clock_get_ms(rtc_clock);
 282     s->last_rcnr += ((rt - s->last_hz) << 15) /
 283             (1000 * ((s->rttr & 0xffff) + 1));
 284     s->last_hz = rt;
 285 }
 286
 287 static inline void strongarm_rtc_timer_update(StrongARMRTCState *s)
 288 {
 289     if ((s->rtsr & RTSR_HZE) && !(s->rtsr & RTSR_HZ)) {
 290         timer_mod(s->rtc_hz, s->last_hz + 1000);
 291     } else {
 292         timer_del(s->rtc_hz);
 293     }
 294
 295     if ((s->rtsr & RTSR_ALE) && !(s->rtsr & RTSR_AL)) {
 296         timer_mod(s->rtc_alarm, s->last_hz +
 297                 (((s->rtar - s->last_rcnr) * 1000 *
 298                   ((s->rttr & 0xffff) + 1)) >> 15));
 299     } else {
 300         timer_del(s->rtc_alarm);
 301     }
 302 }
 303
 304 static inline void strongarm_rtc_alarm_tick(void *opaque)
 305 {
 306     StrongARMRTCState *s = opaque;
 307     s->rtsr |= RTSR_AL;
 308     strongarm_rtc_timer_update(s);
 309     strongarm_rtc_int_update(s);
 310 }
 311
 312 static inline void strongarm_rtc_hz_tick(void *opaque)
 313 {
 314     StrongARMRTCState *s = opaque;
 315     s->rtsr |= RTSR_HZ;
 316     strongarm_rtc_timer_update(s);
 317     strongarm_rtc_int_update(s);
 318 }
 319
 320 static uint64_t strongarm_rtc_read(void *opaque, hwaddr addr,
 321                                    unsigned size)
 322 {
 323     StrongARMRTCState *s = opaque;
 324
 325     switch (addr) {
 326     case RTTR:
 327         return s->rttr;
 328     case RTSR:
 329         return s->rtsr;
 330     case RTAR:
 331         return s->rtar;
 332     case RCNR:
 333         return s->last_rcnr +
 334                 ((qemu_clock_get_ms(rtc_clock) - s->last_hz) << 15) /
 335                 (1000 * ((s->rttr & 0xffff) + 1));
 336     default:
 337         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
 338         return 0;
 339     }
 340 }
 341
 342 static void strongarm_rtc_write(void *opaque, hwaddr addr,
 343                                 uint64_t value, unsigned size)
 344 {
 345     StrongARMRTCState *s = opaque;
 346     uint32_t old_rtsr;
 347
 348     switch (addr) {
 349     case RTTR:
 350         strongarm_rtc_hzupdate(s);
 351         s->rttr = value;
 352         strongarm_rtc_timer_update(s);
 353         break;
 354
 355     case RTSR:
 356         old_rtsr = s->rtsr;
 357         s->rtsr = (value & (RTSR_ALE | RTSR_HZE)) |
 358                   (s->rtsr & ~(value & (RTSR_AL | RTSR_HZ)));
 359
 360         if (s->rtsr != old_rtsr) {
 361             strongarm_rtc_timer_update(s);
 362         }
 363
 364         strongarm_rtc_int_update(s);
 365         break;
 366
 367     case RTAR:
 368         s->rtar = value;
 369         strongarm_rtc_timer_update(s);
 370         break;
 371
 372     case RCNR:
 373         strongarm_rtc_hzupdate(s);
 374         s->last_rcnr = value;
 375         strongarm_rtc_timer_update(s);
 376         break;
 377
 378     default:
 379         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
 380     }
 381 }
 382
 383 static const MemoryRegionOps strongarm_rtc_ops = {
 384     .read = strongarm_rtc_read,
 385     .write = strongarm_rtc_write,
 386     .endianness = DEVICE_NATIVE_ENDIAN,
 387 };
 388
 389 static void strongarm_rtc_init(Object *obj)
 390 {
 391     StrongARMRTCState *s = STRONGARM_RTC(obj);
 392     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 393     struct tm tm;
 394
 395     s->rttr = 0x0;
 396     s->rtsr = 0;
 397
 398     qemu_get_timedate(&tm, 0);
 399
 400     s->last_rcnr = (uint32_t) mktimegm(&tm);
 401     s->last_hz = qemu_clock_get_ms(rtc_clock);
 402
 403     sysbus_init_irq(dev, &s->rtc_irq);
 404     sysbus_init_irq(dev, &s->rtc_hz_irq);
 405
 406     memory_region_init_io(&s->iomem, obj, &strongarm_rtc_ops, s,
 407                           "rtc", 0x10000);
 408     sysbus_init_mmio(dev, &s->iomem);
 409 }
 410
 411 static void strongarm_rtc_realize(DeviceState *dev, Error **errp)
 412 {
 413     StrongARMRTCState *s = STRONGARM_RTC(dev);
 414     s->rtc_alarm = timer_new_ms(rtc_clock, strongarm_rtc_alarm_tick, s);
 415     s->rtc_hz = timer_new_ms(rtc_clock, strongarm_rtc_hz_tick, s);
 416 }
 417
 418 static int strongarm_rtc_pre_save(void *opaque)
 419 {
 420     StrongARMRTCState *s = opaque;
 421
 422     strongarm_rtc_hzupdate(s);
 423
 424     return 0;
 425 }
 426
 427 static int strongarm_rtc_post_load(void *opaque, int version_id)
 428 {
 429     StrongARMRTCState *s = opaque;
 430
 431     strongarm_rtc_timer_update(s);
 432     strongarm_rtc_int_update(s);
 433
 434     return 0;
 435 }
 436
 437 static const VMStateDescription vmstate_strongarm_rtc_regs = {
 438     .name = "strongarm-rtc",
 439     .version_id = 0,
 440     .minimum_version_id = 0,
 441     .pre_save = strongarm_rtc_pre_save,
 442     .post_load = strongarm_rtc_post_load,
 443     .fields = (VMStateField[]) {
 444         VMSTATE_UINT32(rttr, StrongARMRTCState),
 445         VMSTATE_UINT32(rtsr, StrongARMRTCState),
 446         VMSTATE_UINT32(rtar, StrongARMRTCState),
 447         VMSTATE_UINT32(last_rcnr, StrongARMRTCState),
 448         VMSTATE_INT64(last_hz, StrongARMRTCState),
 449         VMSTATE_END_OF_LIST(),
 450     },
 451 };
 452
 453 static void strongarm_rtc_sysbus_class_init(ObjectClass *klass, void *data)
 454 {
 455     DeviceClass *dc = DEVICE_CLASS(klass);
 456
 457     dc->desc = "StrongARM RTC Controller";
 458     dc->vmsd = &vmstate_strongarm_rtc_regs;
 459     dc->realize = strongarm_rtc_realize;
 460 }
 461
 462 static const TypeInfo strongarm_rtc_sysbus_info = {
 463     .name          = TYPE_STRONGARM_RTC,
 464     .parent        = TYPE_SYS_BUS_DEVICE,
 465     .instance_size = sizeof(StrongARMRTCState),
 466     .instance_init = strongarm_rtc_init,
 467     .class_init    = strongarm_rtc_sysbus_class_init,
 468 };
 469
 470 /* GPIO */
 471 #define GPLR 0x00
 472 #define GPDR 0x04
 473 #define GPSR 0x08
 474 #define GPCR 0x0c
 475 #define GRER 0x10
 476 #define GFER 0x14
 477 #define GEDR 0x18
 478 #define GAFR 0x1c
 479
 480 #define TYPE_STRONGARM_GPIO "strongarm-gpio"
 481 #define STRONGARM_GPIO(obj) \
 482     OBJECT_CHECK(StrongARMGPIOInfo, (obj), TYPE_STRONGARM_GPIO)
 483
 484 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo;
 485 struct StrongARMGPIOInfo {
 486     SysBusDevice busdev;
 487     MemoryRegion iomem;
 488     qemu_irq handler[28];
 489     qemu_irq irqs[11];
 490     qemu_irq irqX;
 491
 492     uint32_t ilevel;
 493     uint32_t olevel;
 494     uint32_t dir;
 495     uint32_t rising;
 496     uint32_t falling;
 497     uint32_t status;
 498     uint32_t gafr;
 499
 500     uint32_t prev_level;
 501 };
 502
 503
 504 static void strongarm_gpio_irq_update(StrongARMGPIOInfo *s)
 505 {
 506     int i;
 507     for (i = 0; i < 11; i++) {
 508         qemu_set_irq(s->irqs[i], s->status & (1 << i));
 509     }
 510
 511     qemu_set_irq(s->irqX, (s->status & ~0x7ff));
 512 }
 513
 514 static void strongarm_gpio_set(void *opaque, int line, int level)
 515 {
 516     StrongARMGPIOInfo *s = opaque;
 517     uint32_t mask;
 518
 519     mask = 1 << line;
 520
 521     if (level) {
 522         s->status |= s->rising & mask &
 523                 ~s->ilevel & ~s->dir;
 524         s->ilevel |= mask;
 525     } else {
 526         s->status |= s->falling & mask &
 527                 s->ilevel & ~s->dir;
 528         s->ilevel &= ~mask;
 529     }
 530
 531     if (s->status & mask) {
 532         strongarm_gpio_irq_update(s);
 533     }
 534 }
 535
 536 static void strongarm_gpio_handler_update(StrongARMGPIOInfo *s)
 537 {
 538     uint32_t level, diff;
 539     int bit;
 540
 541     level = s->olevel & s->dir;
 542
 543     for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
 544         bit = ctz32(diff);
 545         qemu_set_irq(s->handler[bit], (level >> bit) & 1);
 546     }
 547
 548     s->prev_level = level;
 549 }
 550
 551 static uint64_t strongarm_gpio_read(void *opaque, hwaddr offset,
 552                                     unsigned size)
 553 {
 554     StrongARMGPIOInfo *s = opaque;
 555
 556     switch (offset) {
 557     case GPDR:        /* GPIO Pin-Direction registers */
 558         return s->dir;
 559
 560     case GPSR:        /* GPIO Pin-Output Set registers */
 561         qemu_log_mask(LOG_GUEST_ERROR,
 562                       "strongarm GPIO: read from write only register GPSR\n");
 563         return 0;
 564
 565     case GPCR:        /* GPIO Pin-Output Clear registers */
 566         qemu_log_mask(LOG_GUEST_ERROR,
 567                       "strongarm GPIO: read from write only register GPCR\n");
 568         return 0;
 569
 570     case GRER:        /* GPIO Rising-Edge Detect Enable registers */
 571         return s->rising;
 572
 573     case GFER:        /* GPIO Falling-Edge Detect Enable registers */
 574         return s->falling;
 575
 576     case GAFR:        /* GPIO Alternate Function registers */
 577         return s->gafr;
 578
 579     case GPLR:        /* GPIO Pin-Level registers */
 580         return (s->olevel & s->dir) |
 581                (s->ilevel & ~s->dir);
 582
 583     case GEDR:        /* GPIO Edge Detect Status registers */
 584         return s->status;
 585
 586     default:
 587         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 588     }
 589
 590     return 0;
 591 }
 592
 593 static void strongarm_gpio_write(void *opaque, hwaddr offset,
 594                                  uint64_t value, unsigned size)
 595 {
 596     StrongARMGPIOInfo *s = opaque;
 597
 598     switch (offset) {
 599     case GPDR:        /* GPIO Pin-Direction registers */
 600         s->dir = value & 0x0fffffff;
 601         strongarm_gpio_handler_update(s);
 602         break;
 603
 604     case GPSR:        /* GPIO Pin-Output Set registers */
 605         s->olevel |= value & 0x0fffffff;
 606         strongarm_gpio_handler_update(s);
 607         break;
 608
 609     case GPCR:        /* GPIO Pin-Output Clear registers */
 610         s->olevel &= ~value;
 611         strongarm_gpio_handler_update(s);
 612         break;
 613
 614     case GRER:        /* GPIO Rising-Edge Detect Enable registers */
 615         s->rising = value;
 616         break;
 617
 618     case GFER:        /* GPIO Falling-Edge Detect Enable registers */
 619         s->falling = value;
 620         break;
 621
 622     case GAFR:        /* GPIO Alternate Function registers */
 623         s->gafr = value;
 624         break;
 625
 626     case GEDR:        /* GPIO Edge Detect Status registers */
 627         s->status &= ~value;
 628         strongarm_gpio_irq_update(s);
 629         break;
 630
 631     default:
 632         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 633     }
 634 }
 635
 636 static const MemoryRegionOps strongarm_gpio_ops = {
 637     .read = strongarm_gpio_read,
 638     .write = strongarm_gpio_write,
 639     .endianness = DEVICE_NATIVE_ENDIAN,
 640 };
 641
 642 static DeviceState *strongarm_gpio_init(hwaddr base,
 643                 DeviceState *pic)
 644 {
 645     DeviceState *dev;
 646     int i;
 647
 648     dev = qdev_new(TYPE_STRONGARM_GPIO);
 649     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
 650
 651     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 652     for (i = 0; i < 12; i++)
 653         sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
 654                     qdev_get_gpio_in(pic, SA_PIC_GPIO0_EDGE + i));
 655
 656     return dev;
 657 }
 658
 659 static void strongarm_gpio_initfn(Object *obj)
 660 {
 661     DeviceState *dev = DEVICE(obj);
 662     StrongARMGPIOInfo *s = STRONGARM_GPIO(obj);
 663     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 664     int i;
 665
 666     qdev_init_gpio_in(dev, strongarm_gpio_set, 28);
 667     qdev_init_gpio_out(dev, s->handler, 28);
 668
 669     memory_region_init_io(&s->iomem, obj, &strongarm_gpio_ops, s,
 670                           "gpio", 0x1000);
 671
 672     sysbus_init_mmio(sbd, &s->iomem);
 673     for (i = 0; i < 11; i++) {
 674         sysbus_init_irq(sbd, &s->irqs[i]);
 675     }
 676     sysbus_init_irq(sbd, &s->irqX);
 677 }
 678
 679 static const VMStateDescription vmstate_strongarm_gpio_regs = {
 680     .name = "strongarm-gpio",
 681     .version_id = 0,
 682     .minimum_version_id = 0,
 683     .fields = (VMStateField[]) {
 684         VMSTATE_UINT32(ilevel, StrongARMGPIOInfo),
 685         VMSTATE_UINT32(olevel, StrongARMGPIOInfo),
 686         VMSTATE_UINT32(dir, StrongARMGPIOInfo),
 687         VMSTATE_UINT32(rising, StrongARMGPIOInfo),
 688         VMSTATE_UINT32(falling, StrongARMGPIOInfo),
 689         VMSTATE_UINT32(status, StrongARMGPIOInfo),
 690         VMSTATE_UINT32(gafr, StrongARMGPIOInfo),
 691         VMSTATE_UINT32(prev_level, StrongARMGPIOInfo),
 692         VMSTATE_END_OF_LIST(),
 693     },
 694 };
 695
 696 static void strongarm_gpio_class_init(ObjectClass *klass, void *data)
 697 {
 698     DeviceClass *dc = DEVICE_CLASS(klass);
 699
 700     dc->desc = "StrongARM GPIO controller";
 701     dc->vmsd = &vmstate_strongarm_gpio_regs;
 702 }
 703
 704 static const TypeInfo strongarm_gpio_info = {
 705     .name          = TYPE_STRONGARM_GPIO,
 706     .parent        = TYPE_SYS_BUS_DEVICE,
 707     .instance_size = sizeof(StrongARMGPIOInfo),
 708     .instance_init = strongarm_gpio_initfn,
 709     .class_init    = strongarm_gpio_class_init,
 710 };
 711
 712 /* Peripheral Pin Controller */
 713 #define PPDR 0x00
 714 #define PPSR 0x04
 715 #define PPAR 0x08
 716 #define PSDR 0x0c
 717 #define PPFR 0x10
 718
 719 #define TYPE_STRONGARM_PPC "strongarm-ppc"
 720 #define STRONGARM_PPC(obj) \
 721     OBJECT_CHECK(StrongARMPPCInfo, (obj), TYPE_STRONGARM_PPC)
 722
 723 typedef struct StrongARMPPCInfo StrongARMPPCInfo;
 724 struct StrongARMPPCInfo {
 725     SysBusDevice parent_obj;
 726
 727     MemoryRegion iomem;
 728     qemu_irq handler[28];
 729
 730     uint32_t ilevel;
 731     uint32_t olevel;
 732     uint32_t dir;
 733     uint32_t ppar;
 734     uint32_t psdr;
 735     uint32_t ppfr;
 736
 737     uint32_t prev_level;
 738 };
 739
 740 static void strongarm_ppc_set(void *opaque, int line, int level)
 741 {
 742     StrongARMPPCInfo *s = opaque;
 743
 744     if (level) {
 745         s->ilevel |= 1 << line;
 746     } else {
 747         s->ilevel &= ~(1 << line);
 748     }
 749 }
 750
 751 static void strongarm_ppc_handler_update(StrongARMPPCInfo *s)
 752 {
 753     uint32_t level, diff;
 754     int bit;
 755
 756     level = s->olevel & s->dir;
 757
 758     for (diff = s->prev_level ^ level; diff; diff ^= 1 << bit) {
 759         bit = ctz32(diff);
 760         qemu_set_irq(s->handler[bit], (level >> bit) & 1);
 761     }
 762
 763     s->prev_level = level;
 764 }
 765
 766 static uint64_t strongarm_ppc_read(void *opaque, hwaddr offset,
 767                                    unsigned size)
 768 {
 769     StrongARMPPCInfo *s = opaque;
 770
 771     switch (offset) {
 772     case PPDR:        /* PPC Pin Direction registers */
 773         return s->dir | ~0x3fffff;
 774
 775     case PPSR:        /* PPC Pin State registers */
 776         return (s->olevel & s->dir) |
 777                (s->ilevel & ~s->dir) |
 778                ~0x3fffff;
 779
 780     case PPAR:
 781         return s->ppar | ~0x41000;
 782
 783     case PSDR:
 784         return s->psdr;
 785
 786     case PPFR:
 787         return s->ppfr | ~0x7f001;
 788
 789     default:
 790         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 791     }
 792
 793     return 0;
 794 }
 795
 796 static void strongarm_ppc_write(void *opaque, hwaddr offset,
 797                                 uint64_t value, unsigned size)
 798 {
 799     StrongARMPPCInfo *s = opaque;
 800
 801     switch (offset) {
 802     case PPDR:        /* PPC Pin Direction registers */
 803         s->dir = value & 0x3fffff;
 804         strongarm_ppc_handler_update(s);
 805         break;
 806
 807     case PPSR:        /* PPC Pin State registers */
 808         s->olevel = value & s->dir & 0x3fffff;
 809         strongarm_ppc_handler_update(s);
 810         break;
 811
 812     case PPAR:
 813         s->ppar = value & 0x41000;
 814         break;
 815
 816     case PSDR:
 817         s->psdr = value & 0x3fffff;
 818         break;
 819
 820     case PPFR:
 821         s->ppfr = value & 0x7f001;
 822         break;
 823
 824     default:
 825         printf("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset);
 826     }
 827 }
 828
 829 static const MemoryRegionOps strongarm_ppc_ops = {
 830     .read = strongarm_ppc_read,
 831     .write = strongarm_ppc_write,
 832     .endianness = DEVICE_NATIVE_ENDIAN,
 833 };
 834
 835 static void strongarm_ppc_init(Object *obj)
 836 {
 837     DeviceState *dev = DEVICE(obj);
 838     StrongARMPPCInfo *s = STRONGARM_PPC(obj);
 839     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 840
 841     qdev_init_gpio_in(dev, strongarm_ppc_set, 22);
 842     qdev_init_gpio_out(dev, s->handler, 22);
 843
 844     memory_region_init_io(&s->iomem, obj, &strongarm_ppc_ops, s,
 845                           "ppc", 0x1000);
 846
 847     sysbus_init_mmio(sbd, &s->iomem);
 848 }
 849
 850 static const VMStateDescription vmstate_strongarm_ppc_regs = {
 851     .name = "strongarm-ppc",
 852     .version_id = 0,
 853     .minimum_version_id = 0,
 854     .fields = (VMStateField[]) {
 855         VMSTATE_UINT32(ilevel, StrongARMPPCInfo),
 856         VMSTATE_UINT32(olevel, StrongARMPPCInfo),
 857         VMSTATE_UINT32(dir, StrongARMPPCInfo),
 858         VMSTATE_UINT32(ppar, StrongARMPPCInfo),
 859         VMSTATE_UINT32(psdr, StrongARMPPCInfo),
 860         VMSTATE_UINT32(ppfr, StrongARMPPCInfo),
 861         VMSTATE_UINT32(prev_level, StrongARMPPCInfo),
 862         VMSTATE_END_OF_LIST(),
 863     },
 864 };
 865
 866 static void strongarm_ppc_class_init(ObjectClass *klass, void *data)
 867 {
 868     DeviceClass *dc = DEVICE_CLASS(klass);
 869
 870     dc->desc = "StrongARM PPC controller";
 871     dc->vmsd = &vmstate_strongarm_ppc_regs;
 872 }
 873
 874 static const TypeInfo strongarm_ppc_info = {
 875     .name          = TYPE_STRONGARM_PPC,
 876     .parent        = TYPE_SYS_BUS_DEVICE,
 877     .instance_size = sizeof(StrongARMPPCInfo),
 878     .instance_init = strongarm_ppc_init,
 879     .class_init    = strongarm_ppc_class_init,
 880 };
 881
 882 /* UART Ports */
 883 #define UTCR0 0x00
 884 #define UTCR1 0x04
 885 #define UTCR2 0x08
 886 #define UTCR3 0x0c
 887 #define UTDR  0x14
 888 #define UTSR0 0x1c
 889 #define UTSR1 0x20
 890
 891 #define UTCR0_PE  (1 << 0) /* Parity enable */
 892 #define UTCR0_OES (1 << 1) /* Even parity */
 893 #define UTCR0_SBS (1 << 2) /* 2 stop bits */
 894 #define UTCR0_DSS (1 << 3) /* 8-bit data */
 895
 896 #define UTCR3_RXE (1 << 0) /* Rx enable */
 897 #define UTCR3_TXE (1 << 1) /* Tx enable */
 898 #define UTCR3_BRK (1 << 2) /* Force Break */
 899 #define UTCR3_RIE (1 << 3) /* Rx int enable */
 900 #define UTCR3_TIE (1 << 4) /* Tx int enable */
 901 #define UTCR3_LBM (1 << 5) /* Loopback */
 902
 903 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */
 904 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */
 905 #define UTSR0_RID (1 << 2) /* Receiver Idle */
 906 #define UTSR0_RBB (1 << 3) /* Receiver begin break */
 907 #define UTSR0_REB (1 << 4) /* Receiver end break */
 908 #define UTSR0_EIF (1 << 5) /* Error in FIFO */
 909
 910 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */
 911 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */
 912 #define UTSR1_PRE (1 << 3) /* Parity error */
 913 #define UTSR1_FRE (1 << 4) /* Frame error */
 914 #define UTSR1_ROR (1 << 5) /* Receive Over Run */
 915
 916 #define RX_FIFO_PRE (1 << 8)
 917 #define RX_FIFO_FRE (1 << 9)
 918 #define RX_FIFO_ROR (1 << 10)
 919
 920 #define TYPE_STRONGARM_UART "strongarm-uart"
 921 #define STRONGARM_UART(obj) \
 922     OBJECT_CHECK(StrongARMUARTState, (obj), TYPE_STRONGARM_UART)
 923
 924 typedef struct StrongARMUARTState {
 925     SysBusDevice parent_obj;
 926
 927     MemoryRegion iomem;
 928     CharBackend chr;
 929     qemu_irq irq;
 930
 931     uint8_t utcr0;
 932     uint16_t brd;
 933     uint8_t utcr3;
 934     uint8_t utsr0;
 935     uint8_t utsr1;
 936
 937     uint8_t tx_fifo[8];
 938     uint8_t tx_start;
 939     uint8_t tx_len;
 940     uint16_t rx_fifo[12]; /* value + error flags in high bits */
 941     uint8_t rx_start;
 942     uint8_t rx_len;
 943
 944     uint64_t char_transmit_time; /* time to transmit a char in ticks*/
 945     bool wait_break_end;
 946     QEMUTimer *rx_timeout_timer;
 947     QEMUTimer *tx_timer;
 948 } StrongARMUARTState;
 949
 950 static void strongarm_uart_update_status(StrongARMUARTState *s)
 951 {
 952     uint16_t utsr1 = 0;
 953
 954     if (s->tx_len != 8) {
 955         utsr1 |= UTSR1_TNF;
 956     }
 957
 958     if (s->rx_len != 0) {
 959         uint16_t ent = s->rx_fifo[s->rx_start];
 960
 961         utsr1 |= UTSR1_RNE;
 962         if (ent & RX_FIFO_PRE) {
 963             s->utsr1 |= UTSR1_PRE;
 964         }
 965         if (ent & RX_FIFO_FRE) {
 966             s->utsr1 |= UTSR1_FRE;
 967         }
 968         if (ent & RX_FIFO_ROR) {
 969             s->utsr1 |= UTSR1_ROR;
 970         }
 971     }
 972
 973     s->utsr1 = utsr1;
 974 }
 975
 976 static void strongarm_uart_update_int_status(StrongARMUARTState *s)
 977 {
 978     uint16_t utsr0 = s->utsr0 &
 979             (UTSR0_REB | UTSR0_RBB | UTSR0_RID);
 980     int i;
 981
 982     if ((s->utcr3 & UTCR3_TXE) &&
 983                 (s->utcr3 & UTCR3_TIE) &&
 984                 s->tx_len <= 4) {
 985         utsr0 |= UTSR0_TFS;
 986     }
 987
 988     if ((s->utcr3 & UTCR3_RXE) &&
 989                 (s->utcr3 & UTCR3_RIE) &&
 990                 s->rx_len > 4) {
 991         utsr0 |= UTSR0_RFS;
 992     }
 993
 994     for (i = 0; i < s->rx_len && i < 4; i++)
 995         if (s->rx_fifo[(s->rx_start + i) % 12] & ~0xff) {
 996             utsr0 |= UTSR0_EIF;
 997             break;
 998         }
 999
1000     s->utsr0 = utsr0;
1001     qemu_set_irq(s->irq, utsr0);
1002 }
1003
1004 static void strongarm_uart_update_parameters(StrongARMUARTState *s)
1005 {
1006     int speed, parity, data_bits, stop_bits, frame_size;
1007     QEMUSerialSetParams ssp;
1008
1009     /* Start bit. */
1010     frame_size = 1;
1011     if (s->utcr0 & UTCR0_PE) {
1012         /* Parity bit. */
1013         frame_size++;
1014         if (s->utcr0 & UTCR0_OES) {
1015             parity = 'E';
1016         } else {
1017             parity = 'O';
1018         }
1019     } else {
1020             parity = 'N';
1021     }
1022     if (s->utcr0 & UTCR0_SBS) {
1023         stop_bits = 2;
1024     } else {
1025         stop_bits = 1;
1026     }
1027
1028     data_bits = (s->utcr0 & UTCR0_DSS) ? 8 : 7;
1029     frame_size += data_bits + stop_bits;
1030     speed = 3686400 / 16 / (s->brd + 1);
1031     ssp.speed = speed;
1032     ssp.parity = parity;
1033     ssp.data_bits = data_bits;
1034     ssp.stop_bits = stop_bits;
1035     s->char_transmit_time =  (NANOSECONDS_PER_SECOND / speed) * frame_size;
1036     qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
1037
1038     DPRINTF(stderr, "%s speed=%d parity=%c data=%d stop=%d\n", s->chr->label,
1039             speed, parity, data_bits, stop_bits);
1040 }
1041
1042 static void strongarm_uart_rx_to(void *opaque)
1043 {
1044     StrongARMUARTState *s = opaque;
1045
1046     if (s->rx_len) {
1047         s->utsr0 |= UTSR0_RID;
1048         strongarm_uart_update_int_status(s);
1049     }
1050 }
1051
1052 static void strongarm_uart_rx_push(StrongARMUARTState *s, uint16_t c)
1053 {
1054     if ((s->utcr3 & UTCR3_RXE) == 0) {
1055         /* rx disabled */
1056         return;
1057     }
1058
1059     if (s->wait_break_end) {
1060         s->utsr0 |= UTSR0_REB;
1061         s->wait_break_end = false;
1062     }
1063
1064     if (s->rx_len < 12) {
1065         s->rx_fifo[(s->rx_start + s->rx_len) % 12] = c;
1066         s->rx_len++;
1067     } else
1068         s->rx_fifo[(s->rx_start + 11) % 12] |= RX_FIFO_ROR;
1069 }
1070
1071 static int strongarm_uart_can_receive(void *opaque)
1072 {
1073     StrongARMUARTState *s = opaque;
1074
1075     if (s->rx_len == 12) {
1076         return 0;
1077     }
1078     /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */
1079     if (s->rx_len < 8) {
1080         return 8 - s->rx_len;
1081     }
1082     return 1;
1083 }
1084
1085 static void strongarm_uart_receive(void *opaque, const uint8_t *buf, int size)
1086 {
1087     StrongARMUARTState *s = opaque;
1088     int i;
1089
1090     for (i = 0; i < size; i++) {
1091         strongarm_uart_rx_push(s, buf[i]);
1092     }
1093
1094     /* call the timeout receive callback in 3 char transmit time */
1095     timer_mod(s->rx_timeout_timer,
1096                     qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3);
1097
1098     strongarm_uart_update_status(s);
1099     strongarm_uart_update_int_status(s);
1100 }
1101
1102 static void strongarm_uart_event(void *opaque, QEMUChrEvent event)
1103 {
1104     StrongARMUARTState *s = opaque;
1105     if (event == CHR_EVENT_BREAK) {
1106         s->utsr0 |= UTSR0_RBB;
1107         strongarm_uart_rx_push(s, RX_FIFO_FRE);
1108         s->wait_break_end = true;
1109         strongarm_uart_update_status(s);
1110         strongarm_uart_update_int_status(s);
1111     }
1112 }
1113
1114 static void strongarm_uart_tx(void *opaque)
1115 {
1116     StrongARMUARTState *s = opaque;
1117     uint64_t new_xmit_ts = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1118
1119     if (s->utcr3 & UTCR3_LBM) /* loopback */ {
1120         strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1);
1121     } else if (qemu_chr_fe_backend_connected(&s->chr)) {
1122         /* XXX this blocks entire thread. Rewrite to use
1123          * qemu_chr_fe_write and background I/O callbacks */
1124         qemu_chr_fe_write_all(&s->chr, &s->tx_fifo[s->tx_start], 1);
1125     }
1126
1127     s->tx_start = (s->tx_start + 1) % 8;
1128     s->tx_len--;
1129     if (s->tx_len) {
1130         timer_mod(s->tx_timer, new_xmit_ts + s->char_transmit_time);
1131     }
1132     strongarm_uart_update_status(s);
1133     strongarm_uart_update_int_status(s);
1134 }
1135
1136 static uint64_t strongarm_uart_read(void *opaque, hwaddr addr,
1137                                     unsigned size)
1138 {
1139     StrongARMUARTState *s = opaque;
1140     uint16_t ret;
1141
1142     switch (addr) {
1143     case UTCR0:
1144         return s->utcr0;
1145
1146     case UTCR1:
1147         return s->brd >> 8;
1148
1149     case UTCR2:
1150         return s->brd & 0xff;
1151
1152     case UTCR3:
1153         return s->utcr3;
1154
1155     case UTDR:
1156         if (s->rx_len != 0) {
1157             ret = s->rx_fifo[s->rx_start];
1158             s->rx_start = (s->rx_start + 1) % 12;
1159             s->rx_len--;
1160             strongarm_uart_update_status(s);
1161             strongarm_uart_update_int_status(s);
1162             return ret;
1163         }
1164         return 0;
1165
1166     case UTSR0:
1167         return s->utsr0;
1168
1169     case UTSR1:
1170         return s->utsr1;
1171
1172     default:
1173         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1174         return 0;
1175     }
1176 }
1177
1178 static void strongarm_uart_write(void *opaque, hwaddr addr,
1179                                  uint64_t value, unsigned size)
1180 {
1181     StrongARMUARTState *s = opaque;
1182
1183     switch (addr) {
1184     case UTCR0:
1185         s->utcr0 = value & 0x7f;
1186         strongarm_uart_update_parameters(s);
1187         break;
1188
1189     case UTCR1:
1190         s->brd = (s->brd & 0xff) | ((value & 0xf) << 8);
1191         strongarm_uart_update_parameters(s);
1192         break;
1193
1194     case UTCR2:
1195         s->brd = (s->brd & 0xf00) | (value & 0xff);
1196         strongarm_uart_update_parameters(s);
1197         break;
1198
1199     case UTCR3:
1200         s->utcr3 = value & 0x3f;
1201         if ((s->utcr3 & UTCR3_RXE) == 0) {
1202             s->rx_len = 0;
1203         }
1204         if ((s->utcr3 & UTCR3_TXE) == 0) {
1205             s->tx_len = 0;
1206         }
1207         strongarm_uart_update_status(s);
1208         strongarm_uart_update_int_status(s);
1209         break;
1210
1211     case UTDR:
1212         if ((s->utcr3 & UTCR3_TXE) && s->tx_len != 8) {
1213             s->tx_fifo[(s->tx_start + s->tx_len) % 8] = value;
1214             s->tx_len++;
1215             strongarm_uart_update_status(s);
1216             strongarm_uart_update_int_status(s);
1217             if (s->tx_len == 1) {
1218                 strongarm_uart_tx(s);
1219             }
1220         }
1221         break;
1222
1223     case UTSR0:
1224         s->utsr0 = s->utsr0 & ~(value &
1225                 (UTSR0_REB | UTSR0_RBB | UTSR0_RID));
1226         strongarm_uart_update_int_status(s);
1227         break;
1228
1229     default:
1230         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1231     }
1232 }
1233
1234 static const MemoryRegionOps strongarm_uart_ops = {
1235     .read = strongarm_uart_read,
1236     .write = strongarm_uart_write,
1237     .endianness = DEVICE_NATIVE_ENDIAN,
1238 };
1239
1240 static void strongarm_uart_init(Object *obj)
1241 {
1242     StrongARMUARTState *s = STRONGARM_UART(obj);
1243     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
1244
1245     memory_region_init_io(&s->iomem, obj, &strongarm_uart_ops, s,
1246                           "uart", 0x10000);
1247     sysbus_init_mmio(dev, &s->iomem);
1248     sysbus_init_irq(dev, &s->irq);
1249 }
1250
1251 static void strongarm_uart_realize(DeviceState *dev, Error **errp)
1252 {
1253     StrongARMUARTState *s = STRONGARM_UART(dev);
1254
1255     s->rx_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
1256                                        strongarm_uart_rx_to,
1257                                        s);
1258     s->tx_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, strongarm_uart_tx, s);
1259     qemu_chr_fe_set_handlers(&s->chr,
1260                              strongarm_uart_can_receive,
1261                              strongarm_uart_receive,
1262                              strongarm_uart_event,
1263                              NULL, s, NULL, true);
1264 }
1265
1266 static void strongarm_uart_reset(DeviceState *dev)
1267 {
1268     StrongARMUARTState *s = STRONGARM_UART(dev);
1269
1270     s->utcr0 = UTCR0_DSS; /* 8 data, no parity */
1271     s->brd = 23;    /* 9600 */
1272     /* enable send & recv - this actually violates spec */
1273     s->utcr3 = UTCR3_TXE | UTCR3_RXE;
1274
1275     s->rx_len = s->tx_len = 0;
1276
1277     strongarm_uart_update_parameters(s);
1278     strongarm_uart_update_status(s);
1279     strongarm_uart_update_int_status(s);
1280 }
1281
1282 static int strongarm_uart_post_load(void *opaque, int version_id)
1283 {
1284     StrongARMUARTState *s = opaque;
1285
1286     strongarm_uart_update_parameters(s);
1287     strongarm_uart_update_status(s);
1288     strongarm_uart_update_int_status(s);
1289
1290     /* tx and restart timer */
1291     if (s->tx_len) {
1292         strongarm_uart_tx(s);
1293     }
1294
1295     /* restart rx timeout timer */
1296     if (s->rx_len) {
1297         timer_mod(s->rx_timeout_timer,
1298                 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->char_transmit_time * 3);
1299     }
1300
1301     return 0;
1302 }
1303
1304 static const VMStateDescription vmstate_strongarm_uart_regs = {
1305     .name = "strongarm-uart",
1306     .version_id = 0,
1307     .minimum_version_id = 0,
1308     .post_load = strongarm_uart_post_load,
1309     .fields = (VMStateField[]) {
1310         VMSTATE_UINT8(utcr0, StrongARMUARTState),
1311         VMSTATE_UINT16(brd, StrongARMUARTState),
1312         VMSTATE_UINT8(utcr3, StrongARMUARTState),
1313         VMSTATE_UINT8(utsr0, StrongARMUARTState),
1314         VMSTATE_UINT8_ARRAY(tx_fifo, StrongARMUARTState, 8),
1315         VMSTATE_UINT8(tx_start, StrongARMUARTState),
1316         VMSTATE_UINT8(tx_len, StrongARMUARTState),
1317         VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMUARTState, 12),
1318         VMSTATE_UINT8(rx_start, StrongARMUARTState),
1319         VMSTATE_UINT8(rx_len, StrongARMUARTState),
1320         VMSTATE_BOOL(wait_break_end, StrongARMUARTState),
1321         VMSTATE_END_OF_LIST(),
1322     },
1323 };
1324
1325 static Property strongarm_uart_properties[] = {
1326     DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr),
1327     DEFINE_PROP_END_OF_LIST(),
1328 };
1329
1330 static void strongarm_uart_class_init(ObjectClass *klass, void *data)
1331 {
1332     DeviceClass *dc = DEVICE_CLASS(klass);
1333
1334     dc->desc = "StrongARM UART controller";
1335     dc->reset = strongarm_uart_reset;
1336     dc->vmsd = &vmstate_strongarm_uart_regs;
1337     device_class_set_props(dc, strongarm_uart_properties);
1338     dc->realize = strongarm_uart_realize;
1339 }
1340
1341 static const TypeInfo strongarm_uart_info = {
1342     .name          = TYPE_STRONGARM_UART,
1343     .parent        = TYPE_SYS_BUS_DEVICE,
1344     .instance_size = sizeof(StrongARMUARTState),
1345     .instance_init = strongarm_uart_init,
1346     .class_init    = strongarm_uart_class_init,
1347 };
1348
1349 /* Synchronous Serial Ports */
1350
1351 #define TYPE_STRONGARM_SSP "strongarm-ssp"
1352 #define STRONGARM_SSP(obj) \
1353     OBJECT_CHECK(StrongARMSSPState, (obj), TYPE_STRONGARM_SSP)
1354
1355 typedef struct StrongARMSSPState {
1356     SysBusDevice parent_obj;
1357
1358     MemoryRegion iomem;
1359     qemu_irq irq;
1360     SSIBus *bus;
1361
1362     uint16_t sscr[2];
1363     uint16_t sssr;
1364
1365     uint16_t rx_fifo[8];
1366     uint8_t rx_level;
1367     uint8_t rx_start;
1368 } StrongARMSSPState;
1369
1370 #define SSCR0 0x60 /* SSP Control register 0 */
1371 #define SSCR1 0x64 /* SSP Control register 1 */
1372 #define SSDR  0x6c /* SSP Data register */
1373 #define SSSR  0x74 /* SSP Status register */
1374
1375 /* Bitfields for above registers */
1376 #define SSCR0_SPI(x)    (((x) & 0x30) == 0x00)
1377 #define SSCR0_SSP(x)    (((x) & 0x30) == 0x10)
1378 #define SSCR0_UWIRE(x)  (((x) & 0x30) == 0x20)
1379 #define SSCR0_PSP(x)    (((x) & 0x30) == 0x30)
1380 #define SSCR0_SSE       (1 << 7)
1381 #define SSCR0_DSS(x)    (((x) & 0xf) + 1)
1382 #define SSCR1_RIE       (1 << 0)
1383 #define SSCR1_TIE       (1 << 1)
1384 #define SSCR1_LBM       (1 << 2)
1385 #define SSSR_TNF        (1 << 2)
1386 #define SSSR_RNE        (1 << 3)
1387 #define SSSR_TFS        (1 << 5)
1388 #define SSSR_RFS        (1 << 6)
1389 #define SSSR_ROR        (1 << 7)
1390 #define SSSR_RW         0x0080
1391
1392 static void strongarm_ssp_int_update(StrongARMSSPState *s)
1393 {
1394     int level = 0;
1395
1396     level |= (s->sssr & SSSR_ROR);
1397     level |= (s->sssr & SSSR_RFS)  &&  (s->sscr[1] & SSCR1_RIE);
1398     level |= (s->sssr & SSSR_TFS)  &&  (s->sscr[1] & SSCR1_TIE);
1399     qemu_set_irq(s->irq, level);
1400 }
1401
1402 static void strongarm_ssp_fifo_update(StrongARMSSPState *s)
1403 {
1404     s->sssr &= ~SSSR_TFS;
1405     s->sssr &= ~SSSR_TNF;
1406     if (s->sscr[0] & SSCR0_SSE) {
1407         if (s->rx_level >= 4) {
1408             s->sssr |= SSSR_RFS;
1409         } else {
1410             s->sssr &= ~SSSR_RFS;
1411         }
1412         if (s->rx_level) {
1413             s->sssr |= SSSR_RNE;
1414         } else {
1415             s->sssr &= ~SSSR_RNE;
1416         }
1417         /* TX FIFO is never filled, so it is always in underrun
1418            condition if SSP is enabled */
1419         s->sssr |= SSSR_TFS;
1420         s->sssr |= SSSR_TNF;
1421     }
1422
1423     strongarm_ssp_int_update(s);
1424 }
1425
1426 static uint64_t strongarm_ssp_read(void *opaque, hwaddr addr,
1427                                    unsigned size)
1428 {
1429     StrongARMSSPState *s = opaque;
1430     uint32_t retval;
1431
1432     switch (addr) {
1433     case SSCR0:
1434         return s->sscr[0];
1435     case SSCR1:
1436         return s->sscr[1];
1437     case SSSR:
1438         return s->sssr;
1439     case SSDR:
1440         if (~s->sscr[0] & SSCR0_SSE) {
1441             return 0xffffffff;
1442         }
1443         if (s->rx_level < 1) {
1444             printf("%s: SSP Rx Underrun\n", __func__);
1445             return 0xffffffff;
1446         }
1447         s->rx_level--;
1448         retval = s->rx_fifo[s->rx_start++];
1449         s->rx_start &= 0x7;
1450         strongarm_ssp_fifo_update(s);
1451         return retval;
1452     default:
1453         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1454         break;
1455     }
1456     return 0;
1457 }
1458
1459 static void strongarm_ssp_write(void *opaque, hwaddr addr,
1460                                 uint64_t value, unsigned size)
1461 {
1462     StrongARMSSPState *s = opaque;
1463
1464     switch (addr) {
1465     case SSCR0:
1466         s->sscr[0] = value & 0xffbf;
1467         if ((s->sscr[0] & SSCR0_SSE) && SSCR0_DSS(value) < 4) {
1468             printf("%s: Wrong data size: %i bits\n", __func__,
1469                    (int)SSCR0_DSS(value));
1470         }
1471         if (!(value & SSCR0_SSE)) {
1472             s->sssr = 0;
1473             s->rx_level = 0;
1474         }
1475         strongarm_ssp_fifo_update(s);
1476         break;
1477
1478     case SSCR1:
1479         s->sscr[1] = value & 0x2f;
1480         if (value & SSCR1_LBM) {
1481             printf("%s: Attempt to use SSP LBM mode\n", __func__);
1482         }
1483         strongarm_ssp_fifo_update(s);
1484         break;
1485
1486     case SSSR:
1487         s->sssr &= ~(value & SSSR_RW);
1488         strongarm_ssp_int_update(s);
1489         break;
1490
1491     case SSDR:
1492         if (SSCR0_UWIRE(s->sscr[0])) {
1493             value &= 0xff;
1494         } else
1495             /* Note how 32bits overflow does no harm here */
1496             value &= (1 << SSCR0_DSS(s->sscr[0])) - 1;
1497
1498         /* Data goes from here to the Tx FIFO and is shifted out from
1499          * there directly to the slave, no need to buffer it.
1500          */
1501         if (s->sscr[0] & SSCR0_SSE) {
1502             uint32_t readval;
1503             if (s->sscr[1] & SSCR1_LBM) {
1504                 readval = value;
1505             } else {
1506                 readval = ssi_transfer(s->bus, value);
1507             }
1508
1509             if (s->rx_level < 0x08) {
1510                 s->rx_fifo[(s->rx_start + s->rx_level++) & 0x7] = readval;
1511             } else {
1512                 s->sssr |= SSSR_ROR;
1513             }
1514         }
1515         strongarm_ssp_fifo_update(s);
1516         break;
1517
1518     default:
1519         printf("%s: Bad register 0x" TARGET_FMT_plx "\n", __func__, addr);
1520         break;
1521     }
1522 }
1523
1524 static const MemoryRegionOps strongarm_ssp_ops = {
1525     .read = strongarm_ssp_read,
1526     .write = strongarm_ssp_write,
1527     .endianness = DEVICE_NATIVE_ENDIAN,
1528 };
1529
1530 static int strongarm_ssp_post_load(void *opaque, int version_id)
1531 {
1532     StrongARMSSPState *s = opaque;
1533
1534     strongarm_ssp_fifo_update(s);
1535
1536     return 0;
1537 }
1538
1539 static void strongarm_ssp_init(Object *obj)
1540 {
1541     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1542     DeviceState *dev = DEVICE(sbd);
1543     StrongARMSSPState *s = STRONGARM_SSP(dev);
1544
1545     sysbus_init_irq(sbd, &s->irq);
1546
1547     memory_region_init_io(&s->iomem, obj, &strongarm_ssp_ops, s,
1548                           "ssp", 0x1000);
1549     sysbus_init_mmio(sbd, &s->iomem);
1550
1551     s->bus = ssi_create_bus(dev, "ssi");
1552 }
1553
1554 static void strongarm_ssp_reset(DeviceState *dev)
1555 {
1556     StrongARMSSPState *s = STRONGARM_SSP(dev);
1557
1558     s->sssr = 0x03; /* 3 bit data, SPI, disabled */
1559     s->rx_start = 0;
1560     s->rx_level = 0;
1561 }
1562
1563 static const VMStateDescription vmstate_strongarm_ssp_regs = {
1564     .name = "strongarm-ssp",
1565     .version_id = 0,
1566     .minimum_version_id = 0,
1567     .post_load = strongarm_ssp_post_load,
1568     .fields = (VMStateField[]) {
1569         VMSTATE_UINT16_ARRAY(sscr, StrongARMSSPState, 2),
1570         VMSTATE_UINT16(sssr, StrongARMSSPState),
1571         VMSTATE_UINT16_ARRAY(rx_fifo, StrongARMSSPState, 8),
1572         VMSTATE_UINT8(rx_start, StrongARMSSPState),
1573         VMSTATE_UINT8(rx_level, StrongARMSSPState),
1574         VMSTATE_END_OF_LIST(),
1575     },
1576 };
1577
1578 static void strongarm_ssp_class_init(ObjectClass *klass, void *data)
1579 {
1580     DeviceClass *dc = DEVICE_CLASS(klass);
1581
1582     dc->desc = "StrongARM SSP controller";
1583     dc->reset = strongarm_ssp_reset;
1584     dc->vmsd = &vmstate_strongarm_ssp_regs;
1585 }
1586
1587 static const TypeInfo strongarm_ssp_info = {
1588     .name          = TYPE_STRONGARM_SSP,
1589     .parent        = TYPE_SYS_BUS_DEVICE,
1590     .instance_size = sizeof(StrongARMSSPState),
1591     .instance_init = strongarm_ssp_init,
1592     .class_init    = strongarm_ssp_class_init,
1593 };
1594
1595 /* Main CPU functions */
1596 StrongARMState *sa1110_init(const char *cpu_type)
1597 {
1598     StrongARMState *s;
1599     int i;
1600
1601     s = g_new0(StrongARMState, 1);
1602
1603     if (strncmp(cpu_type, "sa1110", 6)) {
1604         error_report("Machine requires a SA1110 processor.");
1605         exit(1);
1606     }
1607
1608     s->cpu = ARM_CPU(cpu_create(cpu_type));
1609
1610     s->pic = sysbus_create_varargs("strongarm_pic", 0x90050000,
1611                     qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ),
1612                     qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ),
1613                     NULL);
1614
1615     sysbus_create_varargs("pxa25x-timer", 0x90000000,
1616                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC0),
1617                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC1),
1618                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC2),
1619                     qdev_get_gpio_in(s->pic, SA_PIC_OSTC3),
1620                     NULL);
1621
1622     sysbus_create_simple(TYPE_STRONGARM_RTC, 0x90010000,
1623                     qdev_get_gpio_in(s->pic, SA_PIC_RTC_ALARM));
1624
1625     s->gpio = strongarm_gpio_init(0x90040000, s->pic);
1626
1627     s->ppc = sysbus_create_varargs(TYPE_STRONGARM_PPC, 0x90060000, NULL);
1628
1629     for (i = 0; sa_serial[i].io_base; i++) {
1630         DeviceState *dev = qdev_new(TYPE_STRONGARM_UART);
1631         qdev_prop_set_chr(dev, "chardev", serial_hd(i));
1632         sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1633         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0,
1634                 sa_serial[i].io_base);
1635         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
1636                 qdev_get_gpio_in(s->pic, sa_serial[i].irq));
1637     }
1638
1639     s->ssp = sysbus_create_varargs(TYPE_STRONGARM_SSP, 0x80070000,
1640                 qdev_get_gpio_in(s->pic, SA_PIC_SSP), NULL);
1641     s->ssp_bus = (SSIBus *)qdev_get_child_bus(s->ssp, "ssi");
1642
1643     return s;
1644 }
1645
1646 static void strongarm_register_types(void)
1647 {
1648     type_register_static(&strongarm_pic_info);
1649     type_register_static(&strongarm_rtc_sysbus_info);
1650     type_register_static(&strongarm_gpio_info);
1651     type_register_static(&strongarm_ppc_info);
1652     type_register_static(&strongarm_uart_info);
1653     type_register_static(&strongarm_ssp_info);
1654 }
1655
1656 type_init(strongarm_register_types)