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vmstate: use visitors
[qemu/mdroth.git] / hw / pci.c
blobe955281eef6d5128eb50e68fc31058274582af6c
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "pci.h"
26 #include "pci_bridge.h"
27 #include "pci_internals.h"
28 #include "monitor.h"
29 #include "net.h"
30 #include "sysemu.h"
31 #include "loader.h"
32 #include "qemu-objects.h"
33 #include "range.h"
34
35 //#define DEBUG_PCI
36 #ifdef DEBUG_PCI
37 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
38 #else
39 # define PCI_DPRINTF(format, ...) do { } while (0)
40 #endif
41
42 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
43 static char *pcibus_get_dev_path(DeviceState *dev);
44 static char *pcibus_get_fw_dev_path(DeviceState *dev);
45 static int pcibus_reset(BusState *qbus);
46
47 struct BusInfo pci_bus_info = {
48 .name = "PCI",
49 .size = sizeof(PCIBus),
50 .print_dev = pcibus_dev_print,
51 .get_dev_path = pcibus_get_dev_path,
52 .get_fw_dev_path = pcibus_get_fw_dev_path,
53 .reset = pcibus_reset,
54 .props = (Property[]) {
55 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
56 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
57 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
58 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
59 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
60 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
61 QEMU_PCI_CAP_SERR_BITNR, true),
62 DEFINE_PROP_END_OF_LIST()
63 }
64 };
65
66 static void pci_update_mappings(PCIDevice *d);
67 static void pci_set_irq(void *opaque, int irq_num, int level);
68 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
69 static void pci_del_option_rom(PCIDevice *pdev);
70
71 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
72 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
73
74 struct PCIHostBus {
75 int domain;
76 struct PCIBus *bus;
77 QLIST_ENTRY(PCIHostBus) next;
78 };
79 static QLIST_HEAD(, PCIHostBus) host_buses;
80
81 static const VMStateDescription vmstate_pcibus = {
82 .name = "PCIBUS",
83 .version_id = 1,
84 .minimum_version_id = 1,
85 .minimum_version_id_old = 1,
86 .fields = (VMStateField []) {
87 VMSTATE_INT32_EQUAL(nirq, PCIBus),
88 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
89 VMSTATE_END_OF_LIST()
90 }
91 };
92
93 static int pci_bar(PCIDevice *d, int reg)
94 {
95 uint8_t type;
96
97 if (reg != PCI_ROM_SLOT)
98 return PCI_BASE_ADDRESS_0 + reg * 4;
99
100 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
101 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
102 }
103
104 static inline int pci_irq_state(PCIDevice *d, int irq_num)
105 {
106 return (d->irq_state >> irq_num) & 0x1;
107 }
108
109 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
110 {
111 d->irq_state &= ~(0x1 << irq_num);
112 d->irq_state |= level << irq_num;
113 }
114
115 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
116 {
117 PCIBus *bus;
118 for (;;) {
119 bus = pci_dev->bus;
120 irq_num = bus->map_irq(pci_dev, irq_num);
121 if (bus->set_irq)
122 break;
123 pci_dev = bus->parent_dev;
124 }
125 bus->irq_count[irq_num] += change;
126 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
127 }
128
129 int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
130 {
131 assert(irq_num >= 0);
132 assert(irq_num < bus->nirq);
133 return !!bus->irq_count[irq_num];
134 }
135
136 /* Update interrupt status bit in config space on interrupt
137 * state change. */
138 static void pci_update_irq_status(PCIDevice *dev)
139 {
140 if (dev->irq_state) {
141 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
142 } else {
143 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
144 }
145 }
146
147 void pci_device_deassert_intx(PCIDevice *dev)
148 {
149 int i;
150 for (i = 0; i < PCI_NUM_PINS; ++i) {
151 qemu_set_irq(dev->irq[i], 0);
152 }
153 }
154
155 /*
156 * This function is called on #RST and FLR.
157 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
158 */
159 void pci_device_reset(PCIDevice *dev)
160 {
161 int r;
162 /* TODO: call the below unconditionally once all pci devices
163 * are qdevified */
164 if (dev->qdev.info) {
165 qdev_reset_all(&dev->qdev);
166 }
167
168 dev->irq_state = 0;
169 pci_update_irq_status(dev);
170 pci_device_deassert_intx(dev);
171 /* Clear all writable bits */
172 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
173 pci_get_word(dev->wmask + PCI_COMMAND) |
174 pci_get_word(dev->w1cmask + PCI_COMMAND));
175 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
176 pci_get_word(dev->wmask + PCI_STATUS) |
177 pci_get_word(dev->w1cmask + PCI_STATUS));
178 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
179 dev->config[PCI_INTERRUPT_LINE] = 0x0;
180 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
181 PCIIORegion *region = &dev->io_regions[r];
182 if (!region->size) {
183 continue;
184 }
185
186 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
187 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
188 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
189 } else {
190 pci_set_long(dev->config + pci_bar(dev, r), region->type);
191 }
192 }
193 pci_update_mappings(dev);
194 }
195
196 /*
197 * Trigger pci bus reset under a given bus.
198 * To be called on RST# assert.
199 */
200 void pci_bus_reset(PCIBus *bus)
201 {
202 int i;
203
204 for (i = 0; i < bus->nirq; i++) {
205 bus->irq_count[i] = 0;
206 }
207 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
208 if (bus->devices[i]) {
209 pci_device_reset(bus->devices[i]);
210 }
211 }
212 }
213
214 static int pcibus_reset(BusState *qbus)
215 {
216 pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus));
217
218 /* topology traverse is done by pci_bus_reset().
219 Tell qbus/qdev walker not to traverse the tree */
220 return 1;
221 }
222
223 static void pci_host_bus_register(int domain, PCIBus *bus)
224 {
225 struct PCIHostBus *host;
226 host = g_malloc0(sizeof(*host));
227 host->domain = domain;
228 host->bus = bus;
229 QLIST_INSERT_HEAD(&host_buses, host, next);
230 }
231
232 PCIBus *pci_find_root_bus(int domain)
233 {
234 struct PCIHostBus *host;
235
236 QLIST_FOREACH(host, &host_buses, next) {
237 if (host->domain == domain) {
238 return host->bus;
239 }
240 }
241
242 return NULL;
243 }
244
245 int pci_find_domain(const PCIBus *bus)
246 {
247 PCIDevice *d;
248 struct PCIHostBus *host;
249
250 /* obtain root bus */
251 while ((d = bus->parent_dev) != NULL) {
252 bus = d->bus;
253 }
254
255 QLIST_FOREACH(host, &host_buses, next) {
256 if (host->bus == bus) {
257 return host->domain;
258 }
259 }
260
261 abort(); /* should not be reached */
262 return -1;
263 }
264
265 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
266 const char *name,
267 MemoryRegion *address_space_mem,
268 MemoryRegion *address_space_io,
269 uint8_t devfn_min)
270 {
271 qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
272 assert(PCI_FUNC(devfn_min) == 0);
273 bus->devfn_min = devfn_min;
274 bus->address_space_mem = address_space_mem;
275 bus->address_space_io = address_space_io;
276
277 /* host bridge */
278 QLIST_INIT(&bus->child);
279 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
280
281 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
282 }
283
284 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
285 MemoryRegion *address_space_mem,
286 MemoryRegion *address_space_io,
287 uint8_t devfn_min)
288 {
289 PCIBus *bus;
290
291 bus = g_malloc0(sizeof(*bus));
292 bus->qbus.qdev_allocated = 1;
293 pci_bus_new_inplace(bus, parent, name, address_space_mem,
294 address_space_io, devfn_min);
295 return bus;
296 }
297
298 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
299 void *irq_opaque, int nirq)
300 {
301 bus->set_irq = set_irq;
302 bus->map_irq = map_irq;
303 bus->irq_opaque = irq_opaque;
304 bus->nirq = nirq;
305 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
306 }
307
308 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
309 {
310 bus->qbus.allow_hotplug = 1;
311 bus->hotplug = hotplug;
312 bus->hotplug_qdev = qdev;
313 }
314
315 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
316 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
317 void *irq_opaque,
318 MemoryRegion *address_space_mem,
319 MemoryRegion *address_space_io,
320 uint8_t devfn_min, int nirq)
321 {
322 PCIBus *bus;
323
324 bus = pci_bus_new(parent, name, address_space_mem,
325 address_space_io, devfn_min);
326 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
327 return bus;
328 }
329
330 int pci_bus_num(PCIBus *s)
331 {
332 if (!s->parent_dev)
333 return 0; /* pci host bridge */
334 return s->parent_dev->config[PCI_SECONDARY_BUS];
335 }
336
337 static int get_pci_config_device(Visitor *v, const char *name, void *pv,
338 size_t size, Error **err)
339 {
340 PCIDevice *s = container_of(pv, PCIDevice, config);
341 uint8_t *config = NULL;
342 int i;
343
344 assert(size == pci_config_size(s));
345
346 visit_start_array(v, (void **)&config, name, size, 1, err);
347 for (i = 0; i < size; ++i) {
348 visit_type_uint8(v, &config[i], NULL, err);
349 if ((config[i] ^ s->config[i]) &
350 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
351 g_free(config);
352 return -EINVAL;
353 }
354 }
355 visit_end_array(v, err);
356 memcpy(s->config, config, size);
357
358 pci_update_mappings(s);
359
360 g_free(config);
361 return 0;
362 }
363
364 /* just put buffer */
365 static void put_pci_config_device(Visitor *v, const char *name, void *pv,
366 size_t size, Error **err)
367 {
368 uint8_t *config = *(uint8_t **)pv;
369 int i;
370 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
371 visit_start_array(v, (void **)&config, name, size, 1, err);
372 for (i = 0; i < size; i++) {
373 visit_type_uint8(v, &config[i], NULL, err);
374 }
375 visit_end_array(v, err);
376 }
377
378 static VMStateInfo vmstate_info_pci_config = {
379 .name = "pci config",
380 .get = get_pci_config_device,
381 .put = put_pci_config_device,
382 };
383
384 static int get_pci_irq_state(Visitor *v, const char *name, void *pv,
385 size_t size, Error **err)
386 {
387 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
388 uint32_t irq_state[PCI_NUM_PINS];
389 int i;
390 visit_start_array(v, NULL, name, PCI_NUM_PINS, 4, err);
391 for (i = 0; i < PCI_NUM_PINS; ++i) {
392 visit_type_uint32(v, &irq_state[i], NULL, err);
393 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
394 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
395 irq_state[i]);
396 return -EINVAL;
397 }
398 }
399 visit_end_array(v, err);
400
401 for (i = 0; i < PCI_NUM_PINS; ++i) {
402 pci_set_irq_state(s, i, irq_state[i]);
403 }
404
405 return 0;
406 }
407
408 static void put_pci_irq_state(Visitor *v, const char *name, void *pv,
409 size_t size, Error **err)
410 {
411 int i;
412 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
413 uint32_t irq_state;
414
415 visit_start_array(v, NULL, name, PCI_NUM_PINS, 4, err);
416 for (i = 0; i < PCI_NUM_PINS; ++i) {
417 irq_state = pci_irq_state(s, i);
418 visit_type_uint32(v, &irq_state, NULL, err);
419 }
420 visit_end_array(v, err);
421 }
422
423 static VMStateInfo vmstate_info_pci_irq_state = {
424 .name = "pci irq state",
425 .get = get_pci_irq_state,
426 .put = put_pci_irq_state,
427 };
428
429 const VMStateDescription vmstate_pci_device = {
430 .name = "PCIDevice",
431 .version_id = 2,
432 .minimum_version_id = 1,
433 .minimum_version_id_old = 1,
434 .fields = (VMStateField []) {
435 VMSTATE_INT32_LE(version_id, PCIDevice),
436 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
437 vmstate_info_pci_config,
438 PCI_CONFIG_SPACE_SIZE),
439 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
440 vmstate_info_pci_irq_state,
441 PCI_NUM_PINS * sizeof(int32_t)),
442 VMSTATE_END_OF_LIST()
443 }
444 };
445
446 const VMStateDescription vmstate_pcie_device = {
447 .name = "PCIDevice",
448 .version_id = 2,
449 .minimum_version_id = 1,
450 .minimum_version_id_old = 1,
451 .fields = (VMStateField []) {
452 VMSTATE_INT32_LE(version_id, PCIDevice),
453 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
454 vmstate_info_pci_config,
455 PCIE_CONFIG_SPACE_SIZE),
456 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
457 vmstate_info_pci_irq_state,
458 PCI_NUM_PINS * sizeof(int32_t)),
459 VMSTATE_END_OF_LIST()
460 }
461 };
462
463 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
464 {
465 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
466 }
467
468 void pci_device_save(PCIDevice *s, QEMUFile *f)
469 {
470 /* Clear interrupt status bit: it is implicit
471 * in irq_state which we are saving.
472 * This makes us compatible with old devices
473 * which never set or clear this bit. */
474 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
475 vmstate_save_state(f, pci_get_vmstate(s), s);
476 /* Restore the interrupt status bit. */
477 pci_update_irq_status(s);
478 }
479
480 int pci_device_load(PCIDevice *s, QEMUFile *f)
481 {
482 int ret;
483 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
484 /* Restore the interrupt status bit. */
485 pci_update_irq_status(s);
486 return ret;
487 }
488
489 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
490 {
491 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
492 pci_default_sub_vendor_id);
493 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
494 pci_default_sub_device_id);
495 }
496
497 /*
498 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
499 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
500 */
501 int pci_parse_devaddr(const char *addr, int *domp, int *busp,
502 unsigned int *slotp, unsigned int *funcp)
503 {
504 const char *p;
505 char *e;
506 unsigned long val;
507 unsigned long dom = 0, bus = 0;
508 unsigned int slot = 0;
509 unsigned int func = 0;
510
511 p = addr;
512 val = strtoul(p, &e, 16);
513 if (e == p)
514 return -1;
515 if (*e == ':') {
516 bus = val;
517 p = e + 1;
518 val = strtoul(p, &e, 16);
519 if (e == p)
520 return -1;
521 if (*e == ':') {
522 dom = bus;
523 bus = val;
524 p = e + 1;
525 val = strtoul(p, &e, 16);
526 if (e == p)
527 return -1;
528 }
529 }
530
531 slot = val;
532
533 if (funcp != NULL) {
534 if (*e != '.')
535 return -1;
536
537 p = e + 1;
538 val = strtoul(p, &e, 16);
539 if (e == p)
540 return -1;
541
542 func = val;
543 }
544
545 /* if funcp == NULL func is 0 */
546 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
547 return -1;
548
549 if (*e)
550 return -1;
551
552 /* Note: QEMU doesn't implement domains other than 0 */
553 if (!pci_find_bus(pci_find_root_bus(dom), bus))
554 return -1;
555
556 *domp = dom;
557 *busp = bus;
558 *slotp = slot;
559 if (funcp != NULL)
560 *funcp = func;
561 return 0;
562 }
563
564 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
565 unsigned *slotp)
566 {
567 /* strip legacy tag */
568 if (!strncmp(addr, "pci_addr=", 9)) {
569 addr += 9;
570 }
571 if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
572 monitor_printf(mon, "Invalid pci address\n");
573 return -1;
574 }
575 return 0;
576 }
577
578 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
579 {
580 int dom, bus;
581 unsigned slot;
582
583 if (!devaddr) {
584 *devfnp = -1;
585 return pci_find_bus(pci_find_root_bus(0), 0);
586 }
587
588 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
589 return NULL;
590 }
591
592 *devfnp = PCI_DEVFN(slot, 0);
593 return pci_find_bus(pci_find_root_bus(dom), bus);
594 }
595
596 static void pci_init_cmask(PCIDevice *dev)
597 {
598 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
599 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
600 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
601 dev->cmask[PCI_REVISION_ID] = 0xff;
602 dev->cmask[PCI_CLASS_PROG] = 0xff;
603 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
604 dev->cmask[PCI_HEADER_TYPE] = 0xff;
605 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
606 }
607
608 static void pci_init_wmask(PCIDevice *dev)
609 {
610 int config_size = pci_config_size(dev);
611
612 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
613 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
614 pci_set_word(dev->wmask + PCI_COMMAND,
615 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
616 PCI_COMMAND_INTX_DISABLE);
617 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
618 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
619 }
620
621 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
622 config_size - PCI_CONFIG_HEADER_SIZE);
623 }
624
625 static void pci_init_w1cmask(PCIDevice *dev)
626 {
627 /*
628 * Note: It's okay to set w1cmask even for readonly bits as
629 * long as their value is hardwired to 0.
630 */
631 pci_set_word(dev->w1cmask + PCI_STATUS,
632 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
633 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
634 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
635 }
636
637 static void pci_init_wmask_bridge(PCIDevice *d)
638 {
639 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
640 PCI_SEC_LETENCY_TIMER */
641 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
642
643 /* base and limit */
644 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
645 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
646 pci_set_word(d->wmask + PCI_MEMORY_BASE,
647 PCI_MEMORY_RANGE_MASK & 0xffff);
648 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
649 PCI_MEMORY_RANGE_MASK & 0xffff);
650 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
651 PCI_PREF_RANGE_MASK & 0xffff);
652 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
653 PCI_PREF_RANGE_MASK & 0xffff);
654
655 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
656 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
657
658 /* TODO: add this define to pci_regs.h in linux and then in qemu. */
659 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
660 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */
661 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
662 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
663 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
664 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
665 PCI_BRIDGE_CTL_PARITY |
666 PCI_BRIDGE_CTL_SERR |
667 PCI_BRIDGE_CTL_ISA |
668 PCI_BRIDGE_CTL_VGA |
669 PCI_BRIDGE_CTL_VGA_16BIT |
670 PCI_BRIDGE_CTL_MASTER_ABORT |
671 PCI_BRIDGE_CTL_BUS_RESET |
672 PCI_BRIDGE_CTL_FAST_BACK |
673 PCI_BRIDGE_CTL_DISCARD |
674 PCI_BRIDGE_CTL_SEC_DISCARD |
675 PCI_BRIDGE_CTL_DISCARD_SERR);
676 /* Below does not do anything as we never set this bit, put here for
677 * completeness. */
678 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
679 PCI_BRIDGE_CTL_DISCARD_STATUS);
680 }
681
682 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
683 {
684 uint8_t slot = PCI_SLOT(dev->devfn);
685 uint8_t func;
686
687 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
688 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
689 }
690
691 /*
692 * multifunction bit is interpreted in two ways as follows.
693 * - all functions must set the bit to 1.
694 * Example: Intel X53
695 * - function 0 must set the bit, but the rest function (> 0)
696 * is allowed to leave the bit to 0.
697 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
698 *
699 * So OS (at least Linux) checks the bit of only function 0,
700 * and doesn't see the bit of function > 0.
701 *
702 * The below check allows both interpretation.
703 */
704 if (PCI_FUNC(dev->devfn)) {
705 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
706 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
707 /* function 0 should set multifunction bit */
708 error_report("PCI: single function device can't be populated "
709 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
710 return -1;
711 }
712 return 0;
713 }
714
715 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
716 return 0;
717 }
718 /* function 0 indicates single function, so function > 0 must be NULL */
719 for (func = 1; func < PCI_FUNC_MAX; ++func) {
720 if (bus->devices[PCI_DEVFN(slot, func)]) {
721 error_report("PCI: %x.0 indicates single function, "
722 "but %x.%x is already populated.",
723 slot, slot, func);
724 return -1;
725 }
726 }
727 return 0;
728 }
729
730 static void pci_config_alloc(PCIDevice *pci_dev)
731 {
732 int config_size = pci_config_size(pci_dev);
733
734 pci_dev->config = g_malloc0(config_size);
735 pci_dev->cmask = g_malloc0(config_size);
736 pci_dev->wmask = g_malloc0(config_size);
737 pci_dev->w1cmask = g_malloc0(config_size);
738 pci_dev->used = g_malloc0(config_size);
739 }
740
741 static void pci_config_free(PCIDevice *pci_dev)
742 {
743 g_free(pci_dev->config);
744 g_free(pci_dev->cmask);
745 g_free(pci_dev->wmask);
746 g_free(pci_dev->w1cmask);
747 g_free(pci_dev->used);
748 }
749
750 /* -1 for devfn means auto assign */
751 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
752 const char *name, int devfn,
753 const PCIDeviceInfo *info)
754 {
755 PCIConfigReadFunc *config_read = info->config_read;
756 PCIConfigWriteFunc *config_write = info->config_write;
757
758 if (devfn < 0) {
759 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
760 devfn += PCI_FUNC_MAX) {
761 if (!bus->devices[devfn])
762 goto found;
763 }
764 error_report("PCI: no slot/function available for %s, all in use", name);
765 return NULL;
766 found: ;
767 } else if (bus->devices[devfn]) {
768 error_report("PCI: slot %d function %d not available for %s, in use by %s",
769 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
770 return NULL;
771 }
772 pci_dev->bus = bus;
773 pci_dev->devfn = devfn;
774 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
775 pci_dev->irq_state = 0;
776 pci_config_alloc(pci_dev);
777
778 pci_config_set_vendor_id(pci_dev->config, info->vendor_id);
779 pci_config_set_device_id(pci_dev->config, info->device_id);
780 pci_config_set_revision(pci_dev->config, info->revision);
781 pci_config_set_class(pci_dev->config, info->class_id);
782
783 if (!info->is_bridge) {
784 if (info->subsystem_vendor_id || info->subsystem_id) {
785 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
786 info->subsystem_vendor_id);
787 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
788 info->subsystem_id);
789 } else {
790 pci_set_default_subsystem_id(pci_dev);
791 }
792 } else {
793 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
794 assert(!info->subsystem_vendor_id);
795 assert(!info->subsystem_id);
796 }
797 pci_init_cmask(pci_dev);
798 pci_init_wmask(pci_dev);
799 pci_init_w1cmask(pci_dev);
800 if (info->is_bridge) {
801 pci_init_wmask_bridge(pci_dev);
802 }
803 if (pci_init_multifunction(bus, pci_dev)) {
804 pci_config_free(pci_dev);
805 return NULL;
806 }
807
808 if (!config_read)
809 config_read = pci_default_read_config;
810 if (!config_write)
811 config_write = pci_default_write_config;
812 pci_dev->config_read = config_read;
813 pci_dev->config_write = config_write;
814 bus->devices[devfn] = pci_dev;
815 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
816 pci_dev->version_id = 2; /* Current pci device vmstate version */
817 return pci_dev;
818 }
819
820 static void do_pci_unregister_device(PCIDevice *pci_dev)
821 {
822 qemu_free_irqs(pci_dev->irq);
823 pci_dev->bus->devices[pci_dev->devfn] = NULL;
824 pci_config_free(pci_dev);
825 }
826
827 /* TODO: obsolete. eliminate this once all pci devices are qdevifed. */
828 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
829 int instance_size, int devfn,
830 PCIConfigReadFunc *config_read,
831 PCIConfigWriteFunc *config_write)
832 {
833 PCIDevice *pci_dev;
834 PCIDeviceInfo info = {
835 .config_read = config_read,
836 .config_write = config_write,
837 };
838
839 pci_dev = g_malloc0(instance_size);
840 pci_dev = do_pci_register_device(pci_dev, bus, name, devfn, &info);
841 if (pci_dev == NULL) {
842 hw_error("PCI: can't register device\n");
843 }
844 return pci_dev;
845 }
846
847 static void pci_unregister_io_regions(PCIDevice *pci_dev)
848 {
849 PCIIORegion *r;
850 int i;
851
852 for(i = 0; i < PCI_NUM_REGIONS; i++) {
853 r = &pci_dev->io_regions[i];
854 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
855 continue;
856 memory_region_del_subregion(r->address_space, r->memory);
857 }
858 }
859
860 static int pci_unregister_device(DeviceState *dev)
861 {
862 PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
863 PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
864 int ret = 0;
865
866 if (info->exit)
867 ret = info->exit(pci_dev);
868 if (ret)
869 return ret;
870
871 pci_unregister_io_regions(pci_dev);
872 pci_del_option_rom(pci_dev);
873 g_free(pci_dev->romfile);
874 do_pci_unregister_device(pci_dev);
875 return 0;
876 }
877
878 void pci_register_bar(PCIDevice *pci_dev, int region_num,
879 uint8_t type, MemoryRegion *memory)
880 {
881 PCIIORegion *r;
882 uint32_t addr;
883 uint64_t wmask;
884 pcibus_t size = memory_region_size(memory);
885
886 assert(region_num >= 0);
887 assert(region_num < PCI_NUM_REGIONS);
888 if (size & (size-1)) {
889 fprintf(stderr, "ERROR: PCI region size must be pow2 "
890 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
891 exit(1);
892 }
893
894 r = &pci_dev->io_regions[region_num];
895 r->addr = PCI_BAR_UNMAPPED;
896 r->size = size;
897 r->type = type;
898 r->memory = NULL;
899
900 wmask = ~(size - 1);
901 addr = pci_bar(pci_dev, region_num);
902 if (region_num == PCI_ROM_SLOT) {
903 /* ROM enable bit is writable */
904 wmask |= PCI_ROM_ADDRESS_ENABLE;
905 }
906 pci_set_long(pci_dev->config + addr, type);
907 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
908 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
909 pci_set_quad(pci_dev->wmask + addr, wmask);
910 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
911 } else {
912 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
913 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
914 }
915 pci_dev->io_regions[region_num].memory = memory;
916 pci_dev->io_regions[region_num].address_space
917 = type & PCI_BASE_ADDRESS_SPACE_IO
918 ? pci_dev->bus->address_space_io
919 : pci_dev->bus->address_space_mem;
920 }
921
922 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
923 {
924 return pci_dev->io_regions[region_num].addr;
925 }
926
927 static pcibus_t pci_bar_address(PCIDevice *d,
928 int reg, uint8_t type, pcibus_t size)
929 {
930 pcibus_t new_addr, last_addr;
931 int bar = pci_bar(d, reg);
932 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
933
934 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
935 if (!(cmd & PCI_COMMAND_IO)) {
936 return PCI_BAR_UNMAPPED;
937 }
938 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
939 last_addr = new_addr + size - 1;
940 /* NOTE: we have only 64K ioports on PC */
941 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
942 return PCI_BAR_UNMAPPED;
943 }
944 return new_addr;
945 }
946
947 if (!(cmd & PCI_COMMAND_MEMORY)) {
948 return PCI_BAR_UNMAPPED;
949 }
950 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
951 new_addr = pci_get_quad(d->config + bar);
952 } else {
953 new_addr = pci_get_long(d->config + bar);
954 }
955 /* the ROM slot has a specific enable bit */
956 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
957 return PCI_BAR_UNMAPPED;
958 }
959 new_addr &= ~(size - 1);
960 last_addr = new_addr + size - 1;
961 /* NOTE: we do not support wrapping */
962 /* XXX: as we cannot support really dynamic
963 mappings, we handle specific values as invalid
964 mappings. */
965 if (last_addr <= new_addr || new_addr == 0 ||
966 last_addr == PCI_BAR_UNMAPPED) {
967 return PCI_BAR_UNMAPPED;
968 }
969
970 /* Now pcibus_t is 64bit.
971 * Check if 32 bit BAR wraps around explicitly.
972 * Without this, PC ide doesn't work well.
973 * TODO: remove this work around.
974 */
975 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
976 return PCI_BAR_UNMAPPED;
977 }
978
979 /*
980 * OS is allowed to set BAR beyond its addressable
981 * bits. For example, 32 bit OS can set 64bit bar
982 * to >4G. Check it. TODO: we might need to support
983 * it in the future for e.g. PAE.
984 */
985 if (last_addr >= TARGET_PHYS_ADDR_MAX) {
986 return PCI_BAR_UNMAPPED;
987 }
988
989 return new_addr;
990 }
991
992 static void pci_update_mappings(PCIDevice *d)
993 {
994 PCIIORegion *r;
995 int i;
996 pcibus_t new_addr;
997
998 for(i = 0; i < PCI_NUM_REGIONS; i++) {
999 r = &d->io_regions[i];
1000
1001 /* this region isn't registered */
1002 if (!r->size)
1003 continue;
1004
1005 new_addr = pci_bar_address(d, i, r->type, r->size);
1006
1007 /* This bar isn't changed */
1008 if (new_addr == r->addr)
1009 continue;
1010
1011 /* now do the real mapping */
1012 if (r->addr != PCI_BAR_UNMAPPED) {
1013 memory_region_del_subregion(r->address_space, r->memory);
1014 }
1015 r->addr = new_addr;
1016 if (r->addr != PCI_BAR_UNMAPPED) {
1017 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1018 memory_region_add_subregion_overlap(r->address_space,
1019 r->addr,
1020 r->memory,
1021 1);
1022 } else {
1023 memory_region_add_subregion_overlap(r->address_space,
1024 r->addr,
1025 r->memory,
1026 1);
1027 }
1028 }
1029 }
1030 }
1031
1032 static inline int pci_irq_disabled(PCIDevice *d)
1033 {
1034 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1035 }
1036
1037 /* Called after interrupt disabled field update in config space,
1038 * assert/deassert interrupts if necessary.
1039 * Gets original interrupt disable bit value (before update). */
1040 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1041 {
1042 int i, disabled = pci_irq_disabled(d);
1043 if (disabled == was_irq_disabled)
1044 return;
1045 for (i = 0; i < PCI_NUM_PINS; ++i) {
1046 int state = pci_irq_state(d, i);
1047 pci_change_irq_level(d, i, disabled ? -state : state);
1048 }
1049 }
1050
1051 uint32_t pci_default_read_config(PCIDevice *d,
1052 uint32_t address, int len)
1053 {
1054 uint32_t val = 0;
1055
1056 memcpy(&val, d->config + address, len);
1057 return le32_to_cpu(val);
1058 }
1059
1060 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1061 {
1062 int i, was_irq_disabled = pci_irq_disabled(d);
1063
1064 for (i = 0; i < l; val >>= 8, ++i) {
1065 uint8_t wmask = d->wmask[addr + i];
1066 uint8_t w1cmask = d->w1cmask[addr + i];
1067 assert(!(wmask & w1cmask));
1068 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1069 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1070 }
1071 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1072 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1073 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1074 range_covers_byte(addr, l, PCI_COMMAND))
1075 pci_update_mappings(d);
1076
1077 if (range_covers_byte(addr, l, PCI_COMMAND))
1078 pci_update_irq_disabled(d, was_irq_disabled);
1079 }
1080
1081 /***********************************************************/
1082 /* generic PCI irq support */
1083
1084 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1085 static void pci_set_irq(void *opaque, int irq_num, int level)
1086 {
1087 PCIDevice *pci_dev = opaque;
1088 int change;
1089
1090 change = level - pci_irq_state(pci_dev, irq_num);
1091 if (!change)
1092 return;
1093
1094 pci_set_irq_state(pci_dev, irq_num, level);
1095 pci_update_irq_status(pci_dev);
1096 if (pci_irq_disabled(pci_dev))
1097 return;
1098 pci_change_irq_level(pci_dev, irq_num, change);
1099 }
1100
1101 /***********************************************************/
1102 /* monitor info on PCI */
1103
1104 typedef struct {
1105 uint16_t class;
1106 const char *desc;
1107 const char *fw_name;
1108 uint16_t fw_ign_bits;
1109 } pci_class_desc;
1110
1111 static const pci_class_desc pci_class_descriptions[] =
1112 {
1113 { 0x0001, "VGA controller", "display"},
1114 { 0x0100, "SCSI controller", "scsi"},
1115 { 0x0101, "IDE controller", "ide"},
1116 { 0x0102, "Floppy controller", "fdc"},
1117 { 0x0103, "IPI controller", "ipi"},
1118 { 0x0104, "RAID controller", "raid"},
1119 { 0x0106, "SATA controller"},
1120 { 0x0107, "SAS controller"},
1121 { 0x0180, "Storage controller"},
1122 { 0x0200, "Ethernet controller", "ethernet"},
1123 { 0x0201, "Token Ring controller", "token-ring"},
1124 { 0x0202, "FDDI controller", "fddi"},
1125 { 0x0203, "ATM controller", "atm"},
1126 { 0x0280, "Network controller"},
1127 { 0x0300, "VGA controller", "display", 0x00ff},
1128 { 0x0301, "XGA controller"},
1129 { 0x0302, "3D controller"},
1130 { 0x0380, "Display controller"},
1131 { 0x0400, "Video controller", "video"},
1132 { 0x0401, "Audio controller", "sound"},
1133 { 0x0402, "Phone"},
1134 { 0x0403, "Audio controller", "sound"},
1135 { 0x0480, "Multimedia controller"},
1136 { 0x0500, "RAM controller", "memory"},
1137 { 0x0501, "Flash controller", "flash"},
1138 { 0x0580, "Memory controller"},
1139 { 0x0600, "Host bridge", "host"},
1140 { 0x0601, "ISA bridge", "isa"},
1141 { 0x0602, "EISA bridge", "eisa"},
1142 { 0x0603, "MC bridge", "mca"},
1143 { 0x0604, "PCI bridge", "pci"},
1144 { 0x0605, "PCMCIA bridge", "pcmcia"},
1145 { 0x0606, "NUBUS bridge", "nubus"},
1146 { 0x0607, "CARDBUS bridge", "cardbus"},
1147 { 0x0608, "RACEWAY bridge"},
1148 { 0x0680, "Bridge"},
1149 { 0x0700, "Serial port", "serial"},
1150 { 0x0701, "Parallel port", "parallel"},
1151 { 0x0800, "Interrupt controller", "interrupt-controller"},
1152 { 0x0801, "DMA controller", "dma-controller"},
1153 { 0x0802, "Timer", "timer"},
1154 { 0x0803, "RTC", "rtc"},
1155 { 0x0900, "Keyboard", "keyboard"},
1156 { 0x0901, "Pen", "pen"},
1157 { 0x0902, "Mouse", "mouse"},
1158 { 0x0A00, "Dock station", "dock", 0x00ff},
1159 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1160 { 0x0c00, "Fireware contorller", "fireware"},
1161 { 0x0c01, "Access bus controller", "access-bus"},
1162 { 0x0c02, "SSA controller", "ssa"},
1163 { 0x0c03, "USB controller", "usb"},
1164 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1165 { 0, NULL}
1166 };
1167
1168 static void pci_for_each_device_under_bus(PCIBus *bus,
1169 void (*fn)(PCIBus *b, PCIDevice *d))
1170 {
1171 PCIDevice *d;
1172 int devfn;
1173
1174 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1175 d = bus->devices[devfn];
1176 if (d) {
1177 fn(bus, d);
1178 }
1179 }
1180 }
1181
1182 void pci_for_each_device(PCIBus *bus, int bus_num,
1183 void (*fn)(PCIBus *b, PCIDevice *d))
1184 {
1185 bus = pci_find_bus(bus, bus_num);
1186
1187 if (bus) {
1188 pci_for_each_device_under_bus(bus, fn);
1189 }
1190 }
1191
1192 static void pci_device_print(Monitor *mon, QDict *device)
1193 {
1194 QDict *qdict;
1195 QListEntry *entry;
1196 uint64_t addr, size;
1197
1198 monitor_printf(mon, " Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
1199 monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
1200 qdict_get_int(device, "slot"),
1201 qdict_get_int(device, "function"));
1202 monitor_printf(mon, " ");
1203
1204 qdict = qdict_get_qdict(device, "class_info");
1205 if (qdict_haskey(qdict, "desc")) {
1206 monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
1207 } else {
1208 monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
1209 }
1210
1211 qdict = qdict_get_qdict(device, "id");
1212 monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
1213 qdict_get_int(qdict, "device"),
1214 qdict_get_int(qdict, "vendor"));
1215
1216 if (qdict_haskey(device, "irq")) {
1217 monitor_printf(mon, " IRQ %" PRId64 ".\n",
1218 qdict_get_int(device, "irq"));
1219 }
1220
1221 if (qdict_haskey(device, "pci_bridge")) {
1222 QDict *info;
1223
1224 qdict = qdict_get_qdict(device, "pci_bridge");
1225
1226 info = qdict_get_qdict(qdict, "bus");
1227 monitor_printf(mon, " BUS %" PRId64 ".\n",
1228 qdict_get_int(info, "number"));
1229 monitor_printf(mon, " secondary bus %" PRId64 ".\n",
1230 qdict_get_int(info, "secondary"));
1231 monitor_printf(mon, " subordinate bus %" PRId64 ".\n",
1232 qdict_get_int(info, "subordinate"));
1233
1234 info = qdict_get_qdict(qdict, "io_range");
1235 monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
1236 qdict_get_int(info, "base"),
1237 qdict_get_int(info, "limit"));
1238
1239 info = qdict_get_qdict(qdict, "memory_range");
1240 monitor_printf(mon,
1241 " memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
1242 qdict_get_int(info, "base"),
1243 qdict_get_int(info, "limit"));
1244
1245 info = qdict_get_qdict(qdict, "prefetchable_range");
1246 monitor_printf(mon, " prefetchable memory range "
1247 "[0x%08"PRIx64", 0x%08"PRIx64"]\n",
1248 qdict_get_int(info, "base"),
1249 qdict_get_int(info, "limit"));
1250 }
1251
1252 QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
1253 qdict = qobject_to_qdict(qlist_entry_obj(entry));
1254 monitor_printf(mon, " BAR%d: ", (int) qdict_get_int(qdict, "bar"));
1255
1256 addr = qdict_get_int(qdict, "address");
1257 size = qdict_get_int(qdict, "size");
1258
1259 if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
1260 monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
1261 " [0x%04"FMT_PCIBUS"].\n",
1262 addr, addr + size - 1);
1263 } else {
1264 monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
1265 " [0x%08"FMT_PCIBUS"].\n",
1266 qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
1267 qdict_get_bool(qdict, "prefetch") ?
1268 " prefetchable" : "", addr, addr + size - 1);
1269 }
1270 }
1271
1272 monitor_printf(mon, " id \"%s\"\n", qdict_get_str(device, "qdev_id"));
1273
1274 if (qdict_haskey(device, "pci_bridge")) {
1275 qdict = qdict_get_qdict(device, "pci_bridge");
1276 if (qdict_haskey(qdict, "devices")) {
1277 QListEntry *dev;
1278 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1279 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1280 }
1281 }
1282 }
1283 }
1284
1285 void do_pci_info_print(Monitor *mon, const QObject *data)
1286 {
1287 QListEntry *bus, *dev;
1288
1289 QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
1290 QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
1291 QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
1292 pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
1293 }
1294 }
1295 }
1296
1297 static QObject *pci_get_dev_class(const PCIDevice *dev)
1298 {
1299 int class;
1300 const pci_class_desc *desc;
1301
1302 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1303 desc = pci_class_descriptions;
1304 while (desc->desc && class != desc->class)
1305 desc++;
1306
1307 if (desc->desc) {
1308 return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
1309 desc->desc, class);
1310 } else {
1311 return qobject_from_jsonf("{ 'class': %d }", class);
1312 }
1313 }
1314
1315 static QObject *pci_get_dev_id(const PCIDevice *dev)
1316 {
1317 return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
1318 pci_get_word(dev->config + PCI_VENDOR_ID),
1319 pci_get_word(dev->config + PCI_DEVICE_ID));
1320 }
1321
1322 static QObject *pci_get_regions_list(const PCIDevice *dev)
1323 {
1324 int i;
1325 QList *regions_list;
1326
1327 regions_list = qlist_new();
1328
1329 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1330 QObject *obj;
1331 const PCIIORegion *r = &dev->io_regions[i];
1332
1333 if (!r->size) {
1334 continue;
1335 }
1336
1337 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1338 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
1339 "'address': %" PRId64 ", "
1340 "'size': %" PRId64 " }",
1341 i, r->addr, r->size);
1342 } else {
1343 int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
1344
1345 obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
1346 "'mem_type_64': %i, 'prefetch': %i, "
1347 "'address': %" PRId64 ", "
1348 "'size': %" PRId64 " }",
1349 i, mem_type_64,
1350 r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
1351 r->addr, r->size);
1352 }
1353
1354 qlist_append_obj(regions_list, obj);
1355 }
1356
1357 return QOBJECT(regions_list);
1358 }
1359
1360 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
1361
1362 static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
1363 {
1364 uint8_t type;
1365 QObject *obj;
1366
1367 obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
1368 " 'qdev_id': %s }",
1369 bus_num,
1370 PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
1371 pci_get_dev_class(dev), pci_get_dev_id(dev),
1372 pci_get_regions_list(dev),
1373 dev->qdev.id ? dev->qdev.id : "");
1374
1375 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1376 QDict *qdict = qobject_to_qdict(obj);
1377 qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
1378 }
1379
1380 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1381 if (type == PCI_HEADER_TYPE_BRIDGE) {
1382 QDict *qdict;
1383 QObject *pci_bridge;
1384
1385 pci_bridge = qobject_from_jsonf("{ 'bus': "
1386 "{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
1387 "'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1388 "'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
1389 "'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
1390 dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
1391 dev->config[PCI_SUBORDINATE_BUS],
1392 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
1393 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
1394 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1395 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
1396 pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1397 PCI_BASE_ADDRESS_MEM_PREFETCH),
1398 pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
1399 PCI_BASE_ADDRESS_MEM_PREFETCH));
1400
1401 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1402 PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
1403
1404 if (child_bus) {
1405 qdict = qobject_to_qdict(pci_bridge);
1406 qdict_put_obj(qdict, "devices",
1407 pci_get_devices_list(child_bus,
1408 dev->config[PCI_SECONDARY_BUS]));
1409 }
1410 }
1411 qdict = qobject_to_qdict(obj);
1412 qdict_put_obj(qdict, "pci_bridge", pci_bridge);
1413 }
1414
1415 return obj;
1416 }
1417
1418 static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
1419 {
1420 int devfn;
1421 PCIDevice *dev;
1422 QList *dev_list;
1423
1424 dev_list = qlist_new();
1425
1426 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1427 dev = bus->devices[devfn];
1428 if (dev) {
1429 qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
1430 }
1431 }
1432
1433 return QOBJECT(dev_list);
1434 }
1435
1436 static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
1437 {
1438 bus = pci_find_bus(bus, bus_num);
1439 if (bus) {
1440 return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
1441 bus_num, pci_get_devices_list(bus, bus_num));
1442 }
1443
1444 return NULL;
1445 }
1446
1447 void do_pci_info(Monitor *mon, QObject **ret_data)
1448 {
1449 QList *bus_list;
1450 struct PCIHostBus *host;
1451
1452 bus_list = qlist_new();
1453
1454 QLIST_FOREACH(host, &host_buses, next) {
1455 QObject *obj = pci_get_bus_dict(host->bus, 0);
1456 if (obj) {
1457 qlist_append_obj(bus_list, obj);
1458 }
1459 }
1460
1461 *ret_data = QOBJECT(bus_list);
1462 }
1463
1464 static const char * const pci_nic_models[] = {
1465 "ne2k_pci",
1466 "i82551",
1467 "i82557b",
1468 "i82559er",
1469 "rtl8139",
1470 "e1000",
1471 "pcnet",
1472 "virtio",
1473 NULL
1474 };
1475
1476 static const char * const pci_nic_names[] = {
1477 "ne2k_pci",
1478 "i82551",
1479 "i82557b",
1480 "i82559er",
1481 "rtl8139",
1482 "e1000",
1483 "pcnet",
1484 "virtio-net-pci",
1485 NULL
1486 };
1487
1488 /* Initialize a PCI NIC. */
1489 /* FIXME callers should check for failure, but don't */
1490 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1491 const char *default_devaddr)
1492 {
1493 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1494 PCIBus *bus;
1495 int devfn;
1496 PCIDevice *pci_dev;
1497 DeviceState *dev;
1498 int i;
1499
1500 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1501 if (i < 0)
1502 return NULL;
1503
1504 bus = pci_get_bus_devfn(&devfn, devaddr);
1505 if (!bus) {
1506 error_report("Invalid PCI device address %s for device %s",
1507 devaddr, pci_nic_names[i]);
1508 return NULL;
1509 }
1510
1511 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1512 dev = &pci_dev->qdev;
1513 qdev_set_nic_properties(dev, nd);
1514 if (qdev_init(dev) < 0)
1515 return NULL;
1516 return pci_dev;
1517 }
1518
1519 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1520 const char *default_devaddr)
1521 {
1522 PCIDevice *res;
1523
1524 if (qemu_show_nic_models(nd->model, pci_nic_models))
1525 exit(0);
1526
1527 res = pci_nic_init(nd, default_model, default_devaddr);
1528 if (!res)
1529 exit(1);
1530 return res;
1531 }
1532
1533 /* Whether a given bus number is in range of the secondary
1534 * bus of the given bridge device. */
1535 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1536 {
1537 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1538 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1539 dev->config[PCI_SECONDARY_BUS] < bus_num &&
1540 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1541 }
1542
1543 PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
1544 {
1545 PCIBus *sec;
1546
1547 if (!bus) {
1548 return NULL;
1549 }
1550
1551 if (pci_bus_num(bus) == bus_num) {
1552 return bus;
1553 }
1554
1555 /* Consider all bus numbers in range for the host pci bridge. */
1556 if (bus->parent_dev &&
1557 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1558 return NULL;
1559 }
1560
1561 /* try child bus */
1562 for (; bus; bus = sec) {
1563 QLIST_FOREACH(sec, &bus->child, sibling) {
1564 assert(sec->parent_dev);
1565 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1566 return sec;
1567 }
1568 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1569 break;
1570 }
1571 }
1572 }
1573
1574 return NULL;
1575 }
1576
1577 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
1578 {
1579 bus = pci_find_bus(bus, bus_num);
1580
1581 if (!bus)
1582 return NULL;
1583
1584 return bus->devices[devfn];
1585 }
1586
1587 static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
1588 {
1589 PCIDevice *pci_dev = (PCIDevice *)qdev;
1590 PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
1591 PCIBus *bus;
1592 int rc;
1593 bool is_default_rom;
1594
1595 /* initialize cap_present for pci_is_express() and pci_config_size() */
1596 if (info->is_express) {
1597 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1598 }
1599
1600 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1601 pci_dev = do_pci_register_device(pci_dev, bus, base->name,
1602 pci_dev->devfn, info);
1603 if (pci_dev == NULL)
1604 return -1;
1605 if (qdev->hotplugged && info->no_hotplug) {
1606 qerror_report(QERR_DEVICE_NO_HOTPLUG, info->qdev.name);
1607 do_pci_unregister_device(pci_dev);
1608 return -1;
1609 }
1610 if (info->init) {
1611 rc = info->init(pci_dev);
1612 if (rc != 0) {
1613 do_pci_unregister_device(pci_dev);
1614 return rc;
1615 }
1616 }
1617
1618 /* rom loading */
1619 is_default_rom = false;
1620 if (pci_dev->romfile == NULL && info->romfile != NULL) {
1621 pci_dev->romfile = g_strdup(info->romfile);
1622 is_default_rom = true;
1623 }
1624 pci_add_option_rom(pci_dev, is_default_rom);
1625
1626 if (bus->hotplug) {
1627 /* Let buses differentiate between hotplug and when device is
1628 * enabled during qemu machine creation. */
1629 rc = bus->hotplug(bus->hotplug_qdev, pci_dev,
1630 qdev->hotplugged ? PCI_HOTPLUG_ENABLED:
1631 PCI_COLDPLUG_ENABLED);
1632 if (rc != 0) {
1633 int r = pci_unregister_device(&pci_dev->qdev);
1634 assert(!r);
1635 return rc;
1636 }
1637 }
1638 return 0;
1639 }
1640
1641 static int pci_unplug_device(DeviceState *qdev)
1642 {
1643 PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
1644 PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev);
1645
1646 if (info->no_hotplug) {
1647 qerror_report(QERR_DEVICE_NO_HOTPLUG, info->qdev.name);
1648 return -1;
1649 }
1650 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev,
1651 PCI_HOTPLUG_DISABLED);
1652 }
1653
1654 void pci_qdev_register(PCIDeviceInfo *info)
1655 {
1656 info->qdev.init = pci_qdev_init;
1657 info->qdev.unplug = pci_unplug_device;
1658 info->qdev.exit = pci_unregister_device;
1659 info->qdev.bus_info = &pci_bus_info;
1660 qdev_register(&info->qdev);
1661 }
1662
1663 void pci_qdev_register_many(PCIDeviceInfo *info)
1664 {
1665 while (info->qdev.name) {
1666 pci_qdev_register(info);
1667 info++;
1668 }
1669 }
1670
1671 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1672 const char *name)
1673 {
1674 DeviceState *dev;
1675
1676 dev = qdev_create(&bus->qbus, name);
1677 qdev_prop_set_uint32(dev, "addr", devfn);
1678 qdev_prop_set_bit(dev, "multifunction", multifunction);
1679 return DO_UPCAST(PCIDevice, qdev, dev);
1680 }
1681
1682 PCIDevice *pci_try_create_multifunction(PCIBus *bus, int devfn,
1683 bool multifunction,
1684 const char *name)
1685 {
1686 DeviceState *dev;
1687
1688 dev = qdev_try_create(&bus->qbus, name);
1689 if (!dev) {
1690 return NULL;
1691 }
1692 qdev_prop_set_uint32(dev, "addr", devfn);
1693 qdev_prop_set_bit(dev, "multifunction", multifunction);
1694 return DO_UPCAST(PCIDevice, qdev, dev);
1695 }
1696
1697 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1698 bool multifunction,
1699 const char *name)
1700 {
1701 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1702 qdev_init_nofail(&dev->qdev);
1703 return dev;
1704 }
1705
1706 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1707 {
1708 return pci_create_multifunction(bus, devfn, false, name);
1709 }
1710
1711 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1712 {
1713 return pci_create_simple_multifunction(bus, devfn, false, name);
1714 }
1715
1716 PCIDevice *pci_try_create(PCIBus *bus, int devfn, const char *name)
1717 {
1718 return pci_try_create_multifunction(bus, devfn, false, name);
1719 }
1720
1721 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1722 {
1723 int config_size = pci_config_size(pdev);
1724 int offset = PCI_CONFIG_HEADER_SIZE;
1725 int i;
1726 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1727 if (pdev->used[i])
1728 offset = i + 1;
1729 else if (i - offset + 1 == size)
1730 return offset;
1731 return 0;
1732 }
1733
1734 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1735 uint8_t *prev_p)
1736 {
1737 uint8_t next, prev;
1738
1739 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1740 return 0;
1741
1742 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1743 prev = next + PCI_CAP_LIST_NEXT)
1744 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1745 break;
1746
1747 if (prev_p)
1748 *prev_p = prev;
1749 return next;
1750 }
1751
1752 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
1753 {
1754 uint8_t next, prev, found = 0;
1755
1756 if (!(pdev->used[offset])) {
1757 return 0;
1758 }
1759
1760 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
1761
1762 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1763 prev = next + PCI_CAP_LIST_NEXT) {
1764 if (next <= offset && next > found) {
1765 found = next;
1766 }
1767 }
1768 return found;
1769 }
1770
1771 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1772 This is needed for an option rom which is used for more than one device. */
1773 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
1774 {
1775 uint16_t vendor_id;
1776 uint16_t device_id;
1777 uint16_t rom_vendor_id;
1778 uint16_t rom_device_id;
1779 uint16_t rom_magic;
1780 uint16_t pcir_offset;
1781 uint8_t checksum;
1782
1783 /* Words in rom data are little endian (like in PCI configuration),
1784 so they can be read / written with pci_get_word / pci_set_word. */
1785
1786 /* Only a valid rom will be patched. */
1787 rom_magic = pci_get_word(ptr);
1788 if (rom_magic != 0xaa55) {
1789 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
1790 return;
1791 }
1792 pcir_offset = pci_get_word(ptr + 0x18);
1793 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
1794 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
1795 return;
1796 }
1797
1798 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
1799 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
1800 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
1801 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
1802
1803 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
1804 vendor_id, device_id, rom_vendor_id, rom_device_id);
1805
1806 checksum = ptr[6];
1807
1808 if (vendor_id != rom_vendor_id) {
1809 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1810 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
1811 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
1812 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1813 ptr[6] = checksum;
1814 pci_set_word(ptr + pcir_offset + 4, vendor_id);
1815 }
1816
1817 if (device_id != rom_device_id) {
1818 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1819 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
1820 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
1821 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1822 ptr[6] = checksum;
1823 pci_set_word(ptr + pcir_offset + 6, device_id);
1824 }
1825 }
1826
1827 /* Add an option rom for the device */
1828 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
1829 {
1830 int size;
1831 char *path;
1832 void *ptr;
1833 char name[32];
1834
1835 if (!pdev->romfile)
1836 return 0;
1837 if (strlen(pdev->romfile) == 0)
1838 return 0;
1839
1840 if (!pdev->rom_bar) {
1841 /*
1842 * Load rom via fw_cfg instead of creating a rom bar,
1843 * for 0.11 compatibility.
1844 */
1845 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1846 if (class == 0x0300) {
1847 rom_add_vga(pdev->romfile);
1848 } else {
1849 rom_add_option(pdev->romfile, -1);
1850 }
1851 return 0;
1852 }
1853
1854 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1855 if (path == NULL) {
1856 path = g_strdup(pdev->romfile);
1857 }
1858
1859 size = get_image_size(path);
1860 if (size < 0) {
1861 error_report("%s: failed to find romfile \"%s\"",
1862 __FUNCTION__, pdev->romfile);
1863 g_free(path);
1864 return -1;
1865 }
1866 if (size & (size - 1)) {
1867 size = 1 << qemu_fls(size);
1868 }
1869
1870 if (pdev->qdev.info->vmsd)
1871 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
1872 else
1873 snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
1874 pdev->has_rom = true;
1875 memory_region_init_ram(&pdev->rom, &pdev->qdev, name, size);
1876 ptr = memory_region_get_ram_ptr(&pdev->rom);
1877 load_image(path, ptr);
1878 g_free(path);
1879
1880 if (is_default_rom) {
1881 /* Only the default rom images will be patched (if needed). */
1882 pci_patch_ids(pdev, ptr, size);
1883 }
1884
1885 qemu_put_ram_ptr(ptr);
1886
1887 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
1888
1889 return 0;
1890 }
1891
1892 static void pci_del_option_rom(PCIDevice *pdev)
1893 {
1894 if (!pdev->has_rom)
1895 return;
1896
1897 memory_region_destroy(&pdev->rom);
1898 pdev->has_rom = false;
1899 }
1900
1901 /*
1902 * if !offset
1903 * Reserve space and add capability to the linked list in pci config space
1904 *
1905 * if offset = 0,
1906 * Find and reserve space and add capability to the linked list
1907 * in pci config space */
1908 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
1909 uint8_t offset, uint8_t size)
1910 {
1911 uint8_t *config;
1912 int i, overlapping_cap;
1913
1914 if (!offset) {
1915 offset = pci_find_space(pdev, size);
1916 if (!offset) {
1917 return -ENOSPC;
1918 }
1919 } else {
1920 /* Verify that capabilities don't overlap. Note: device assignment
1921 * depends on this check to verify that the device is not broken.
1922 * Should never trigger for emulated devices, but it's helpful
1923 * for debugging these. */
1924 for (i = offset; i < offset + size; i++) {
1925 overlapping_cap = pci_find_capability_at_offset(pdev, i);
1926 if (overlapping_cap) {
1927 fprintf(stderr, "ERROR: %04x:%02x:%02x.%x "
1928 "Attempt to add PCI capability %x at offset "
1929 "%x overlaps existing capability %x at offset %x\n",
1930 pci_find_domain(pdev->bus), pci_bus_num(pdev->bus),
1931 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1932 cap_id, offset, overlapping_cap, i);
1933 return -EINVAL;
1934 }
1935 }
1936 }
1937
1938 config = pdev->config + offset;
1939 config[PCI_CAP_LIST_ID] = cap_id;
1940 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1941 pdev->config[PCI_CAPABILITY_LIST] = offset;
1942 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1943 memset(pdev->used + offset, 0xFF, size);
1944 /* Make capability read-only by default */
1945 memset(pdev->wmask + offset, 0, size);
1946 /* Check capability by default */
1947 memset(pdev->cmask + offset, 0xFF, size);
1948 return offset;
1949 }
1950
1951 /* Unlink capability from the pci config space. */
1952 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1953 {
1954 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1955 if (!offset)
1956 return;
1957 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1958 /* Make capability writable again */
1959 memset(pdev->wmask + offset, 0xff, size);
1960 memset(pdev->w1cmask + offset, 0, size);
1961 /* Clear cmask as device-specific registers can't be checked */
1962 memset(pdev->cmask + offset, 0, size);
1963 memset(pdev->used + offset, 0, size);
1964
1965 if (!pdev->config[PCI_CAPABILITY_LIST])
1966 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1967 }
1968
1969 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1970 {
1971 return pci_find_capability_list(pdev, cap_id, NULL);
1972 }
1973
1974 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1975 {
1976 PCIDevice *d = (PCIDevice *)dev;
1977 const pci_class_desc *desc;
1978 char ctxt[64];
1979 PCIIORegion *r;
1980 int i, class;
1981
1982 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1983 desc = pci_class_descriptions;
1984 while (desc->desc && class != desc->class)
1985 desc++;
1986 if (desc->desc) {
1987 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1988 } else {
1989 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1990 }
1991
1992 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1993 "pci id %04x:%04x (sub %04x:%04x)\n",
1994 indent, "", ctxt, pci_bus_num(d->bus),
1995 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1996 pci_get_word(d->config + PCI_VENDOR_ID),
1997 pci_get_word(d->config + PCI_DEVICE_ID),
1998 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1999 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
2000 for (i = 0; i < PCI_NUM_REGIONS; i++) {
2001 r = &d->io_regions[i];
2002 if (!r->size)
2003 continue;
2004 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
2005 " [0x%"FMT_PCIBUS"]\n",
2006 indent, "",
2007 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
2008 r->addr, r->addr + r->size - 1);
2009 }
2010 }
2011
2012 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
2013 {
2014 PCIDevice *d = (PCIDevice *)dev;
2015 const char *name = NULL;
2016 const pci_class_desc *desc = pci_class_descriptions;
2017 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
2018
2019 while (desc->desc &&
2020 (class & ~desc->fw_ign_bits) !=
2021 (desc->class & ~desc->fw_ign_bits)) {
2022 desc++;
2023 }
2024
2025 if (desc->desc) {
2026 name = desc->fw_name;
2027 }
2028
2029 if (name) {
2030 pstrcpy(buf, len, name);
2031 } else {
2032 snprintf(buf, len, "pci%04x,%04x",
2033 pci_get_word(d->config + PCI_VENDOR_ID),
2034 pci_get_word(d->config + PCI_DEVICE_ID));
2035 }
2036
2037 return buf;
2038 }
2039
2040 static char *pcibus_get_fw_dev_path(DeviceState *dev)
2041 {
2042 PCIDevice *d = (PCIDevice *)dev;
2043 char path[50], name[33];
2044 int off;
2045
2046 off = snprintf(path, sizeof(path), "%s@%x",
2047 pci_dev_fw_name(dev, name, sizeof name),
2048 PCI_SLOT(d->devfn));
2049 if (PCI_FUNC(d->devfn))
2050 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
2051 return strdup(path);
2052 }
2053
2054 static char *pcibus_get_dev_path(DeviceState *dev)
2055 {
2056 PCIDevice *d = container_of(dev, PCIDevice, qdev);
2057 PCIDevice *t;
2058 int slot_depth;
2059 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
2060 * 00 is added here to make this format compatible with
2061 * domain:Bus:Slot.Func for systems without nested PCI bridges.
2062 * Slot.Function list specifies the slot and function numbers for all
2063 * devices on the path from root to the specific device. */
2064 char domain[] = "DDDD:00";
2065 char slot[] = ":SS.F";
2066 int domain_len = sizeof domain - 1 /* For '\0' */;
2067 int slot_len = sizeof slot - 1 /* For '\0' */;
2068 int path_len;
2069 char *path, *p;
2070 int s;
2071
2072 /* Calculate # of slots on path between device and root. */;
2073 slot_depth = 0;
2074 for (t = d; t; t = t->bus->parent_dev) {
2075 ++slot_depth;
2076 }
2077
2078 path_len = domain_len + slot_len * slot_depth;
2079
2080 /* Allocate memory, fill in the terminating null byte. */
2081 path = g_malloc(path_len + 1 /* For '\0' */);
2082 path[path_len] = '\0';
2083
2084 /* First field is the domain. */
2085 s = snprintf(domain, sizeof domain, "%04x:00", pci_find_domain(d->bus));
2086 assert(s == domain_len);
2087 memcpy(path, domain, domain_len);
2088
2089 /* Fill in slot numbers. We walk up from device to root, so need to print
2090 * them in the reverse order, last to first. */
2091 p = path + path_len;
2092 for (t = d; t; t = t->bus->parent_dev) {
2093 p -= slot_len;
2094 s = snprintf(slot, sizeof slot, ":%02x.%x",
2095 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
2096 assert(s == slot_len);
2097 memcpy(p, slot, slot_len);
2098 }
2099
2100 return path;
2101 }
2102
2103 static int pci_qdev_find_recursive(PCIBus *bus,
2104 const char *id, PCIDevice **pdev)
2105 {
2106 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
2107 if (!qdev) {
2108 return -ENODEV;
2109 }
2110
2111 /* roughly check if given qdev is pci device */
2112 if (qdev->info->init == &pci_qdev_init &&
2113 qdev->parent_bus->info == &pci_bus_info) {
2114 *pdev = DO_UPCAST(PCIDevice, qdev, qdev);
2115 return 0;
2116 }
2117 return -EINVAL;
2118 }
2119
2120 int pci_qdev_find_device(const char *id, PCIDevice **pdev)
2121 {
2122 struct PCIHostBus *host;
2123 int rc = -ENODEV;
2124
2125 QLIST_FOREACH(host, &host_buses, next) {
2126 int tmp = pci_qdev_find_recursive(host->bus, id, pdev);
2127 if (!tmp) {
2128 rc = 0;
2129 break;
2130 }
2131 if (tmp != -ENODEV) {
2132 rc = tmp;
2133 }
2134 }
2135
2136 return rc;
2137 }
2138
2139 MemoryRegion *pci_address_space(PCIDevice *dev)
2140 {
2141 return dev->bus->address_space_mem;
2142 }
2143
2144 MemoryRegion *pci_address_space_io(PCIDevice *dev)
2145 {
2146 return dev->bus->address_space_io;
2147 }
various patches