2 * This declarations of the PIC16F785 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:22:59 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16F785_H__
26 #define __PIC16F785_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF_ADDR 0x0000
37 #define TMR0_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR_ADDR 0x0004
41 #define PORTA_ADDR 0x0005
42 #define PORTB_ADDR 0x0006
43 #define PORTC_ADDR 0x0007
44 #define PCLATH_ADDR 0x000A
45 #define INTCON_ADDR 0x000B
46 #define PIR1_ADDR 0x000C
47 #define TMR1_ADDR 0x000E
48 #define TMR1L_ADDR 0x000E
49 #define TMR1H_ADDR 0x000F
50 #define T1CON_ADDR 0x0010
51 #define TMR2_ADDR 0x0011
52 #define T2CON_ADDR 0x0012
53 #define CCPR_ADDR 0x0013
54 #define CCPR1L_ADDR 0x0013
55 #define CCPR1H_ADDR 0x0014
56 #define CCP1CON_ADDR 0x0015
57 #define WDTCON_ADDR 0x0018
58 #define ADRESH_ADDR 0x001E
59 #define ADCON0_ADDR 0x001F
60 #define OPTION_REG_ADDR 0x0081
61 #define TRISA_ADDR 0x0085
62 #define TRISB_ADDR 0x0086
63 #define TRISC_ADDR 0x0087
64 #define PIE1_ADDR 0x008C
65 #define PCON_ADDR 0x008E
66 #define OSCCON_ADDR 0x008F
67 #define OSCTUNE_ADDR 0x0090
68 #define ANSEL_ADDR 0x0091
69 #define ANSEL0_ADDR 0x0091
70 #define PR2_ADDR 0x0092
71 #define ANSEL1_ADDR 0x0093
72 #define WPU_ADDR 0x0095
73 #define WPUA_ADDR 0x0095
74 #define IOC_ADDR 0x0096
75 #define IOCA_ADDR 0x0096
76 #define REFCON_ADDR 0x0098
77 #define VRCON_ADDR 0x0099
78 #define EEDAT_ADDR 0x009A
79 #define EEDATA_ADDR 0x009A
80 #define EEADR_ADDR 0x009B
81 #define EECON1_ADDR 0x009C
82 #define EECON2_ADDR 0x009D
83 #define ADRESL_ADDR 0x009E
84 #define ADCON1_ADDR 0x009F
85 #define PWMCON1_ADDR 0x0110
86 #define PWMCON0_ADDR 0x0111
87 #define PWMCLK_ADDR 0x0112
88 #define PWMPH1_ADDR 0x0113
89 #define PWMPH2_ADDR 0x0114
90 #define CM1CON0_ADDR 0x0119
91 #define CM2CON0_ADDR 0x011A
92 #define CM2CON1_ADDR 0x011B
93 #define OPA1CON_ADDR 0x011C
94 #define OPA2CON_ADDR 0x011D
96 #endif // #ifndef NO_ADDR_DEFINES
98 //==============================================================================
100 // Register Definitions
102 //==============================================================================
104 extern __at(0x0000) __sfr INDF
;
105 extern __at(0x0001) __sfr TMR0
;
106 extern __at(0x0002) __sfr PCL
;
108 //==============================================================================
111 extern __at(0x0003) __sfr STATUS
;
135 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
146 //==============================================================================
148 extern __at(0x0004) __sfr FSR
;
150 //==============================================================================
153 extern __at(0x0005) __sfr PORTA
;
176 extern __at(0x0005) volatile __PORTAbits_t PORTAbits
;
185 //==============================================================================
188 //==============================================================================
191 extern __at(0x0006) __sfr PORTB
;
205 extern __at(0x0006) volatile __PORTBbits_t PORTBbits
;
212 //==============================================================================
215 //==============================================================================
218 extern __at(0x0007) __sfr PORTC
;
232 extern __at(0x0007) volatile __PORTCbits_t PORTCbits
;
243 //==============================================================================
245 extern __at(0x000A) __sfr PCLATH
;
247 //==============================================================================
250 extern __at(0x000B) __sfr INTCON
;
279 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
292 //==============================================================================
295 //==============================================================================
298 extern __at(0x000C) __sfr PIR1
;
327 extern __at(0x000C) volatile __PIR1bits_t PIR1bits
;
340 //==============================================================================
342 extern __at(0x000E) __sfr TMR1
;
343 extern __at(0x000E) __sfr TMR1L
;
344 extern __at(0x000F) __sfr TMR1H
;
346 //==============================================================================
349 extern __at(0x0010) __sfr T1CON
;
357 unsigned NOT_T1SYNC
: 1;
358 unsigned T1OSCEN
: 1;
359 unsigned T1CKPS0
: 1;
360 unsigned T1CKPS1
: 1;
385 extern __at(0x0010) volatile __T1CONbits_t T1CONbits
;
389 #define _NOT_T1SYNC 0x04
390 #define _T1OSCEN 0x08
391 #define _T1CKPS0 0x10
392 #define _T1CKPS1 0x20
397 //==============================================================================
399 extern __at(0x0011) __sfr TMR2
;
401 //==============================================================================
404 extern __at(0x0012) __sfr T2CON
;
410 unsigned T2CKPS0
: 1;
411 unsigned T2CKPS1
: 1;
413 unsigned TOUTPS0
: 1;
414 unsigned TOUTPS1
: 1;
415 unsigned TOUTPS2
: 1;
416 unsigned TOUTPS3
: 1;
434 extern __at(0x0012) volatile __T2CONbits_t T2CONbits
;
436 #define _T2CKPS0 0x01
437 #define _T2CKPS1 0x02
439 #define _TOUTPS0 0x08
440 #define _TOUTPS1 0x10
441 #define _TOUTPS2 0x20
442 #define _TOUTPS3 0x40
444 //==============================================================================
446 extern __at(0x0013) __sfr CCPR
;
447 extern __at(0x0013) __sfr CCPR1L
;
448 extern __at(0x0014) __sfr CCPR1H
;
450 //==============================================================================
453 extern __at(0x0015) __sfr CCP1CON
;
483 extern __at(0x0015) volatile __CCP1CONbits_t CCP1CONbits
;
492 //==============================================================================
495 //==============================================================================
498 extern __at(0x0018) __sfr WDTCON
;
522 extern __at(0x0018) volatile __WDTCONbits_t WDTCONbits
;
530 //==============================================================================
532 extern __at(0x001E) __sfr ADRESH
;
534 //==============================================================================
537 extern __at(0x001F) __sfr ADCON0
;
544 unsigned GO_NOT_DONE
: 1;
568 unsigned NOT_DONE
: 1;
580 unsigned GO_DONE
: 1;
597 extern __at(0x001F) volatile __ADCON0bits_t ADCON0bits
;
600 #define _GO_NOT_DONE 0x02
602 #define _NOT_DONE 0x02
603 #define _GO_DONE 0x02
611 //==============================================================================
614 //==============================================================================
617 extern __at(0x0081) __sfr OPTION_REG
;
630 unsigned NOT_RAPU
: 1;
638 } __OPTION_REGbits_t
;
640 extern __at(0x0081) volatile __OPTION_REGbits_t OPTION_REGbits
;
649 #define _NOT_RAPU 0x80
651 //==============================================================================
654 //==============================================================================
657 extern __at(0x0085) __sfr TRISA
;
680 extern __at(0x0085) volatile __TRISAbits_t TRISAbits
;
689 //==============================================================================
692 //==============================================================================
695 extern __at(0x0086) __sfr TRISB
;
709 extern __at(0x0086) volatile __TRISBbits_t TRISBbits
;
716 //==============================================================================
719 //==============================================================================
722 extern __at(0x0087) __sfr TRISC
;
736 extern __at(0x0087) volatile __TRISCbits_t TRISCbits
;
747 //==============================================================================
750 //==============================================================================
753 extern __at(0x008C) __sfr PIE1
;
782 extern __at(0x008C) volatile __PIE1bits_t PIE1bits
;
795 //==============================================================================
798 //==============================================================================
801 extern __at(0x008E) __sfr PCON
;
807 unsigned NOT_BOR
: 1;
808 unsigned NOT_POR
: 1;
819 unsigned NOT_BOD
: 1;
830 extern __at(0x008E) volatile __PCONbits_t PCONbits
;
832 #define _NOT_BOR 0x01
833 #define _NOT_BOD 0x01
834 #define _NOT_POR 0x02
838 //==============================================================================
841 //==============================================================================
844 extern __at(0x008F) __sfr OSCCON
;
868 extern __at(0x008F) volatile __OSCCONbits_t OSCCONbits
;
878 //==============================================================================
881 //==============================================================================
884 extern __at(0x0090) __sfr OSCTUNE
;
907 extern __at(0x0090) volatile __OSCTUNEbits_t OSCTUNEbits
;
915 //==============================================================================
918 //==============================================================================
921 extern __at(0x0091) __sfr ANSEL
;
935 extern __at(0x0091) volatile __ANSELbits_t ANSELbits
;
946 //==============================================================================
949 //==============================================================================
952 extern __at(0x0091) __sfr ANSEL0
;
966 extern __at(0x0091) volatile __ANSEL0bits_t ANSEL0bits
;
968 #define _ANSEL0_ANS0 0x01
969 #define _ANSEL0_ANS1 0x02
970 #define _ANSEL0_ANS2 0x04
971 #define _ANSEL0_ANS3 0x08
972 #define _ANSEL0_ANS4 0x10
973 #define _ANSEL0_ANS5 0x20
974 #define _ANSEL0_ANS6 0x40
975 #define _ANSEL0_ANS7 0x80
977 //==============================================================================
979 extern __at(0x0092) __sfr PR2
;
981 //==============================================================================
984 extern __at(0x0093) __sfr ANSEL1
;
998 extern __at(0x0093) volatile __ANSEL1bits_t ANSEL1bits
;
1005 //==============================================================================
1008 //==============================================================================
1011 extern __at(0x0095) __sfr WPU
;
1052 extern __at(0x0095) volatile __WPUbits_t WPUbits
;
1067 //==============================================================================
1070 //==============================================================================
1073 extern __at(0x0095) __sfr WPUA
;
1114 extern __at(0x0095) volatile __WPUAbits_t WPUAbits
;
1116 #define _WPUA_WPUA0 0x01
1117 #define _WPUA_WPU0 0x01
1118 #define _WPUA_WPUA1 0x02
1119 #define _WPUA_WPU1 0x02
1120 #define _WPUA_WPUA2 0x04
1121 #define _WPUA_WPU2 0x04
1122 #define _WPUA_WPUA3 0x08
1123 #define _WPUA_WPU3 0x08
1124 #define _WPUA_WPUA4 0x10
1125 #define _WPUA_WPU4 0x10
1126 #define _WPUA_WPUA5 0x20
1127 #define _WPUA_WPU5 0x20
1129 //==============================================================================
1132 //==============================================================================
1135 extern __at(0x0096) __sfr IOC
;
1176 extern __at(0x0096) volatile __IOCbits_t IOCbits
;
1191 //==============================================================================
1194 //==============================================================================
1197 extern __at(0x0096) __sfr IOCA
;
1238 extern __at(0x0096) volatile __IOCAbits_t IOCAbits
;
1240 #define _IOCA_IOCA0 0x01
1241 #define _IOCA_IOC0 0x01
1242 #define _IOCA_IOCA1 0x02
1243 #define _IOCA_IOC1 0x02
1244 #define _IOCA_IOCA2 0x04
1245 #define _IOCA_IOC2 0x04
1246 #define _IOCA_IOCA3 0x08
1247 #define _IOCA_IOC3 0x08
1248 #define _IOCA_IOCA4 0x10
1249 #define _IOCA_IOC4 0x10
1250 #define _IOCA_IOCA5 0x20
1251 #define _IOCA_IOC5 0x20
1253 //==============================================================================
1256 //==============================================================================
1259 extern __at(0x0098) __sfr REFCON
;
1273 extern __at(0x0098) volatile __REFCONbits_t REFCONbits
;
1281 //==============================================================================
1284 //==============================================================================
1287 extern __at(0x0099) __sfr VRCON
;
1299 unsigned C2VREN
: 1;
1300 unsigned C1VREN
: 1;
1310 extern __at(0x0099) volatile __VRCONbits_t VRCONbits
;
1317 #define _C2VREN 0x40
1318 #define _C1VREN 0x80
1320 //==============================================================================
1322 extern __at(0x009A) __sfr EEDAT
;
1323 extern __at(0x009A) __sfr EEDATA
;
1324 extern __at(0x009B) __sfr EEADR
;
1326 //==============================================================================
1329 extern __at(0x009C) __sfr EECON1
;
1343 extern __at(0x009C) volatile __EECON1bits_t EECON1bits
;
1350 //==============================================================================
1352 extern __at(0x009D) __sfr EECON2
;
1353 extern __at(0x009E) __sfr ADRESL
;
1355 //==============================================================================
1358 extern __at(0x009F) __sfr ADCON1
;
1382 extern __at(0x009F) volatile __ADCON1bits_t ADCON1bits
;
1388 //==============================================================================
1391 //==============================================================================
1394 extern __at(0x0110) __sfr PWMCON1
;
1400 unsigned CMDLY0
: 1;
1401 unsigned CMDLY1
: 1;
1402 unsigned CMDLY2
: 1;
1403 unsigned CMDLY3
: 1;
1404 unsigned CMDLY4
: 1;
1405 unsigned COMOD0
: 1;
1406 unsigned COMOD1
: 1;
1424 extern __at(0x0110) volatile __PWMCON1bits_t PWMCON1bits
;
1426 #define _CMDLY0 0x01
1427 #define _CMDLY1 0x02
1428 #define _CMDLY2 0x04
1429 #define _CMDLY3 0x08
1430 #define _CMDLY4 0x10
1431 #define _COMOD0 0x20
1432 #define _COMOD1 0x40
1435 //==============================================================================
1438 //==============================================================================
1441 extern __at(0x0111) __sfr PWMCON0
;
1451 unsigned BLANK1
: 1;
1452 unsigned BLANK2
: 1;
1465 extern __at(0x0111) volatile __PWMCON0bits_t PWMCON0bits
;
1471 #define _BLANK1 0x10
1472 #define _BLANK2 0x20
1476 //==============================================================================
1479 //==============================================================================
1482 extern __at(0x0112) __sfr PWMCLK
;
1495 unsigned PWMASE
: 1;
1512 extern __at(0x0112) volatile __PWMCLKbits_t PWMCLKbits
;
1521 #define _PWMASE 0x80
1523 //==============================================================================
1526 //==============================================================================
1529 extern __at(0x0113) __sfr PWMPH1
;
1552 extern __at(0x0113) volatile __PWMPH1bits_t PWMPH1bits
;
1563 //==============================================================================
1566 //==============================================================================
1569 extern __at(0x0114) __sfr PWMPH2
;
1592 extern __at(0x0114) volatile __PWMPH2bits_t PWMPH2bits
;
1594 #define _PWMPH2_PH0 0x01
1595 #define _PWMPH2_PH1 0x02
1596 #define _PWMPH2_PH2 0x04
1597 #define _PWMPH2_PH3 0x08
1598 #define _PWMPH2_PH4 0x10
1599 #define _PWMPH2_C1EN 0x20
1600 #define _PWMPH2_C2EN 0x40
1601 #define _PWMPH2_POL 0x80
1603 //==============================================================================
1606 //==============================================================================
1609 extern __at(0x0119) __sfr CM1CON0
;
1632 extern __at(0x0119) volatile __CM1CON0bits_t CM1CON0bits
;
1643 //==============================================================================
1646 //==============================================================================
1649 extern __at(0x011A) __sfr CM2CON0
;
1672 extern __at(0x011A) volatile __CM2CON0bits_t CM2CON0bits
;
1683 //==============================================================================
1686 //==============================================================================
1689 extern __at(0x011B) __sfr CM2CON1
;
1693 unsigned C2SYNC
: 1;
1699 unsigned MC2OUT
: 1;
1700 unsigned MC1OUT
: 1;
1703 extern __at(0x011B) volatile __CM2CON1bits_t CM2CON1bits
;
1705 #define _C2SYNC 0x01
1707 #define _MC2OUT 0x40
1708 #define _MC1OUT 0x80
1710 //==============================================================================
1713 //==============================================================================
1716 extern __at(0x011C) __sfr OPA1CON
;
1730 extern __at(0x011C) volatile __OPA1CONbits_t OPA1CONbits
;
1734 //==============================================================================
1737 //==============================================================================
1740 extern __at(0x011D) __sfr OPA2CON
;
1754 extern __at(0x011D) volatile __OPA2CONbits_t OPA2CONbits
;
1756 #define _OPA2CON_OPAON 0x80
1758 //==============================================================================
1761 //==============================================================================
1763 // Configuration Bits
1765 //==============================================================================
1767 #define _CONFIG 0x2007
1769 //----------------------------- CONFIG Options -------------------------------
1771 #define _FOSC_LP 0x3FF8 // LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN.
1772 #define _LP_OSC 0x3FF8 // LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN.
1773 #define _FOSC_XT 0x3FF9 // XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKINT.
1774 #define _XT_OSC 0x3FF9 // XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKINT.
1775 #define _FOSC_HS 0x3FFA // HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN.
1776 #define _HS_OSC 0x3FFA // HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN.
1777 #define _FOSC_EC 0x3FFB // EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN.
1778 #define _EC_OSC 0x3FFB // EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN.
1779 #define _FOSC_INTOSCIO 0x3FFC // INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1780 #define _INTOSCIO 0x3FFC // INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1781 #define _INTRC_OSC_NOCLKOUT 0x3FFC // INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1782 #define _FOSC_INTOSCCLK 0x3FFD // INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1783 #define _INTOSC 0x3FFD // INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1784 #define _INTRC_OSC_CLKOUT 0x3FFD // INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1785 #define _FOSC_EXTRCIO 0x3FFE // EXTRCIO oscillator: External RC on RA5/OSC1/CLKIN, I/O function on RA4/OSC2/CLKOUT pin.
1786 #define _EXTRCIO 0x3FFE // EXTRCIO oscillator: External RC on RA5/OSC1/CLKIN, I/O function on RA4/OSC2/CLKOUT pin.
1787 #define _EXTRC_OSC_NOCLKOUT 0x3FFE // EXTRCIO oscillator: External RC on RA5/OSC1/CLKIN, I/O function on RA4/OSC2/CLKOUT pin.
1788 #define _FOSC_EXTRCCLK 0x3FFF // EXTRC oscillator: External RC on RA5/OSC1/CLKIN, CLKOUT function on RA4/OSC2/CLKOUT pin.
1789 #define _EXTRC 0x3FFF // EXTRC oscillator: External RC on RA5/OSC1/CLKIN, CLKOUT function on RA4/OSC2/CLKOUT pin.
1790 #define _EXTRC_OSC_CLKOUT 0x3FFF // EXTRC oscillator: External RC on RA5/OSC1/CLKIN, CLKOUT function on RA4/OSC2/CLKOUT pin.
1791 #define _WDTE_OFF 0x3FF7 // WDT disabled.
1792 #define _WDT_OFF 0x3FF7 // WDT disabled.
1793 #define _WDTE_ON 0x3FFF // WDT enabled.
1794 #define _WDT_ON 0x3FFF // WDT enabled.
1795 #define _PWRTE_ON 0x3FEF // PWRT enabled.
1796 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
1797 #define _MCLRE_OFF 0x3FDF // MCLR pin function is digital input, MCLR internally tied to VDD.
1798 #define _MCLRE_ON 0x3FFF // MCLR pin function is MCLR.
1799 #define _CP_ON 0x3FBF // Program memory code protection is enabled.
1800 #define _CP_OFF 0x3FFF // Program memory code protection is disabled.
1801 #define _CPD_ON 0x3F7F // Data memory code protection is enabled.
1802 #define _CPD_OFF 0x3FFF // Data memory code protection is disabled.
1803 #define _BOREN_OFF 0x3CFF // BOR disabled.
1804 #define _BOD_OFF 0x3CFF // BOR disabled.
1805 #define _BOR_OFF 0x3CFF // BOR disabled.
1806 #define _BOREN_SBODEN 0x3DFF // BOR controlled by SBOREN bit of the PCON register.
1807 #define _BOR_SBOREN 0x3DFF // BOR controlled by SBOREN bit of the PCON register.
1808 #define _BOD_SBODEN 0x3DFF // BOR controlled by SBOREN bit of the PCON register.
1809 #define _BOR_SBODEN 0x3DFF // BOR controlled by SBOREN bit of the PCON register.
1810 #define _BOREN_NSLEEP 0x3EFF // BOR enabled during operation and disabled in Sleep.
1811 #define _BOD_NSLEEP 0x3EFF // BOR enabled during operation and disabled in Sleep.
1812 #define _BOR_NSLEEP 0x3EFF // BOR enabled during operation and disabled in Sleep.
1813 #define _BOREN_ON 0x3FFF // BOR enabled.
1814 #define _BOD_ON 0x3FFF // BOR enabled.
1815 #define _BOR_ON 0x3FFF // BOR enabled.
1816 #define _IESO_OFF 0x3BFF // Internal External Switchover mode is disabled.
1817 #define _IESO_ON 0x3FFF // Internal External Switchover mode is enabled.
1818 #define _FCMEN_OFF 0x37FF // Fail-Safe Clock Monitor is disabled.
1819 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
1821 //==============================================================================
1823 #define _DEVID1 0x2006
1825 #define _IDLOC0 0x2000
1826 #define _IDLOC1 0x2001
1827 #define _IDLOC2 0x2002
1828 #define _IDLOC3 0x2003
1830 //==============================================================================
1832 #ifndef NO_BIT_DEFINES
1834 #define ADON ADCON0bits.ADON // bit 0
1835 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
1836 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
1837 #define NOT_DONE ADCON0bits.NOT_DONE // bit 1, shadows bit in ADCON0bits
1838 #define GO_DONE ADCON0bits.GO_DONE // bit 1, shadows bit in ADCON0bits
1839 #define CHS0 ADCON0bits.CHS0 // bit 2
1840 #define CHS1 ADCON0bits.CHS1 // bit 3
1841 #define CHS2 ADCON0bits.CHS2 // bit 4
1842 #define CHS3 ADCON0bits.CHS3 // bit 5
1843 #define VCFG ADCON0bits.VCFG // bit 6
1844 #define ADFM ADCON0bits.ADFM // bit 7
1846 #define ADCS0 ADCON1bits.ADCS0 // bit 4
1847 #define ADCS1 ADCON1bits.ADCS1 // bit 5
1848 #define ADCS2 ADCON1bits.ADCS2 // bit 6
1850 #define ANS0 ANSELbits.ANS0 // bit 0
1851 #define ANS1 ANSELbits.ANS1 // bit 1
1852 #define ANS2 ANSELbits.ANS2 // bit 2
1853 #define ANS3 ANSELbits.ANS3 // bit 3
1854 #define ANS4 ANSELbits.ANS4 // bit 4
1855 #define ANS5 ANSELbits.ANS5 // bit 5
1856 #define ANS6 ANSELbits.ANS6 // bit 6
1857 #define ANS7 ANSELbits.ANS7 // bit 7
1859 #define ANS8 ANSEL1bits.ANS8 // bit 0
1860 #define ANS9 ANSEL1bits.ANS9 // bit 1
1861 #define ANS10 ANSEL1bits.ANS10 // bit 2
1862 #define ANS11 ANSEL1bits.ANS11 // bit 3
1864 #define CCP1M0 CCP1CONbits.CCP1M0 // bit 0
1865 #define CCP1M1 CCP1CONbits.CCP1M1 // bit 1
1866 #define CCP1M2 CCP1CONbits.CCP1M2 // bit 2
1867 #define CCP1M3 CCP1CONbits.CCP1M3 // bit 3
1868 #define DC1B0 CCP1CONbits.DC1B0 // bit 4
1869 #define DC1B1 CCP1CONbits.DC1B1 // bit 5
1871 #define C1CH0 CM1CON0bits.C1CH0 // bit 0
1872 #define C1CH1 CM1CON0bits.C1CH1 // bit 1
1873 #define C1R CM1CON0bits.C1R // bit 2
1874 #define C1SP CM1CON0bits.C1SP // bit 3
1875 #define C1POL CM1CON0bits.C1POL // bit 4
1876 #define C1OE CM1CON0bits.C1OE // bit 5
1877 #define C1OUT CM1CON0bits.C1OUT // bit 6
1878 #define C1ON CM1CON0bits.C1ON // bit 7
1880 #define C2CH0 CM2CON0bits.C2CH0 // bit 0
1881 #define C2CH1 CM2CON0bits.C2CH1 // bit 1
1882 #define C2R CM2CON0bits.C2R // bit 2
1883 #define C2SP CM2CON0bits.C2SP // bit 3
1884 #define C2POL CM2CON0bits.C2POL // bit 4
1885 #define C2OE CM2CON0bits.C2OE // bit 5
1886 #define C2OUT CM2CON0bits.C2OUT // bit 6
1887 #define C2ON CM2CON0bits.C2ON // bit 7
1889 #define C2SYNC CM2CON1bits.C2SYNC // bit 0
1890 #define T1GSS CM2CON1bits.T1GSS // bit 1
1891 #define MC2OUT CM2CON1bits.MC2OUT // bit 6
1892 #define MC1OUT CM2CON1bits.MC1OUT // bit 7
1894 #define RD EECON1bits.RD // bit 0
1895 #define WR EECON1bits.WR // bit 1
1896 #define WREN EECON1bits.WREN // bit 2
1897 #define WRERR EECON1bits.WRERR // bit 3
1899 #define RAIF INTCONbits.RAIF // bit 0
1900 #define INTF INTCONbits.INTF // bit 1
1901 #define T0IF INTCONbits.T0IF // bit 2, shadows bit in INTCONbits
1902 #define TMR0IF INTCONbits.TMR0IF // bit 2, shadows bit in INTCONbits
1903 #define RAIE INTCONbits.RAIE // bit 3
1904 #define INTE INTCONbits.INTE // bit 4
1905 #define T0IE INTCONbits.T0IE // bit 5, shadows bit in INTCONbits
1906 #define TMR0IE INTCONbits.TMR0IE // bit 5, shadows bit in INTCONbits
1907 #define PEIE INTCONbits.PEIE // bit 6
1908 #define GIE INTCONbits.GIE // bit 7
1910 #define IOCA0 IOCbits.IOCA0 // bit 0, shadows bit in IOCbits
1911 #define IOC0 IOCbits.IOC0 // bit 0, shadows bit in IOCbits
1912 #define IOCA1 IOCbits.IOCA1 // bit 1, shadows bit in IOCbits
1913 #define IOC1 IOCbits.IOC1 // bit 1, shadows bit in IOCbits
1914 #define IOCA2 IOCbits.IOCA2 // bit 2, shadows bit in IOCbits
1915 #define IOC2 IOCbits.IOC2 // bit 2, shadows bit in IOCbits
1916 #define IOCA3 IOCbits.IOCA3 // bit 3, shadows bit in IOCbits
1917 #define IOC3 IOCbits.IOC3 // bit 3, shadows bit in IOCbits
1918 #define IOCA4 IOCbits.IOCA4 // bit 4, shadows bit in IOCbits
1919 #define IOC4 IOCbits.IOC4 // bit 4, shadows bit in IOCbits
1920 #define IOCA5 IOCbits.IOCA5 // bit 5, shadows bit in IOCbits
1921 #define IOC5 IOCbits.IOC5 // bit 5, shadows bit in IOCbits
1923 #define OPAON OPA1CONbits.OPAON // bit 7
1925 #define PS0 OPTION_REGbits.PS0 // bit 0
1926 #define PS1 OPTION_REGbits.PS1 // bit 1
1927 #define PS2 OPTION_REGbits.PS2 // bit 2
1928 #define PSA OPTION_REGbits.PSA // bit 3
1929 #define T0SE OPTION_REGbits.T0SE // bit 4
1930 #define T0CS OPTION_REGbits.T0CS // bit 5
1931 #define INTEDG OPTION_REGbits.INTEDG // bit 6
1932 #define NOT_RAPU OPTION_REGbits.NOT_RAPU // bit 7
1934 #define SCS OSCCONbits.SCS // bit 0
1935 #define LTS OSCCONbits.LTS // bit 1
1936 #define HTS OSCCONbits.HTS // bit 2
1937 #define OSTS OSCCONbits.OSTS // bit 3
1938 #define IRCF0 OSCCONbits.IRCF0 // bit 4
1939 #define IRCF1 OSCCONbits.IRCF1 // bit 5
1940 #define IRCF2 OSCCONbits.IRCF2 // bit 6
1942 #define TUN0 OSCTUNEbits.TUN0 // bit 0
1943 #define TUN1 OSCTUNEbits.TUN1 // bit 1
1944 #define TUN2 OSCTUNEbits.TUN2 // bit 2
1945 #define TUN3 OSCTUNEbits.TUN3 // bit 3
1946 #define TUN4 OSCTUNEbits.TUN4 // bit 4
1948 #define NOT_BOR PCONbits.NOT_BOR // bit 0, shadows bit in PCONbits
1949 #define NOT_BOD PCONbits.NOT_BOD // bit 0, shadows bit in PCONbits
1950 #define NOT_POR PCONbits.NOT_POR // bit 1
1951 #define SBOREN PCONbits.SBOREN // bit 4, shadows bit in PCONbits
1952 #define SBODEN PCONbits.SBODEN // bit 4, shadows bit in PCONbits
1954 #define TMR1IE PIE1bits.TMR1IE // bit 0, shadows bit in PIE1bits
1955 #define T1IE PIE1bits.T1IE // bit 0, shadows bit in PIE1bits
1956 #define TMR2IE PIE1bits.TMR2IE // bit 1, shadows bit in PIE1bits
1957 #define T2IE PIE1bits.T2IE // bit 1, shadows bit in PIE1bits
1958 #define OSFIE PIE1bits.OSFIE // bit 2
1959 #define C1IE PIE1bits.C1IE // bit 3
1960 #define C2IE PIE1bits.C2IE // bit 4
1961 #define CCP1IE PIE1bits.CCP1IE // bit 5
1962 #define ADIE PIE1bits.ADIE // bit 6
1963 #define EEIE PIE1bits.EEIE // bit 7
1965 #define TMR1IF PIR1bits.TMR1IF // bit 0, shadows bit in PIR1bits
1966 #define T1IF PIR1bits.T1IF // bit 0, shadows bit in PIR1bits
1967 #define TMR2IF PIR1bits.TMR2IF // bit 1, shadows bit in PIR1bits
1968 #define T2IF PIR1bits.T2IF // bit 1, shadows bit in PIR1bits
1969 #define OSFIF PIR1bits.OSFIF // bit 2
1970 #define C1IF PIR1bits.C1IF // bit 3
1971 #define C2IF PIR1bits.C2IF // bit 4
1972 #define CCP1IF PIR1bits.CCP1IF // bit 5
1973 #define ADIF PIR1bits.ADIF // bit 6
1974 #define EEIF PIR1bits.EEIF // bit 7
1976 #define RA0 PORTAbits.RA0 // bit 0
1977 #define RA1 PORTAbits.RA1 // bit 1
1978 #define RA2 PORTAbits.RA2 // bit 2
1979 #define RA3 PORTAbits.RA3 // bit 3
1980 #define RA4 PORTAbits.RA4 // bit 4
1981 #define RA5 PORTAbits.RA5 // bit 5
1983 #define RB4 PORTBbits.RB4 // bit 4
1984 #define RB5 PORTBbits.RB5 // bit 5
1985 #define RB6 PORTBbits.RB6 // bit 6
1986 #define RB7 PORTBbits.RB7 // bit 7
1988 #define RC0 PORTCbits.RC0 // bit 0
1989 #define RC1 PORTCbits.RC1 // bit 1
1990 #define RC2 PORTCbits.RC2 // bit 2
1991 #define RC3 PORTCbits.RC3 // bit 3
1992 #define RC4 PORTCbits.RC4 // bit 4
1993 #define RC5 PORTCbits.RC5 // bit 5
1994 #define RC6 PORTCbits.RC6 // bit 6
1995 #define RC7 PORTCbits.RC7 // bit 7
1997 #define PER0 PWMCLKbits.PER0 // bit 0
1998 #define PER1 PWMCLKbits.PER1 // bit 1
1999 #define PER2 PWMCLKbits.PER2 // bit 2
2000 #define PER3 PWMCLKbits.PER3 // bit 3
2001 #define PER4 PWMCLKbits.PER4 // bit 4
2002 #define PWMP0 PWMCLKbits.PWMP0 // bit 5
2003 #define PWMP1 PWMCLKbits.PWMP1 // bit 6
2004 #define PWMASE PWMCLKbits.PWMASE // bit 7
2006 #define PH1EN PWMCON0bits.PH1EN // bit 0
2007 #define PH2EN PWMCON0bits.PH2EN // bit 1
2008 #define SYNC0 PWMCON0bits.SYNC0 // bit 2
2009 #define SYNC1 PWMCON0bits.SYNC1 // bit 3
2010 #define BLANK1 PWMCON0bits.BLANK1 // bit 4
2011 #define BLANK2 PWMCON0bits.BLANK2 // bit 5
2012 #define PASEN PWMCON0bits.PASEN // bit 6
2013 #define PRSEN PWMCON0bits.PRSEN // bit 7
2015 #define CMDLY0 PWMCON1bits.CMDLY0 // bit 0
2016 #define CMDLY1 PWMCON1bits.CMDLY1 // bit 1
2017 #define CMDLY2 PWMCON1bits.CMDLY2 // bit 2
2018 #define CMDLY3 PWMCON1bits.CMDLY3 // bit 3
2019 #define CMDLY4 PWMCON1bits.CMDLY4 // bit 4
2020 #define COMOD0 PWMCON1bits.COMOD0 // bit 5
2021 #define COMOD1 PWMCON1bits.COMOD1 // bit 6
2022 #define OVRLP PWMCON1bits.OVRLP // bit 7
2024 #define PH0 PWMPH1bits.PH0 // bit 0
2025 #define PH1 PWMPH1bits.PH1 // bit 1
2026 #define PH2 PWMPH1bits.PH2 // bit 2
2027 #define PH3 PWMPH1bits.PH3 // bit 3
2028 #define PH4 PWMPH1bits.PH4 // bit 4
2029 #define C1EN PWMPH1bits.C1EN // bit 5
2030 #define C2EN PWMPH1bits.C2EN // bit 6
2031 #define POL PWMPH1bits.POL // bit 7
2033 #define CVROE REFCONbits.CVROE // bit 1
2034 #define VROE REFCONbits.VROE // bit 2
2035 #define VREN REFCONbits.VREN // bit 3
2036 #define VRBB REFCONbits.VRBB // bit 4
2037 #define BGST REFCONbits.BGST // bit 5
2039 #define C STATUSbits.C // bit 0
2040 #define DC STATUSbits.DC // bit 1
2041 #define Z STATUSbits.Z // bit 2
2042 #define NOT_PD STATUSbits.NOT_PD // bit 3
2043 #define NOT_TO STATUSbits.NOT_TO // bit 4
2044 #define RP0 STATUSbits.RP0 // bit 5
2045 #define RP1 STATUSbits.RP1 // bit 6
2046 #define IRP STATUSbits.IRP // bit 7
2048 #define TMR1ON T1CONbits.TMR1ON // bit 0
2049 #define TMR1CS T1CONbits.TMR1CS // bit 1
2050 #define NOT_T1SYNC T1CONbits.NOT_T1SYNC // bit 2
2051 #define T1OSCEN T1CONbits.T1OSCEN // bit 3
2052 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
2053 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
2054 #define TMR1GE T1CONbits.TMR1GE // bit 6, shadows bit in T1CONbits
2055 #define T1GE T1CONbits.T1GE // bit 6, shadows bit in T1CONbits
2056 #define T1GINV T1CONbits.T1GINV // bit 7
2058 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
2059 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
2060 #define TMR2ON T2CONbits.TMR2ON // bit 2
2061 #define TOUTPS0 T2CONbits.TOUTPS0 // bit 3
2062 #define TOUTPS1 T2CONbits.TOUTPS1 // bit 4
2063 #define TOUTPS2 T2CONbits.TOUTPS2 // bit 5
2064 #define TOUTPS3 T2CONbits.TOUTPS3 // bit 6
2066 #define TRISA0 TRISAbits.TRISA0 // bit 0
2067 #define TRISA1 TRISAbits.TRISA1 // bit 1
2068 #define TRISA2 TRISAbits.TRISA2 // bit 2
2069 #define TRISA3 TRISAbits.TRISA3 // bit 3
2070 #define TRISA4 TRISAbits.TRISA4 // bit 4
2071 #define TRISA5 TRISAbits.TRISA5 // bit 5
2073 #define TRISB4 TRISBbits.TRISB4 // bit 4
2074 #define TRISB5 TRISBbits.TRISB5 // bit 5
2075 #define TRISB6 TRISBbits.TRISB6 // bit 6
2076 #define TRISB7 TRISBbits.TRISB7 // bit 7
2078 #define TRISC0 TRISCbits.TRISC0 // bit 0
2079 #define TRISC1 TRISCbits.TRISC1 // bit 1
2080 #define TRISC2 TRISCbits.TRISC2 // bit 2
2081 #define TRISC3 TRISCbits.TRISC3 // bit 3
2082 #define TRISC4 TRISCbits.TRISC4 // bit 4
2083 #define TRISC5 TRISCbits.TRISC5 // bit 5
2084 #define TRISC6 TRISCbits.TRISC6 // bit 6
2085 #define TRISC7 TRISCbits.TRISC7 // bit 7
2087 #define VR0 VRCONbits.VR0 // bit 0
2088 #define VR1 VRCONbits.VR1 // bit 1
2089 #define VR2 VRCONbits.VR2 // bit 2
2090 #define VR3 VRCONbits.VR3 // bit 3
2091 #define VRR VRCONbits.VRR // bit 5
2092 #define C2VREN VRCONbits.C2VREN // bit 6
2093 #define C1VREN VRCONbits.C1VREN // bit 7
2095 #define SWDTEN WDTCONbits.SWDTEN // bit 0
2096 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
2097 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
2098 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
2099 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
2101 #define WPUA0 WPUbits.WPUA0 // bit 0, shadows bit in WPUbits
2102 #define WPU0 WPUbits.WPU0 // bit 0, shadows bit in WPUbits
2103 #define WPUA1 WPUbits.WPUA1 // bit 1, shadows bit in WPUbits
2104 #define WPU1 WPUbits.WPU1 // bit 1, shadows bit in WPUbits
2105 #define WPUA2 WPUbits.WPUA2 // bit 2, shadows bit in WPUbits
2106 #define WPU2 WPUbits.WPU2 // bit 2, shadows bit in WPUbits
2107 #define WPUA3 WPUbits.WPUA3 // bit 3, shadows bit in WPUbits
2108 #define WPU3 WPUbits.WPU3 // bit 3, shadows bit in WPUbits
2109 #define WPUA4 WPUbits.WPUA4 // bit 4, shadows bit in WPUbits
2110 #define WPU4 WPUbits.WPU4 // bit 4, shadows bit in WPUbits
2111 #define WPUA5 WPUbits.WPUA5 // bit 5, shadows bit in WPUbits
2112 #define WPU5 WPUbits.WPU5 // bit 5, shadows bit in WPUbits
2114 #endif // #ifndef NO_BIT_DEFINES
2116 #endif // #ifndef __PIC16F785_H__