2 * This declarations of the PIC16LF1507 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:06 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16LF1507_H__
26 #define __PIC16LF1507_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTB_ADDR 0x000D
52 #define PORTC_ADDR 0x000E
53 #define PIR1_ADDR 0x0011
54 #define PIR2_ADDR 0x0012
55 #define PIR3_ADDR 0x0013
56 #define TMR0_ADDR 0x0015
57 #define TMR1_ADDR 0x0016
58 #define TMR1L_ADDR 0x0016
59 #define TMR1H_ADDR 0x0017
60 #define T1CON_ADDR 0x0018
61 #define T1GCON_ADDR 0x0019
62 #define TMR2_ADDR 0x001A
63 #define PR2_ADDR 0x001B
64 #define T2CON_ADDR 0x001C
65 #define TRISA_ADDR 0x008C
66 #define TRISB_ADDR 0x008D
67 #define TRISC_ADDR 0x008E
68 #define PIE1_ADDR 0x0091
69 #define PIE2_ADDR 0x0092
70 #define PIE3_ADDR 0x0093
71 #define OPTION_REG_ADDR 0x0095
72 #define PCON_ADDR 0x0096
73 #define WDTCON_ADDR 0x0097
74 #define OSCCON_ADDR 0x0099
75 #define OSCSTAT_ADDR 0x009A
76 #define ADRES_ADDR 0x009B
77 #define ADRESL_ADDR 0x009B
78 #define ADRESH_ADDR 0x009C
79 #define ADCON0_ADDR 0x009D
80 #define ADCON1_ADDR 0x009E
81 #define ADCON2_ADDR 0x009F
82 #define LATA_ADDR 0x010C
83 #define LATB_ADDR 0x010D
84 #define LATC_ADDR 0x010E
85 #define BORCON_ADDR 0x0116
86 #define FVRCON_ADDR 0x0117
87 #define APFCON_ADDR 0x011D
88 #define ANSELA_ADDR 0x018C
89 #define ANSELB_ADDR 0x018D
90 #define ANSELC_ADDR 0x018E
91 #define PMADR_ADDR 0x0191
92 #define PMADRL_ADDR 0x0191
93 #define PMADRH_ADDR 0x0192
94 #define PMDAT_ADDR 0x0193
95 #define PMDATL_ADDR 0x0193
96 #define PMDATH_ADDR 0x0194
97 #define PMCON1_ADDR 0x0195
98 #define PMCON2_ADDR 0x0196
99 #define WPUA_ADDR 0x020C
100 #define WPUB_ADDR 0x020D
101 #define IOCAP_ADDR 0x0391
102 #define IOCAN_ADDR 0x0392
103 #define IOCAF_ADDR 0x0393
104 #define IOCBP_ADDR 0x0394
105 #define IOCBN_ADDR 0x0395
106 #define IOCBF_ADDR 0x0396
107 #define NCO1ACC_ADDR 0x0498
108 #define NCO1ACCL_ADDR 0x0498
109 #define NCO1ACCH_ADDR 0x0499
110 #define NCO1ACCU_ADDR 0x049A
111 #define NCO1INC_ADDR 0x049B
112 #define NCO1INCL_ADDR 0x049B
113 #define NCO1INCH_ADDR 0x049C
114 #define NCO1INCU_ADDR 0x049D
115 #define NCO1CON_ADDR 0x049E
116 #define NCO1CLK_ADDR 0x049F
117 #define PWM1DCL_ADDR 0x0611
118 #define PWM1DCH_ADDR 0x0612
119 #define PWM1CON_ADDR 0x0613
120 #define PWM1CON0_ADDR 0x0613
121 #define PWM2DCL_ADDR 0x0614
122 #define PWM2DCH_ADDR 0x0615
123 #define PWM2CON_ADDR 0x0616
124 #define PWM2CON0_ADDR 0x0616
125 #define PWM3DCL_ADDR 0x0617
126 #define PWM3DCH_ADDR 0x0618
127 #define PWM3CON_ADDR 0x0619
128 #define PWM3CON0_ADDR 0x0619
129 #define PWM4DCL_ADDR 0x061A
130 #define PWM4DCH_ADDR 0x061B
131 #define PWM4CON_ADDR 0x061C
132 #define PWM4CON0_ADDR 0x061C
133 #define CWG1DBR_ADDR 0x0691
134 #define CWG1DBF_ADDR 0x0692
135 #define CWG1CON0_ADDR 0x0693
136 #define CWG1CON1_ADDR 0x0694
137 #define CWG1CON2_ADDR 0x0695
138 #define CLCDATA_ADDR 0x0F0F
139 #define CLC1CON_ADDR 0x0F10
140 #define CLC1POL_ADDR 0x0F11
141 #define CLC1SEL0_ADDR 0x0F12
142 #define CLC1SEL1_ADDR 0x0F13
143 #define CLC1GLS0_ADDR 0x0F14
144 #define CLC1GLS1_ADDR 0x0F15
145 #define CLC1GLS2_ADDR 0x0F16
146 #define CLC1GLS3_ADDR 0x0F17
147 #define CLC2CON_ADDR 0x0F18
148 #define CLC2POL_ADDR 0x0F19
149 #define CLC2SEL0_ADDR 0x0F1A
150 #define CLC2SEL1_ADDR 0x0F1B
151 #define CLC2GLS0_ADDR 0x0F1C
152 #define CLC2GLS1_ADDR 0x0F1D
153 #define CLC2GLS2_ADDR 0x0F1E
154 #define CLC2GLS3_ADDR 0x0F1F
155 #define BSR_ICDSHAD_ADDR 0x0FE3
156 #define STATUS_SHAD_ADDR 0x0FE4
157 #define WREG_SHAD_ADDR 0x0FE5
158 #define BSR_SHAD_ADDR 0x0FE6
159 #define PCLATH_SHAD_ADDR 0x0FE7
160 #define FSR0L_SHAD_ADDR 0x0FE8
161 #define FSR0H_SHAD_ADDR 0x0FE9
162 #define FSR1L_SHAD_ADDR 0x0FEA
163 #define FSR1H_SHAD_ADDR 0x0FEB
164 #define STKPTR_ADDR 0x0FED
165 #define TOSL_ADDR 0x0FEE
166 #define TOSH_ADDR 0x0FEF
168 #endif // #ifndef NO_ADDR_DEFINES
170 //==============================================================================
172 // Register Definitions
174 //==============================================================================
176 extern __at(0x0000) __sfr INDF0
;
177 extern __at(0x0001) __sfr INDF1
;
178 extern __at(0x0002) __sfr PCL
;
180 //==============================================================================
183 extern __at(0x0003) __sfr STATUS
;
197 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
205 //==============================================================================
207 extern __at(0x0004) __sfr FSR0
;
208 extern __at(0x0004) __sfr FSR0L
;
209 extern __at(0x0005) __sfr FSR0H
;
210 extern __at(0x0006) __sfr FSR1
;
211 extern __at(0x0006) __sfr FSR1L
;
212 extern __at(0x0007) __sfr FSR1H
;
214 //==============================================================================
217 extern __at(0x0008) __sfr BSR
;
240 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
248 //==============================================================================
250 extern __at(0x0009) __sfr WREG
;
251 extern __at(0x000A) __sfr PCLATH
;
253 //==============================================================================
256 extern __at(0x000B) __sfr INTCON
;
285 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
298 //==============================================================================
301 //==============================================================================
304 extern __at(0x000C) __sfr PORTA
;
327 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
336 //==============================================================================
339 //==============================================================================
342 extern __at(0x000D) __sfr PORTB
;
356 extern __at(0x000D) volatile __PORTBbits_t PORTBbits
;
363 //==============================================================================
366 //==============================================================================
369 extern __at(0x000E) __sfr PORTC
;
383 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
394 //==============================================================================
397 //==============================================================================
400 extern __at(0x0011) __sfr PIR1
;
411 unsigned TMR1GIF
: 1;
414 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
419 #define _TMR1GIF 0x80
421 //==============================================================================
424 //==============================================================================
427 extern __at(0x0012) __sfr PIR2
;
441 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
445 //==============================================================================
448 //==============================================================================
451 extern __at(0x0013) __sfr PIR3
;
465 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
470 //==============================================================================
472 extern __at(0x0015) __sfr TMR0
;
473 extern __at(0x0016) __sfr TMR1
;
474 extern __at(0x0016) __sfr TMR1L
;
475 extern __at(0x0017) __sfr TMR1H
;
477 //==============================================================================
480 extern __at(0x0018) __sfr T1CON
;
488 unsigned NOT_T1SYNC
: 1;
489 unsigned T1OSCEN
: 1;
490 unsigned T1CKPS0
: 1;
491 unsigned T1CKPS1
: 1;
492 unsigned TMR1CS0
: 1;
493 unsigned TMR1CS1
: 1;
510 extern __at(0x0018) volatile __T1CONbits_t T1CONbits
;
513 #define _NOT_T1SYNC 0x04
514 #define _T1OSCEN 0x08
515 #define _T1CKPS0 0x10
516 #define _T1CKPS1 0x20
517 #define _TMR1CS0 0x40
518 #define _TMR1CS1 0x80
520 //==============================================================================
523 //==============================================================================
526 extern __at(0x0019) __sfr T1GCON
;
535 unsigned T1GGO_NOT_DONE
: 1;
549 extern __at(0x0019) volatile __T1GCONbits_t T1GCONbits
;
554 #define _T1GGO_NOT_DONE 0x08
560 //==============================================================================
562 extern __at(0x001A) __sfr TMR2
;
563 extern __at(0x001B) __sfr PR2
;
565 //==============================================================================
568 extern __at(0x001C) __sfr T2CON
;
574 unsigned T2CKPS0
: 1;
575 unsigned T2CKPS1
: 1;
577 unsigned TOUTPS0
: 1;
578 unsigned TOUTPS1
: 1;
579 unsigned TOUTPS2
: 1;
580 unsigned TOUTPS3
: 1;
598 extern __at(0x001C) volatile __T2CONbits_t T2CONbits
;
600 #define _T2CKPS0 0x01
601 #define _T2CKPS1 0x02
603 #define _TOUTPS0 0x08
604 #define _TOUTPS1 0x10
605 #define _TOUTPS2 0x20
606 #define _TOUTPS3 0x40
608 //==============================================================================
611 //==============================================================================
614 extern __at(0x008C) __sfr TRISA
;
637 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
646 //==============================================================================
649 //==============================================================================
652 extern __at(0x008D) __sfr TRISB
;
666 extern __at(0x008D) volatile __TRISBbits_t TRISBbits
;
673 //==============================================================================
676 //==============================================================================
679 extern __at(0x008E) __sfr TRISC
;
693 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
704 //==============================================================================
707 //==============================================================================
710 extern __at(0x0091) __sfr PIE1
;
721 unsigned TMR1GIE
: 1;
724 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
729 #define _TMR1GIE 0x80
731 //==============================================================================
734 //==============================================================================
737 extern __at(0x0092) __sfr PIE2
;
751 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
755 //==============================================================================
758 //==============================================================================
761 extern __at(0x0093) __sfr PIE3
;
775 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
780 //==============================================================================
783 //==============================================================================
786 extern __at(0x0095) __sfr OPTION_REG
;
799 unsigned NOT_WPUEN
: 1;
819 } __OPTION_REGbits_t
;
821 extern __at(0x0095) volatile __OPTION_REGbits_t OPTION_REGbits
;
832 #define _NOT_WPUEN 0x80
834 //==============================================================================
837 //==============================================================================
840 extern __at(0x0096) __sfr PCON
;
844 unsigned NOT_BOR
: 1;
845 unsigned NOT_POR
: 1;
847 unsigned NOT_RMCLR
: 1;
848 unsigned NOT_RWDT
: 1;
854 extern __at(0x0096) volatile __PCONbits_t PCONbits
;
856 #define _NOT_BOR 0x01
857 #define _NOT_POR 0x02
859 #define _NOT_RMCLR 0x08
860 #define _NOT_RWDT 0x10
864 //==============================================================================
867 //==============================================================================
870 extern __at(0x0097) __sfr WDTCON
;
894 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
903 //==============================================================================
906 //==============================================================================
909 extern __at(0x0099) __sfr OSCCON
;
939 extern __at(0x0099) volatile __OSCCONbits_t OSCCONbits
;
948 //==============================================================================
951 //==============================================================================
954 extern __at(0x009A) __sfr OSCSTAT
;
968 extern __at(0x009A) volatile __OSCSTATbits_t OSCSTATbits
;
976 //==============================================================================
978 extern __at(0x009B) __sfr ADRES
;
979 extern __at(0x009B) __sfr ADRESL
;
980 extern __at(0x009C) __sfr ADRESH
;
982 //==============================================================================
985 extern __at(0x009D) __sfr ADCON0
;
992 unsigned GO_NOT_DONE
: 1;
1033 extern __at(0x009D) volatile __ADCON0bits_t ADCON0bits
;
1036 #define _GO_NOT_DONE 0x02
1045 //==============================================================================
1048 //==============================================================================
1051 extern __at(0x009E) __sfr ADCON1
;
1057 unsigned ADPREF0
: 1;
1058 unsigned ADPREF1
: 1;
1069 unsigned ADPREF
: 2;
1081 extern __at(0x009E) volatile __ADCON1bits_t ADCON1bits
;
1083 #define _ADPREF0 0x01
1084 #define _ADPREF1 0x02
1090 //==============================================================================
1093 //==============================================================================
1096 extern __at(0x009F) __sfr ADCON2
;
1106 unsigned TRIGSEL0
: 1;
1107 unsigned TRIGSEL1
: 1;
1108 unsigned TRIGSEL2
: 1;
1109 unsigned TRIGSEL3
: 1;
1115 unsigned TRIGSEL
: 4;
1119 extern __at(0x009F) volatile __ADCON2bits_t ADCON2bits
;
1121 #define _TRIGSEL0 0x10
1122 #define _TRIGSEL1 0x20
1123 #define _TRIGSEL2 0x40
1124 #define _TRIGSEL3 0x80
1126 //==============================================================================
1129 //==============================================================================
1132 extern __at(0x010C) __sfr LATA
;
1146 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
1154 //==============================================================================
1157 //==============================================================================
1160 extern __at(0x010D) __sfr LATB
;
1174 extern __at(0x010D) volatile __LATBbits_t LATBbits
;
1181 //==============================================================================
1184 //==============================================================================
1187 extern __at(0x010E) __sfr LATC
;
1201 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
1212 //==============================================================================
1215 //==============================================================================
1218 extern __at(0x0116) __sfr BORCON
;
1222 unsigned BORRDY
: 1;
1229 unsigned SBOREN
: 1;
1232 extern __at(0x0116) volatile __BORCONbits_t BORCONbits
;
1234 #define _BORRDY 0x01
1236 #define _SBOREN 0x80
1238 //==============================================================================
1241 //==============================================================================
1244 extern __at(0x0117) __sfr FVRCON
;
1250 unsigned ADFVR0
: 1;
1251 unsigned ADFVR1
: 1;
1256 unsigned FVRRDY
: 1;
1267 extern __at(0x0117) volatile __FVRCONbits_t FVRCONbits
;
1269 #define _ADFVR0 0x01
1270 #define _ADFVR1 0x02
1273 #define _FVRRDY 0x40
1276 //==============================================================================
1279 //==============================================================================
1282 extern __at(0x011D) __sfr APFCON
;
1286 unsigned NCO1SEL
: 1;
1287 unsigned CLC1SEL
: 1;
1296 extern __at(0x011D) volatile __APFCONbits_t APFCONbits
;
1298 #define _NCO1SEL 0x01
1299 #define _CLC1SEL 0x02
1301 //==============================================================================
1304 //==============================================================================
1307 extern __at(0x018C) __sfr ANSELA
;
1321 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
1328 //==============================================================================
1331 //==============================================================================
1334 extern __at(0x018D) __sfr ANSELB
;
1348 extern __at(0x018D) volatile __ANSELBbits_t ANSELBbits
;
1353 //==============================================================================
1356 //==============================================================================
1359 extern __at(0x018E) __sfr ANSELC
;
1373 extern __at(0x018E) volatile __ANSELCbits_t ANSELCbits
;
1382 //==============================================================================
1384 extern __at(0x0191) __sfr PMADR
;
1385 extern __at(0x0191) __sfr PMADRL
;
1386 extern __at(0x0192) __sfr PMADRH
;
1387 extern __at(0x0193) __sfr PMDAT
;
1388 extern __at(0x0193) __sfr PMDATL
;
1389 extern __at(0x0194) __sfr PMDATH
;
1391 //==============================================================================
1394 extern __at(0x0195) __sfr PMCON1
;
1408 extern __at(0x0195) volatile __PMCON1bits_t PMCON1bits
;
1418 //==============================================================================
1420 extern __at(0x0196) __sfr PMCON2
;
1422 //==============================================================================
1425 extern __at(0x020C) __sfr WPUA
;
1448 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
1457 //==============================================================================
1460 //==============================================================================
1463 extern __at(0x020D) __sfr WPUB
;
1477 extern __at(0x020D) volatile __WPUBbits_t WPUBbits
;
1484 //==============================================================================
1487 //==============================================================================
1490 extern __at(0x0391) __sfr IOCAP
;
1496 unsigned IOCAP0
: 1;
1497 unsigned IOCAP1
: 1;
1498 unsigned IOCAP2
: 1;
1499 unsigned IOCAP3
: 1;
1500 unsigned IOCAP4
: 1;
1501 unsigned IOCAP5
: 1;
1513 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
1515 #define _IOCAP0 0x01
1516 #define _IOCAP1 0x02
1517 #define _IOCAP2 0x04
1518 #define _IOCAP3 0x08
1519 #define _IOCAP4 0x10
1520 #define _IOCAP5 0x20
1522 //==============================================================================
1525 //==============================================================================
1528 extern __at(0x0392) __sfr IOCAN
;
1534 unsigned IOCAN0
: 1;
1535 unsigned IOCAN1
: 1;
1536 unsigned IOCAN2
: 1;
1537 unsigned IOCAN3
: 1;
1538 unsigned IOCAN4
: 1;
1539 unsigned IOCAN5
: 1;
1551 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
1553 #define _IOCAN0 0x01
1554 #define _IOCAN1 0x02
1555 #define _IOCAN2 0x04
1556 #define _IOCAN3 0x08
1557 #define _IOCAN4 0x10
1558 #define _IOCAN5 0x20
1560 //==============================================================================
1563 //==============================================================================
1566 extern __at(0x0393) __sfr IOCAF
;
1572 unsigned IOCAF0
: 1;
1573 unsigned IOCAF1
: 1;
1574 unsigned IOCAF2
: 1;
1575 unsigned IOCAF3
: 1;
1576 unsigned IOCAF4
: 1;
1577 unsigned IOCAF5
: 1;
1589 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
1591 #define _IOCAF0 0x01
1592 #define _IOCAF1 0x02
1593 #define _IOCAF2 0x04
1594 #define _IOCAF3 0x08
1595 #define _IOCAF4 0x10
1596 #define _IOCAF5 0x20
1598 //==============================================================================
1601 //==============================================================================
1604 extern __at(0x0394) __sfr IOCBP
;
1612 unsigned IOCBP4
: 1;
1613 unsigned IOCBP5
: 1;
1614 unsigned IOCBP6
: 1;
1615 unsigned IOCBP7
: 1;
1618 extern __at(0x0394) volatile __IOCBPbits_t IOCBPbits
;
1620 #define _IOCBP4 0x10
1621 #define _IOCBP5 0x20
1622 #define _IOCBP6 0x40
1623 #define _IOCBP7 0x80
1625 //==============================================================================
1628 //==============================================================================
1631 extern __at(0x0395) __sfr IOCBN
;
1639 unsigned IOCBN4
: 1;
1640 unsigned IOCBN5
: 1;
1641 unsigned IOCBN6
: 1;
1642 unsigned IOCBN7
: 1;
1645 extern __at(0x0395) volatile __IOCBNbits_t IOCBNbits
;
1647 #define _IOCBN4 0x10
1648 #define _IOCBN5 0x20
1649 #define _IOCBN6 0x40
1650 #define _IOCBN7 0x80
1652 //==============================================================================
1655 //==============================================================================
1658 extern __at(0x0396) __sfr IOCBF
;
1666 unsigned IOCBF4
: 1;
1667 unsigned IOCBF5
: 1;
1668 unsigned IOCBF6
: 1;
1669 unsigned IOCBF7
: 1;
1672 extern __at(0x0396) volatile __IOCBFbits_t IOCBFbits
;
1674 #define _IOCBF4 0x10
1675 #define _IOCBF5 0x20
1676 #define _IOCBF6 0x40
1677 #define _IOCBF7 0x80
1679 //==============================================================================
1681 extern __at(0x0498) __sfr NCO1ACC
;
1683 //==============================================================================
1686 extern __at(0x0498) __sfr NCO1ACCL
;
1690 unsigned NCO1ACC0
: 1;
1691 unsigned NCO1ACC1
: 1;
1692 unsigned NCO1ACC2
: 1;
1693 unsigned NCO1ACC3
: 1;
1694 unsigned NCO1ACC4
: 1;
1695 unsigned NCO1ACC5
: 1;
1696 unsigned NCO1ACC6
: 1;
1697 unsigned NCO1ACC7
: 1;
1700 extern __at(0x0498) volatile __NCO1ACCLbits_t NCO1ACCLbits
;
1702 #define _NCO1ACC0 0x01
1703 #define _NCO1ACC1 0x02
1704 #define _NCO1ACC2 0x04
1705 #define _NCO1ACC3 0x08
1706 #define _NCO1ACC4 0x10
1707 #define _NCO1ACC5 0x20
1708 #define _NCO1ACC6 0x40
1709 #define _NCO1ACC7 0x80
1711 //==============================================================================
1714 //==============================================================================
1717 extern __at(0x0499) __sfr NCO1ACCH
;
1721 unsigned NCO1ACC8
: 1;
1722 unsigned NCO1ACC9
: 1;
1723 unsigned NCO1ACC10
: 1;
1724 unsigned NCO1ACC11
: 1;
1725 unsigned NCO1ACC12
: 1;
1726 unsigned NCO1ACC13
: 1;
1727 unsigned NCO1ACC14
: 1;
1728 unsigned NCO1ACC15
: 1;
1731 extern __at(0x0499) volatile __NCO1ACCHbits_t NCO1ACCHbits
;
1733 #define _NCO1ACC8 0x01
1734 #define _NCO1ACC9 0x02
1735 #define _NCO1ACC10 0x04
1736 #define _NCO1ACC11 0x08
1737 #define _NCO1ACC12 0x10
1738 #define _NCO1ACC13 0x20
1739 #define _NCO1ACC14 0x40
1740 #define _NCO1ACC15 0x80
1742 //==============================================================================
1745 //==============================================================================
1748 extern __at(0x049A) __sfr NCO1ACCU
;
1752 unsigned NCO1ACC16
: 1;
1753 unsigned NCO1ACC17
: 1;
1754 unsigned NCO1ACC18
: 1;
1755 unsigned NCO1ACC19
: 1;
1762 extern __at(0x049A) volatile __NCO1ACCUbits_t NCO1ACCUbits
;
1764 #define _NCO1ACC16 0x01
1765 #define _NCO1ACC17 0x02
1766 #define _NCO1ACC18 0x04
1767 #define _NCO1ACC19 0x08
1769 //==============================================================================
1771 extern __at(0x049B) __sfr NCO1INC
;
1773 //==============================================================================
1776 extern __at(0x049B) __sfr NCO1INCL
;
1780 unsigned NCO1INC0
: 1;
1781 unsigned NCO1INC1
: 1;
1782 unsigned NCO1INC2
: 1;
1783 unsigned NCO1INC3
: 1;
1784 unsigned NCO1INC4
: 1;
1785 unsigned NCO1INC5
: 1;
1786 unsigned NCO1INC6
: 1;
1787 unsigned NCO1INC7
: 1;
1790 extern __at(0x049B) volatile __NCO1INCLbits_t NCO1INCLbits
;
1792 #define _NCO1INC0 0x01
1793 #define _NCO1INC1 0x02
1794 #define _NCO1INC2 0x04
1795 #define _NCO1INC3 0x08
1796 #define _NCO1INC4 0x10
1797 #define _NCO1INC5 0x20
1798 #define _NCO1INC6 0x40
1799 #define _NCO1INC7 0x80
1801 //==============================================================================
1804 //==============================================================================
1807 extern __at(0x049C) __sfr NCO1INCH
;
1811 unsigned NCO1INC8
: 1;
1812 unsigned NCO1INC9
: 1;
1813 unsigned NCO1INC10
: 1;
1814 unsigned NCO1INC11
: 1;
1815 unsigned NCO1INC12
: 1;
1816 unsigned NCO1INC13
: 1;
1817 unsigned NCO1INC14
: 1;
1818 unsigned NCO1INC15
: 1;
1821 extern __at(0x049C) volatile __NCO1INCHbits_t NCO1INCHbits
;
1823 #define _NCO1INC8 0x01
1824 #define _NCO1INC9 0x02
1825 #define _NCO1INC10 0x04
1826 #define _NCO1INC11 0x08
1827 #define _NCO1INC12 0x10
1828 #define _NCO1INC13 0x20
1829 #define _NCO1INC14 0x40
1830 #define _NCO1INC15 0x80
1832 //==============================================================================
1834 extern __at(0x049D) __sfr NCO1INCU
;
1836 //==============================================================================
1839 extern __at(0x049E) __sfr NCO1CON
;
1853 extern __at(0x049E) volatile __NCO1CONbits_t NCO1CONbits
;
1861 //==============================================================================
1864 //==============================================================================
1867 extern __at(0x049F) __sfr NCO1CLK
;
1873 unsigned N1CKS0
: 1;
1874 unsigned N1CKS1
: 1;
1878 unsigned N1PWS0
: 1;
1879 unsigned N1PWS1
: 1;
1880 unsigned N1PWS2
: 1;
1896 extern __at(0x049F) volatile __NCO1CLKbits_t NCO1CLKbits
;
1898 #define _N1CKS0 0x01
1899 #define _N1CKS1 0x02
1900 #define _N1PWS0 0x20
1901 #define _N1PWS1 0x40
1902 #define _N1PWS2 0x80
1904 //==============================================================================
1907 //==============================================================================
1910 extern __at(0x0611) __sfr PWM1DCL
;
1922 unsigned PWM1DCL0
: 1;
1923 unsigned PWM1DCL1
: 1;
1929 unsigned PWM1DCL
: 2;
1933 extern __at(0x0611) volatile __PWM1DCLbits_t PWM1DCLbits
;
1935 #define _PWM1DCL0 0x40
1936 #define _PWM1DCL1 0x80
1938 //==============================================================================
1941 //==============================================================================
1944 extern __at(0x0612) __sfr PWM1DCH
;
1948 unsigned PWM1DCH0
: 1;
1949 unsigned PWM1DCH1
: 1;
1950 unsigned PWM1DCH2
: 1;
1951 unsigned PWM1DCH3
: 1;
1952 unsigned PWM1DCH4
: 1;
1953 unsigned PWM1DCH5
: 1;
1954 unsigned PWM1DCH6
: 1;
1955 unsigned PWM1DCH7
: 1;
1958 extern __at(0x0612) volatile __PWM1DCHbits_t PWM1DCHbits
;
1960 #define _PWM1DCH0 0x01
1961 #define _PWM1DCH1 0x02
1962 #define _PWM1DCH2 0x04
1963 #define _PWM1DCH3 0x08
1964 #define _PWM1DCH4 0x10
1965 #define _PWM1DCH5 0x20
1966 #define _PWM1DCH6 0x40
1967 #define _PWM1DCH7 0x80
1969 //==============================================================================
1972 //==============================================================================
1975 extern __at(0x0613) __sfr PWM1CON
;
1983 unsigned PWM1POL
: 1;
1984 unsigned PWM1OUT
: 1;
1985 unsigned PWM1OE
: 1;
1986 unsigned PWM1EN
: 1;
1989 extern __at(0x0613) volatile __PWM1CONbits_t PWM1CONbits
;
1991 #define _PWM1POL 0x10
1992 #define _PWM1OUT 0x20
1993 #define _PWM1OE 0x40
1994 #define _PWM1EN 0x80
1996 //==============================================================================
1999 //==============================================================================
2002 extern __at(0x0613) __sfr PWM1CON0
;
2010 unsigned PWM1POL
: 1;
2011 unsigned PWM1OUT
: 1;
2012 unsigned PWM1OE
: 1;
2013 unsigned PWM1EN
: 1;
2016 extern __at(0x0613) volatile __PWM1CON0bits_t PWM1CON0bits
;
2018 #define _PWM1CON0_PWM1POL 0x10
2019 #define _PWM1CON0_PWM1OUT 0x20
2020 #define _PWM1CON0_PWM1OE 0x40
2021 #define _PWM1CON0_PWM1EN 0x80
2023 //==============================================================================
2026 //==============================================================================
2029 extern __at(0x0614) __sfr PWM2DCL
;
2041 unsigned PWM2DCL0
: 1;
2042 unsigned PWM2DCL1
: 1;
2048 unsigned PWM2DCL
: 2;
2052 extern __at(0x0614) volatile __PWM2DCLbits_t PWM2DCLbits
;
2054 #define _PWM2DCL0 0x40
2055 #define _PWM2DCL1 0x80
2057 //==============================================================================
2060 //==============================================================================
2063 extern __at(0x0615) __sfr PWM2DCH
;
2067 unsigned PWM2DCH0
: 1;
2068 unsigned PWM2DCH1
: 1;
2069 unsigned PWM2DCH2
: 1;
2070 unsigned PWM2DCH3
: 1;
2071 unsigned PWM2DCH4
: 1;
2072 unsigned PWM2DCH5
: 1;
2073 unsigned PWM2DCH6
: 1;
2074 unsigned PWM2DCH7
: 1;
2077 extern __at(0x0615) volatile __PWM2DCHbits_t PWM2DCHbits
;
2079 #define _PWM2DCH0 0x01
2080 #define _PWM2DCH1 0x02
2081 #define _PWM2DCH2 0x04
2082 #define _PWM2DCH3 0x08
2083 #define _PWM2DCH4 0x10
2084 #define _PWM2DCH5 0x20
2085 #define _PWM2DCH6 0x40
2086 #define _PWM2DCH7 0x80
2088 //==============================================================================
2091 //==============================================================================
2094 extern __at(0x0616) __sfr PWM2CON
;
2102 unsigned PWM2POL
: 1;
2103 unsigned PWM2OUT
: 1;
2104 unsigned PWM2OE
: 1;
2105 unsigned PWM2EN
: 1;
2108 extern __at(0x0616) volatile __PWM2CONbits_t PWM2CONbits
;
2110 #define _PWM2POL 0x10
2111 #define _PWM2OUT 0x20
2112 #define _PWM2OE 0x40
2113 #define _PWM2EN 0x80
2115 //==============================================================================
2118 //==============================================================================
2121 extern __at(0x0616) __sfr PWM2CON0
;
2129 unsigned PWM2POL
: 1;
2130 unsigned PWM2OUT
: 1;
2131 unsigned PWM2OE
: 1;
2132 unsigned PWM2EN
: 1;
2135 extern __at(0x0616) volatile __PWM2CON0bits_t PWM2CON0bits
;
2137 #define _PWM2CON0_PWM2POL 0x10
2138 #define _PWM2CON0_PWM2OUT 0x20
2139 #define _PWM2CON0_PWM2OE 0x40
2140 #define _PWM2CON0_PWM2EN 0x80
2142 //==============================================================================
2145 //==============================================================================
2148 extern __at(0x0617) __sfr PWM3DCL
;
2160 unsigned PWM3DCL0
: 1;
2161 unsigned PWM3DCL1
: 1;
2167 unsigned PWM3DCL
: 2;
2171 extern __at(0x0617) volatile __PWM3DCLbits_t PWM3DCLbits
;
2173 #define _PWM3DCL0 0x40
2174 #define _PWM3DCL1 0x80
2176 //==============================================================================
2179 //==============================================================================
2182 extern __at(0x0618) __sfr PWM3DCH
;
2186 unsigned PWM3DCH0
: 1;
2187 unsigned PWM3DCH1
: 1;
2188 unsigned PWM3DCH2
: 1;
2189 unsigned PWM3DCH3
: 1;
2190 unsigned PWM3DCH4
: 1;
2191 unsigned PWM3DCH5
: 1;
2192 unsigned PWM3DCH6
: 1;
2193 unsigned PWM3DCH7
: 1;
2196 extern __at(0x0618) volatile __PWM3DCHbits_t PWM3DCHbits
;
2198 #define _PWM3DCH0 0x01
2199 #define _PWM3DCH1 0x02
2200 #define _PWM3DCH2 0x04
2201 #define _PWM3DCH3 0x08
2202 #define _PWM3DCH4 0x10
2203 #define _PWM3DCH5 0x20
2204 #define _PWM3DCH6 0x40
2205 #define _PWM3DCH7 0x80
2207 //==============================================================================
2210 //==============================================================================
2213 extern __at(0x0619) __sfr PWM3CON
;
2221 unsigned PWM3POL
: 1;
2222 unsigned PWM3OUT
: 1;
2223 unsigned PWM3OE
: 1;
2224 unsigned PWM3EN
: 1;
2227 extern __at(0x0619) volatile __PWM3CONbits_t PWM3CONbits
;
2229 #define _PWM3POL 0x10
2230 #define _PWM3OUT 0x20
2231 #define _PWM3OE 0x40
2232 #define _PWM3EN 0x80
2234 //==============================================================================
2237 //==============================================================================
2240 extern __at(0x0619) __sfr PWM3CON0
;
2248 unsigned PWM3POL
: 1;
2249 unsigned PWM3OUT
: 1;
2250 unsigned PWM3OE
: 1;
2251 unsigned PWM3EN
: 1;
2254 extern __at(0x0619) volatile __PWM3CON0bits_t PWM3CON0bits
;
2256 #define _PWM3CON0_PWM3POL 0x10
2257 #define _PWM3CON0_PWM3OUT 0x20
2258 #define _PWM3CON0_PWM3OE 0x40
2259 #define _PWM3CON0_PWM3EN 0x80
2261 //==============================================================================
2264 //==============================================================================
2267 extern __at(0x061A) __sfr PWM4DCL
;
2279 unsigned PWM4DCL0
: 1;
2280 unsigned PWM4DCL1
: 1;
2286 unsigned PWM4DCL
: 2;
2290 extern __at(0x061A) volatile __PWM4DCLbits_t PWM4DCLbits
;
2292 #define _PWM4DCL0 0x40
2293 #define _PWM4DCL1 0x80
2295 //==============================================================================
2298 //==============================================================================
2301 extern __at(0x061B) __sfr PWM4DCH
;
2305 unsigned PWM4DCH0
: 1;
2306 unsigned PWM4DCH1
: 1;
2307 unsigned PWM4DCH2
: 1;
2308 unsigned PWM4DCH3
: 1;
2309 unsigned PWM4DCH4
: 1;
2310 unsigned PWM4DCH5
: 1;
2311 unsigned PWM4DCH6
: 1;
2312 unsigned PWM4DCH7
: 1;
2315 extern __at(0x061B) volatile __PWM4DCHbits_t PWM4DCHbits
;
2317 #define _PWM4DCH0 0x01
2318 #define _PWM4DCH1 0x02
2319 #define _PWM4DCH2 0x04
2320 #define _PWM4DCH3 0x08
2321 #define _PWM4DCH4 0x10
2322 #define _PWM4DCH5 0x20
2323 #define _PWM4DCH6 0x40
2324 #define _PWM4DCH7 0x80
2326 //==============================================================================
2329 //==============================================================================
2332 extern __at(0x061C) __sfr PWM4CON
;
2340 unsigned PWM4POL
: 1;
2341 unsigned PWM4OUT
: 1;
2342 unsigned PWM4OE
: 1;
2343 unsigned PWM4EN
: 1;
2346 extern __at(0x061C) volatile __PWM4CONbits_t PWM4CONbits
;
2348 #define _PWM4POL 0x10
2349 #define _PWM4OUT 0x20
2350 #define _PWM4OE 0x40
2351 #define _PWM4EN 0x80
2353 //==============================================================================
2356 //==============================================================================
2359 extern __at(0x061C) __sfr PWM4CON0
;
2367 unsigned PWM4POL
: 1;
2368 unsigned PWM4OUT
: 1;
2369 unsigned PWM4OE
: 1;
2370 unsigned PWM4EN
: 1;
2373 extern __at(0x061C) volatile __PWM4CON0bits_t PWM4CON0bits
;
2375 #define _PWM4CON0_PWM4POL 0x10
2376 #define _PWM4CON0_PWM4OUT 0x20
2377 #define _PWM4CON0_PWM4OE 0x40
2378 #define _PWM4CON0_PWM4EN 0x80
2380 //==============================================================================
2383 //==============================================================================
2386 extern __at(0x0691) __sfr CWG1DBR
;
2392 unsigned CWG1DBR0
: 1;
2393 unsigned CWG1DBR1
: 1;
2394 unsigned CWG1DBR2
: 1;
2395 unsigned CWG1DBR3
: 1;
2396 unsigned CWG1DBR4
: 1;
2397 unsigned CWG1DBR5
: 1;
2404 unsigned CWG1DBR
: 6;
2409 extern __at(0x0691) volatile __CWG1DBRbits_t CWG1DBRbits
;
2411 #define _CWG1DBR0 0x01
2412 #define _CWG1DBR1 0x02
2413 #define _CWG1DBR2 0x04
2414 #define _CWG1DBR3 0x08
2415 #define _CWG1DBR4 0x10
2416 #define _CWG1DBR5 0x20
2418 //==============================================================================
2421 //==============================================================================
2424 extern __at(0x0692) __sfr CWG1DBF
;
2430 unsigned CWG1DBF0
: 1;
2431 unsigned CWG1DBF1
: 1;
2432 unsigned CWG1DBF2
: 1;
2433 unsigned CWG1DBF3
: 1;
2434 unsigned CWG1DBF4
: 1;
2435 unsigned CWG1DBF5
: 1;
2442 unsigned CWG1DBF
: 6;
2447 extern __at(0x0692) volatile __CWG1DBFbits_t CWG1DBFbits
;
2449 #define _CWG1DBF0 0x01
2450 #define _CWG1DBF1 0x02
2451 #define _CWG1DBF2 0x04
2452 #define _CWG1DBF3 0x08
2453 #define _CWG1DBF4 0x10
2454 #define _CWG1DBF5 0x20
2456 //==============================================================================
2459 //==============================================================================
2462 extern __at(0x0693) __sfr CWG1CON0
;
2469 unsigned G1POLA
: 1;
2470 unsigned G1POLB
: 1;
2476 extern __at(0x0693) volatile __CWG1CON0bits_t CWG1CON0bits
;
2479 #define _G1POLA 0x08
2480 #define _G1POLB 0x10
2485 //==============================================================================
2488 //==============================================================================
2491 extern __at(0x0694) __sfr CWG1CON1
;
2501 unsigned G1ASDLA0
: 1;
2502 unsigned G1ASDLA1
: 1;
2503 unsigned G1ASDLB0
: 1;
2504 unsigned G1ASDLB1
: 1;
2516 unsigned G1ASDLA
: 2;
2523 unsigned G1ASDLB
: 2;
2527 extern __at(0x0694) volatile __CWG1CON1bits_t CWG1CON1bits
;
2532 #define _G1ASDLA0 0x10
2533 #define _G1ASDLA1 0x20
2534 #define _G1ASDLB0 0x40
2535 #define _G1ASDLB1 0x80
2537 //==============================================================================
2540 //==============================================================================
2543 extern __at(0x0695) __sfr CWG1CON2
;
2547 unsigned G1ASDSCLC2
: 1;
2548 unsigned G1ASDSFLT
: 1;
2553 unsigned G1ARSEN
: 1;
2557 extern __at(0x0695) volatile __CWG1CON2bits_t CWG1CON2bits
;
2559 #define _G1ASDSCLC2 0x01
2560 #define _G1ASDSFLT 0x02
2561 #define _G1ARSEN 0x40
2564 //==============================================================================
2567 //==============================================================================
2570 extern __at(0x0F0F) __sfr CLCDATA
;
2574 unsigned MCLC1OUT
: 1;
2575 unsigned MCLC2OUT
: 1;
2584 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
2586 #define _MCLC1OUT 0x01
2587 #define _MCLC2OUT 0x02
2589 //==============================================================================
2592 //==============================================================================
2595 extern __at(0x0F10) __sfr CLC1CON
;
2601 unsigned LC1MODE0
: 1;
2602 unsigned LC1MODE1
: 1;
2603 unsigned LC1MODE2
: 1;
2604 unsigned LC1INTN
: 1;
2605 unsigned LC1INTP
: 1;
2606 unsigned LC1OUT
: 1;
2613 unsigned LCMODE0
: 1;
2614 unsigned LCMODE1
: 1;
2615 unsigned LCMODE2
: 1;
2616 unsigned LCINTN
: 1;
2617 unsigned LCINTP
: 1;
2625 unsigned LCMODE
: 3;
2631 unsigned LC1MODE
: 3;
2636 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
2638 #define _LC1MODE0 0x01
2639 #define _LCMODE0 0x01
2640 #define _LC1MODE1 0x02
2641 #define _LCMODE1 0x02
2642 #define _LC1MODE2 0x04
2643 #define _LCMODE2 0x04
2644 #define _LC1INTN 0x08
2645 #define _LCINTN 0x08
2646 #define _LC1INTP 0x10
2647 #define _LCINTP 0x10
2648 #define _LC1OUT 0x20
2655 //==============================================================================
2658 //==============================================================================
2661 extern __at(0x0F11) __sfr CLC1POL
;
2667 unsigned LC1G1POL
: 1;
2668 unsigned LC1G2POL
: 1;
2669 unsigned LC1G3POL
: 1;
2670 unsigned LC1G4POL
: 1;
2674 unsigned LC1POL
: 1;
2690 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
2692 #define _LC1G1POL 0x01
2694 #define _LC1G2POL 0x02
2696 #define _LC1G3POL 0x04
2698 #define _LC1G4POL 0x08
2700 #define _LC1POL 0x80
2703 //==============================================================================
2706 //==============================================================================
2709 extern __at(0x0F12) __sfr CLC1SEL0
;
2715 unsigned LC1D1S0
: 1;
2716 unsigned LC1D1S1
: 1;
2717 unsigned LC1D1S2
: 1;
2719 unsigned LC1D2S0
: 1;
2720 unsigned LC1D2S1
: 1;
2721 unsigned LC1D2S2
: 1;
2745 unsigned LC1D1S
: 3;
2752 unsigned LC1D2S
: 3;
2764 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
2766 #define _LC1D1S0 0x01
2768 #define _LC1D1S1 0x02
2770 #define _LC1D1S2 0x04
2772 #define _LC1D2S0 0x10
2774 #define _LC1D2S1 0x20
2776 #define _LC1D2S2 0x40
2779 //==============================================================================
2782 //==============================================================================
2785 extern __at(0x0F13) __sfr CLC1SEL1
;
2791 unsigned LC1D3S0
: 1;
2792 unsigned LC1D3S1
: 1;
2793 unsigned LC1D3S2
: 1;
2795 unsigned LC1D4S0
: 1;
2796 unsigned LC1D4S1
: 1;
2797 unsigned LC1D4S2
: 1;
2815 unsigned LC1D3S
: 3;
2835 unsigned LC1D4S
: 3;
2840 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
2842 #define _LC1D3S0 0x01
2844 #define _LC1D3S1 0x02
2846 #define _LC1D3S2 0x04
2848 #define _LC1D4S0 0x10
2850 #define _LC1D4S1 0x20
2852 #define _LC1D4S2 0x40
2855 //==============================================================================
2858 //==============================================================================
2861 extern __at(0x0F14) __sfr CLC1GLS0
;
2867 unsigned LC1G1D1N
: 1;
2868 unsigned LC1G1D1T
: 1;
2869 unsigned LC1G1D2N
: 1;
2870 unsigned LC1G1D2T
: 1;
2871 unsigned LC1G1D3N
: 1;
2872 unsigned LC1G1D3T
: 1;
2873 unsigned LC1G1D4N
: 1;
2874 unsigned LC1G1D4T
: 1;
2890 extern __at(0x0F14) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
2892 #define _LC1G1D1N 0x01
2894 #define _LC1G1D1T 0x02
2896 #define _LC1G1D2N 0x04
2898 #define _LC1G1D2T 0x08
2900 #define _LC1G1D3N 0x10
2902 #define _LC1G1D3T 0x20
2904 #define _LC1G1D4N 0x40
2906 #define _LC1G1D4T 0x80
2909 //==============================================================================
2912 //==============================================================================
2915 extern __at(0x0F15) __sfr CLC1GLS1
;
2921 unsigned LC1G2D1N
: 1;
2922 unsigned LC1G2D1T
: 1;
2923 unsigned LC1G2D2N
: 1;
2924 unsigned LC1G2D2T
: 1;
2925 unsigned LC1G2D3N
: 1;
2926 unsigned LC1G2D3T
: 1;
2927 unsigned LC1G2D4N
: 1;
2928 unsigned LC1G2D4T
: 1;
2944 extern __at(0x0F15) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
2946 #define _CLC1GLS1_LC1G2D1N 0x01
2947 #define _CLC1GLS1_D1N 0x01
2948 #define _CLC1GLS1_LC1G2D1T 0x02
2949 #define _CLC1GLS1_D1T 0x02
2950 #define _CLC1GLS1_LC1G2D2N 0x04
2951 #define _CLC1GLS1_D2N 0x04
2952 #define _CLC1GLS1_LC1G2D2T 0x08
2953 #define _CLC1GLS1_D2T 0x08
2954 #define _CLC1GLS1_LC1G2D3N 0x10
2955 #define _CLC1GLS1_D3N 0x10
2956 #define _CLC1GLS1_LC1G2D3T 0x20
2957 #define _CLC1GLS1_D3T 0x20
2958 #define _CLC1GLS1_LC1G2D4N 0x40
2959 #define _CLC1GLS1_D4N 0x40
2960 #define _CLC1GLS1_LC1G2D4T 0x80
2961 #define _CLC1GLS1_D4T 0x80
2963 //==============================================================================
2966 //==============================================================================
2969 extern __at(0x0F16) __sfr CLC1GLS2
;
2975 unsigned LC1G3D1N
: 1;
2976 unsigned LC1G3D1T
: 1;
2977 unsigned LC1G3D2N
: 1;
2978 unsigned LC1G3D2T
: 1;
2979 unsigned LC1G3D3N
: 1;
2980 unsigned LC1G3D3T
: 1;
2981 unsigned LC1G3D4N
: 1;
2982 unsigned LC1G3D4T
: 1;
2998 extern __at(0x0F16) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
3000 #define _CLC1GLS2_LC1G3D1N 0x01
3001 #define _CLC1GLS2_D1N 0x01
3002 #define _CLC1GLS2_LC1G3D1T 0x02
3003 #define _CLC1GLS2_D1T 0x02
3004 #define _CLC1GLS2_LC1G3D2N 0x04
3005 #define _CLC1GLS2_D2N 0x04
3006 #define _CLC1GLS2_LC1G3D2T 0x08
3007 #define _CLC1GLS2_D2T 0x08
3008 #define _CLC1GLS2_LC1G3D3N 0x10
3009 #define _CLC1GLS2_D3N 0x10
3010 #define _CLC1GLS2_LC1G3D3T 0x20
3011 #define _CLC1GLS2_D3T 0x20
3012 #define _CLC1GLS2_LC1G3D4N 0x40
3013 #define _CLC1GLS2_D4N 0x40
3014 #define _CLC1GLS2_LC1G3D4T 0x80
3015 #define _CLC1GLS2_D4T 0x80
3017 //==============================================================================
3020 //==============================================================================
3023 extern __at(0x0F17) __sfr CLC1GLS3
;
3029 unsigned LC1G4D1N
: 1;
3030 unsigned LC1G4D1T
: 1;
3031 unsigned LC1G4D2N
: 1;
3032 unsigned LC1G4D2T
: 1;
3033 unsigned LC1G4D3N
: 1;
3034 unsigned LC1G4D3T
: 1;
3035 unsigned LC1G4D4N
: 1;
3036 unsigned LC1G4D4T
: 1;
3052 extern __at(0x0F17) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
3054 #define _LC1G4D1N 0x01
3056 #define _LC1G4D1T 0x02
3058 #define _LC1G4D2N 0x04
3060 #define _LC1G4D2T 0x08
3062 #define _LC1G4D3N 0x10
3064 #define _LC1G4D3T 0x20
3066 #define _LC1G4D4N 0x40
3068 #define _LC1G4D4T 0x80
3071 //==============================================================================
3074 //==============================================================================
3077 extern __at(0x0F18) __sfr CLC2CON
;
3083 unsigned LC2MODE0
: 1;
3084 unsigned LC2MODE1
: 1;
3085 unsigned LC2MODE2
: 1;
3086 unsigned LC2INTN
: 1;
3087 unsigned LC2INTP
: 1;
3088 unsigned LC2OUT
: 1;
3095 unsigned LCMODE0
: 1;
3096 unsigned LCMODE1
: 1;
3097 unsigned LCMODE2
: 1;
3098 unsigned LCINTN
: 1;
3099 unsigned LCINTP
: 1;
3107 unsigned LC2MODE
: 3;
3113 unsigned LCMODE
: 3;
3118 extern __at(0x0F18) volatile __CLC2CONbits_t CLC2CONbits
;
3120 #define _CLC2CON_LC2MODE0 0x01
3121 #define _CLC2CON_LCMODE0 0x01
3122 #define _CLC2CON_LC2MODE1 0x02
3123 #define _CLC2CON_LCMODE1 0x02
3124 #define _CLC2CON_LC2MODE2 0x04
3125 #define _CLC2CON_LCMODE2 0x04
3126 #define _CLC2CON_LC2INTN 0x08
3127 #define _CLC2CON_LCINTN 0x08
3128 #define _CLC2CON_LC2INTP 0x10
3129 #define _CLC2CON_LCINTP 0x10
3130 #define _CLC2CON_LC2OUT 0x20
3131 #define _CLC2CON_LCOUT 0x20
3132 #define _CLC2CON_LC2OE 0x40
3133 #define _CLC2CON_LCOE 0x40
3134 #define _CLC2CON_LC2EN 0x80
3135 #define _CLC2CON_LCEN 0x80
3137 //==============================================================================
3140 //==============================================================================
3143 extern __at(0x0F19) __sfr CLC2POL
;
3149 unsigned LC2G1POL
: 1;
3150 unsigned LC2G2POL
: 1;
3151 unsigned LC2G3POL
: 1;
3152 unsigned LC2G4POL
: 1;
3156 unsigned LC2POL
: 1;
3172 extern __at(0x0F19) volatile __CLC2POLbits_t CLC2POLbits
;
3174 #define _CLC2POL_LC2G1POL 0x01
3175 #define _CLC2POL_G1POL 0x01
3176 #define _CLC2POL_LC2G2POL 0x02
3177 #define _CLC2POL_G2POL 0x02
3178 #define _CLC2POL_LC2G3POL 0x04
3179 #define _CLC2POL_G3POL 0x04
3180 #define _CLC2POL_LC2G4POL 0x08
3181 #define _CLC2POL_G4POL 0x08
3182 #define _CLC2POL_LC2POL 0x80
3183 #define _CLC2POL_POL 0x80
3185 //==============================================================================
3188 //==============================================================================
3191 extern __at(0x0F1A) __sfr CLC2SEL0
;
3197 unsigned LC2D1S0
: 1;
3198 unsigned LC2D1S1
: 1;
3199 unsigned LC2D1S2
: 1;
3201 unsigned LC2D2S0
: 1;
3202 unsigned LC2D2S1
: 1;
3203 unsigned LC2D2S2
: 1;
3221 unsigned LC2D1S
: 3;
3241 unsigned LC2D2S
: 3;
3246 extern __at(0x0F1A) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
3248 #define _CLC2SEL0_LC2D1S0 0x01
3249 #define _CLC2SEL0_D1S0 0x01
3250 #define _CLC2SEL0_LC2D1S1 0x02
3251 #define _CLC2SEL0_D1S1 0x02
3252 #define _CLC2SEL0_LC2D1S2 0x04
3253 #define _CLC2SEL0_D1S2 0x04
3254 #define _CLC2SEL0_LC2D2S0 0x10
3255 #define _CLC2SEL0_D2S0 0x10
3256 #define _CLC2SEL0_LC2D2S1 0x20
3257 #define _CLC2SEL0_D2S1 0x20
3258 #define _CLC2SEL0_LC2D2S2 0x40
3259 #define _CLC2SEL0_D2S2 0x40
3261 //==============================================================================
3264 //==============================================================================
3267 extern __at(0x0F1B) __sfr CLC2SEL1
;
3273 unsigned LC2D3S0
: 1;
3274 unsigned LC2D3S1
: 1;
3275 unsigned LC2D3S2
: 1;
3277 unsigned LC2D4S0
: 1;
3278 unsigned LC2D4S1
: 1;
3279 unsigned LC2D4S2
: 1;
3297 unsigned LC2D3S
: 3;
3317 unsigned LC2D4S
: 3;
3322 extern __at(0x0F1B) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
3324 #define _CLC2SEL1_LC2D3S0 0x01
3325 #define _CLC2SEL1_D3S0 0x01
3326 #define _CLC2SEL1_LC2D3S1 0x02
3327 #define _CLC2SEL1_D3S1 0x02
3328 #define _CLC2SEL1_LC2D3S2 0x04
3329 #define _CLC2SEL1_D3S2 0x04
3330 #define _CLC2SEL1_LC2D4S0 0x10
3331 #define _CLC2SEL1_D4S0 0x10
3332 #define _CLC2SEL1_LC2D4S1 0x20
3333 #define _CLC2SEL1_D4S1 0x20
3334 #define _CLC2SEL1_LC2D4S2 0x40
3335 #define _CLC2SEL1_D4S2 0x40
3337 //==============================================================================
3340 //==============================================================================
3343 extern __at(0x0F1C) __sfr CLC2GLS0
;
3349 unsigned LC2G1D1N
: 1;
3350 unsigned LC2G1D1T
: 1;
3351 unsigned LC2G1D2N
: 1;
3352 unsigned LC2G1D2T
: 1;
3353 unsigned LC2G1D3N
: 1;
3354 unsigned LC2G1D3T
: 1;
3355 unsigned LC2G1D4N
: 1;
3356 unsigned LC2G1D4T
: 1;
3372 extern __at(0x0F1C) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
3374 #define _CLC2GLS0_LC2G1D1N 0x01
3375 #define _CLC2GLS0_D1N 0x01
3376 #define _CLC2GLS0_LC2G1D1T 0x02
3377 #define _CLC2GLS0_D1T 0x02
3378 #define _CLC2GLS0_LC2G1D2N 0x04
3379 #define _CLC2GLS0_D2N 0x04
3380 #define _CLC2GLS0_LC2G1D2T 0x08
3381 #define _CLC2GLS0_D2T 0x08
3382 #define _CLC2GLS0_LC2G1D3N 0x10
3383 #define _CLC2GLS0_D3N 0x10
3384 #define _CLC2GLS0_LC2G1D3T 0x20
3385 #define _CLC2GLS0_D3T 0x20
3386 #define _CLC2GLS0_LC2G1D4N 0x40
3387 #define _CLC2GLS0_D4N 0x40
3388 #define _CLC2GLS0_LC2G1D4T 0x80
3389 #define _CLC2GLS0_D4T 0x80
3391 //==============================================================================
3394 //==============================================================================
3397 extern __at(0x0F1D) __sfr CLC2GLS1
;
3403 unsigned LC2G2D1N
: 1;
3404 unsigned LC2G2D1T
: 1;
3405 unsigned LC2G2D2N
: 1;
3406 unsigned LC2G2D2T
: 1;
3407 unsigned LC2G2D3N
: 1;
3408 unsigned LC2G2D3T
: 1;
3409 unsigned LC2G2D4N
: 1;
3410 unsigned LC2G2D4T
: 1;
3426 extern __at(0x0F1D) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
3428 #define _CLC2GLS1_LC2G2D1N 0x01
3429 #define _CLC2GLS1_D1N 0x01
3430 #define _CLC2GLS1_LC2G2D1T 0x02
3431 #define _CLC2GLS1_D1T 0x02
3432 #define _CLC2GLS1_LC2G2D2N 0x04
3433 #define _CLC2GLS1_D2N 0x04
3434 #define _CLC2GLS1_LC2G2D2T 0x08
3435 #define _CLC2GLS1_D2T 0x08
3436 #define _CLC2GLS1_LC2G2D3N 0x10
3437 #define _CLC2GLS1_D3N 0x10
3438 #define _CLC2GLS1_LC2G2D3T 0x20
3439 #define _CLC2GLS1_D3T 0x20
3440 #define _CLC2GLS1_LC2G2D4N 0x40
3441 #define _CLC2GLS1_D4N 0x40
3442 #define _CLC2GLS1_LC2G2D4T 0x80
3443 #define _CLC2GLS1_D4T 0x80
3445 //==============================================================================
3448 //==============================================================================
3451 extern __at(0x0F1E) __sfr CLC2GLS2
;
3457 unsigned LC2G3D1N
: 1;
3458 unsigned LC2G3D1T
: 1;
3459 unsigned LC2G3D2N
: 1;
3460 unsigned LC2G3D2T
: 1;
3461 unsigned LC2G3D3N
: 1;
3462 unsigned LC2G3D3T
: 1;
3463 unsigned LC2G3D4N
: 1;
3464 unsigned LC2G3D4T
: 1;
3480 extern __at(0x0F1E) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
3482 #define _CLC2GLS2_LC2G3D1N 0x01
3483 #define _CLC2GLS2_D1N 0x01
3484 #define _CLC2GLS2_LC2G3D1T 0x02
3485 #define _CLC2GLS2_D1T 0x02
3486 #define _CLC2GLS2_LC2G3D2N 0x04
3487 #define _CLC2GLS2_D2N 0x04
3488 #define _CLC2GLS2_LC2G3D2T 0x08
3489 #define _CLC2GLS2_D2T 0x08
3490 #define _CLC2GLS2_LC2G3D3N 0x10
3491 #define _CLC2GLS2_D3N 0x10
3492 #define _CLC2GLS2_LC2G3D3T 0x20
3493 #define _CLC2GLS2_D3T 0x20
3494 #define _CLC2GLS2_LC2G3D4N 0x40
3495 #define _CLC2GLS2_D4N 0x40
3496 #define _CLC2GLS2_LC2G3D4T 0x80
3497 #define _CLC2GLS2_D4T 0x80
3499 //==============================================================================
3502 //==============================================================================
3505 extern __at(0x0F1F) __sfr CLC2GLS3
;
3511 unsigned LC2G4D1N
: 1;
3512 unsigned LC2G4D1T
: 1;
3513 unsigned LC2G4D2N
: 1;
3514 unsigned LC2G4D2T
: 1;
3515 unsigned LC2G4D3N
: 1;
3516 unsigned LC2G4D3T
: 1;
3517 unsigned LC2G4D4N
: 1;
3518 unsigned LC2G4D4T
: 1;
3534 extern __at(0x0F1F) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
3536 #define _CLC2GLS3_LC2G4D1N 0x01
3537 #define _CLC2GLS3_G4D1N 0x01
3538 #define _CLC2GLS3_LC2G4D1T 0x02
3539 #define _CLC2GLS3_G4D1T 0x02
3540 #define _CLC2GLS3_LC2G4D2N 0x04
3541 #define _CLC2GLS3_G4D2N 0x04
3542 #define _CLC2GLS3_LC2G4D2T 0x08
3543 #define _CLC2GLS3_G4D2T 0x08
3544 #define _CLC2GLS3_LC2G4D3N 0x10
3545 #define _CLC2GLS3_G4D3N 0x10
3546 #define _CLC2GLS3_LC2G4D3T 0x20
3547 #define _CLC2GLS3_G4D3T 0x20
3548 #define _CLC2GLS3_LC2G4D4N 0x40
3549 #define _CLC2GLS3_G4D4N 0x40
3550 #define _CLC2GLS3_LC2G4D4T 0x80
3551 #define _CLC2GLS3_G4D4T 0x80
3553 //==============================================================================
3555 extern __at(0x0FE3) __sfr BSR_ICDSHAD
;
3557 //==============================================================================
3560 extern __at(0x0FE4) __sfr STATUS_SHAD
;
3564 unsigned C_SHAD
: 1;
3565 unsigned DC_SHAD
: 1;
3566 unsigned Z_SHAD
: 1;
3572 } __STATUS_SHADbits_t
;
3574 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
3576 #define _C_SHAD 0x01
3577 #define _DC_SHAD 0x02
3578 #define _Z_SHAD 0x04
3580 //==============================================================================
3582 extern __at(0x0FE5) __sfr WREG_SHAD
;
3583 extern __at(0x0FE6) __sfr BSR_SHAD
;
3584 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
3585 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
3586 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
3587 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
3588 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
3589 extern __at(0x0FED) __sfr STKPTR
;
3590 extern __at(0x0FEE) __sfr TOSL
;
3591 extern __at(0x0FEF) __sfr TOSH
;
3593 //==============================================================================
3595 // Configuration Bits
3597 //==============================================================================
3599 #define _CONFIG1 0x8007
3600 #define _CONFIG2 0x8008
3602 //----------------------------- CONFIG1 Options -------------------------------
3604 #define _FOSC_INTOSC 0x3FFC // Internal Oscillator, I/O function on OSC1.
3605 #define _FOSC_ECL 0x3FFD // External Clock, Low Power Mode.
3606 #define _FOSC_ECM 0x3FFE // External Clock, Medium Power Mode.
3607 #define _FOSC_ECH 0x3FFF // External Clock, High Power Mode.
3608 #define _WDTE_OFF 0x3FE7 // WDT disabled.
3609 #define _WDTE_SWDTEN 0x3FEF // WDT controlled by the SWDTEN bit in the WDTCON register.
3610 #define _WDTE_NSLEEP 0x3FF7 // WDT enabled while running and disabled in Sleep.
3611 #define _WDTE_ON 0x3FFF // WDT enabled.
3612 #define _PWRTE_ON 0x3FDF // PWRT enabled.
3613 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
3614 #define _MCLRE_OFF 0x3FBF // MCLR/VPP pin function is digital input.
3615 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR.
3616 #define _CP_ON 0x3F7F // Program memory code protection is enabled.
3617 #define _CP_OFF 0x3FFF // Program memory code protection is disabled.
3618 #define _BOREN_OFF 0x39FF // Brown-out Reset disabled.
3619 #define _BOREN_SBODEN 0x3BFF // Brown-out Reset controlled by the SBOREN bit in the BORCON register.
3620 #define _BOREN_NSLEEP 0x3DFF // Brown-out Reset enabled while running and disabled in Sleep.
3621 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled.
3622 #define _CLKOUTEN_ON 0x37FF // CLKOUT function is enabled on the CLKOUT pin.
3623 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin.
3625 //----------------------------- CONFIG2 Options -------------------------------
3627 #define _WRT_ALL 0x3FFC // 000h to 1FFFh write protected, no addresses may be modified by EECON control.
3628 #define _WRT_HALF 0x3FFD // 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control.
3629 #define _WRT_BOOT 0x3FFE // 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control.
3630 #define _WRT_OFF 0x3FFF // Write protection off.
3631 #define _STVREN_OFF 0x3DFF // Stack Overflow or Underflow will not cause a Reset.
3632 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
3633 #define _BORV_HI 0x3BFF // Brown-out Reset Voltage (Vbor), high trip point selected.
3634 #define _BORV_LO 0x3FFF // Brown-out Reset Voltage (Vbor), low trip point selected.
3635 #define _LPBOR_ON 0x37FF // Low-Power BOR is enabled.
3636 #define _LPBOR_OFF 0x3FFF // Low-Power BOR is disabled.
3637 #define _LVP_OFF 0x1FFF // High-voltage on MCLR/VPP must be used for programming.
3638 #define _LVP_ON 0x3FFF // Low-voltage programming enabled.
3640 //==============================================================================
3642 #define _DEVID1 0x8006
3644 #define _IDLOC0 0x8000
3645 #define _IDLOC1 0x8001
3646 #define _IDLOC2 0x8002
3647 #define _IDLOC3 0x8003
3649 //==============================================================================
3651 #ifndef NO_BIT_DEFINES
3653 #define ADON ADCON0bits.ADON // bit 0
3654 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
3655 #define ADGO ADCON0bits.ADGO // bit 1, shadows bit in ADCON0bits
3656 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
3657 #define CHS0 ADCON0bits.CHS0 // bit 2
3658 #define CHS1 ADCON0bits.CHS1 // bit 3
3659 #define CHS2 ADCON0bits.CHS2 // bit 4
3660 #define CHS3 ADCON0bits.CHS3 // bit 5
3661 #define CHS4 ADCON0bits.CHS4 // bit 6
3663 #define ADPREF0 ADCON1bits.ADPREF0 // bit 0
3664 #define ADPREF1 ADCON1bits.ADPREF1 // bit 1
3665 #define ADCS0 ADCON1bits.ADCS0 // bit 4
3666 #define ADCS1 ADCON1bits.ADCS1 // bit 5
3667 #define ADCS2 ADCON1bits.ADCS2 // bit 6
3668 #define ADFM ADCON1bits.ADFM // bit 7
3670 #define TRIGSEL0 ADCON2bits.TRIGSEL0 // bit 4
3671 #define TRIGSEL1 ADCON2bits.TRIGSEL1 // bit 5
3672 #define TRIGSEL2 ADCON2bits.TRIGSEL2 // bit 6
3673 #define TRIGSEL3 ADCON2bits.TRIGSEL3 // bit 7
3675 #define ANSA0 ANSELAbits.ANSA0 // bit 0
3676 #define ANSA1 ANSELAbits.ANSA1 // bit 1
3677 #define ANSA2 ANSELAbits.ANSA2 // bit 2
3678 #define ANSA4 ANSELAbits.ANSA4 // bit 4
3680 #define ANSB4 ANSELBbits.ANSB4 // bit 4
3681 #define ANSB5 ANSELBbits.ANSB5 // bit 5
3683 #define ANSC0 ANSELCbits.ANSC0 // bit 0
3684 #define ANSC1 ANSELCbits.ANSC1 // bit 1
3685 #define ANSC2 ANSELCbits.ANSC2 // bit 2
3686 #define ANSC3 ANSELCbits.ANSC3 // bit 3
3687 #define ANSC6 ANSELCbits.ANSC6 // bit 6
3688 #define ANSC7 ANSELCbits.ANSC7 // bit 7
3690 #define NCO1SEL APFCONbits.NCO1SEL // bit 0
3691 #define CLC1SEL APFCONbits.CLC1SEL // bit 1
3693 #define BORRDY BORCONbits.BORRDY // bit 0
3694 #define BORFS BORCONbits.BORFS // bit 6
3695 #define SBOREN BORCONbits.SBOREN // bit 7
3697 #define BSR0 BSRbits.BSR0 // bit 0
3698 #define BSR1 BSRbits.BSR1 // bit 1
3699 #define BSR2 BSRbits.BSR2 // bit 2
3700 #define BSR3 BSRbits.BSR3 // bit 3
3701 #define BSR4 BSRbits.BSR4 // bit 4
3703 #define LC1MODE0 CLC1CONbits.LC1MODE0 // bit 0, shadows bit in CLC1CONbits
3704 #define LCMODE0 CLC1CONbits.LCMODE0 // bit 0, shadows bit in CLC1CONbits
3705 #define LC1MODE1 CLC1CONbits.LC1MODE1 // bit 1, shadows bit in CLC1CONbits
3706 #define LCMODE1 CLC1CONbits.LCMODE1 // bit 1, shadows bit in CLC1CONbits
3707 #define LC1MODE2 CLC1CONbits.LC1MODE2 // bit 2, shadows bit in CLC1CONbits
3708 #define LCMODE2 CLC1CONbits.LCMODE2 // bit 2, shadows bit in CLC1CONbits
3709 #define LC1INTN CLC1CONbits.LC1INTN // bit 3, shadows bit in CLC1CONbits
3710 #define LCINTN CLC1CONbits.LCINTN // bit 3, shadows bit in CLC1CONbits
3711 #define LC1INTP CLC1CONbits.LC1INTP // bit 4, shadows bit in CLC1CONbits
3712 #define LCINTP CLC1CONbits.LCINTP // bit 4, shadows bit in CLC1CONbits
3713 #define LC1OUT CLC1CONbits.LC1OUT // bit 5, shadows bit in CLC1CONbits
3714 #define LCOUT CLC1CONbits.LCOUT // bit 5, shadows bit in CLC1CONbits
3715 #define LC1OE CLC1CONbits.LC1OE // bit 6, shadows bit in CLC1CONbits
3716 #define LCOE CLC1CONbits.LCOE // bit 6, shadows bit in CLC1CONbits
3717 #define LC1EN CLC1CONbits.LC1EN // bit 7, shadows bit in CLC1CONbits
3718 #define LCEN CLC1CONbits.LCEN // bit 7, shadows bit in CLC1CONbits
3720 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
3721 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
3722 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
3723 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
3724 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
3725 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
3726 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
3727 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
3728 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
3729 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
3730 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
3731 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
3732 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
3733 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
3734 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
3735 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
3737 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
3738 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
3739 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
3740 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
3741 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
3742 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
3743 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
3744 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
3745 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
3746 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
3747 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
3748 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
3749 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
3750 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
3751 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
3752 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
3754 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
3755 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
3756 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
3757 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
3758 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
3759 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
3760 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
3761 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
3762 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
3763 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
3765 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
3766 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
3767 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
3768 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
3769 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
3770 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
3771 #define LC1D2S0 CLC1SEL0bits.LC1D2S0 // bit 4, shadows bit in CLC1SEL0bits
3772 #define D2S0 CLC1SEL0bits.D2S0 // bit 4, shadows bit in CLC1SEL0bits
3773 #define LC1D2S1 CLC1SEL0bits.LC1D2S1 // bit 5, shadows bit in CLC1SEL0bits
3774 #define D2S1 CLC1SEL0bits.D2S1 // bit 5, shadows bit in CLC1SEL0bits
3775 #define LC1D2S2 CLC1SEL0bits.LC1D2S2 // bit 6, shadows bit in CLC1SEL0bits
3776 #define D2S2 CLC1SEL0bits.D2S2 // bit 6, shadows bit in CLC1SEL0bits
3778 #define LC1D3S0 CLC1SEL1bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL1bits
3779 #define D3S0 CLC1SEL1bits.D3S0 // bit 0, shadows bit in CLC1SEL1bits
3780 #define LC1D3S1 CLC1SEL1bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL1bits
3781 #define D3S1 CLC1SEL1bits.D3S1 // bit 1, shadows bit in CLC1SEL1bits
3782 #define LC1D3S2 CLC1SEL1bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL1bits
3783 #define D3S2 CLC1SEL1bits.D3S2 // bit 2, shadows bit in CLC1SEL1bits
3784 #define LC1D4S0 CLC1SEL1bits.LC1D4S0 // bit 4, shadows bit in CLC1SEL1bits
3785 #define D4S0 CLC1SEL1bits.D4S0 // bit 4, shadows bit in CLC1SEL1bits
3786 #define LC1D4S1 CLC1SEL1bits.LC1D4S1 // bit 5, shadows bit in CLC1SEL1bits
3787 #define D4S1 CLC1SEL1bits.D4S1 // bit 5, shadows bit in CLC1SEL1bits
3788 #define LC1D4S2 CLC1SEL1bits.LC1D4S2 // bit 6, shadows bit in CLC1SEL1bits
3789 #define D4S2 CLC1SEL1bits.D4S2 // bit 6, shadows bit in CLC1SEL1bits
3791 #define MCLC1OUT CLCDATAbits.MCLC1OUT // bit 0
3792 #define MCLC2OUT CLCDATAbits.MCLC2OUT // bit 1
3794 #define G1CS0 CWG1CON0bits.G1CS0 // bit 0
3795 #define G1POLA CWG1CON0bits.G1POLA // bit 3
3796 #define G1POLB CWG1CON0bits.G1POLB // bit 4
3797 #define G1OEA CWG1CON0bits.G1OEA // bit 5
3798 #define G1OEB CWG1CON0bits.G1OEB // bit 6
3799 #define G1EN CWG1CON0bits.G1EN // bit 7
3801 #define G1IS0 CWG1CON1bits.G1IS0 // bit 0
3802 #define G1IS1 CWG1CON1bits.G1IS1 // bit 1
3803 #define G1IS2 CWG1CON1bits.G1IS2 // bit 2
3804 #define G1ASDLA0 CWG1CON1bits.G1ASDLA0 // bit 4
3805 #define G1ASDLA1 CWG1CON1bits.G1ASDLA1 // bit 5
3806 #define G1ASDLB0 CWG1CON1bits.G1ASDLB0 // bit 6
3807 #define G1ASDLB1 CWG1CON1bits.G1ASDLB1 // bit 7
3809 #define G1ASDSCLC2 CWG1CON2bits.G1ASDSCLC2 // bit 0
3810 #define G1ASDSFLT CWG1CON2bits.G1ASDSFLT // bit 1
3811 #define G1ARSEN CWG1CON2bits.G1ARSEN // bit 6
3812 #define G1ASE CWG1CON2bits.G1ASE // bit 7
3814 #define CWG1DBF0 CWG1DBFbits.CWG1DBF0 // bit 0
3815 #define CWG1DBF1 CWG1DBFbits.CWG1DBF1 // bit 1
3816 #define CWG1DBF2 CWG1DBFbits.CWG1DBF2 // bit 2
3817 #define CWG1DBF3 CWG1DBFbits.CWG1DBF3 // bit 3
3818 #define CWG1DBF4 CWG1DBFbits.CWG1DBF4 // bit 4
3819 #define CWG1DBF5 CWG1DBFbits.CWG1DBF5 // bit 5
3821 #define CWG1DBR0 CWG1DBRbits.CWG1DBR0 // bit 0
3822 #define CWG1DBR1 CWG1DBRbits.CWG1DBR1 // bit 1
3823 #define CWG1DBR2 CWG1DBRbits.CWG1DBR2 // bit 2
3824 #define CWG1DBR3 CWG1DBRbits.CWG1DBR3 // bit 3
3825 #define CWG1DBR4 CWG1DBRbits.CWG1DBR4 // bit 4
3826 #define CWG1DBR5 CWG1DBRbits.CWG1DBR5 // bit 5
3828 #define ADFVR0 FVRCONbits.ADFVR0 // bit 0
3829 #define ADFVR1 FVRCONbits.ADFVR1 // bit 1
3830 #define TSRNG FVRCONbits.TSRNG // bit 4
3831 #define TSEN FVRCONbits.TSEN // bit 5
3832 #define FVRRDY FVRCONbits.FVRRDY // bit 6
3833 #define FVREN FVRCONbits.FVREN // bit 7
3835 #define IOCIF INTCONbits.IOCIF // bit 0
3836 #define INTF INTCONbits.INTF // bit 1
3837 #define TMR0IF INTCONbits.TMR0IF // bit 2, shadows bit in INTCONbits
3838 #define T0IF INTCONbits.T0IF // bit 2, shadows bit in INTCONbits
3839 #define IOCIE INTCONbits.IOCIE // bit 3
3840 #define INTE INTCONbits.INTE // bit 4
3841 #define TMR0IE INTCONbits.TMR0IE // bit 5, shadows bit in INTCONbits
3842 #define T0IE INTCONbits.T0IE // bit 5, shadows bit in INTCONbits
3843 #define PEIE INTCONbits.PEIE // bit 6
3844 #define GIE INTCONbits.GIE // bit 7
3846 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
3847 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
3848 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
3849 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
3850 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
3851 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
3853 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
3854 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
3855 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
3856 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
3857 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
3858 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
3860 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
3861 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
3862 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
3863 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
3864 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
3865 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
3867 #define IOCBF4 IOCBFbits.IOCBF4 // bit 4
3868 #define IOCBF5 IOCBFbits.IOCBF5 // bit 5
3869 #define IOCBF6 IOCBFbits.IOCBF6 // bit 6
3870 #define IOCBF7 IOCBFbits.IOCBF7 // bit 7
3872 #define IOCBN4 IOCBNbits.IOCBN4 // bit 4
3873 #define IOCBN5 IOCBNbits.IOCBN5 // bit 5
3874 #define IOCBN6 IOCBNbits.IOCBN6 // bit 6
3875 #define IOCBN7 IOCBNbits.IOCBN7 // bit 7
3877 #define IOCBP4 IOCBPbits.IOCBP4 // bit 4
3878 #define IOCBP5 IOCBPbits.IOCBP5 // bit 5
3879 #define IOCBP6 IOCBPbits.IOCBP6 // bit 6
3880 #define IOCBP7 IOCBPbits.IOCBP7 // bit 7
3882 #define LATA0 LATAbits.LATA0 // bit 0
3883 #define LATA1 LATAbits.LATA1 // bit 1
3884 #define LATA2 LATAbits.LATA2 // bit 2
3885 #define LATA4 LATAbits.LATA4 // bit 4
3886 #define LATA5 LATAbits.LATA5 // bit 5
3888 #define LATB4 LATBbits.LATB4 // bit 4
3889 #define LATB5 LATBbits.LATB5 // bit 5
3890 #define LATB6 LATBbits.LATB6 // bit 6
3891 #define LATB7 LATBbits.LATB7 // bit 7
3893 #define LATC0 LATCbits.LATC0 // bit 0
3894 #define LATC1 LATCbits.LATC1 // bit 1
3895 #define LATC2 LATCbits.LATC2 // bit 2
3896 #define LATC3 LATCbits.LATC3 // bit 3
3897 #define LATC4 LATCbits.LATC4 // bit 4
3898 #define LATC5 LATCbits.LATC5 // bit 5
3899 #define LATC6 LATCbits.LATC6 // bit 6
3900 #define LATC7 LATCbits.LATC7 // bit 7
3902 #define NCO1ACC8 NCO1ACCHbits.NCO1ACC8 // bit 0
3903 #define NCO1ACC9 NCO1ACCHbits.NCO1ACC9 // bit 1
3904 #define NCO1ACC10 NCO1ACCHbits.NCO1ACC10 // bit 2
3905 #define NCO1ACC11 NCO1ACCHbits.NCO1ACC11 // bit 3
3906 #define NCO1ACC12 NCO1ACCHbits.NCO1ACC12 // bit 4
3907 #define NCO1ACC13 NCO1ACCHbits.NCO1ACC13 // bit 5
3908 #define NCO1ACC14 NCO1ACCHbits.NCO1ACC14 // bit 6
3909 #define NCO1ACC15 NCO1ACCHbits.NCO1ACC15 // bit 7
3911 #define NCO1ACC0 NCO1ACCLbits.NCO1ACC0 // bit 0
3912 #define NCO1ACC1 NCO1ACCLbits.NCO1ACC1 // bit 1
3913 #define NCO1ACC2 NCO1ACCLbits.NCO1ACC2 // bit 2
3914 #define NCO1ACC3 NCO1ACCLbits.NCO1ACC3 // bit 3
3915 #define NCO1ACC4 NCO1ACCLbits.NCO1ACC4 // bit 4
3916 #define NCO1ACC5 NCO1ACCLbits.NCO1ACC5 // bit 5
3917 #define NCO1ACC6 NCO1ACCLbits.NCO1ACC6 // bit 6
3918 #define NCO1ACC7 NCO1ACCLbits.NCO1ACC7 // bit 7
3920 #define NCO1ACC16 NCO1ACCUbits.NCO1ACC16 // bit 0
3921 #define NCO1ACC17 NCO1ACCUbits.NCO1ACC17 // bit 1
3922 #define NCO1ACC18 NCO1ACCUbits.NCO1ACC18 // bit 2
3923 #define NCO1ACC19 NCO1ACCUbits.NCO1ACC19 // bit 3
3925 #define N1CKS0 NCO1CLKbits.N1CKS0 // bit 0
3926 #define N1CKS1 NCO1CLKbits.N1CKS1 // bit 1
3927 #define N1PWS0 NCO1CLKbits.N1PWS0 // bit 5
3928 #define N1PWS1 NCO1CLKbits.N1PWS1 // bit 6
3929 #define N1PWS2 NCO1CLKbits.N1PWS2 // bit 7
3931 #define N1PFM NCO1CONbits.N1PFM // bit 0
3932 #define N1POL NCO1CONbits.N1POL // bit 4
3933 #define N1OUT NCO1CONbits.N1OUT // bit 5
3934 #define N1OE NCO1CONbits.N1OE // bit 6
3935 #define N1EN NCO1CONbits.N1EN // bit 7
3937 #define NCO1INC8 NCO1INCHbits.NCO1INC8 // bit 0
3938 #define NCO1INC9 NCO1INCHbits.NCO1INC9 // bit 1
3939 #define NCO1INC10 NCO1INCHbits.NCO1INC10 // bit 2
3940 #define NCO1INC11 NCO1INCHbits.NCO1INC11 // bit 3
3941 #define NCO1INC12 NCO1INCHbits.NCO1INC12 // bit 4
3942 #define NCO1INC13 NCO1INCHbits.NCO1INC13 // bit 5
3943 #define NCO1INC14 NCO1INCHbits.NCO1INC14 // bit 6
3944 #define NCO1INC15 NCO1INCHbits.NCO1INC15 // bit 7
3946 #define NCO1INC0 NCO1INCLbits.NCO1INC0 // bit 0
3947 #define NCO1INC1 NCO1INCLbits.NCO1INC1 // bit 1
3948 #define NCO1INC2 NCO1INCLbits.NCO1INC2 // bit 2
3949 #define NCO1INC3 NCO1INCLbits.NCO1INC3 // bit 3
3950 #define NCO1INC4 NCO1INCLbits.NCO1INC4 // bit 4
3951 #define NCO1INC5 NCO1INCLbits.NCO1INC5 // bit 5
3952 #define NCO1INC6 NCO1INCLbits.NCO1INC6 // bit 6
3953 #define NCO1INC7 NCO1INCLbits.NCO1INC7 // bit 7
3955 #define PS0 OPTION_REGbits.PS0 // bit 0
3956 #define PS1 OPTION_REGbits.PS1 // bit 1
3957 #define PS2 OPTION_REGbits.PS2 // bit 2
3958 #define PSA OPTION_REGbits.PSA // bit 3
3959 #define TMR0SE OPTION_REGbits.TMR0SE // bit 4, shadows bit in OPTION_REGbits
3960 #define T0SE OPTION_REGbits.T0SE // bit 4, shadows bit in OPTION_REGbits
3961 #define TMR0CS OPTION_REGbits.TMR0CS // bit 5, shadows bit in OPTION_REGbits
3962 #define T0CS OPTION_REGbits.T0CS // bit 5, shadows bit in OPTION_REGbits
3963 #define INTEDG OPTION_REGbits.INTEDG // bit 6
3964 #define NOT_WPUEN OPTION_REGbits.NOT_WPUEN // bit 7
3966 #define SCS0 OSCCONbits.SCS0 // bit 0
3967 #define SCS1 OSCCONbits.SCS1 // bit 1
3968 #define IRCF0 OSCCONbits.IRCF0 // bit 3
3969 #define IRCF1 OSCCONbits.IRCF1 // bit 4
3970 #define IRCF2 OSCCONbits.IRCF2 // bit 5
3971 #define IRCF3 OSCCONbits.IRCF3 // bit 6
3973 #define HFIOFS OSCSTATbits.HFIOFS // bit 0
3974 #define LFIOFR OSCSTATbits.LFIOFR // bit 1
3975 #define HFIOFR OSCSTATbits.HFIOFR // bit 4
3976 #define OSTS OSCSTATbits.OSTS // bit 5
3977 #define SOSCR OSCSTATbits.SOSCR // bit 7
3979 #define NOT_BOR PCONbits.NOT_BOR // bit 0
3980 #define NOT_POR PCONbits.NOT_POR // bit 1
3981 #define NOT_RI PCONbits.NOT_RI // bit 2
3982 #define NOT_RMCLR PCONbits.NOT_RMCLR // bit 3
3983 #define NOT_RWDT PCONbits.NOT_RWDT // bit 4
3984 #define STKUNF PCONbits.STKUNF // bit 6
3985 #define STKOVF PCONbits.STKOVF // bit 7
3987 #define TMR1IE PIE1bits.TMR1IE // bit 0
3988 #define TMR2IE PIE1bits.TMR2IE // bit 1
3989 #define ADIE PIE1bits.ADIE // bit 6
3990 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
3992 #define NCO1IE PIE2bits.NCO1IE // bit 2
3994 #define CLC1IE PIE3bits.CLC1IE // bit 0
3995 #define CLC2IE PIE3bits.CLC2IE // bit 1
3997 #define TMR1IF PIR1bits.TMR1IF // bit 0
3998 #define TMR2IF PIR1bits.TMR2IF // bit 1
3999 #define ADIF PIR1bits.ADIF // bit 6
4000 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
4002 #define NCO1IF PIR2bits.NCO1IF // bit 2
4004 #define CLC1IF PIR3bits.CLC1IF // bit 0
4005 #define CLC2IF PIR3bits.CLC2IF // bit 1
4007 #define RD PMCON1bits.RD // bit 0
4008 #define WR PMCON1bits.WR // bit 1
4009 #define WREN PMCON1bits.WREN // bit 2
4010 #define WRERR PMCON1bits.WRERR // bit 3
4011 #define FREE PMCON1bits.FREE // bit 4
4012 #define LWLO PMCON1bits.LWLO // bit 5
4013 #define CFGS PMCON1bits.CFGS // bit 6
4015 #define RA0 PORTAbits.RA0 // bit 0
4016 #define RA1 PORTAbits.RA1 // bit 1
4017 #define RA2 PORTAbits.RA2 // bit 2
4018 #define RA3 PORTAbits.RA3 // bit 3
4019 #define RA4 PORTAbits.RA4 // bit 4
4020 #define RA5 PORTAbits.RA5 // bit 5
4022 #define RB4 PORTBbits.RB4 // bit 4
4023 #define RB5 PORTBbits.RB5 // bit 5
4024 #define RB6 PORTBbits.RB6 // bit 6
4025 #define RB7 PORTBbits.RB7 // bit 7
4027 #define RC0 PORTCbits.RC0 // bit 0
4028 #define RC1 PORTCbits.RC1 // bit 1
4029 #define RC2 PORTCbits.RC2 // bit 2
4030 #define RC3 PORTCbits.RC3 // bit 3
4031 #define RC4 PORTCbits.RC4 // bit 4
4032 #define RC5 PORTCbits.RC5 // bit 5
4033 #define RC6 PORTCbits.RC6 // bit 6
4034 #define RC7 PORTCbits.RC7 // bit 7
4036 #define PWM1POL PWM1CONbits.PWM1POL // bit 4
4037 #define PWM1OUT PWM1CONbits.PWM1OUT // bit 5
4038 #define PWM1OE PWM1CONbits.PWM1OE // bit 6
4039 #define PWM1EN PWM1CONbits.PWM1EN // bit 7
4041 #define PWM1DCH0 PWM1DCHbits.PWM1DCH0 // bit 0
4042 #define PWM1DCH1 PWM1DCHbits.PWM1DCH1 // bit 1
4043 #define PWM1DCH2 PWM1DCHbits.PWM1DCH2 // bit 2
4044 #define PWM1DCH3 PWM1DCHbits.PWM1DCH3 // bit 3
4045 #define PWM1DCH4 PWM1DCHbits.PWM1DCH4 // bit 4
4046 #define PWM1DCH5 PWM1DCHbits.PWM1DCH5 // bit 5
4047 #define PWM1DCH6 PWM1DCHbits.PWM1DCH6 // bit 6
4048 #define PWM1DCH7 PWM1DCHbits.PWM1DCH7 // bit 7
4050 #define PWM1DCL0 PWM1DCLbits.PWM1DCL0 // bit 6
4051 #define PWM1DCL1 PWM1DCLbits.PWM1DCL1 // bit 7
4053 #define PWM2POL PWM2CONbits.PWM2POL // bit 4
4054 #define PWM2OUT PWM2CONbits.PWM2OUT // bit 5
4055 #define PWM2OE PWM2CONbits.PWM2OE // bit 6
4056 #define PWM2EN PWM2CONbits.PWM2EN // bit 7
4058 #define PWM2DCH0 PWM2DCHbits.PWM2DCH0 // bit 0
4059 #define PWM2DCH1 PWM2DCHbits.PWM2DCH1 // bit 1
4060 #define PWM2DCH2 PWM2DCHbits.PWM2DCH2 // bit 2
4061 #define PWM2DCH3 PWM2DCHbits.PWM2DCH3 // bit 3
4062 #define PWM2DCH4 PWM2DCHbits.PWM2DCH4 // bit 4
4063 #define PWM2DCH5 PWM2DCHbits.PWM2DCH5 // bit 5
4064 #define PWM2DCH6 PWM2DCHbits.PWM2DCH6 // bit 6
4065 #define PWM2DCH7 PWM2DCHbits.PWM2DCH7 // bit 7
4067 #define PWM2DCL0 PWM2DCLbits.PWM2DCL0 // bit 6
4068 #define PWM2DCL1 PWM2DCLbits.PWM2DCL1 // bit 7
4070 #define PWM3POL PWM3CONbits.PWM3POL // bit 4
4071 #define PWM3OUT PWM3CONbits.PWM3OUT // bit 5
4072 #define PWM3OE PWM3CONbits.PWM3OE // bit 6
4073 #define PWM3EN PWM3CONbits.PWM3EN // bit 7
4075 #define PWM3DCH0 PWM3DCHbits.PWM3DCH0 // bit 0
4076 #define PWM3DCH1 PWM3DCHbits.PWM3DCH1 // bit 1
4077 #define PWM3DCH2 PWM3DCHbits.PWM3DCH2 // bit 2
4078 #define PWM3DCH3 PWM3DCHbits.PWM3DCH3 // bit 3
4079 #define PWM3DCH4 PWM3DCHbits.PWM3DCH4 // bit 4
4080 #define PWM3DCH5 PWM3DCHbits.PWM3DCH5 // bit 5
4081 #define PWM3DCH6 PWM3DCHbits.PWM3DCH6 // bit 6
4082 #define PWM3DCH7 PWM3DCHbits.PWM3DCH7 // bit 7
4084 #define PWM3DCL0 PWM3DCLbits.PWM3DCL0 // bit 6
4085 #define PWM3DCL1 PWM3DCLbits.PWM3DCL1 // bit 7
4087 #define PWM4POL PWM4CONbits.PWM4POL // bit 4
4088 #define PWM4OUT PWM4CONbits.PWM4OUT // bit 5
4089 #define PWM4OE PWM4CONbits.PWM4OE // bit 6
4090 #define PWM4EN PWM4CONbits.PWM4EN // bit 7
4092 #define PWM4DCH0 PWM4DCHbits.PWM4DCH0 // bit 0
4093 #define PWM4DCH1 PWM4DCHbits.PWM4DCH1 // bit 1
4094 #define PWM4DCH2 PWM4DCHbits.PWM4DCH2 // bit 2
4095 #define PWM4DCH3 PWM4DCHbits.PWM4DCH3 // bit 3
4096 #define PWM4DCH4 PWM4DCHbits.PWM4DCH4 // bit 4
4097 #define PWM4DCH5 PWM4DCHbits.PWM4DCH5 // bit 5
4098 #define PWM4DCH6 PWM4DCHbits.PWM4DCH6 // bit 6
4099 #define PWM4DCH7 PWM4DCHbits.PWM4DCH7 // bit 7
4101 #define PWM4DCL0 PWM4DCLbits.PWM4DCL0 // bit 6
4102 #define PWM4DCL1 PWM4DCLbits.PWM4DCL1 // bit 7
4104 #define C STATUSbits.C // bit 0
4105 #define DC STATUSbits.DC // bit 1
4106 #define Z STATUSbits.Z // bit 2
4107 #define NOT_PD STATUSbits.NOT_PD // bit 3
4108 #define NOT_TO STATUSbits.NOT_TO // bit 4
4110 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
4111 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
4112 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
4114 #define TMR1ON T1CONbits.TMR1ON // bit 0
4115 #define NOT_T1SYNC T1CONbits.NOT_T1SYNC // bit 2
4116 #define T1OSCEN T1CONbits.T1OSCEN // bit 3
4117 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
4118 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
4119 #define TMR1CS0 T1CONbits.TMR1CS0 // bit 6
4120 #define TMR1CS1 T1CONbits.TMR1CS1 // bit 7
4122 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0
4123 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1
4124 #define T1GVAL T1GCONbits.T1GVAL // bit 2
4125 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3
4126 #define T1GSPM T1GCONbits.T1GSPM // bit 4
4127 #define T1GTM T1GCONbits.T1GTM // bit 5
4128 #define T1GPOL T1GCONbits.T1GPOL // bit 6
4129 #define TMR1GE T1GCONbits.TMR1GE // bit 7
4131 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
4132 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
4133 #define TMR2ON T2CONbits.TMR2ON // bit 2
4134 #define TOUTPS0 T2CONbits.TOUTPS0 // bit 3
4135 #define TOUTPS1 T2CONbits.TOUTPS1 // bit 4
4136 #define TOUTPS2 T2CONbits.TOUTPS2 // bit 5
4137 #define TOUTPS3 T2CONbits.TOUTPS3 // bit 6
4139 #define TRISA0 TRISAbits.TRISA0 // bit 0
4140 #define TRISA1 TRISAbits.TRISA1 // bit 1
4141 #define TRISA2 TRISAbits.TRISA2 // bit 2
4142 #define TRISA3 TRISAbits.TRISA3 // bit 3
4143 #define TRISA4 TRISAbits.TRISA4 // bit 4
4144 #define TRISA5 TRISAbits.TRISA5 // bit 5
4146 #define TRISB4 TRISBbits.TRISB4 // bit 4
4147 #define TRISB5 TRISBbits.TRISB5 // bit 5
4148 #define TRISB6 TRISBbits.TRISB6 // bit 6
4149 #define TRISB7 TRISBbits.TRISB7 // bit 7
4151 #define TRISC0 TRISCbits.TRISC0 // bit 0
4152 #define TRISC1 TRISCbits.TRISC1 // bit 1
4153 #define TRISC2 TRISCbits.TRISC2 // bit 2
4154 #define TRISC3 TRISCbits.TRISC3 // bit 3
4155 #define TRISC4 TRISCbits.TRISC4 // bit 4
4156 #define TRISC5 TRISCbits.TRISC5 // bit 5
4157 #define TRISC6 TRISCbits.TRISC6 // bit 6
4158 #define TRISC7 TRISCbits.TRISC7 // bit 7
4160 #define SWDTEN WDTCONbits.SWDTEN // bit 0
4161 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
4162 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
4163 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
4164 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
4165 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
4167 #define WPUA0 WPUAbits.WPUA0 // bit 0
4168 #define WPUA1 WPUAbits.WPUA1 // bit 1
4169 #define WPUA2 WPUAbits.WPUA2 // bit 2
4170 #define WPUA3 WPUAbits.WPUA3 // bit 3
4171 #define WPUA4 WPUAbits.WPUA4 // bit 4
4172 #define WPUA5 WPUAbits.WPUA5 // bit 5
4174 #define WPUB4 WPUBbits.WPUB4 // bit 4
4175 #define WPUB5 WPUBbits.WPUB5 // bit 5
4176 #define WPUB6 WPUBbits.WPUB6 // bit 6
4177 #define WPUB7 WPUBbits.WPUB7 // bit 7
4179 #endif // #ifndef NO_BIT_DEFINES
4181 #endif // #ifndef __PIC16LF1507_H__