arch/common/hidd.pci/include/pci_hidd.h

   1 #ifndef HIDD_PCI_H
   2 #define HIDD_PCI_H
   3
   4 /*
   5     Copyright © 2003, The AROS Development Team. All rights reserved.
   6     $Id$
   7 */
   8
   9 #ifndef EXEC_TYPES_H
  10 #include <exec/types.h>
  11 #endif
  12
  13 #ifndef HIDD_HIDD_H
  14 #include <hidd/hidd.h>
  15 #endif
  16
  17 #ifndef OOP_OOP_H
  18 #include <oop/oop.h>
  19 #endif
  20
  21 #ifndef UTILITY_HOOKS_H
  22 #include <utility/hooks.h>
  23 #endif
  24
  25 #ifndef UTILITY_TAGITEM_H
  26 #include <utility/tagitem.h>
  27 #endif
  28
  29 /* Base PCI class */
  30
  31 #define CLID_Hidd_PCI   "hidd.pci"
  32 #define IID_Hidd_PCI    "hidd.pci"
  33
  34 #define HiddPCIAttrBase __IHidd_PCI
  35
  36 #ifndef __OOP_NOATTRBASES__
  37 extern OOP_AttrBase HiddPCIAttrBase;
  38 #endif
  39
  40 /* PCI Class methods */
  41 enum
  42 {
  43     moHidd_PCI_AddHardwareDriver = 0,
  44     moHidd_PCI_EnumDevices,
  45     moHidd_PCI_RemHardwareDriver,
  46
  47     NUM_PCI_METHODS
  48 };
  49
  50 /* Tags for EnumDevices method */
  51 enum
  52 {
  53     tHidd_PCI_VendorID          = TAG_USER,
  54     tHidd_PCI_ProductID,
  55     tHidd_PCI_RevisionID,
  56     tHidd_PCI_Interface,
  57     tHidd_PCI_Class,
  58     tHidd_PCI_SubClass,
  59     tHidd_PCI_SubsystemVendorID,
  60     tHidd_PCI_SubsystemID
  61 };
  62
  63 struct pHidd_PCI_AddHardwareDriver
  64 {
  65     OOP_MethodID    mID;
  66     OOP_Class       *driverClass;
  67 };
  68
  69 struct pHidd_PCI_EnumDevices
  70 {
  71     OOP_MethodID    mID;
  72     struct Hook     *callback;
  73     struct TagItem  *requirements;
  74 };
  75
  76 struct pHidd_PCI_RemHardwareDriver
  77 {
  78     OOP_MethodID    mID;
  79     OOP_Class       *driverClass;
  80 };
  81
  82 /* PCI device class */
  83
  84 #define CLID_Hidd_PCIDevice     "hidd.pci.device"
  85 #define IID_Hidd_PCIDevice      "hidd.pci.device"
  86
  87 #define HiddPCIDeviceAttrBase   __IHidd_PCIDev
  88
  89 #ifndef __OOP_NOATTRBASES__
  90 extern OOP_AttrBase HiddPCIDeviceAttrBase;
  91 #endif
  92
  93 enum
  94 {
  95     moHidd_PCIDevice_ReadConfigByte,
  96     moHidd_PCIDevice_ReadConfigWord,
  97     moHidd_PCIDevice_ReadConfigLong,
  98     moHidd_PCIDevice_WriteConfigByte,
  99     moHidd_PCIDevice_WriteConfigWord,
 100     moHidd_PCIDevice_WriteConfigLong,
 101
 102     NUM_PCIDEVICE_METHODS
 103 };
 104
 105 enum
 106 {
 107     aoHidd_PCIDevice_Driver,    /* [I.G] Hardware PCI driver that handles this device */
 108     aoHidd_PCIDevice_Bus,       /* [I.G] Bus the device is on */
 109     aoHidd_PCIDevice_Dev,       /* [I.G] Device number */
 110     aoHidd_PCIDevice_Sub,       /* [I.G] Function number */
 111
 112     aoHidd_PCIDevice_VendorID,  /* [..G] VendorID of device as defined in PCI specs */
 113     aoHidd_PCIDevice_ProductID, /* [..G] ProductID */
 114     aoHidd_PCIDevice_RevisionID,/* [..G] RevisionID */
 115
 116     aoHidd_PCIDevice_Interface, /* [..G] */
 117     aoHidd_PCIDevice_Class,     /* [..G] */
 118     aoHidd_PCIDevice_SubClass,  /* [..G] */
 119
 120     aoHidd_PCIDevice_SubsystemVendorID, /* [..G] */
 121     aoHidd_PCIDevice_SubsystemID,       /* [..G] */
 122
 123     aoHidd_PCIDevice_INTLine,   /* [..G] */
 124     aoHidd_PCIDevice_IRQLine,   /* [..G] */
 125
 126     aoHidd_PCIDevice_RomBase,   /* [.SG] Location of ROM on the PCI bus (if ROM exists) */
 127     aoHidd_PCIDevice_RomSize,   /* [..G] Size of ROM area */
 128
 129     aoHidd_PCIDevice_Base0,     /* [.SG] Location of Memory Area 0 */
 130     aoHidd_PCIDevice_Size0,     /* [..G] Size of Memory Area 0 */
 131     aoHidd_PCIDevice_Type0,     /* [..G] Type of Memory Area 0 */
 132     aoHidd_PCIDevice_Base1,     /* [.SG] Ditto */
 133     aoHidd_PCIDevice_Size1,     /* [..G] */
 134     aoHidd_PCIDevice_Type1,     /* [..G] */
 135     aoHidd_PCIDevice_Base2,     /* [.SG] */
 136     aoHidd_PCIDevice_Size2,     /* [..G] */
 137     aoHidd_PCIDevice_Type2,     /* [..G] */
 138     aoHidd_PCIDevice_Base3,     /* [.SG] */
 139     aoHidd_PCIDevice_Size3,     /* [..G] */
 140     aoHidd_PCIDevice_Type3,     /* [..G] */
 141     aoHidd_PCIDevice_Base4,     /* [.SG] */
 142     aoHidd_PCIDevice_Size4,     /* [..G] */
 143     aoHidd_PCIDevice_Type4,     /* [..G] */
 144     aoHidd_PCIDevice_Base5,     /* [.SG] */
 145     aoHidd_PCIDevice_Size5,     /* [..G] */
 146     aoHidd_PCIDevice_Type5,     /* [..G] */
 147
 148     aoHidd_PCIDevice_isIO,      /* [.SG] Can device access IO space? */
 149     aoHidd_PCIDevice_isMEM,     /* [.SG] Can device access Mem space? */
 150     aoHidd_PCIDevice_isMaster,  /* [.SG] Can device work in BusMaster mode? */
 151     aoHidd_PCIDevice_paletteSnoop,  /* [.SG] Should VGA compatible card snoop the palette? */
 152
 153     aoHidd_PCIDevice_is66MHz,   /* [..G] Is device 66MHz capable? */
 154
 155     aoHidd_PCIDevice_ClassDesc,     /* [..G] String description of device Class */
 156     aoHidd_PCIDevice_SubClassDesc,  /* [..G] String description of device SubClass */
 157     aoHidd_PCIDevice_InterfaceDesc, /* [..G] String description of defice Interface */
 158
 159     aoHidd_PCIDevice_isBridge,  /* [..G] Is the device a PCI-PCI bridge? */
 160     aoHidd_PCIDevice_SubBus,    /* [..G] Bus number managed by bridge */
 161     aoHidd_PCIDevice_MemoryBase,/* [.SG] PCI bridge will forwart addresses from MemoryBase to */
 162     aoHidd_PCIDevice_MemoryLimit,/*[.SG] MemoryLimit through */
 163     aoHidd_PCIDevice_PrefetchableBase, /* [.SG] like above, regarding the prefetchable memory */
 164     aoHidd_PCIDevice_PrefetchableLimit,/* [.SG] */
 165     aoHidd_PCIDevice_IOBase,    /* [.SG] PCI bridge will forward IO accesses from IOBase to IOLimit */
 166     aoHidd_PCIDevice_IOLimit,   /* [.SG] */
 167     aoHidd_PCIDevice_ISAEnable, /* [.SG] Enable ISA-specific IO forwarding */
 168     aoHidd_PCIDevice_VGAEnable, /* [.SG] Enable VGA-specific IO/MEM forwarding regardless of limits */
 169
 170     num_Hidd_PCIDevice_Attrs
 171 };
 172
 173 #define aHidd_PCIDevice_Driver      (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Driver)
 174 #define aHidd_PCIDevice_Bus         (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Bus)
 175 #define aHidd_PCIDevice_Dev         (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Dev)
 176 #define aHidd_PCIDevice_Sub         (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Sub)
 177 #define aHidd_PCIDevice_VendorID    (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_VendorID)
 178 #define aHidd_PCIDevice_ProductID   (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_ProductID)
 179 #define aHidd_PCIDevice_RevisionID  (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_RevisionID)
 180 #define aHidd_PCIDevice_Interface   (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Interface)
 181 #define aHidd_PCIDevice_Class       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Class)
 182 #define aHidd_PCIDevice_SubClass    (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_SubClass)
 183 #define aHidd_PCIDevice_SubsystemVendorID   (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_SubsystemVendorID)
 184 #define aHidd_PCIDevice_SubsystemID (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_SubsystemID)
 185 #define aHidd_PCIDevice_INTLine     (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_INTLine)
 186 #define aHidd_PCIDevice_IRQLine     (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_IRQLine)
 187 #define aHidd_PCIDevice_RomBase     (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_RomBase)
 188 #define aHidd_PCIDevice_RomSize     (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_RomSize)
 189
 190 #define aHidd_PCIDevice_Base0       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Base0)
 191 #define aHidd_PCIDevice_Base1       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Base1)
 192 #define aHidd_PCIDevice_Base2       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Base2)
 193 #define aHidd_PCIDevice_Base3       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Base3)
 194 #define aHidd_PCIDevice_Base4       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Base4)
 195 #define aHidd_PCIDevice_Base5       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Base5)
 196
 197 #define aHidd_PCIDevice_Size0       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Size0)
 198 #define aHidd_PCIDevice_Size1       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Size1)
 199 #define aHidd_PCIDevice_Size2       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Size2)
 200 #define aHidd_PCIDevice_Size3       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Size3)
 201 #define aHidd_PCIDevice_Size4       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Size4)
 202 #define aHidd_PCIDevice_Size5       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Size5)
 203
 204 #define aHidd_PCIDevice_Type0       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Type0)
 205 #define aHidd_PCIDevice_Type1       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Type1)
 206 #define aHidd_PCIDevice_Type2       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Type2)
 207 #define aHidd_PCIDevice_Type3       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Type3)
 208 #define aHidd_PCIDevice_Type4       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Type4)
 209 #define aHidd_PCIDevice_Type5       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_Type5)
 210
 211 #define aHidd_PCIDevice_isIO        (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_isIO)
 212 #define aHidd_PCIDevice_isMEM       (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_isMEM)
 213 #define aHidd_PCIDevice_isMaster    (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_isMaster)
 214 #define aHidd_PCIDevice_paletteSnoop (HiddPCIDeviceAttrBase +aoHidd_PCIDevice_paletteSnoop)
 215 #define aHidd_PCIDevice_is66MHz     (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_is66MHz)
 216
 217 #define aHidd_PCIDevice_ClassDesc   (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_ClassDesc)
 218 #define aHidd_PCIDevice_SubClassDesc (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_SubClassDesc)
 219 #define aHidd_PCIDevice_InterfaceDesc (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_InterfaceDesc)
 220
 221 #define aHidd_PCIDevice_isBridge    (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_isBridge)
 222 #define aHidd_PCIDevice_SubBus      (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_SubBus)
 223 #define aHidd_PCIDevice_MemoryBase  (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_MemoryBase)
 224 #define aHidd_PCIDevice_MemoryLimit (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_MemoryLimit)
 225 #define aHidd_PCIDevice_PrefetchableBase (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_PrefetchableBase)
 226 #define aHidd_PCIDevice_PrefetchableLimit (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_PrefetchableLimit)
 227 #define aHidd_PCIDevice_IOBase      (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_IOBase)
 228 #define aHidd_PCIDevice_IOLimit     (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_IOLimit)
 229 #define aHidd_PCIDevice_ISAEnable   (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_ISAEnable)
 230 #define aHidd_PCIDevice_VGAEnable   (HiddPCIDeviceAttrBase + aoHidd_PCIDevice_VGAEnable)
 231
 232 #define IS_PCIDEV_ATTR(attr, idx) \
 233     (((idx) = (attr) - HiddPCIDeviceAttrBase) < num_Hidd_PCIDevice_Attrs)
 234
 235 /* Types of BaseAddresses */
 236 #define ADDRB_IO        0
 237 #define ADDRB_PREFETCH  3
 238
 239 #define ADDRF_IO        (1 << ADDRB_IO)
 240 #define ADDRF_PREFETCH  (1 << ADDRB_PREFETCH)
 241
 242 struct pHidd_PCIDevice_ReadConfigByte
 243 {
 244     OOP_MethodID    mID;
 245     UBYTE           reg;    /* Register number */
 246 };
 247
 248 struct pHidd_PCIDevice_ReadConfigWord
 249 {
 250     OOP_MethodID    mID;
 251     UBYTE           reg;    /* Register number */
 252 };
 253
 254 struct pHidd_PCIDevice_ReadConfigLong
 255 {
 256     OOP_MethodID    mID;
 257     UBYTE           reg;    /* Register number */
 258 };
 259
 260 struct pHidd_PCIDevice_WriteConfigByte
 261 {
 262     OOP_MethodID    mID;
 263     UBYTE           reg;    /* Register number */
 264     UBYTE           val;    /* Value to be written */
 265 };
 266
 267 struct pHidd_PCIDevice_WriteConfigWord
 268 {
 269     OOP_MethodID    mID;
 270     UBYTE           reg;    /* Register number */
 271     UWORD           val;    /* Value to be written */
 272 };
 273
 274
 275 struct pHidd_PCIDevice_WriteConfigLong
 276 {
 277     OOP_MethodID    mID;
 278     UBYTE           reg;    /* Register number */
 279     ULONG           val;    /* Value to be written */
 280 };
 281
 282
 283 /* PCI driver class */
 284
 285 #define CLID_Hidd_PCIDriver     "hidd.pci.driver"
 286 #define IID_Hidd_PCIDriver      "hidd.pci.driver"
 287
 288 #define HiddPCIDriverAttrBase   __IHidd_PCIDrv
 289
 290 enum
 291 {
 292     moHidd_PCIDriver_ReadConfigByte,
 293     moHidd_PCIDriver_ReadConfigWord,
 294     moHidd_PCIDriver_ReadConfigLong,
 295     moHidd_PCIDriver_WriteConfigByte,
 296     moHidd_PCIDriver_WriteConfigWord,
 297     moHidd_PCIDriver_WriteConfigLong,
 298     moHidd_PCIDriver_CPUtoPCI,
 299     moHidd_PCIDriver_PCItoCPU,
 300     moHidd_PCIDriver_MapPCI,
 301     moHidd_PCIDriver_UnmapPCI,
 302     moHidd_PCIDriver_AllocPCIMem,
 303     moHidd_PCIDriver_FreePCIMem,
 304
 305     NUM_PCIDRIVER_METHODS
 306 };
 307
 308 enum
 309 {
 310     aoHidd_PCIDriver_DirectBus,  /* [..G] DirectBus shows whether CPUtoPCI and PCItoCPU methods are usable */
 311
 312     num_Hidd_PCIDriver_Attrs
 313 };
 314
 315 #define aHidd_PCIDriver_DirectBus   (aoHidd_PCIDriver_DirectBus + HiddPCIDriverAttrBase)
 316
 317 #define IS_PCIDRV_ATTR(attr, idx) \
 318     (((idx) = (attr) - HiddPCIDriverAttrBase) < num_Hidd_PCIDriver_Attrs)
 319
 320
 321 struct pHidd_PCIDriver_ReadConfigByte
 322 {
 323     OOP_MethodID    mID;
 324     UBYTE           bus;    /* Bus number */
 325     UBYTE           dev;    /* Device number */
 326     UBYTE           sub;    /* Function number */
 327     UBYTE           reg;    /* Register number */
 328 };
 329
 330 struct pHidd_PCIDriver_ReadConfigWord
 331 {
 332     OOP_MethodID    mID;
 333     UBYTE           bus;    /* Bus number */
 334     UBYTE           dev;    /* Device number */
 335     UBYTE           sub;    /* Function number */
 336     UBYTE           reg;    /* Register number */
 337 };
 338
 339 struct pHidd_PCIDriver_ReadConfigLong
 340 {
 341     OOP_MethodID    mID;
 342     UBYTE           bus;    /* Bus number */
 343     UBYTE           dev;    /* Device number */
 344     UBYTE           sub;    /* Function number */
 345     UBYTE           reg;    /* Register number */
 346 };
 347
 348 struct pHidd_PCIDriver_WriteConfigByte
 349 {
 350     OOP_MethodID    mID;
 351     UBYTE           bus;    /* Bus number */
 352     UBYTE           dev;    /* Device number */
 353     UBYTE           sub;    /* Function number */
 354     UBYTE           reg;    /* Register number */
 355     UBYTE           val;    /* Value to be written */
 356 };
 357
 358 struct pHidd_PCIDriver_WriteConfigWord
 359 {
 360     OOP_MethodID    mID;
 361     UBYTE           bus;    /* Bus number */
 362     UBYTE           dev;    /* Device number */
 363     UBYTE           sub;    /* Function number */
 364     UBYTE           reg;    /* Register number */
 365     UWORD           val;    /* Value to be written */
 366 };
 367
 368
 369 struct pHidd_PCIDriver_WriteConfigLong
 370 {
 371     OOP_MethodID    mID;
 372     UBYTE           bus;    /* Bus number */
 373     UBYTE           dev;    /* Device number */
 374     UBYTE           sub;    /* Function number */
 375     UBYTE           reg;    /* Register number */
 376     ULONG           val;    /* Value to be written */
 377 };
 378
 379 struct pHidd_PCIDriver_CPUtoPCI
 380 {
 381     OOP_MethodID    mID;
 382     APTR            address;    /* CPU address to be translated */
 383 };
 384
 385 struct pHidd_PCIDriver_PCItoCPU
 386 {
 387     OOP_MethodID    mID;
 388     APTR            address;    /* PCI address to be translated */
 389 };
 390
 391 struct pHidd_PCIDriver_MapPCI
 392 {
 393     OOP_MethodID    mID;
 394     APTR            PCIAddress; /* Address on the PCIBus to be mapped to CPU address space */
 395     ULONG           Length;     /* Length of mapped area */
 396 };
 397
 398 struct pHidd_PCIDriver_UnmapPCI
 399 {
 400     OOP_MethodID    mID;
 401     APTR            CPUAddress; /* Address as seen by the CPU of the PCI address space to unmap */
 402     ULONG           Length;     /* Length of unmapped area */
 403 };
 404
 405 struct pHidd_PCIDriver_AllocPCIMem
 406 {
 407     OOP_MethodID    mID;
 408     ULONG           Size;
 409 };
 410
 411 struct pHidd_PCIDriver_FreePCIMem
 412 {
 413     OOP_MethodID    mID;
 414     APTR            Address;
 415 };
 416
 417 /* Prototypes for stubs */
 418 VOID HIDD_PCI_EnumDevices(OOP_Object *obj, struct Hook *hook, struct TagItem *requirements);
 419 VOID HIDD_PCI_AddHardwareDriver(OOP_Object *obj, OOP_Class *driver);
 420 APTR HIDD_PCIDriver_CPUtoPCI(OOP_Object *obj, APTR address);
 421 APTR HIDD_PCIDriver_PCItoCPU(OOP_Object *obj, APTR address);
 422 APTR HIDD_PCIDriver_MapPCI(OOP_Object *obj, APTR address, ULONG length);
 423 VOID HIDD_PCIDriver_UnmapPCI(OOP_Object *obj, APTR address, ULONG length);
 424 APTR HIDD_PCIDriver_AllocPCIMem(OOP_Object *obj, ULONG length);
 425 VOID HIDD_PCIDriver_FreePCIMem(OOP_Object *obj, APTR address);
 426
 427 #endif
 428