verilog_src/fulladder_2b.v

   1 module Fulladder_2b (
   2         output reg[1:0] result,
   3     output reg overflow,
   4     input wire [1:0] a, b
   5     );
   6
   7     always @ (*) {overflow,result} = #1 a + b;
   8
   9 endmodule
  10 /*
  11 module Fulladder_2b (
  12         result,
  13         overflow,
  14         a, b
  15     );
  16         output [1:0] result;
  17         reg[1:0] result;
  18     output overflow;
  19     reg overflow;
  20     input [1:0] a, b;
  21     wire [1:0] a, b;
  22
  23     always @ (a or b) {overflow,result} = #1 a + b;
  24
  25
  26 endmodule*/