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Release 1.2-rc6.
[wine/gsoc-2012-control.git] / programs / winedbg / be_x86_64.c
blob6099a784ba67bd124a7a198fd99cf77ef58da077
1 /*
2 * Debugger x86_64 specific functions
3 *
4 * Copyright 2004 Vincent Béron
5 * Copyright 2009 Eric Pouech
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
20 */
21
22 #include "debugger.h"
23 #include "wine/debug.h"
24
25 WINE_DEFAULT_DEBUG_CHANNEL(winedbg);
26
27 #if defined(__x86_64__)
28
29 #define STEP_FLAG 0x00000100 /* single step flag */
30
31 static unsigned be_x86_64_get_addr(HANDLE hThread, const CONTEXT* ctx,
32 enum be_cpu_addr bca, ADDRESS64* addr)
33 {
34 addr->Mode = AddrModeFlat;
35 switch (bca)
36 {
37 case be_cpu_addr_pc:
38 addr->Segment = ctx->SegCs;
39 addr->Offset = ctx->Rip;
40 return TRUE;
41 case be_cpu_addr_stack:
42 addr->Segment = ctx->SegSs;
43 addr->Offset = ctx->Rsp;
44 return TRUE;
45 case be_cpu_addr_frame:
46 addr->Segment = ctx->SegSs;
47 addr->Offset = ctx->Rbp;
48 return TRUE;
49 default:
50 addr->Mode = -1;
51 return FALSE;
52 }
53 }
54
55 static unsigned be_x86_64_get_register_info(int regno, enum be_cpu_addr* kind)
56 {
57 /* this is true when running in 32bit mode... and wrong in 64 :-/ */
58 switch (regno)
59 {
60 case CV_AMD64_RIP: *kind = be_cpu_addr_pc; return TRUE;
61 case CV_AMD64_EBP: *kind = be_cpu_addr_frame; return TRUE;
62 case CV_AMD64_ESP: *kind = be_cpu_addr_stack; return TRUE;
63 }
64 return FALSE;
65 }
66
67 static void be_x86_64_single_step(CONTEXT* ctx, unsigned enable)
68 {
69 if (enable) ctx->EFlags |= STEP_FLAG;
70 else ctx->EFlags &= ~STEP_FLAG;
71 }
72
73 static void be_x86_64_print_context(HANDLE hThread, const CONTEXT* ctx,
74 int all_regs)
75 {
76 static const char flags[] = "aVR-N--ODITSZ-A-P-C";
77 char buf[33];
78 int i;
79
80 strcpy(buf, flags);
81 for (i = 0; buf[i]; i++)
82 if (buf[i] != '-' && !(ctx->EFlags & (1 << (sizeof(flags) - 2 - i))))
83 buf[i] = ' ';
84
85 dbg_printf("Register dump:\n");
86 dbg_printf(" rip:%016lx rsp:%016lx rbp:%016lx eflags:%08x (%s)\n",
87 ctx->Rip, ctx->Rsp, ctx->Rbp, ctx->EFlags, buf);
88 dbg_printf(" rax:%016lx rbx:%016lx rcx:%016lx rdx:%016lx\n",
89 ctx->Rax, ctx->Rbx, ctx->Rcx, ctx->Rdx);
90 dbg_printf(" rsi:%016lx rdi:%016lx r8:%016lx r9:%016lx r10:%016lx\n",
91 ctx->Rsi, ctx->Rdi, ctx->R8, ctx->R9, ctx->R10 );
92 dbg_printf(" r11:%016lx r12:%016lx r13:%016lx r14:%016lx r15:%016lx\n",
93 ctx->R11, ctx->R12, ctx->R13, ctx->R14, ctx->R15 );
94
95 if (all_regs) dbg_printf( "Floating point x86_64 dump not implemented\n" );
96 }
97
98 static void be_x86_64_print_segment_info(HANDLE hThread, const CONTEXT* ctx)
99 {
100 }
101
102 static struct dbg_internal_var be_x86_64_ctx[] =
103 {
104 {CV_AMD64_AL, "AL", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_char_int},
105 {CV_AMD64_BL, "BL", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_char_int},
106 {CV_AMD64_CL, "CL", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_char_int},
107 {CV_AMD64_DL, "DL", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_char_int},
108 {CV_AMD64_AH, "AH", (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rax)+1), dbg_itype_unsigned_char_int},
109 {CV_AMD64_BH, "BH", (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rbx)+1), dbg_itype_unsigned_char_int},
110 {CV_AMD64_CH, "CH", (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rcx)+1), dbg_itype_unsigned_char_int},
111 {CV_AMD64_DH, "DH", (DWORD_PTR*)(FIELD_OFFSET(CONTEXT, Rdx)+1), dbg_itype_unsigned_char_int},
112 {CV_AMD64_AX, "AX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_short_int},
113 {CV_AMD64_BX, "BX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_short_int},
114 {CV_AMD64_CX, "CX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_short_int},
115 {CV_AMD64_DX, "DX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_short_int},
116 {CV_AMD64_SP, "SP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsp), dbg_itype_unsigned_short_int},
117 {CV_AMD64_BP, "BP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbp), dbg_itype_unsigned_short_int},
118 {CV_AMD64_SI, "SI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsi), dbg_itype_unsigned_short_int},
119 {CV_AMD64_DI, "DI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdi), dbg_itype_unsigned_short_int},
120 {CV_AMD64_EAX, "EAX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_int},
121 {CV_AMD64_EBX, "EBX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_int},
122 {CV_AMD64_ECX, "ECX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_int},
123 {CV_AMD64_EDX, "EDX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_int},
124 {CV_AMD64_ESP, "ESP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsp), dbg_itype_unsigned_int},
125 {CV_AMD64_EBP, "EBP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbp), dbg_itype_unsigned_int},
126 {CV_AMD64_ESI, "ESI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsi), dbg_itype_unsigned_int},
127 {CV_AMD64_EDI, "EDI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdi), dbg_itype_unsigned_int},
128 {CV_AMD64_ES, "ES", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegEs), dbg_itype_unsigned_short_int},
129 {CV_AMD64_CS, "CS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegCs), dbg_itype_unsigned_short_int},
130 {CV_AMD64_SS, "SS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegSs), dbg_itype_unsigned_short_int},
131 {CV_AMD64_DS, "DS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegDs), dbg_itype_unsigned_short_int},
132 {CV_AMD64_FS, "FS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegFs), dbg_itype_unsigned_short_int},
133 {CV_AMD64_GS, "GS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, SegGs), dbg_itype_unsigned_short_int},
134 {CV_AMD64_FLAGS, "FLAGS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, EFlags), dbg_itype_unsigned_short_int},
135 {CV_AMD64_EFLAGS, "EFLAGS", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, EFlags), dbg_itype_unsigned_int},
136 {CV_AMD64_RIP, "RIP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rip), dbg_itype_unsigned_long_int},
137 {CV_AMD64_RAX, "RAX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rax), dbg_itype_unsigned_long_int},
138 {CV_AMD64_RBX, "RBX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbx), dbg_itype_unsigned_long_int},
139 {CV_AMD64_RCX, "RCX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rcx), dbg_itype_unsigned_long_int},
140 {CV_AMD64_RDX, "RDX", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdx), dbg_itype_unsigned_long_int},
141 {CV_AMD64_RSP, "RSP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsp), dbg_itype_unsigned_long_int},
142 {CV_AMD64_RBP, "RBP", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rbp), dbg_itype_unsigned_long_int},
143 {CV_AMD64_RSI, "RSI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rsi), dbg_itype_unsigned_long_int},
144 {CV_AMD64_RDI, "RDI", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, Rdi), dbg_itype_unsigned_long_int},
145 {CV_AMD64_R8, "R8", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R8), dbg_itype_unsigned_long_int},
146 {CV_AMD64_R9, "R9", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R9), dbg_itype_unsigned_long_int},
147 {CV_AMD64_R10, "R10", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R10), dbg_itype_unsigned_long_int},
148 {CV_AMD64_R11, "R11", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R11), dbg_itype_unsigned_long_int},
149 {CV_AMD64_R12, "R12", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R12), dbg_itype_unsigned_long_int},
150 {CV_AMD64_R13, "R13", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R13), dbg_itype_unsigned_long_int},
151 {CV_AMD64_R14, "R14", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R14), dbg_itype_unsigned_long_int},
152 {CV_AMD64_R15, "R15", (DWORD_PTR*)FIELD_OFFSET(CONTEXT, R15), dbg_itype_unsigned_long_int},
153 {0, NULL, 0, dbg_itype_none}
154 };
155
156 #define f_mod(b) ((b)>>6)
157 #define f_reg(b) (((b)>>3)&0x7)
158 #define f_rm(b) ((b)&0x7)
159
160 static unsigned be_x86_64_is_step_over_insn(const void* insn)
161 {
162 BYTE ch;
163
164 for (;;)
165 {
166 if (!dbg_read_memory(insn, &ch, sizeof(ch))) return FALSE;
167
168 switch (ch)
169 {
170 /* Skip all prefixes */
171 case 0x2e: /* cs: */
172 case 0x36: /* ss: */
173 case 0x3e: /* ds: */
174 case 0x26: /* es: */
175 case 0x64: /* fs: */
176 case 0x65: /* gs: */
177 case 0x66: /* opcode size prefix */
178 case 0x67: /* addr size prefix */
179 case 0xf0: /* lock */
180 case 0xf2: /* repne */
181 case 0xf3: /* repe */
182 insn = (const char*)insn + 1;
183 continue;
184
185 /* Handle call instructions */
186 case 0xcd: /* int <intno> */
187 case 0xe8: /* call <offset> */
188 case 0x9a: /* lcall <seg>:<off> */
189 return TRUE;
190
191 case 0xff: /* call <regmodrm> */
192 if (!dbg_read_memory((const char*)insn + 1, &ch, sizeof(ch)))
193 return FALSE;
194 return (((ch & 0x38) == 0x10) || ((ch & 0x38) == 0x18));
195
196 /* Handle string instructions */
197 case 0x6c: /* insb */
198 case 0x6d: /* insw */
199 case 0x6e: /* outsb */
200 case 0x6f: /* outsw */
201 case 0xa4: /* movsb */
202 case 0xa5: /* movsw */
203 case 0xa6: /* cmpsb */
204 case 0xa7: /* cmpsw */
205 case 0xaa: /* stosb */
206 case 0xab: /* stosw */
207 case 0xac: /* lodsb */
208 case 0xad: /* lodsw */
209 case 0xae: /* scasb */
210 case 0xaf: /* scasw */
211 return TRUE;
212
213 default:
214 return FALSE;
215 }
216 }
217 }
218
219 static unsigned be_x86_64_is_function_return(const void* insn)
220 {
221 BYTE c;
222 return dbg_read_memory(insn, &c, sizeof(c)) && ((c == 0xC2) || (c == 0xC3));
223 }
224
225 static unsigned be_x86_64_is_break_insn(const void* insn)
226 {
227 BYTE c;
228 return dbg_read_memory(insn, &c, sizeof(c)) && c == 0xCC;
229 }
230
231 static BOOL fetch_value(const char* addr, unsigned sz, int* value)
232 {
233 char value8;
234 short value16;
235
236 switch (sz)
237 {
238 case 8:
239 if (!dbg_read_memory(addr, &value8, sizeof(value8))) return FALSE;
240 *value = value8;
241 break;
242 case 16:
243 if (!dbg_read_memory(addr, &value16, sizeof(value16))) return FALSE;
244 *value = value16;
245 case 32:
246 if (!dbg_read_memory(addr, value, sizeof(*value))) return FALSE;
247 break;
248 default: return FALSE;
249 }
250 return TRUE;
251 }
252
253 static unsigned be_x86_64_is_func_call(const void* insn, ADDRESS64* callee)
254 {
255 BYTE ch;
256 LONG delta;
257 short segment;
258 unsigned op_size = 32, rex = 0;
259 DWORD64 dst;
260
261 /* we assume 64bit mode all over the place */
262 for (;;)
263 {
264 if (!dbg_read_memory(insn, &ch, sizeof(ch))) return FALSE;
265 if (ch == 0x66) op_size = 16;
266 else if (ch == 0x67) WINE_FIXME("prefix not supported %x\n", ch);
267 else if (ch >= 0x40 && ch <= 0x4f) rex = ch & 0xf;
268 else break;
269 insn = (const char*)insn + 1;
270 } while (0);
271
272 /* that's the only mode we support anyway */
273 callee->Mode = AddrModeFlat;
274 callee->Segment = dbg_context.SegCs;
275
276 switch (ch)
277 {
278 case 0xe8: /* relative near call */
279 assert(op_size == 32);
280 if (!fetch_value((const char*)insn + 1, sizeof(delta), &delta))
281 return FALSE;
282 callee->Offset = (DWORD_PTR)insn + 1 + 4 + delta;
283 return TRUE;
284
285 case 0xff:
286 if (!dbg_read_memory((const char*)insn + 1, &ch, sizeof(ch)))
287 return FALSE;
288 WINE_TRACE("Got 0xFF %x (&C7=%x) with rex=%x\n", ch, ch & 0xC7, rex);
289 /* keep only the CALL and LCALL insn:s */
290 switch (f_reg(ch))
291 {
292 case 0x02:
293 segment = dbg_context.SegCs;
294 break;
295 default: return FALSE;
296 }
297 if (rex == 0) switch (ch & 0xC7) /* keep Mod R/M only (skip reg) */
298 {
299 case 0x04:
300 case 0x44:
301 case 0x84:
302 WINE_FIXME("Unsupported yet call insn (0xFF 0x%02x) (SIB bytes) at %p\n", ch, insn);
303 return FALSE;
304 case 0x05: /* addr32 */
305 if (f_reg(ch) == 0x2)
306 {
307 /* rip-relative to next insn */
308 if (!dbg_read_memory((const char*)insn + 2, &delta, sizeof(delta)) ||
309 !dbg_read_memory((const char*)insn + 6 + delta, &dst, sizeof(dst)))
310 return FALSE;
311
312 callee->Offset = dst;
313 return TRUE;
314 }
315 WINE_FIXME("Unsupported yet call insn (0xFF 0x%02x) at %p\n", ch, insn);
316 return FALSE;
317 default:
318 switch (f_rm(ch))
319 {
320 case 0x00: dst = dbg_context.Rax; break;
321 case 0x01: dst = dbg_context.Rcx; break;
322 case 0x02: dst = dbg_context.Rdx; break;
323 case 0x03: dst = dbg_context.Rbx; break;
324 case 0x04: dst = dbg_context.Rsp; break;
325 case 0x05: dst = dbg_context.Rbp; break;
326 case 0x06: dst = dbg_context.Rsi; break;
327 case 0x07: dst = dbg_context.Rdi; break;
328 }
329 if (f_mod(ch) != 0x03)
330 WINE_FIXME("Unsupported yet call insn (0xFF 0x%02x) at %p\n", ch, insn);
331 else
332 {
333 callee->Offset = dst;
334 }
335 break;
336 }
337 else
338 WINE_FIXME("Unsupported yet call insn (rex=0x%02x 0xFF 0x%02x) at %p\n", rex, ch, insn);
339 return FALSE;
340
341 default:
342 return FALSE;
343 }
344 }
345
346 extern void be_x86_64_disasm_one_insn(ADDRESS64* addr, int display);
347
348 #define DR7_CONTROL_SHIFT 16
349 #define DR7_CONTROL_SIZE 4
350
351 #define DR7_RW_EXECUTE (0x0)
352 #define DR7_RW_WRITE (0x1)
353 #define DR7_RW_READ (0x3)
354
355 #define DR7_LEN_1 (0x0)
356 #define DR7_LEN_2 (0x4)
357 #define DR7_LEN_4 (0xC)
358 #define DR7_LEN_8 (0x8)
359
360 #define DR7_LOCAL_ENABLE_SHIFT 0
361 #define DR7_GLOBAL_ENABLE_SHIFT 1
362 #define DR7_ENABLE_SIZE 2
363
364 #define DR7_LOCAL_ENABLE_MASK (0x55)
365 #define DR7_GLOBAL_ENABLE_MASK (0xAA)
366
367 #define DR7_CONTROL_RESERVED (0xFC00)
368 #define DR7_LOCAL_SLOWDOWN (0x100)
369 #define DR7_GLOBAL_SLOWDOWN (0x200)
370
371 #define DR7_ENABLE_MASK(dr) (1<<(DR7_LOCAL_ENABLE_SHIFT+DR7_ENABLE_SIZE*(dr)))
372 #define IS_DR7_SET(ctrl,dr) ((ctrl)&DR7_ENABLE_MASK(dr))
373
374 static inline int be_x86_64_get_unused_DR(CONTEXT* ctx, DWORD64** r)
375 {
376 if (!IS_DR7_SET(ctx->Dr7, 0))
377 {
378 *r = &ctx->Dr0;
379 return 0;
380 }
381 if (!IS_DR7_SET(ctx->Dr7, 1))
382 {
383 *r = &ctx->Dr1;
384 return 1;
385 }
386 if (!IS_DR7_SET(ctx->Dr7, 2))
387 {
388 *r = &ctx->Dr2;
389 return 2;
390 }
391 if (!IS_DR7_SET(ctx->Dr7, 3))
392 {
393 *r = &ctx->Dr3;
394 return 3;
395 }
396 dbg_printf("All hardware registers have been used\n");
397
398 return -1;
399 }
400
401 static unsigned be_x86_64_insert_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
402 CONTEXT* ctx, enum be_xpoint_type type,
403 void* addr, unsigned long* val, unsigned size)
404 {
405 unsigned char ch;
406 SIZE_T sz;
407 DWORD64 *pr;
408 int reg;
409 unsigned long bits;
410
411 switch (type)
412 {
413 case be_xpoint_break:
414 if (size != 0) return 0;
415 if (!pio->read(hProcess, addr, &ch, 1, &sz) || sz != 1) return 0;
416 *val = ch;
417 ch = 0xcc;
418 if (!pio->write(hProcess, addr, &ch, 1, &sz) || sz != 1) return 0;
419 break;
420 case be_xpoint_watch_exec:
421 bits = DR7_RW_EXECUTE;
422 goto hw_bp;
423 case be_xpoint_watch_read:
424 bits = DR7_RW_READ;
425 goto hw_bp;
426 case be_xpoint_watch_write:
427 bits = DR7_RW_WRITE;
428 hw_bp:
429 if ((reg = be_x86_64_get_unused_DR(ctx, &pr)) == -1) return 0;
430 *pr = (DWORD64)addr;
431 if (type != be_xpoint_watch_exec) switch (size)
432 {
433 case 8: bits |= DR7_LEN_8; break;
434 case 4: bits |= DR7_LEN_4; break;
435 case 2: bits |= DR7_LEN_2; break;
436 case 1: bits |= DR7_LEN_1; break;
437 default: WINE_FIXME("Unsupported xpoint_watch of size %d\n", size); return 0;
438 }
439 *val = reg;
440 /* clear old values */
441 ctx->Dr7 &= ~(0x0F << (DR7_CONTROL_SHIFT + DR7_CONTROL_SIZE * reg));
442 /* set the correct ones */
443 ctx->Dr7 |= bits << (DR7_CONTROL_SHIFT + DR7_CONTROL_SIZE * reg);
444 ctx->Dr7 |= DR7_ENABLE_MASK(reg) | DR7_LOCAL_SLOWDOWN;
445 break;
446 default:
447 dbg_printf("Unknown bp type %c\n", type);
448 return 0;
449 }
450 return 1;
451 }
452
453 static unsigned be_x86_64_remove_Xpoint(HANDLE hProcess, const struct be_process_io* pio,
454 CONTEXT* ctx, enum be_xpoint_type type,
455 void* addr, unsigned long val, unsigned size)
456 {
457 SIZE_T sz;
458 unsigned char ch;
459
460 switch (type)
461 {
462 case be_xpoint_break:
463 if (size != 0) return 0;
464 if (!pio->read(hProcess, addr, &ch, 1, &sz) || sz != 1) return 0;
465 if (ch != (unsigned char)0xCC)
466 WINE_FIXME("Cannot get back %02x instead of 0xCC at %08lx\n",
467 ch, (unsigned long)addr);
468 ch = (unsigned char)val;
469 if (!pio->write(hProcess, addr, &ch, 1, &sz) || sz != 1) return 0;
470 break;
471 case be_xpoint_watch_exec:
472 case be_xpoint_watch_read:
473 case be_xpoint_watch_write:
474 /* simply disable the entry */
475 ctx->Dr7 &= ~DR7_ENABLE_MASK(val);
476 break;
477 default:
478 dbg_printf("Unknown bp type %c\n", type);
479 return 0;
480 }
481 return 1;
482 }
483
484 static unsigned be_x86_64_is_watchpoint_set(const CONTEXT* ctx, unsigned idx)
485 {
486 return ctx->Dr6 & (1 << idx);
487 }
488
489 static void be_x86_64_clear_watchpoint(CONTEXT* ctx, unsigned idx)
490 {
491 ctx->Dr6 &= ~(1 << idx);
492 }
493
494 static int be_x86_64_adjust_pc_for_break(CONTEXT* ctx, BOOL way)
495 {
496 if (way)
497 {
498 ctx->Rip--;
499 return -1;
500 }
501 ctx->Rip++;
502 return 1;
503 }
504
505 static int be_x86_64_fetch_integer(const struct dbg_lvalue* lvalue, unsigned size,
506 unsigned ext_sign, LONGLONG* ret)
507 {
508 if (size != 1 && size != 2 && size != 4 && size != 8 && size != 16)
509 return FALSE;
510
511 memset(ret, 0, sizeof(*ret)); /* clear unread bytes */
512 /* FIXME: this assumes that debuggee and debugger use the same
513 * integral representation
514 */
515 if (!memory_read_value(lvalue, size, ret)) return FALSE;
516
517 /* propagate sign information */
518 if (ext_sign && size < 16 && (*ret >> (size * 8 - 1)) != 0)
519 {
520 ULONGLONG neg = -1;
521 *ret |= neg << (size * 8);
522 }
523 return TRUE;
524 }
525
526 static int be_x86_64_fetch_float(const struct dbg_lvalue* lvalue, unsigned size,
527 long double* ret)
528 {
529 char tmp[sizeof(long double)];
530
531 /* FIXME: this assumes that debuggee and debugger use the same
532 * representation for reals
533 */
534 if (!memory_read_value(lvalue, size, tmp)) return FALSE;
535
536 /* float & double types have to be promoted to a long double */
537 switch (size)
538 {
539 case sizeof(float): *ret = *(float*)tmp; break;
540 case sizeof(double): *ret = *(double*)tmp; break;
541 case sizeof(long double): *ret = *(long double*)tmp; break;
542 default: return FALSE;
543 }
544 return TRUE;
545 }
546
547 struct backend_cpu be_x86_64 =
548 {
549 IMAGE_FILE_MACHINE_AMD64,
550 8,
551 be_cpu_linearize,
552 be_cpu_build_addr,
553 be_x86_64_get_addr,
554 be_x86_64_get_register_info,
555 be_x86_64_single_step,
556 be_x86_64_print_context,
557 be_x86_64_print_segment_info,
558 be_x86_64_ctx,
559 be_x86_64_is_step_over_insn,
560 be_x86_64_is_function_return,
561 be_x86_64_is_break_insn,
562 be_x86_64_is_func_call,
563 be_x86_64_disasm_one_insn,
564 be_x86_64_insert_Xpoint,
565 be_x86_64_remove_Xpoint,
566 be_x86_64_is_watchpoint_set,
567 be_x86_64_clear_watchpoint,
568 be_x86_64_adjust_pc_for_break,
569 be_x86_64_fetch_integer,
570 be_x86_64_fetch_float,
571 };
572 #endif
GSOC 2012 project to enhance the control panel