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Merge git://git.kernel.org/pub/scm/linux/kernel/git/mingo/linux-2.6-sched
[wrt350n-kernel.git] / sound / pci / hda / hda_intel.c
blob4be36c84b36c7c8354a707d9956430602de45e73
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <asm/io.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <sound/core.h>
48 #include <sound/initval.h>
49 #include "hda_codec.h"
50
51
52 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
53 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
54 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
55 static char *model[SNDRV_CARDS];
56 static int position_fix[SNDRV_CARDS];
57 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
58 static int single_cmd;
59 static int enable_msi;
60
61 module_param_array(index, int, NULL, 0444);
62 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
63 module_param_array(id, charp, NULL, 0444);
64 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
65 module_param_array(enable, bool, NULL, 0444);
66 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
67 module_param_array(model, charp, NULL, 0444);
68 MODULE_PARM_DESC(model, "Use the given board model.");
69 module_param_array(position_fix, int, NULL, 0444);
70 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
71 "(0 = auto, 1 = none, 2 = POSBUF, 3 = FIFO size).");
72 module_param_array(probe_mask, int, NULL, 0444);
73 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
74 module_param(single_cmd, bool, 0444);
75 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
76 "(for debugging only).");
77 module_param(enable_msi, int, 0444);
78 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
79
80 #ifdef CONFIG_SND_HDA_POWER_SAVE
81 /* power_save option is defined in hda_codec.c */
82
83 /* reset the HD-audio controller in power save mode.
84 * this may give more power-saving, but will take longer time to
85 * wake up.
86 */
87 static int power_save_controller = 1;
88 module_param(power_save_controller, bool, 0644);
89 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
90 #endif
91
92 MODULE_LICENSE("GPL");
93 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
94 "{Intel, ICH6M},"
95 "{Intel, ICH7},"
96 "{Intel, ESB2},"
97 "{Intel, ICH8},"
98 "{Intel, ICH9},"
99 "{Intel, ICH10},"
100 "{Intel, SCH},"
101 "{ATI, SB450},"
102 "{ATI, SB600},"
103 "{ATI, RS600},"
104 "{ATI, RS690},"
105 "{ATI, RS780},"
106 "{ATI, R600},"
107 "{ATI, RV630},"
108 "{ATI, RV610},"
109 "{ATI, RV670},"
110 "{ATI, RV635},"
111 "{ATI, RV620},"
112 "{ATI, RV770},"
113 "{VIA, VT8251},"
114 "{VIA, VT8237A},"
115 "{SiS, SIS966},"
116 "{ULI, M5461}}");
117 MODULE_DESCRIPTION("Intel HDA driver");
118
119 #define SFX "hda-intel: "
120
121
122 /*
123 * registers
124 */
125 #define ICH6_REG_GCAP 0x00
126 #define ICH6_REG_VMIN 0x02
127 #define ICH6_REG_VMAJ 0x03
128 #define ICH6_REG_OUTPAY 0x04
129 #define ICH6_REG_INPAY 0x06
130 #define ICH6_REG_GCTL 0x08
131 #define ICH6_REG_WAKEEN 0x0c
132 #define ICH6_REG_STATESTS 0x0e
133 #define ICH6_REG_GSTS 0x10
134 #define ICH6_REG_INTCTL 0x20
135 #define ICH6_REG_INTSTS 0x24
136 #define ICH6_REG_WALCLK 0x30
137 #define ICH6_REG_SYNC 0x34
138 #define ICH6_REG_CORBLBASE 0x40
139 #define ICH6_REG_CORBUBASE 0x44
140 #define ICH6_REG_CORBWP 0x48
141 #define ICH6_REG_CORBRP 0x4A
142 #define ICH6_REG_CORBCTL 0x4c
143 #define ICH6_REG_CORBSTS 0x4d
144 #define ICH6_REG_CORBSIZE 0x4e
145
146 #define ICH6_REG_RIRBLBASE 0x50
147 #define ICH6_REG_RIRBUBASE 0x54
148 #define ICH6_REG_RIRBWP 0x58
149 #define ICH6_REG_RINTCNT 0x5a
150 #define ICH6_REG_RIRBCTL 0x5c
151 #define ICH6_REG_RIRBSTS 0x5d
152 #define ICH6_REG_RIRBSIZE 0x5e
153
154 #define ICH6_REG_IC 0x60
155 #define ICH6_REG_IR 0x64
156 #define ICH6_REG_IRS 0x68
157 #define ICH6_IRS_VALID (1<<1)
158 #define ICH6_IRS_BUSY (1<<0)
159
160 #define ICH6_REG_DPLBASE 0x70
161 #define ICH6_REG_DPUBASE 0x74
162 #define ICH6_DPLBASE_ENABLE 0x1 /* Enable position buffer */
163
164 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
165 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
166
167 /* stream register offsets from stream base */
168 #define ICH6_REG_SD_CTL 0x00
169 #define ICH6_REG_SD_STS 0x03
170 #define ICH6_REG_SD_LPIB 0x04
171 #define ICH6_REG_SD_CBL 0x08
172 #define ICH6_REG_SD_LVI 0x0c
173 #define ICH6_REG_SD_FIFOW 0x0e
174 #define ICH6_REG_SD_FIFOSIZE 0x10
175 #define ICH6_REG_SD_FORMAT 0x12
176 #define ICH6_REG_SD_BDLPL 0x18
177 #define ICH6_REG_SD_BDLPU 0x1c
178
179 /* PCI space */
180 #define ICH6_PCIREG_TCSEL 0x44
181
182 /*
183 * other constants
184 */
185
186 /* max number of SDs */
187 /* ICH, ATI and VIA have 4 playback and 4 capture */
188 #define ICH6_CAPTURE_INDEX 0
189 #define ICH6_NUM_CAPTURE 4
190 #define ICH6_PLAYBACK_INDEX 4
191 #define ICH6_NUM_PLAYBACK 4
192
193 /* ULI has 6 playback and 5 capture */
194 #define ULI_CAPTURE_INDEX 0
195 #define ULI_NUM_CAPTURE 5
196 #define ULI_PLAYBACK_INDEX 5
197 #define ULI_NUM_PLAYBACK 6
198
199 /* ATI HDMI has 1 playback and 0 capture */
200 #define ATIHDMI_CAPTURE_INDEX 0
201 #define ATIHDMI_NUM_CAPTURE 0
202 #define ATIHDMI_PLAYBACK_INDEX 0
203 #define ATIHDMI_NUM_PLAYBACK 1
204
205 /* this number is statically defined for simplicity */
206 #define MAX_AZX_DEV 16
207
208 /* max number of fragments - we may use more if allocating more pages for BDL */
209 #define BDL_SIZE PAGE_ALIGN(8192)
210 #define AZX_MAX_FRAG (BDL_SIZE / (MAX_AZX_DEV * 16))
211 /* max buffer size - no h/w limit, you can increase as you like */
212 #define AZX_MAX_BUF_SIZE (1024*1024*1024)
213 /* max number of PCM devics per card */
214 #define AZX_MAX_AUDIO_PCMS 6
215 #define AZX_MAX_MODEM_PCMS 2
216 #define AZX_MAX_PCMS (AZX_MAX_AUDIO_PCMS + AZX_MAX_MODEM_PCMS)
217
218 /* RIRB int mask: overrun[2], response[0] */
219 #define RIRB_INT_RESPONSE 0x01
220 #define RIRB_INT_OVERRUN 0x04
221 #define RIRB_INT_MASK 0x05
222
223 /* STATESTS int mask: SD2,SD1,SD0 */
224 #define AZX_MAX_CODECS 3
225 #define STATESTS_INT_MASK 0x07
226
227 /* SD_CTL bits */
228 #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
229 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
230 #define SD_CTL_STREAM_TAG_MASK (0xf << 20)
231 #define SD_CTL_STREAM_TAG_SHIFT 20
232
233 /* SD_CTL and SD_STS */
234 #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
235 #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
236 #define SD_INT_COMPLETE 0x04 /* completion interrupt */
237 #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
238 SD_INT_COMPLETE)
239
240 /* SD_STS */
241 #define SD_STS_FIFO_READY 0x20 /* FIFO ready */
242
243 /* INTCTL and INTSTS */
244 #define ICH6_INT_ALL_STREAM 0xff /* all stream interrupts */
245 #define ICH6_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
246 #define ICH6_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
247
248 /* GCTL unsolicited response enable bit */
249 #define ICH6_GCTL_UREN (1<<8)
250
251 /* GCTL reset bit */
252 #define ICH6_GCTL_RESET (1<<0)
253
254 /* CORB/RIRB control, read/write pointer */
255 #define ICH6_RBCTL_DMA_EN 0x02 /* enable DMA */
256 #define ICH6_RBCTL_IRQ_EN 0x01 /* enable IRQ */
257 #define ICH6_RBRWP_CLR 0x8000 /* read/write pointer clear */
258 /* below are so far hardcoded - should read registers in future */
259 #define ICH6_MAX_CORB_ENTRIES 256
260 #define ICH6_MAX_RIRB_ENTRIES 256
261
262 /* position fix mode */
263 enum {
264 POS_FIX_AUTO,
265 POS_FIX_NONE,
266 POS_FIX_POSBUF,
267 POS_FIX_FIFO,
268 };
269
270 /* Defines for ATI HD Audio support in SB450 south bridge */
271 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR 0x42
272 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP 0x02
273
274 /* Defines for Nvidia HDA support */
275 #define NVIDIA_HDA_TRANSREG_ADDR 0x4e
276 #define NVIDIA_HDA_ENABLE_COHBITS 0x0f
277
278 /* Defines for Intel SCH HDA snoop control */
279 #define INTEL_SCH_HDA_DEVC 0x78
280 #define INTEL_SCH_HDA_DEVC_NOSNOOP (0x1<<11)
281
282
283 /*
284 */
285
286 struct azx_dev {
287 u32 *bdl; /* virtual address of the BDL */
288 dma_addr_t bdl_addr; /* physical address of the BDL */
289 u32 *posbuf; /* position buffer pointer */
290
291 unsigned int bufsize; /* size of the play buffer in bytes */
292 unsigned int fragsize; /* size of each period in bytes */
293 unsigned int frags; /* number for period in the play buffer */
294 unsigned int fifo_size; /* FIFO size */
295
296 void __iomem *sd_addr; /* stream descriptor pointer */
297
298 u32 sd_int_sta_mask; /* stream int status mask */
299
300 /* pcm support */
301 struct snd_pcm_substream *substream; /* assigned substream,
302 * set in PCM open
303 */
304 unsigned int format_val; /* format value to be set in the
305 * controller and the codec
306 */
307 unsigned char stream_tag; /* assigned stream */
308 unsigned char index; /* stream index */
309 /* for sanity check of position buffer */
310 unsigned int period_intr;
311
312 unsigned int opened :1;
313 unsigned int running :1;
314 };
315
316 /* CORB/RIRB */
317 struct azx_rb {
318 u32 *buf; /* CORB/RIRB buffer
319 * Each CORB entry is 4byte, RIRB is 8byte
320 */
321 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
322 /* for RIRB */
323 unsigned short rp, wp; /* read/write pointers */
324 int cmds; /* number of pending requests */
325 u32 res; /* last read value */
326 };
327
328 struct azx {
329 struct snd_card *card;
330 struct pci_dev *pci;
331
332 /* chip type specific */
333 int driver_type;
334 int playback_streams;
335 int playback_index_offset;
336 int capture_streams;
337 int capture_index_offset;
338 int num_streams;
339
340 /* pci resources */
341 unsigned long addr;
342 void __iomem *remap_addr;
343 int irq;
344
345 /* locks */
346 spinlock_t reg_lock;
347 struct mutex open_mutex;
348
349 /* streams (x num_streams) */
350 struct azx_dev *azx_dev;
351
352 /* PCM */
353 unsigned int pcm_devs;
354 struct snd_pcm *pcm[AZX_MAX_PCMS];
355
356 /* HD codec */
357 unsigned short codec_mask;
358 struct hda_bus *bus;
359
360 /* CORB/RIRB */
361 struct azx_rb corb;
362 struct azx_rb rirb;
363
364 /* BDL, CORB/RIRB and position buffers */
365 struct snd_dma_buffer bdl;
366 struct snd_dma_buffer rb;
367 struct snd_dma_buffer posbuf;
368
369 /* flags */
370 int position_fix;
371 unsigned int running :1;
372 unsigned int initialized :1;
373 unsigned int single_cmd :1;
374 unsigned int polling_mode :1;
375 unsigned int msi :1;
376
377 /* for debugging */
378 unsigned int last_cmd; /* last issued command (to sync) */
379 };
380
381 /* driver types */
382 enum {
383 AZX_DRIVER_ICH,
384 AZX_DRIVER_SCH,
385 AZX_DRIVER_ATI,
386 AZX_DRIVER_ATIHDMI,
387 AZX_DRIVER_VIA,
388 AZX_DRIVER_SIS,
389 AZX_DRIVER_ULI,
390 AZX_DRIVER_NVIDIA,
391 };
392
393 static char *driver_short_names[] __devinitdata = {
394 [AZX_DRIVER_ICH] = "HDA Intel",
395 [AZX_DRIVER_SCH] = "HDA Intel MID",
396 [AZX_DRIVER_ATI] = "HDA ATI SB",
397 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
398 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
399 [AZX_DRIVER_SIS] = "HDA SIS966",
400 [AZX_DRIVER_ULI] = "HDA ULI M5461",
401 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
402 };
403
404 /*
405 * macros for easy use
406 */
407 #define azx_writel(chip,reg,value) \
408 writel(value, (chip)->remap_addr + ICH6_REG_##reg)
409 #define azx_readl(chip,reg) \
410 readl((chip)->remap_addr + ICH6_REG_##reg)
411 #define azx_writew(chip,reg,value) \
412 writew(value, (chip)->remap_addr + ICH6_REG_##reg)
413 #define azx_readw(chip,reg) \
414 readw((chip)->remap_addr + ICH6_REG_##reg)
415 #define azx_writeb(chip,reg,value) \
416 writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
417 #define azx_readb(chip,reg) \
418 readb((chip)->remap_addr + ICH6_REG_##reg)
419
420 #define azx_sd_writel(dev,reg,value) \
421 writel(value, (dev)->sd_addr + ICH6_REG_##reg)
422 #define azx_sd_readl(dev,reg) \
423 readl((dev)->sd_addr + ICH6_REG_##reg)
424 #define azx_sd_writew(dev,reg,value) \
425 writew(value, (dev)->sd_addr + ICH6_REG_##reg)
426 #define azx_sd_readw(dev,reg) \
427 readw((dev)->sd_addr + ICH6_REG_##reg)
428 #define azx_sd_writeb(dev,reg,value) \
429 writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
430 #define azx_sd_readb(dev,reg) \
431 readb((dev)->sd_addr + ICH6_REG_##reg)
432
433 /* for pcm support */
434 #define get_azx_dev(substream) (substream->runtime->private_data)
435
436 /* Get the upper 32bit of the given dma_addr_t
437 * Compiler should optimize and eliminate the code if dma_addr_t is 32bit
438 */
439 #define upper_32bit(addr) (sizeof(addr) > 4 ? (u32)((addr) >> 32) : (u32)0)
440
441 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
442
443 /*
444 * Interface for HD codec
445 */
446
447 /*
448 * CORB / RIRB interface
449 */
450 static int azx_alloc_cmd_io(struct azx *chip)
451 {
452 int err;
453
454 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
455 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
456 snd_dma_pci_data(chip->pci),
457 PAGE_SIZE, &chip->rb);
458 if (err < 0) {
459 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
460 return err;
461 }
462 return 0;
463 }
464
465 static void azx_init_cmd_io(struct azx *chip)
466 {
467 /* CORB set up */
468 chip->corb.addr = chip->rb.addr;
469 chip->corb.buf = (u32 *)chip->rb.area;
470 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
471 azx_writel(chip, CORBUBASE, upper_32bit(chip->corb.addr));
472
473 /* set the corb size to 256 entries (ULI requires explicitly) */
474 azx_writeb(chip, CORBSIZE, 0x02);
475 /* set the corb write pointer to 0 */
476 azx_writew(chip, CORBWP, 0);
477 /* reset the corb hw read pointer */
478 azx_writew(chip, CORBRP, ICH6_RBRWP_CLR);
479 /* enable corb dma */
480 azx_writeb(chip, CORBCTL, ICH6_RBCTL_DMA_EN);
481
482 /* RIRB set up */
483 chip->rirb.addr = chip->rb.addr + 2048;
484 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
485 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
486 azx_writel(chip, RIRBUBASE, upper_32bit(chip->rirb.addr));
487
488 /* set the rirb size to 256 entries (ULI requires explicitly) */
489 azx_writeb(chip, RIRBSIZE, 0x02);
490 /* reset the rirb hw write pointer */
491 azx_writew(chip, RIRBWP, ICH6_RBRWP_CLR);
492 /* set N=1, get RIRB response interrupt for new entry */
493 azx_writew(chip, RINTCNT, 1);
494 /* enable rirb dma and response irq */
495 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
496 chip->rirb.rp = chip->rirb.cmds = 0;
497 }
498
499 static void azx_free_cmd_io(struct azx *chip)
500 {
501 /* disable ringbuffer DMAs */
502 azx_writeb(chip, RIRBCTL, 0);
503 azx_writeb(chip, CORBCTL, 0);
504 }
505
506 /* send a command */
507 static int azx_corb_send_cmd(struct hda_codec *codec, u32 val)
508 {
509 struct azx *chip = codec->bus->private_data;
510 unsigned int wp;
511
512 /* add command to corb */
513 wp = azx_readb(chip, CORBWP);
514 wp++;
515 wp %= ICH6_MAX_CORB_ENTRIES;
516
517 spin_lock_irq(&chip->reg_lock);
518 chip->rirb.cmds++;
519 chip->corb.buf[wp] = cpu_to_le32(val);
520 azx_writel(chip, CORBWP, wp);
521 spin_unlock_irq(&chip->reg_lock);
522
523 return 0;
524 }
525
526 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
527
528 /* retrieve RIRB entry - called from interrupt handler */
529 static void azx_update_rirb(struct azx *chip)
530 {
531 unsigned int rp, wp;
532 u32 res, res_ex;
533
534 wp = azx_readb(chip, RIRBWP);
535 if (wp == chip->rirb.wp)
536 return;
537 chip->rirb.wp = wp;
538
539 while (chip->rirb.rp != wp) {
540 chip->rirb.rp++;
541 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
542
543 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
544 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
545 res = le32_to_cpu(chip->rirb.buf[rp]);
546 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
547 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
548 else if (chip->rirb.cmds) {
549 chip->rirb.cmds--;
550 chip->rirb.res = res;
551 }
552 }
553 }
554
555 /* receive a response */
556 static unsigned int azx_rirb_get_response(struct hda_codec *codec)
557 {
558 struct azx *chip = codec->bus->private_data;
559 unsigned long timeout;
560
561 again:
562 timeout = jiffies + msecs_to_jiffies(1000);
563 for (;;) {
564 if (chip->polling_mode) {
565 spin_lock_irq(&chip->reg_lock);
566 azx_update_rirb(chip);
567 spin_unlock_irq(&chip->reg_lock);
568 }
569 if (!chip->rirb.cmds)
570 return chip->rirb.res; /* the last value */
571 if (time_after(jiffies, timeout))
572 break;
573 if (codec->bus->needs_damn_long_delay)
574 msleep(2); /* temporary workaround */
575 else {
576 udelay(10);
577 cond_resched();
578 }
579 }
580
581 if (chip->msi) {
582 snd_printk(KERN_WARNING "hda_intel: No response from codec, "
583 "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
584 free_irq(chip->irq, chip);
585 chip->irq = -1;
586 pci_disable_msi(chip->pci);
587 chip->msi = 0;
588 if (azx_acquire_irq(chip, 1) < 0)
589 return -1;
590 goto again;
591 }
592
593 if (!chip->polling_mode) {
594 snd_printk(KERN_WARNING "hda_intel: azx_get_response timeout, "
595 "switching to polling mode: last cmd=0x%08x\n",
596 chip->last_cmd);
597 chip->polling_mode = 1;
598 goto again;
599 }
600
601 snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
602 "switching to single_cmd mode: last cmd=0x%08x\n",
603 chip->last_cmd);
604 chip->rirb.rp = azx_readb(chip, RIRBWP);
605 chip->rirb.cmds = 0;
606 /* switch to single_cmd mode */
607 chip->single_cmd = 1;
608 azx_free_cmd_io(chip);
609 return -1;
610 }
611
612 /*
613 * Use the single immediate command instead of CORB/RIRB for simplicity
614 *
615 * Note: according to Intel, this is not preferred use. The command was
616 * intended for the BIOS only, and may get confused with unsolicited
617 * responses. So, we shouldn't use it for normal operation from the
618 * driver.
619 * I left the codes, however, for debugging/testing purposes.
620 */
621
622 /* send a command */
623 static int azx_single_send_cmd(struct hda_codec *codec, u32 val)
624 {
625 struct azx *chip = codec->bus->private_data;
626 int timeout = 50;
627
628 while (timeout--) {
629 /* check ICB busy bit */
630 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
631 /* Clear IRV valid bit */
632 azx_writew(chip, IRS, azx_readw(chip, IRS) |
633 ICH6_IRS_VALID);
634 azx_writel(chip, IC, val);
635 azx_writew(chip, IRS, azx_readw(chip, IRS) |
636 ICH6_IRS_BUSY);
637 return 0;
638 }
639 udelay(1);
640 }
641 if (printk_ratelimit())
642 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
643 azx_readw(chip, IRS), val);
644 return -EIO;
645 }
646
647 /* receive a response */
648 static unsigned int azx_single_get_response(struct hda_codec *codec)
649 {
650 struct azx *chip = codec->bus->private_data;
651 int timeout = 50;
652
653 while (timeout--) {
654 /* check IRV busy bit */
655 if (azx_readw(chip, IRS) & ICH6_IRS_VALID)
656 return azx_readl(chip, IR);
657 udelay(1);
658 }
659 if (printk_ratelimit())
660 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
661 azx_readw(chip, IRS));
662 return (unsigned int)-1;
663 }
664
665 /*
666 * The below are the main callbacks from hda_codec.
667 *
668 * They are just the skeleton to call sub-callbacks according to the
669 * current setting of chip->single_cmd.
670 */
671
672 /* send a command */
673 static int azx_send_cmd(struct hda_codec *codec, hda_nid_t nid,
674 int direct, unsigned int verb,
675 unsigned int para)
676 {
677 struct azx *chip = codec->bus->private_data;
678 u32 val;
679
680 val = (u32)(codec->addr & 0x0f) << 28;
681 val |= (u32)direct << 27;
682 val |= (u32)nid << 20;
683 val |= verb << 8;
684 val |= para;
685 chip->last_cmd = val;
686
687 if (chip->single_cmd)
688 return azx_single_send_cmd(codec, val);
689 else
690 return azx_corb_send_cmd(codec, val);
691 }
692
693 /* get a response */
694 static unsigned int azx_get_response(struct hda_codec *codec)
695 {
696 struct azx *chip = codec->bus->private_data;
697 if (chip->single_cmd)
698 return azx_single_get_response(codec);
699 else
700 return azx_rirb_get_response(codec);
701 }
702
703 #ifdef CONFIG_SND_HDA_POWER_SAVE
704 static void azx_power_notify(struct hda_codec *codec);
705 #endif
706
707 /* reset codec link */
708 static int azx_reset(struct azx *chip)
709 {
710 int count;
711
712 /* clear STATESTS */
713 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
714
715 /* reset controller */
716 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
717
718 count = 50;
719 while (azx_readb(chip, GCTL) && --count)
720 msleep(1);
721
722 /* delay for >= 100us for codec PLL to settle per spec
723 * Rev 0.9 section 5.5.1
724 */
725 msleep(1);
726
727 /* Bring controller out of reset */
728 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
729
730 count = 50;
731 while (!azx_readb(chip, GCTL) && --count)
732 msleep(1);
733
734 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
735 msleep(1);
736
737 /* check to see if controller is ready */
738 if (!azx_readb(chip, GCTL)) {
739 snd_printd("azx_reset: controller not ready!\n");
740 return -EBUSY;
741 }
742
743 /* Accept unsolicited responses */
744 azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UREN);
745
746 /* detect codecs */
747 if (!chip->codec_mask) {
748 chip->codec_mask = azx_readw(chip, STATESTS);
749 snd_printdd("codec_mask = 0x%x\n", chip->codec_mask);
750 }
751
752 return 0;
753 }
754
755
756 /*
757 * Lowlevel interface
758 */
759
760 /* enable interrupts */
761 static void azx_int_enable(struct azx *chip)
762 {
763 /* enable controller CIE and GIE */
764 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
765 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
766 }
767
768 /* disable interrupts */
769 static void azx_int_disable(struct azx *chip)
770 {
771 int i;
772
773 /* disable interrupts in stream descriptor */
774 for (i = 0; i < chip->num_streams; i++) {
775 struct azx_dev *azx_dev = &chip->azx_dev[i];
776 azx_sd_writeb(azx_dev, SD_CTL,
777 azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
778 }
779
780 /* disable SIE for all streams */
781 azx_writeb(chip, INTCTL, 0);
782
783 /* disable controller CIE and GIE */
784 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
785 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
786 }
787
788 /* clear interrupts */
789 static void azx_int_clear(struct azx *chip)
790 {
791 int i;
792
793 /* clear stream status */
794 for (i = 0; i < chip->num_streams; i++) {
795 struct azx_dev *azx_dev = &chip->azx_dev[i];
796 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
797 }
798
799 /* clear STATESTS */
800 azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
801
802 /* clear rirb status */
803 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
804
805 /* clear int status */
806 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
807 }
808
809 /* start a stream */
810 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
811 {
812 /* enable SIE */
813 azx_writeb(chip, INTCTL,
814 azx_readb(chip, INTCTL) | (1 << azx_dev->index));
815 /* set DMA start and interrupt mask */
816 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
817 SD_CTL_DMA_START | SD_INT_MASK);
818 }
819
820 /* stop a stream */
821 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
822 {
823 /* stop DMA */
824 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
825 ~(SD_CTL_DMA_START | SD_INT_MASK));
826 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
827 /* disable SIE */
828 azx_writeb(chip, INTCTL,
829 azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
830 }
831
832
833 /*
834 * reset and start the controller registers
835 */
836 static void azx_init_chip(struct azx *chip)
837 {
838 if (chip->initialized)
839 return;
840
841 /* reset controller */
842 azx_reset(chip);
843
844 /* initialize interrupts */
845 azx_int_clear(chip);
846 azx_int_enable(chip);
847
848 /* initialize the codec command I/O */
849 if (!chip->single_cmd)
850 azx_init_cmd_io(chip);
851
852 /* program the position buffer */
853 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
854 azx_writel(chip, DPUBASE, upper_32bit(chip->posbuf.addr));
855
856 chip->initialized = 1;
857 }
858
859 /*
860 * initialize the PCI registers
861 */
862 /* update bits in a PCI register byte */
863 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
864 unsigned char mask, unsigned char val)
865 {
866 unsigned char data;
867
868 pci_read_config_byte(pci, reg, &data);
869 data &= ~mask;
870 data |= (val & mask);
871 pci_write_config_byte(pci, reg, data);
872 }
873
874 static void azx_init_pci(struct azx *chip)
875 {
876 unsigned short snoop;
877
878 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
879 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
880 * Ensuring these bits are 0 clears playback static on some HD Audio
881 * codecs
882 */
883 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
884
885 switch (chip->driver_type) {
886 case AZX_DRIVER_ATI:
887 /* For ATI SB450 azalia HD audio, we need to enable snoop */
888 update_pci_byte(chip->pci,
889 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
890 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
891 break;
892 case AZX_DRIVER_NVIDIA:
893 /* For NVIDIA HDA, enable snoop */
894 update_pci_byte(chip->pci,
895 NVIDIA_HDA_TRANSREG_ADDR,
896 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
897 break;
898 case AZX_DRIVER_SCH:
899 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
900 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
901 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, \
902 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
903 pci_read_config_word(chip->pci,
904 INTEL_SCH_HDA_DEVC, &snoop);
905 snd_printdd("HDA snoop disabled, enabling ... %s\n",\
906 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) \
907 ? "Failed" : "OK");
908 }
909 break;
910
911 }
912 }
913
914
915 /*
916 * interrupt handler
917 */
918 static irqreturn_t azx_interrupt(int irq, void *dev_id)
919 {
920 struct azx *chip = dev_id;
921 struct azx_dev *azx_dev;
922 u32 status;
923 int i;
924
925 spin_lock(&chip->reg_lock);
926
927 status = azx_readl(chip, INTSTS);
928 if (status == 0) {
929 spin_unlock(&chip->reg_lock);
930 return IRQ_NONE;
931 }
932
933 for (i = 0; i < chip->num_streams; i++) {
934 azx_dev = &chip->azx_dev[i];
935 if (status & azx_dev->sd_int_sta_mask) {
936 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
937 if (azx_dev->substream && azx_dev->running) {
938 azx_dev->period_intr++;
939 spin_unlock(&chip->reg_lock);
940 snd_pcm_period_elapsed(azx_dev->substream);
941 spin_lock(&chip->reg_lock);
942 }
943 }
944 }
945
946 /* clear rirb int */
947 status = azx_readb(chip, RIRBSTS);
948 if (status & RIRB_INT_MASK) {
949 if (!chip->single_cmd && (status & RIRB_INT_RESPONSE))
950 azx_update_rirb(chip);
951 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
952 }
953
954 #if 0
955 /* clear state status int */
956 if (azx_readb(chip, STATESTS) & 0x04)
957 azx_writeb(chip, STATESTS, 0x04);
958 #endif
959 spin_unlock(&chip->reg_lock);
960
961 return IRQ_HANDLED;
962 }
963
964
965 /*
966 * set up BDL entries
967 */
968 static void azx_setup_periods(struct azx_dev *azx_dev)
969 {
970 u32 *bdl = azx_dev->bdl;
971 dma_addr_t dma_addr = azx_dev->substream->runtime->dma_addr;
972 int idx;
973
974 /* reset BDL address */
975 azx_sd_writel(azx_dev, SD_BDLPL, 0);
976 azx_sd_writel(azx_dev, SD_BDLPU, 0);
977
978 /* program the initial BDL entries */
979 for (idx = 0; idx < azx_dev->frags; idx++) {
980 unsigned int off = idx << 2; /* 4 dword step */
981 dma_addr_t addr = dma_addr + idx * azx_dev->fragsize;
982 /* program the address field of the BDL entry */
983 bdl[off] = cpu_to_le32((u32)addr);
984 bdl[off+1] = cpu_to_le32(upper_32bit(addr));
985
986 /* program the size field of the BDL entry */
987 bdl[off+2] = cpu_to_le32(azx_dev->fragsize);
988
989 /* program the IOC to enable interrupt when buffer completes */
990 bdl[off+3] = cpu_to_le32(0x01);
991 }
992 }
993
994 /*
995 * set up the SD for streaming
996 */
997 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
998 {
999 unsigned char val;
1000 int timeout;
1001
1002 /* make sure the run bit is zero for SD */
1003 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1004 ~SD_CTL_DMA_START);
1005 /* reset stream */
1006 azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1007 SD_CTL_STREAM_RESET);
1008 udelay(3);
1009 timeout = 300;
1010 while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1011 --timeout)
1012 ;
1013 val &= ~SD_CTL_STREAM_RESET;
1014 azx_sd_writeb(azx_dev, SD_CTL, val);
1015 udelay(3);
1016
1017 timeout = 300;
1018 /* waiting for hardware to report that the stream is out of reset */
1019 while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1020 --timeout)
1021 ;
1022
1023 /* program the stream_tag */
1024 azx_sd_writel(azx_dev, SD_CTL,
1025 (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1026 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1027
1028 /* program the length of samples in cyclic buffer */
1029 azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1030
1031 /* program the stream format */
1032 /* this value needs to be the same as the one programmed */
1033 azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1034
1035 /* program the stream LVI (last valid index) of the BDL */
1036 azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1037
1038 /* program the BDL address */
1039 /* lower BDL address */
1040 azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl_addr);
1041 /* upper BDL address */
1042 azx_sd_writel(azx_dev, SD_BDLPU, upper_32bit(azx_dev->bdl_addr));
1043
1044 /* enable the position buffer */
1045 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1046 azx_writel(chip, DPLBASE,
1047 (u32)chip->posbuf.addr |ICH6_DPLBASE_ENABLE);
1048
1049 /* set the interrupt enable bits in the descriptor control register */
1050 azx_sd_writel(azx_dev, SD_CTL,
1051 azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1052
1053 return 0;
1054 }
1055
1056
1057 /*
1058 * Codec initialization
1059 */
1060
1061 static unsigned int azx_max_codecs[] __devinitdata = {
1062 [AZX_DRIVER_ICH] = 3,
1063 [AZX_DRIVER_SCH] = 3,
1064 [AZX_DRIVER_ATI] = 4,
1065 [AZX_DRIVER_ATIHDMI] = 4,
1066 [AZX_DRIVER_VIA] = 3, /* FIXME: correct? */
1067 [AZX_DRIVER_SIS] = 3, /* FIXME: correct? */
1068 [AZX_DRIVER_ULI] = 3, /* FIXME: correct? */
1069 [AZX_DRIVER_NVIDIA] = 3, /* FIXME: correct? */
1070 };
1071
1072 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1073 unsigned int codec_probe_mask)
1074 {
1075 struct hda_bus_template bus_temp;
1076 int c, codecs, audio_codecs, err;
1077
1078 memset(&bus_temp, 0, sizeof(bus_temp));
1079 bus_temp.private_data = chip;
1080 bus_temp.modelname = model;
1081 bus_temp.pci = chip->pci;
1082 bus_temp.ops.command = azx_send_cmd;
1083 bus_temp.ops.get_response = azx_get_response;
1084 #ifdef CONFIG_SND_HDA_POWER_SAVE
1085 bus_temp.ops.pm_notify = azx_power_notify;
1086 #endif
1087
1088 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1089 if (err < 0)
1090 return err;
1091
1092 codecs = audio_codecs = 0;
1093 for (c = 0; c < AZX_MAX_CODECS; c++) {
1094 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1095 struct hda_codec *codec;
1096 err = snd_hda_codec_new(chip->bus, c, &codec);
1097 if (err < 0)
1098 continue;
1099 codecs++;
1100 if (codec->afg)
1101 audio_codecs++;
1102 }
1103 }
1104 if (!audio_codecs) {
1105 /* probe additional slots if no codec is found */
1106 for (; c < azx_max_codecs[chip->driver_type]; c++) {
1107 if ((chip->codec_mask & (1 << c)) & codec_probe_mask) {
1108 err = snd_hda_codec_new(chip->bus, c, NULL);
1109 if (err < 0)
1110 continue;
1111 codecs++;
1112 }
1113 }
1114 }
1115 if (!codecs) {
1116 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1117 return -ENXIO;
1118 }
1119
1120 return 0;
1121 }
1122
1123
1124 /*
1125 * PCM support
1126 */
1127
1128 /* assign a stream for the PCM */
1129 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1130 {
1131 int dev, i, nums;
1132 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1133 dev = chip->playback_index_offset;
1134 nums = chip->playback_streams;
1135 } else {
1136 dev = chip->capture_index_offset;
1137 nums = chip->capture_streams;
1138 }
1139 for (i = 0; i < nums; i++, dev++)
1140 if (!chip->azx_dev[dev].opened) {
1141 chip->azx_dev[dev].opened = 1;
1142 return &chip->azx_dev[dev];
1143 }
1144 return NULL;
1145 }
1146
1147 /* release the assigned stream */
1148 static inline void azx_release_device(struct azx_dev *azx_dev)
1149 {
1150 azx_dev->opened = 0;
1151 }
1152
1153 static struct snd_pcm_hardware azx_pcm_hw = {
1154 .info = (SNDRV_PCM_INFO_MMAP |
1155 SNDRV_PCM_INFO_INTERLEAVED |
1156 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1157 SNDRV_PCM_INFO_MMAP_VALID |
1158 /* No full-resume yet implemented */
1159 /* SNDRV_PCM_INFO_RESUME |*/
1160 SNDRV_PCM_INFO_PAUSE),
1161 .formats = SNDRV_PCM_FMTBIT_S16_LE,
1162 .rates = SNDRV_PCM_RATE_48000,
1163 .rate_min = 48000,
1164 .rate_max = 48000,
1165 .channels_min = 2,
1166 .channels_max = 2,
1167 .buffer_bytes_max = AZX_MAX_BUF_SIZE,
1168 .period_bytes_min = 128,
1169 .period_bytes_max = AZX_MAX_BUF_SIZE / 2,
1170 .periods_min = 2,
1171 .periods_max = AZX_MAX_FRAG,
1172 .fifo_size = 0,
1173 };
1174
1175 struct azx_pcm {
1176 struct azx *chip;
1177 struct hda_codec *codec;
1178 struct hda_pcm_stream *hinfo[2];
1179 };
1180
1181 static int azx_pcm_open(struct snd_pcm_substream *substream)
1182 {
1183 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1184 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1185 struct azx *chip = apcm->chip;
1186 struct azx_dev *azx_dev;
1187 struct snd_pcm_runtime *runtime = substream->runtime;
1188 unsigned long flags;
1189 int err;
1190
1191 mutex_lock(&chip->open_mutex);
1192 azx_dev = azx_assign_device(chip, substream->stream);
1193 if (azx_dev == NULL) {
1194 mutex_unlock(&chip->open_mutex);
1195 return -EBUSY;
1196 }
1197 runtime->hw = azx_pcm_hw;
1198 runtime->hw.channels_min = hinfo->channels_min;
1199 runtime->hw.channels_max = hinfo->channels_max;
1200 runtime->hw.formats = hinfo->formats;
1201 runtime->hw.rates = hinfo->rates;
1202 snd_pcm_limit_hw_rates(runtime);
1203 snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1204 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1205 128);
1206 snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1207 128);
1208 snd_hda_power_up(apcm->codec);
1209 err = hinfo->ops.open(hinfo, apcm->codec, substream);
1210 if (err < 0) {
1211 azx_release_device(azx_dev);
1212 snd_hda_power_down(apcm->codec);
1213 mutex_unlock(&chip->open_mutex);
1214 return err;
1215 }
1216 spin_lock_irqsave(&chip->reg_lock, flags);
1217 azx_dev->substream = substream;
1218 azx_dev->running = 0;
1219 spin_unlock_irqrestore(&chip->reg_lock, flags);
1220
1221 runtime->private_data = azx_dev;
1222 mutex_unlock(&chip->open_mutex);
1223 return 0;
1224 }
1225
1226 static int azx_pcm_close(struct snd_pcm_substream *substream)
1227 {
1228 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1229 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1230 struct azx *chip = apcm->chip;
1231 struct azx_dev *azx_dev = get_azx_dev(substream);
1232 unsigned long flags;
1233
1234 mutex_lock(&chip->open_mutex);
1235 spin_lock_irqsave(&chip->reg_lock, flags);
1236 azx_dev->substream = NULL;
1237 azx_dev->running = 0;
1238 spin_unlock_irqrestore(&chip->reg_lock, flags);
1239 azx_release_device(azx_dev);
1240 hinfo->ops.close(hinfo, apcm->codec, substream);
1241 snd_hda_power_down(apcm->codec);
1242 mutex_unlock(&chip->open_mutex);
1243 return 0;
1244 }
1245
1246 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1247 struct snd_pcm_hw_params *hw_params)
1248 {
1249 return snd_pcm_lib_malloc_pages(substream,
1250 params_buffer_bytes(hw_params));
1251 }
1252
1253 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1254 {
1255 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1256 struct azx_dev *azx_dev = get_azx_dev(substream);
1257 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1258
1259 /* reset BDL address */
1260 azx_sd_writel(azx_dev, SD_BDLPL, 0);
1261 azx_sd_writel(azx_dev, SD_BDLPU, 0);
1262 azx_sd_writel(azx_dev, SD_CTL, 0);
1263
1264 hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1265
1266 return snd_pcm_lib_free_pages(substream);
1267 }
1268
1269 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1270 {
1271 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1272 struct azx *chip = apcm->chip;
1273 struct azx_dev *azx_dev = get_azx_dev(substream);
1274 struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1275 struct snd_pcm_runtime *runtime = substream->runtime;
1276
1277 azx_dev->bufsize = snd_pcm_lib_buffer_bytes(substream);
1278 azx_dev->fragsize = snd_pcm_lib_period_bytes(substream);
1279 azx_dev->frags = azx_dev->bufsize / azx_dev->fragsize;
1280 azx_dev->format_val = snd_hda_calc_stream_format(runtime->rate,
1281 runtime->channels,
1282 runtime->format,
1283 hinfo->maxbps);
1284 if (!azx_dev->format_val) {
1285 snd_printk(KERN_ERR SFX
1286 "invalid format_val, rate=%d, ch=%d, format=%d\n",
1287 runtime->rate, runtime->channels, runtime->format);
1288 return -EINVAL;
1289 }
1290
1291 snd_printdd("azx_pcm_prepare: bufsize=0x%x, fragsize=0x%x, "
1292 "format=0x%x\n",
1293 azx_dev->bufsize, azx_dev->fragsize, azx_dev->format_val);
1294 azx_setup_periods(azx_dev);
1295 azx_setup_controller(chip, azx_dev);
1296 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1297 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1298 else
1299 azx_dev->fifo_size = 0;
1300
1301 return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1302 azx_dev->format_val, substream);
1303 }
1304
1305 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1306 {
1307 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1308 struct azx_dev *azx_dev = get_azx_dev(substream);
1309 struct azx *chip = apcm->chip;
1310 int err = 0;
1311
1312 spin_lock(&chip->reg_lock);
1313 switch (cmd) {
1314 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1315 case SNDRV_PCM_TRIGGER_RESUME:
1316 case SNDRV_PCM_TRIGGER_START:
1317 azx_stream_start(chip, azx_dev);
1318 azx_dev->running = 1;
1319 break;
1320 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1321 case SNDRV_PCM_TRIGGER_SUSPEND:
1322 case SNDRV_PCM_TRIGGER_STOP:
1323 azx_stream_stop(chip, azx_dev);
1324 azx_dev->running = 0;
1325 break;
1326 default:
1327 err = -EINVAL;
1328 }
1329 spin_unlock(&chip->reg_lock);
1330 if (cmd == SNDRV_PCM_TRIGGER_PAUSE_PUSH ||
1331 cmd == SNDRV_PCM_TRIGGER_SUSPEND ||
1332 cmd == SNDRV_PCM_TRIGGER_STOP) {
1333 int timeout = 5000;
1334 while ((azx_sd_readb(azx_dev, SD_CTL) & SD_CTL_DMA_START) &&
1335 --timeout)
1336 ;
1337 }
1338 return err;
1339 }
1340
1341 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1342 {
1343 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1344 struct azx *chip = apcm->chip;
1345 struct azx_dev *azx_dev = get_azx_dev(substream);
1346 unsigned int pos;
1347
1348 if (chip->position_fix == POS_FIX_POSBUF ||
1349 chip->position_fix == POS_FIX_AUTO) {
1350 /* use the position buffer */
1351 pos = le32_to_cpu(*azx_dev->posbuf);
1352 if (chip->position_fix == POS_FIX_AUTO &&
1353 azx_dev->period_intr == 1 && !pos) {
1354 printk(KERN_WARNING
1355 "hda-intel: Invalid position buffer, "
1356 "using LPIB read method instead.\n");
1357 chip->position_fix = POS_FIX_NONE;
1358 goto read_lpib;
1359 }
1360 } else {
1361 read_lpib:
1362 /* read LPIB */
1363 pos = azx_sd_readl(azx_dev, SD_LPIB);
1364 if (chip->position_fix == POS_FIX_FIFO)
1365 pos += azx_dev->fifo_size;
1366 }
1367 if (pos >= azx_dev->bufsize)
1368 pos = 0;
1369 return bytes_to_frames(substream->runtime, pos);
1370 }
1371
1372 static struct snd_pcm_ops azx_pcm_ops = {
1373 .open = azx_pcm_open,
1374 .close = azx_pcm_close,
1375 .ioctl = snd_pcm_lib_ioctl,
1376 .hw_params = azx_pcm_hw_params,
1377 .hw_free = azx_pcm_hw_free,
1378 .prepare = azx_pcm_prepare,
1379 .trigger = azx_pcm_trigger,
1380 .pointer = azx_pcm_pointer,
1381 };
1382
1383 static void azx_pcm_free(struct snd_pcm *pcm)
1384 {
1385 kfree(pcm->private_data);
1386 }
1387
1388 static int __devinit create_codec_pcm(struct azx *chip, struct hda_codec *codec,
1389 struct hda_pcm *cpcm, int pcm_dev)
1390 {
1391 int err;
1392 struct snd_pcm *pcm;
1393 struct azx_pcm *apcm;
1394
1395 /* if no substreams are defined for both playback and capture,
1396 * it's just a placeholder. ignore it.
1397 */
1398 if (!cpcm->stream[0].substreams && !cpcm->stream[1].substreams)
1399 return 0;
1400
1401 snd_assert(cpcm->name, return -EINVAL);
1402
1403 err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1404 cpcm->stream[0].substreams,
1405 cpcm->stream[1].substreams,
1406 &pcm);
1407 if (err < 0)
1408 return err;
1409 strcpy(pcm->name, cpcm->name);
1410 apcm = kmalloc(sizeof(*apcm), GFP_KERNEL);
1411 if (apcm == NULL)
1412 return -ENOMEM;
1413 apcm->chip = chip;
1414 apcm->codec = codec;
1415 apcm->hinfo[0] = &cpcm->stream[0];
1416 apcm->hinfo[1] = &cpcm->stream[1];
1417 pcm->private_data = apcm;
1418 pcm->private_free = azx_pcm_free;
1419 if (cpcm->stream[0].substreams)
1420 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &azx_pcm_ops);
1421 if (cpcm->stream[1].substreams)
1422 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &azx_pcm_ops);
1423 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1424 snd_dma_pci_data(chip->pci),
1425 1024 * 64, 1024 * 1024);
1426 chip->pcm[pcm_dev] = pcm;
1427 if (chip->pcm_devs < pcm_dev + 1)
1428 chip->pcm_devs = pcm_dev + 1;
1429
1430 return 0;
1431 }
1432
1433 static int __devinit azx_pcm_create(struct azx *chip)
1434 {
1435 struct hda_codec *codec;
1436 int c, err;
1437 int pcm_dev;
1438
1439 err = snd_hda_build_pcms(chip->bus);
1440 if (err < 0)
1441 return err;
1442
1443 /* create audio PCMs */
1444 pcm_dev = 0;
1445 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1446 for (c = 0; c < codec->num_pcms; c++) {
1447 if (codec->pcm_info[c].is_modem)
1448 continue; /* create later */
1449 if (pcm_dev >= AZX_MAX_AUDIO_PCMS) {
1450 snd_printk(KERN_ERR SFX
1451 "Too many audio PCMs\n");
1452 return -EINVAL;
1453 }
1454 err = create_codec_pcm(chip, codec,
1455 &codec->pcm_info[c], pcm_dev);
1456 if (err < 0)
1457 return err;
1458 pcm_dev++;
1459 }
1460 }
1461
1462 /* create modem PCMs */
1463 pcm_dev = AZX_MAX_AUDIO_PCMS;
1464 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1465 for (c = 0; c < codec->num_pcms; c++) {
1466 if (!codec->pcm_info[c].is_modem)
1467 continue; /* already created */
1468 if (pcm_dev >= AZX_MAX_PCMS) {
1469 snd_printk(KERN_ERR SFX
1470 "Too many modem PCMs\n");
1471 return -EINVAL;
1472 }
1473 err = create_codec_pcm(chip, codec,
1474 &codec->pcm_info[c], pcm_dev);
1475 if (err < 0)
1476 return err;
1477 chip->pcm[pcm_dev]->dev_class = SNDRV_PCM_CLASS_MODEM;
1478 pcm_dev++;
1479 }
1480 }
1481 return 0;
1482 }
1483
1484 /*
1485 * mixer creation - all stuff is implemented in hda module
1486 */
1487 static int __devinit azx_mixer_create(struct azx *chip)
1488 {
1489 return snd_hda_build_controls(chip->bus);
1490 }
1491
1492
1493 /*
1494 * initialize SD streams
1495 */
1496 static int __devinit azx_init_stream(struct azx *chip)
1497 {
1498 int i;
1499
1500 /* initialize each stream (aka device)
1501 * assign the starting bdl address to each stream (device)
1502 * and initialize
1503 */
1504 for (i = 0; i < chip->num_streams; i++) {
1505 unsigned int off = sizeof(u32) * (i * AZX_MAX_FRAG * 4);
1506 struct azx_dev *azx_dev = &chip->azx_dev[i];
1507 azx_dev->bdl = (u32 *)(chip->bdl.area + off);
1508 azx_dev->bdl_addr = chip->bdl.addr + off;
1509 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1510 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1511 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1512 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1513 azx_dev->sd_int_sta_mask = 1 << i;
1514 /* stream tag: must be non-zero and unique */
1515 azx_dev->index = i;
1516 azx_dev->stream_tag = i + 1;
1517 }
1518
1519 return 0;
1520 }
1521
1522 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1523 {
1524 if (request_irq(chip->pci->irq, azx_interrupt,
1525 chip->msi ? 0 : IRQF_SHARED,
1526 "HDA Intel", chip)) {
1527 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1528 "disabling device\n", chip->pci->irq);
1529 if (do_disconnect)
1530 snd_card_disconnect(chip->card);
1531 return -1;
1532 }
1533 chip->irq = chip->pci->irq;
1534 pci_intx(chip->pci, !chip->msi);
1535 return 0;
1536 }
1537
1538
1539 static void azx_stop_chip(struct azx *chip)
1540 {
1541 if (!chip->initialized)
1542 return;
1543
1544 /* disable interrupts */
1545 azx_int_disable(chip);
1546 azx_int_clear(chip);
1547
1548 /* disable CORB/RIRB */
1549 azx_free_cmd_io(chip);
1550
1551 /* disable position buffer */
1552 azx_writel(chip, DPLBASE, 0);
1553 azx_writel(chip, DPUBASE, 0);
1554
1555 chip->initialized = 0;
1556 }
1557
1558 #ifdef CONFIG_SND_HDA_POWER_SAVE
1559 /* power-up/down the controller */
1560 static void azx_power_notify(struct hda_codec *codec)
1561 {
1562 struct azx *chip = codec->bus->private_data;
1563 struct hda_codec *c;
1564 int power_on = 0;
1565
1566 list_for_each_entry(c, &codec->bus->codec_list, list) {
1567 if (c->power_on) {
1568 power_on = 1;
1569 break;
1570 }
1571 }
1572 if (power_on)
1573 azx_init_chip(chip);
1574 else if (chip->running && power_save_controller)
1575 azx_stop_chip(chip);
1576 }
1577 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1578
1579 #ifdef CONFIG_PM
1580 /*
1581 * power management
1582 */
1583 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1584 {
1585 struct snd_card *card = pci_get_drvdata(pci);
1586 struct azx *chip = card->private_data;
1587 int i;
1588
1589 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1590 for (i = 0; i < chip->pcm_devs; i++)
1591 snd_pcm_suspend_all(chip->pcm[i]);
1592 if (chip->initialized)
1593 snd_hda_suspend(chip->bus, state);
1594 azx_stop_chip(chip);
1595 if (chip->irq >= 0) {
1596 synchronize_irq(chip->irq);
1597 free_irq(chip->irq, chip);
1598 chip->irq = -1;
1599 }
1600 if (chip->msi)
1601 pci_disable_msi(chip->pci);
1602 pci_disable_device(pci);
1603 pci_save_state(pci);
1604 pci_set_power_state(pci, pci_choose_state(pci, state));
1605 return 0;
1606 }
1607
1608 static int azx_resume(struct pci_dev *pci)
1609 {
1610 struct snd_card *card = pci_get_drvdata(pci);
1611 struct azx *chip = card->private_data;
1612
1613 pci_set_power_state(pci, PCI_D0);
1614 pci_restore_state(pci);
1615 if (pci_enable_device(pci) < 0) {
1616 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
1617 "disabling device\n");
1618 snd_card_disconnect(card);
1619 return -EIO;
1620 }
1621 pci_set_master(pci);
1622 if (chip->msi)
1623 if (pci_enable_msi(pci) < 0)
1624 chip->msi = 0;
1625 if (azx_acquire_irq(chip, 1) < 0)
1626 return -EIO;
1627 azx_init_pci(chip);
1628
1629 if (snd_hda_codecs_inuse(chip->bus))
1630 azx_init_chip(chip);
1631
1632 snd_hda_resume(chip->bus);
1633 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1634 return 0;
1635 }
1636 #endif /* CONFIG_PM */
1637
1638
1639 /*
1640 * destructor
1641 */
1642 static int azx_free(struct azx *chip)
1643 {
1644 if (chip->initialized) {
1645 int i;
1646 for (i = 0; i < chip->num_streams; i++)
1647 azx_stream_stop(chip, &chip->azx_dev[i]);
1648 azx_stop_chip(chip);
1649 }
1650
1651 if (chip->irq >= 0) {
1652 synchronize_irq(chip->irq);
1653 free_irq(chip->irq, (void*)chip);
1654 }
1655 if (chip->msi)
1656 pci_disable_msi(chip->pci);
1657 if (chip->remap_addr)
1658 iounmap(chip->remap_addr);
1659
1660 if (chip->bdl.area)
1661 snd_dma_free_pages(&chip->bdl);
1662 if (chip->rb.area)
1663 snd_dma_free_pages(&chip->rb);
1664 if (chip->posbuf.area)
1665 snd_dma_free_pages(&chip->posbuf);
1666 pci_release_regions(chip->pci);
1667 pci_disable_device(chip->pci);
1668 kfree(chip->azx_dev);
1669 kfree(chip);
1670
1671 return 0;
1672 }
1673
1674 static int azx_dev_free(struct snd_device *device)
1675 {
1676 return azx_free(device->device_data);
1677 }
1678
1679 /*
1680 * white/black-listing for position_fix
1681 */
1682 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
1683 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_NONE),
1684 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_NONE),
1685 {}
1686 };
1687
1688 static int __devinit check_position_fix(struct azx *chip, int fix)
1689 {
1690 const struct snd_pci_quirk *q;
1691
1692 if (fix == POS_FIX_AUTO) {
1693 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1694 if (q) {
1695 printk(KERN_INFO
1696 "hda_intel: position_fix set to %d "
1697 "for device %04x:%04x\n",
1698 q->value, q->subvendor, q->subdevice);
1699 return q->value;
1700 }
1701 }
1702 return fix;
1703 }
1704
1705 /*
1706 * black-lists for probe_mask
1707 */
1708 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
1709 /* Thinkpad often breaks the controller communication when accessing
1710 * to the non-working (or non-existing) modem codec slot.
1711 */
1712 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1713 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1714 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1715 {}
1716 };
1717
1718 static void __devinit check_probe_mask(struct azx *chip, int dev)
1719 {
1720 const struct snd_pci_quirk *q;
1721
1722 if (probe_mask[dev] == -1) {
1723 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
1724 if (q) {
1725 printk(KERN_INFO
1726 "hda_intel: probe_mask set to 0x%x "
1727 "for device %04x:%04x\n",
1728 q->value, q->subvendor, q->subdevice);
1729 probe_mask[dev] = q->value;
1730 }
1731 }
1732 }
1733
1734
1735 /*
1736 * constructor
1737 */
1738 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
1739 int dev, int driver_type,
1740 struct azx **rchip)
1741 {
1742 struct azx *chip;
1743 int err;
1744 unsigned short gcap;
1745 static struct snd_device_ops ops = {
1746 .dev_free = azx_dev_free,
1747 };
1748
1749 *rchip = NULL;
1750
1751 err = pci_enable_device(pci);
1752 if (err < 0)
1753 return err;
1754
1755 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
1756 if (!chip) {
1757 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
1758 pci_disable_device(pci);
1759 return -ENOMEM;
1760 }
1761
1762 spin_lock_init(&chip->reg_lock);
1763 mutex_init(&chip->open_mutex);
1764 chip->card = card;
1765 chip->pci = pci;
1766 chip->irq = -1;
1767 chip->driver_type = driver_type;
1768 chip->msi = enable_msi;
1769
1770 chip->position_fix = check_position_fix(chip, position_fix[dev]);
1771 check_probe_mask(chip, dev);
1772
1773 chip->single_cmd = single_cmd;
1774
1775 #if BITS_PER_LONG != 64
1776 /* Fix up base address on ULI M5461 */
1777 if (chip->driver_type == AZX_DRIVER_ULI) {
1778 u16 tmp3;
1779 pci_read_config_word(pci, 0x40, &tmp3);
1780 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
1781 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
1782 }
1783 #endif
1784
1785 err = pci_request_regions(pci, "ICH HD audio");
1786 if (err < 0) {
1787 kfree(chip);
1788 pci_disable_device(pci);
1789 return err;
1790 }
1791
1792 chip->addr = pci_resource_start(pci, 0);
1793 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci,0));
1794 if (chip->remap_addr == NULL) {
1795 snd_printk(KERN_ERR SFX "ioremap error\n");
1796 err = -ENXIO;
1797 goto errout;
1798 }
1799
1800 if (chip->msi)
1801 if (pci_enable_msi(pci) < 0)
1802 chip->msi = 0;
1803
1804 if (azx_acquire_irq(chip, 0) < 0) {
1805 err = -EBUSY;
1806 goto errout;
1807 }
1808
1809 pci_set_master(pci);
1810 synchronize_irq(chip->irq);
1811
1812 gcap = azx_readw(chip, GCAP);
1813 snd_printdd("chipset global capabilities = 0x%x\n", gcap);
1814
1815 if (gcap) {
1816 /* read number of streams from GCAP register instead of using
1817 * hardcoded value
1818 */
1819 chip->playback_streams = (gcap & (0xF << 12)) >> 12;
1820 chip->capture_streams = (gcap & (0xF << 8)) >> 8;
1821 chip->playback_index_offset = chip->capture_streams;
1822 chip->capture_index_offset = 0;
1823 } else {
1824 /* gcap didn't give any info, switching to old method */
1825
1826 switch (chip->driver_type) {
1827 case AZX_DRIVER_ULI:
1828 chip->playback_streams = ULI_NUM_PLAYBACK;
1829 chip->capture_streams = ULI_NUM_CAPTURE;
1830 chip->playback_index_offset = ULI_PLAYBACK_INDEX;
1831 chip->capture_index_offset = ULI_CAPTURE_INDEX;
1832 break;
1833 case AZX_DRIVER_ATIHDMI:
1834 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
1835 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
1836 chip->playback_index_offset = ATIHDMI_PLAYBACK_INDEX;
1837 chip->capture_index_offset = ATIHDMI_CAPTURE_INDEX;
1838 break;
1839 default:
1840 chip->playback_streams = ICH6_NUM_PLAYBACK;
1841 chip->capture_streams = ICH6_NUM_CAPTURE;
1842 chip->playback_index_offset = ICH6_PLAYBACK_INDEX;
1843 chip->capture_index_offset = ICH6_CAPTURE_INDEX;
1844 break;
1845 }
1846 }
1847 chip->num_streams = chip->playback_streams + chip->capture_streams;
1848 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
1849 GFP_KERNEL);
1850 if (!chip->azx_dev) {
1851 snd_printk(KERN_ERR "cannot malloc azx_dev\n");
1852 goto errout;
1853 }
1854
1855 /* allocate memory for the BDL for each stream */
1856 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1857 snd_dma_pci_data(chip->pci),
1858 BDL_SIZE, &chip->bdl);
1859 if (err < 0) {
1860 snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
1861 goto errout;
1862 }
1863 /* allocate memory for the position buffer */
1864 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
1865 snd_dma_pci_data(chip->pci),
1866 chip->num_streams * 8, &chip->posbuf);
1867 if (err < 0) {
1868 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
1869 goto errout;
1870 }
1871 /* allocate CORB/RIRB */
1872 if (!chip->single_cmd) {
1873 err = azx_alloc_cmd_io(chip);
1874 if (err < 0)
1875 goto errout;
1876 }
1877
1878 /* initialize streams */
1879 azx_init_stream(chip);
1880
1881 /* initialize chip */
1882 azx_init_pci(chip);
1883 azx_init_chip(chip);
1884
1885 /* codec detection */
1886 if (!chip->codec_mask) {
1887 snd_printk(KERN_ERR SFX "no codecs found!\n");
1888 err = -ENODEV;
1889 goto errout;
1890 }
1891
1892 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
1893 if (err <0) {
1894 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
1895 goto errout;
1896 }
1897
1898 strcpy(card->driver, "HDA-Intel");
1899 strcpy(card->shortname, driver_short_names[chip->driver_type]);
1900 sprintf(card->longname, "%s at 0x%lx irq %i",
1901 card->shortname, chip->addr, chip->irq);
1902
1903 *rchip = chip;
1904 return 0;
1905
1906 errout:
1907 azx_free(chip);
1908 return err;
1909 }
1910
1911 static void power_down_all_codecs(struct azx *chip)
1912 {
1913 #ifdef CONFIG_SND_HDA_POWER_SAVE
1914 /* The codecs were powered up in snd_hda_codec_new().
1915 * Now all initialization done, so turn them down if possible
1916 */
1917 struct hda_codec *codec;
1918 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1919 snd_hda_power_down(codec);
1920 }
1921 #endif
1922 }
1923
1924 static int __devinit azx_probe(struct pci_dev *pci,
1925 const struct pci_device_id *pci_id)
1926 {
1927 static int dev;
1928 struct snd_card *card;
1929 struct azx *chip;
1930 int err;
1931
1932 if (dev >= SNDRV_CARDS)
1933 return -ENODEV;
1934 if (!enable[dev]) {
1935 dev++;
1936 return -ENOENT;
1937 }
1938
1939 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1940 if (!card) {
1941 snd_printk(KERN_ERR SFX "Error creating card!\n");
1942 return -ENOMEM;
1943 }
1944
1945 err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
1946 if (err < 0) {
1947 snd_card_free(card);
1948 return err;
1949 }
1950 card->private_data = chip;
1951
1952 /* create codec instances */
1953 err = azx_codec_create(chip, model[dev], probe_mask[dev]);
1954 if (err < 0) {
1955 snd_card_free(card);
1956 return err;
1957 }
1958
1959 /* create PCM streams */
1960 err = azx_pcm_create(chip);
1961 if (err < 0) {
1962 snd_card_free(card);
1963 return err;
1964 }
1965
1966 /* create mixer controls */
1967 err = azx_mixer_create(chip);
1968 if (err < 0) {
1969 snd_card_free(card);
1970 return err;
1971 }
1972
1973 snd_card_set_dev(card, &pci->dev);
1974
1975 err = snd_card_register(card);
1976 if (err < 0) {
1977 snd_card_free(card);
1978 return err;
1979 }
1980
1981 pci_set_drvdata(pci, card);
1982 chip->running = 1;
1983 power_down_all_codecs(chip);
1984
1985 dev++;
1986 return err;
1987 }
1988
1989 static void __devexit azx_remove(struct pci_dev *pci)
1990 {
1991 snd_card_free(pci_get_drvdata(pci));
1992 pci_set_drvdata(pci, NULL);
1993 }
1994
1995 /* PCI IDs */
1996 static struct pci_device_id azx_ids[] = {
1997 { 0x8086, 0x2668, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH6 */
1998 { 0x8086, 0x27d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH7 */
1999 { 0x8086, 0x269a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ESB2 */
2000 { 0x8086, 0x284b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH8 */
2001 { 0x8086, 0x293e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
2002 { 0x8086, 0x293f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH9 */
2003 { 0x8086, 0x3a3e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH10 */
2004 { 0x8086, 0x3a6e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ICH }, /* ICH10 */
2005 { 0x8086, 0x811b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SCH }, /* SCH*/
2006 { 0x1002, 0x437b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB450 */
2007 { 0x1002, 0x4383, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATI }, /* ATI SB600 */
2008 { 0x1002, 0x793b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS600 HDMI */
2009 { 0x1002, 0x7919, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS690 HDMI */
2010 { 0x1002, 0x960f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RS780 HDMI */
2011 { 0x1002, 0xaa00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI R600 HDMI */
2012 { 0x1002, 0xaa08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV630 HDMI */
2013 { 0x1002, 0xaa10, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV610 HDMI */
2014 { 0x1002, 0xaa18, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV670 HDMI */
2015 { 0x1002, 0xaa20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV635 HDMI */
2016 { 0x1002, 0xaa28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV620 HDMI */
2017 { 0x1002, 0xaa30, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ATIHDMI }, /* ATI RV770 HDMI */
2018 { 0x1106, 0x3288, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_VIA }, /* VIA VT8251/VT8237A */
2019 { 0x1039, 0x7502, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_SIS }, /* SIS966 */
2020 { 0x10b9, 0x5461, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_ULI }, /* ULI M5461 */
2021 { 0x10de, 0x026c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP51 */
2022 { 0x10de, 0x0371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP55 */
2023 { 0x10de, 0x03e4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
2024 { 0x10de, 0x03f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP61 */
2025 { 0x10de, 0x044a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
2026 { 0x10de, 0x044b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP65 */
2027 { 0x10de, 0x055c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
2028 { 0x10de, 0x055d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP67 */
2029 { 0x10de, 0x07fc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
2030 { 0x10de, 0x07fd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP73 */
2031 { 0x10de, 0x0774, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2032 { 0x10de, 0x0775, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2033 { 0x10de, 0x0776, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2034 { 0x10de, 0x0777, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP77 */
2035 { 0x10de, 0x0ac0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2036 { 0x10de, 0x0ac1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2037 { 0x10de, 0x0ac2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2038 { 0x10de, 0x0ac3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AZX_DRIVER_NVIDIA }, /* NVIDIA MCP79 */
2039 { 0, }
2040 };
2041 MODULE_DEVICE_TABLE(pci, azx_ids);
2042
2043 /* pci_driver definition */
2044 static struct pci_driver driver = {
2045 .name = "HDA Intel",
2046 .id_table = azx_ids,
2047 .probe = azx_probe,
2048 .remove = __devexit_p(azx_remove),
2049 #ifdef CONFIG_PM
2050 .suspend = azx_suspend,
2051 .resume = azx_resume,
2052 #endif
2053 };
2054
2055 static int __init alsa_card_azx_init(void)
2056 {
2057 return pci_register_driver(&driver);
2058 }
2059
2060 static void __exit alsa_card_azx_exit(void)
2061 {
2062 pci_unregister_driver(&driver);
2063 }
2064
2065 module_init(alsa_card_azx_init)
2066 module_exit(alsa_card_azx_exit)
WRT350N Kernel Patches