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Initial commit
[wrt350n-kernel.git] / arch / x86 / kernel / setup_64.c
blobc0d8208af12a2d92e4e5bee3baf6b52dadb3efd6
1 /*
2 * Copyright (C) 1995 Linus Torvalds
3 */
4
5 /*
6 * This file handles the architecture-dependent parts of initialization
7 */
8
9 #include <linux/errno.h>
10 #include <linux/sched.h>
11 #include <linux/kernel.h>
12 #include <linux/mm.h>
13 #include <linux/stddef.h>
14 #include <linux/unistd.h>
15 #include <linux/ptrace.h>
16 #include <linux/slab.h>
17 #include <linux/user.h>
18 #include <linux/screen_info.h>
19 #include <linux/ioport.h>
20 #include <linux/delay.h>
21 #include <linux/init.h>
22 #include <linux/initrd.h>
23 #include <linux/highmem.h>
24 #include <linux/bootmem.h>
25 #include <linux/module.h>
26 #include <asm/processor.h>
27 #include <linux/console.h>
28 #include <linux/seq_file.h>
29 #include <linux/crash_dump.h>
30 #include <linux/root_dev.h>
31 #include <linux/pci.h>
32 #include <linux/efi.h>
33 #include <linux/acpi.h>
34 #include <linux/kallsyms.h>
35 #include <linux/edd.h>
36 #include <linux/mmzone.h>
37 #include <linux/kexec.h>
38 #include <linux/cpufreq.h>
39 #include <linux/dmi.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/ctype.h>
42 #include <linux/uaccess.h>
43 #include <linux/init_ohci1394_dma.h>
44
45 #include <asm/mtrr.h>
46 #include <asm/uaccess.h>
47 #include <asm/system.h>
48 #include <asm/vsyscall.h>
49 #include <asm/io.h>
50 #include <asm/smp.h>
51 #include <asm/msr.h>
52 #include <asm/desc.h>
53 #include <video/edid.h>
54 #include <asm/e820.h>
55 #include <asm/dma.h>
56 #include <asm/gart.h>
57 #include <asm/mpspec.h>
58 #include <asm/mmu_context.h>
59 #include <asm/proto.h>
60 #include <asm/setup.h>
61 #include <asm/mach_apic.h>
62 #include <asm/numa.h>
63 #include <asm/sections.h>
64 #include <asm/dmi.h>
65 #include <asm/cacheflush.h>
66 #include <asm/mce.h>
67 #include <asm/ds.h>
68 #include <asm/topology.h>
69
70 #ifdef CONFIG_PARAVIRT
71 #include <asm/paravirt.h>
72 #else
73 #define ARCH_SETUP
74 #endif
75
76 /*
77 * Machine setup..
78 */
79
80 struct cpuinfo_x86 boot_cpu_data __read_mostly;
81 EXPORT_SYMBOL(boot_cpu_data);
82
83 __u32 cleared_cpu_caps[NCAPINTS] __cpuinitdata;
84
85 unsigned long mmu_cr4_features;
86
87 /* Boot loader ID as an integer, for the benefit of proc_dointvec */
88 int bootloader_type;
89
90 unsigned long saved_video_mode;
91
92 int force_mwait __cpuinitdata;
93
94 /*
95 * Early DMI memory
96 */
97 int dmi_alloc_index;
98 char dmi_alloc_data[DMI_MAX_DATA];
99
100 /*
101 * Setup options
102 */
103 struct screen_info screen_info;
104 EXPORT_SYMBOL(screen_info);
105 struct sys_desc_table_struct {
106 unsigned short length;
107 unsigned char table[0];
108 };
109
110 struct edid_info edid_info;
111 EXPORT_SYMBOL_GPL(edid_info);
112
113 extern int root_mountflags;
114
115 char __initdata command_line[COMMAND_LINE_SIZE];
116
117 struct resource standard_io_resources[] = {
118 { .name = "dma1", .start = 0x00, .end = 0x1f,
119 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
120 { .name = "pic1", .start = 0x20, .end = 0x21,
121 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
122 { .name = "timer0", .start = 0x40, .end = 0x43,
123 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
124 { .name = "timer1", .start = 0x50, .end = 0x53,
125 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
126 { .name = "keyboard", .start = 0x60, .end = 0x6f,
127 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
128 { .name = "dma page reg", .start = 0x80, .end = 0x8f,
129 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
130 { .name = "pic2", .start = 0xa0, .end = 0xa1,
131 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
132 { .name = "dma2", .start = 0xc0, .end = 0xdf,
133 .flags = IORESOURCE_BUSY | IORESOURCE_IO },
134 { .name = "fpu", .start = 0xf0, .end = 0xff,
135 .flags = IORESOURCE_BUSY | IORESOURCE_IO }
136 };
137
138 #define IORESOURCE_RAM (IORESOURCE_BUSY | IORESOURCE_MEM)
139
140 static struct resource data_resource = {
141 .name = "Kernel data",
142 .start = 0,
143 .end = 0,
144 .flags = IORESOURCE_RAM,
145 };
146 static struct resource code_resource = {
147 .name = "Kernel code",
148 .start = 0,
149 .end = 0,
150 .flags = IORESOURCE_RAM,
151 };
152 static struct resource bss_resource = {
153 .name = "Kernel bss",
154 .start = 0,
155 .end = 0,
156 .flags = IORESOURCE_RAM,
157 };
158
159 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c);
160
161 #ifdef CONFIG_PROC_VMCORE
162 /* elfcorehdr= specifies the location of elf core header
163 * stored by the crashed kernel. This option will be passed
164 * by kexec loader to the capture kernel.
165 */
166 static int __init setup_elfcorehdr(char *arg)
167 {
168 char *end;
169 if (!arg)
170 return -EINVAL;
171 elfcorehdr_addr = memparse(arg, &end);
172 return end > arg ? 0 : -EINVAL;
173 }
174 early_param("elfcorehdr", setup_elfcorehdr);
175 #endif
176
177 #ifndef CONFIG_NUMA
178 static void __init
179 contig_initmem_init(unsigned long start_pfn, unsigned long end_pfn)
180 {
181 unsigned long bootmap_size, bootmap;
182
183 bootmap_size = bootmem_bootmap_pages(end_pfn)<<PAGE_SHIFT;
184 bootmap = find_e820_area(0, end_pfn<<PAGE_SHIFT, bootmap_size,
185 PAGE_SIZE);
186 if (bootmap == -1L)
187 panic("Cannot find bootmem map of size %ld\n", bootmap_size);
188 bootmap_size = init_bootmem(bootmap >> PAGE_SHIFT, end_pfn);
189 e820_register_active_regions(0, start_pfn, end_pfn);
190 free_bootmem_with_active_regions(0, end_pfn);
191 reserve_bootmem(bootmap, bootmap_size, BOOTMEM_DEFAULT);
192 }
193 #endif
194
195 #if defined(CONFIG_EDD) || defined(CONFIG_EDD_MODULE)
196 struct edd edd;
197 #ifdef CONFIG_EDD_MODULE
198 EXPORT_SYMBOL(edd);
199 #endif
200 /**
201 * copy_edd() - Copy the BIOS EDD information
202 * from boot_params into a safe place.
203 *
204 */
205 static inline void copy_edd(void)
206 {
207 memcpy(edd.mbr_signature, boot_params.edd_mbr_sig_buffer,
208 sizeof(edd.mbr_signature));
209 memcpy(edd.edd_info, boot_params.eddbuf, sizeof(edd.edd_info));
210 edd.mbr_signature_nr = boot_params.edd_mbr_sig_buf_entries;
211 edd.edd_info_nr = boot_params.eddbuf_entries;
212 }
213 #else
214 static inline void copy_edd(void)
215 {
216 }
217 #endif
218
219 #ifdef CONFIG_KEXEC
220 static void __init reserve_crashkernel(void)
221 {
222 unsigned long long total_mem;
223 unsigned long long crash_size, crash_base;
224 int ret;
225
226 total_mem = ((unsigned long long)max_low_pfn - min_low_pfn) << PAGE_SHIFT;
227
228 ret = parse_crashkernel(boot_command_line, total_mem,
229 &crash_size, &crash_base);
230 if (ret == 0 && crash_size) {
231 if (crash_base <= 0) {
232 printk(KERN_INFO "crashkernel reservation failed - "
233 "you have to specify a base address\n");
234 return;
235 }
236
237 if (reserve_bootmem(crash_base, crash_size,
238 BOOTMEM_EXCLUSIVE) < 0) {
239 printk(KERN_INFO "crashkernel reservation failed - "
240 "memory is in use\n");
241 return;
242 }
243
244 printk(KERN_INFO "Reserving %ldMB of memory at %ldMB "
245 "for crashkernel (System RAM: %ldMB)\n",
246 (unsigned long)(crash_size >> 20),
247 (unsigned long)(crash_base >> 20),
248 (unsigned long)(total_mem >> 20));
249 crashk_res.start = crash_base;
250 crashk_res.end = crash_base + crash_size - 1;
251 }
252 }
253 #else
254 static inline void __init reserve_crashkernel(void)
255 {}
256 #endif
257
258 /* Overridden in paravirt.c if CONFIG_PARAVIRT */
259 void __attribute__((weak)) __init memory_setup(void)
260 {
261 machine_specific_memory_setup();
262 }
263
264 /*
265 * setup_arch - architecture-specific boot-time initializations
266 *
267 * Note: On x86_64, fixmaps are ready for use even before this is called.
268 */
269 void __init setup_arch(char **cmdline_p)
270 {
271 unsigned i;
272
273 printk(KERN_INFO "Command line: %s\n", boot_command_line);
274
275 ROOT_DEV = old_decode_dev(boot_params.hdr.root_dev);
276 screen_info = boot_params.screen_info;
277 edid_info = boot_params.edid_info;
278 saved_video_mode = boot_params.hdr.vid_mode;
279 bootloader_type = boot_params.hdr.type_of_loader;
280
281 #ifdef CONFIG_BLK_DEV_RAM
282 rd_image_start = boot_params.hdr.ram_size & RAMDISK_IMAGE_START_MASK;
283 rd_prompt = ((boot_params.hdr.ram_size & RAMDISK_PROMPT_FLAG) != 0);
284 rd_doload = ((boot_params.hdr.ram_size & RAMDISK_LOAD_FLAG) != 0);
285 #endif
286 #ifdef CONFIG_EFI
287 if (!strncmp((char *)&boot_params.efi_info.efi_loader_signature,
288 "EL64", 4))
289 efi_enabled = 1;
290 #endif
291
292 ARCH_SETUP
293
294 memory_setup();
295 copy_edd();
296
297 if (!boot_params.hdr.root_flags)
298 root_mountflags &= ~MS_RDONLY;
299 init_mm.start_code = (unsigned long) &_text;
300 init_mm.end_code = (unsigned long) &_etext;
301 init_mm.end_data = (unsigned long) &_edata;
302 init_mm.brk = (unsigned long) &_end;
303
304 code_resource.start = virt_to_phys(&_text);
305 code_resource.end = virt_to_phys(&_etext)-1;
306 data_resource.start = virt_to_phys(&_etext);
307 data_resource.end = virt_to_phys(&_edata)-1;
308 bss_resource.start = virt_to_phys(&__bss_start);
309 bss_resource.end = virt_to_phys(&__bss_stop)-1;
310
311 early_identify_cpu(&boot_cpu_data);
312
313 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
314 *cmdline_p = command_line;
315
316 parse_early_param();
317
318 #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
319 if (init_ohci1394_dma_early)
320 init_ohci1394_dma_on_all_controllers();
321 #endif
322
323 finish_e820_parsing();
324
325 early_gart_iommu_check();
326
327 e820_register_active_regions(0, 0, -1UL);
328 /*
329 * partially used pages are not usable - thus
330 * we are rounding upwards:
331 */
332 end_pfn = e820_end_of_ram();
333 /* update e820 for memory not covered by WB MTRRs */
334 mtrr_bp_init();
335 if (mtrr_trim_uncached_memory(end_pfn)) {
336 e820_register_active_regions(0, 0, -1UL);
337 end_pfn = e820_end_of_ram();
338 }
339
340 num_physpages = end_pfn;
341
342 check_efer();
343
344 init_memory_mapping(0, (end_pfn_map << PAGE_SHIFT));
345 if (efi_enabled)
346 efi_init();
347
348 dmi_scan_machine();
349
350 io_delay_init();
351
352 #ifdef CONFIG_SMP
353 /* setup to use the early static init tables during kernel startup */
354 x86_cpu_to_apicid_early_ptr = (void *)x86_cpu_to_apicid_init;
355 x86_bios_cpu_apicid_early_ptr = (void *)x86_bios_cpu_apicid_init;
356 #ifdef CONFIG_NUMA
357 x86_cpu_to_node_map_early_ptr = (void *)x86_cpu_to_node_map_init;
358 #endif
359 #endif
360
361 #ifdef CONFIG_ACPI
362 /*
363 * Initialize the ACPI boot-time table parser (gets the RSDP and SDT).
364 * Call this early for SRAT node setup.
365 */
366 acpi_boot_table_init();
367 #endif
368
369 /* How many end-of-memory variables you have, grandma! */
370 max_low_pfn = end_pfn;
371 max_pfn = end_pfn;
372 high_memory = (void *)__va(end_pfn * PAGE_SIZE - 1) + 1;
373
374 /* Remove active ranges so rediscovery with NUMA-awareness happens */
375 remove_all_active_ranges();
376
377 #ifdef CONFIG_ACPI_NUMA
378 /*
379 * Parse SRAT to discover nodes.
380 */
381 acpi_numa_init();
382 #endif
383
384 #ifdef CONFIG_NUMA
385 numa_initmem_init(0, end_pfn);
386 #else
387 contig_initmem_init(0, end_pfn);
388 #endif
389
390 early_res_to_bootmem();
391
392 #ifdef CONFIG_ACPI_SLEEP
393 /*
394 * Reserve low memory region for sleep support.
395 */
396 acpi_reserve_bootmem();
397 #endif
398
399 if (efi_enabled)
400 efi_reserve_bootmem();
401
402 /*
403 * Find and reserve possible boot-time SMP configuration:
404 */
405 find_smp_config();
406 #ifdef CONFIG_BLK_DEV_INITRD
407 if (boot_params.hdr.type_of_loader && boot_params.hdr.ramdisk_image) {
408 unsigned long ramdisk_image = boot_params.hdr.ramdisk_image;
409 unsigned long ramdisk_size = boot_params.hdr.ramdisk_size;
410 unsigned long ramdisk_end = ramdisk_image + ramdisk_size;
411 unsigned long end_of_mem = end_pfn << PAGE_SHIFT;
412
413 if (ramdisk_end <= end_of_mem) {
414 reserve_bootmem_generic(ramdisk_image, ramdisk_size);
415 initrd_start = ramdisk_image + PAGE_OFFSET;
416 initrd_end = initrd_start+ramdisk_size;
417 } else {
418 /* Assumes everything on node 0 */
419 free_bootmem(ramdisk_image, ramdisk_size);
420 printk(KERN_ERR "initrd extends beyond end of memory "
421 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
422 ramdisk_end, end_of_mem);
423 initrd_start = 0;
424 }
425 }
426 #endif
427 reserve_crashkernel();
428 paging_init();
429 map_vsyscall();
430
431 early_quirks();
432
433 #ifdef CONFIG_ACPI
434 /*
435 * Read APIC and some other early information from ACPI tables.
436 */
437 acpi_boot_init();
438 #endif
439
440 init_cpu_to_node();
441
442 /*
443 * get boot-time SMP configuration:
444 */
445 if (smp_found_config)
446 get_smp_config();
447 init_apic_mappings();
448 ioapic_init_mappings();
449
450 /*
451 * We trust e820 completely. No explicit ROM probing in memory.
452 */
453 e820_reserve_resources(&code_resource, &data_resource, &bss_resource);
454 e820_mark_nosave_regions();
455
456 /* request I/O space for devices used on all i[345]86 PCs */
457 for (i = 0; i < ARRAY_SIZE(standard_io_resources); i++)
458 request_resource(&ioport_resource, &standard_io_resources[i]);
459
460 e820_setup_gap();
461
462 #ifdef CONFIG_VT
463 #if defined(CONFIG_VGA_CONSOLE)
464 if (!efi_enabled || (efi_mem_type(0xa0000) != EFI_CONVENTIONAL_MEMORY))
465 conswitchp = &vga_con;
466 #elif defined(CONFIG_DUMMY_CONSOLE)
467 conswitchp = &dummy_con;
468 #endif
469 #endif
470 }
471
472 static int __cpuinit get_model_name(struct cpuinfo_x86 *c)
473 {
474 unsigned int *v;
475
476 if (c->extended_cpuid_level < 0x80000004)
477 return 0;
478
479 v = (unsigned int *) c->x86_model_id;
480 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
481 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
482 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
483 c->x86_model_id[48] = 0;
484 return 1;
485 }
486
487
488 static void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
489 {
490 unsigned int n, dummy, eax, ebx, ecx, edx;
491
492 n = c->extended_cpuid_level;
493
494 if (n >= 0x80000005) {
495 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
496 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), "
497 "D cache %dK (%d bytes/line)\n",
498 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
499 c->x86_cache_size = (ecx>>24) + (edx>>24);
500 /* On K8 L1 TLB is inclusive, so don't count it */
501 c->x86_tlbsize = 0;
502 }
503
504 if (n >= 0x80000006) {
505 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
506 ecx = cpuid_ecx(0x80000006);
507 c->x86_cache_size = ecx >> 16;
508 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
509
510 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
511 c->x86_cache_size, ecx & 0xFF);
512 }
513 if (n >= 0x80000008) {
514 cpuid(0x80000008, &eax, &dummy, &dummy, &dummy);
515 c->x86_virt_bits = (eax >> 8) & 0xff;
516 c->x86_phys_bits = eax & 0xff;
517 }
518 }
519
520 #ifdef CONFIG_NUMA
521 static int nearby_node(int apicid)
522 {
523 int i, node;
524
525 for (i = apicid - 1; i >= 0; i--) {
526 node = apicid_to_node[i];
527 if (node != NUMA_NO_NODE && node_online(node))
528 return node;
529 }
530 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
531 node = apicid_to_node[i];
532 if (node != NUMA_NO_NODE && node_online(node))
533 return node;
534 }
535 return first_node(node_online_map); /* Shouldn't happen */
536 }
537 #endif
538
539 /*
540 * On a AMD dual core setup the lower bits of the APIC id distingush the cores.
541 * Assumes number of cores is a power of two.
542 */
543 static void __cpuinit amd_detect_cmp(struct cpuinfo_x86 *c)
544 {
545 #ifdef CONFIG_SMP
546 unsigned bits;
547 #ifdef CONFIG_NUMA
548 int cpu = smp_processor_id();
549 int node = 0;
550 unsigned apicid = hard_smp_processor_id();
551 #endif
552 bits = c->x86_coreid_bits;
553
554 /* Low order bits define the core id (index of core in socket) */
555 c->cpu_core_id = c->phys_proc_id & ((1 << bits)-1);
556 /* Convert the APIC ID into the socket ID */
557 c->phys_proc_id = phys_pkg_id(bits);
558
559 #ifdef CONFIG_NUMA
560 node = c->phys_proc_id;
561 if (apicid_to_node[apicid] != NUMA_NO_NODE)
562 node = apicid_to_node[apicid];
563 if (!node_online(node)) {
564 /* Two possibilities here:
565 - The CPU is missing memory and no node was created.
566 In that case try picking one from a nearby CPU
567 - The APIC IDs differ from the HyperTransport node IDs
568 which the K8 northbridge parsing fills in.
569 Assume they are all increased by a constant offset,
570 but in the same order as the HT nodeids.
571 If that doesn't result in a usable node fall back to the
572 path for the previous case. */
573
574 int ht_nodeid = apicid - (cpu_data(0).phys_proc_id << bits);
575
576 if (ht_nodeid >= 0 &&
577 apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
578 node = apicid_to_node[ht_nodeid];
579 /* Pick a nearby node */
580 if (!node_online(node))
581 node = nearby_node(apicid);
582 }
583 numa_set_node(cpu, node);
584
585 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
586 #endif
587 #endif
588 }
589
590 static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
591 {
592 #ifdef CONFIG_SMP
593 unsigned bits, ecx;
594
595 /* Multi core CPU? */
596 if (c->extended_cpuid_level < 0x80000008)
597 return;
598
599 ecx = cpuid_ecx(0x80000008);
600
601 c->x86_max_cores = (ecx & 0xff) + 1;
602
603 /* CPU telling us the core id bits shift? */
604 bits = (ecx >> 12) & 0xF;
605
606 /* Otherwise recompute */
607 if (bits == 0) {
608 while ((1 << bits) < c->x86_max_cores)
609 bits++;
610 }
611
612 c->x86_coreid_bits = bits;
613
614 #endif
615 }
616
617 #define ENABLE_C1E_MASK 0x18000000
618 #define CPUID_PROCESSOR_SIGNATURE 1
619 #define CPUID_XFAM 0x0ff00000
620 #define CPUID_XFAM_K8 0x00000000
621 #define CPUID_XFAM_10H 0x00100000
622 #define CPUID_XFAM_11H 0x00200000
623 #define CPUID_XMOD 0x000f0000
624 #define CPUID_XMOD_REV_F 0x00040000
625
626 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
627 static __cpuinit int amd_apic_timer_broken(void)
628 {
629 u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
630
631 switch (eax & CPUID_XFAM) {
632 case CPUID_XFAM_K8:
633 if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
634 break;
635 case CPUID_XFAM_10H:
636 case CPUID_XFAM_11H:
637 rdmsr(MSR_K8_ENABLE_C1E, lo, hi);
638 if (lo & ENABLE_C1E_MASK)
639 return 1;
640 break;
641 default:
642 /* err on the side of caution */
643 return 1;
644 }
645 return 0;
646 }
647
648 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c)
649 {
650 early_init_amd_mc(c);
651
652 /* c->x86_power is 8000_0007 edx. Bit 8 is constant TSC */
653 if (c->x86_power & (1<<8))
654 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
655 }
656
657 static void __cpuinit init_amd(struct cpuinfo_x86 *c)
658 {
659 unsigned level;
660
661 #ifdef CONFIG_SMP
662 unsigned long value;
663
664 /*
665 * Disable TLB flush filter by setting HWCR.FFDIS on K8
666 * bit 6 of msr C001_0015
667 *
668 * Errata 63 for SH-B3 steppings
669 * Errata 122 for all steppings (F+ have it disabled by default)
670 */
671 if (c->x86 == 15) {
672 rdmsrl(MSR_K8_HWCR, value);
673 value |= 1 << 6;
674 wrmsrl(MSR_K8_HWCR, value);
675 }
676 #endif
677
678 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;
679 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */
680 clear_bit(0*32+31, (unsigned long *)&c->x86_capability);
681
682 /* On C+ stepping K8 rep microcode works well for copy/memset */
683 level = cpuid_eax(1);
684 if (c->x86 == 15 && ((level >= 0x0f48 && level < 0x0f50) ||
685 level >= 0x0f58))
686 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
687 if (c->x86 == 0x10 || c->x86 == 0x11)
688 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
689
690 /* Enable workaround for FXSAVE leak */
691 if (c->x86 >= 6)
692 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK);
693
694 level = get_model_name(c);
695 if (!level) {
696 switch (c->x86) {
697 case 15:
698 /* Should distinguish Models here, but this is only
699 a fallback anyways. */
700 strcpy(c->x86_model_id, "Hammer");
701 break;
702 }
703 }
704 display_cacheinfo(c);
705
706 /* Multi core CPU? */
707 if (c->extended_cpuid_level >= 0x80000008)
708 amd_detect_cmp(c);
709
710 if (c->extended_cpuid_level >= 0x80000006 &&
711 (cpuid_edx(0x80000006) & 0xf000))
712 num_cache_leaves = 4;
713 else
714 num_cache_leaves = 3;
715
716 if (c->x86 == 0xf || c->x86 == 0x10 || c->x86 == 0x11)
717 set_cpu_cap(c, X86_FEATURE_K8);
718
719 /* MFENCE stops RDTSC speculation */
720 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
721
722 if (amd_apic_timer_broken())
723 disable_apic_timer = 1;
724 }
725
726 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
727 {
728 #ifdef CONFIG_SMP
729 u32 eax, ebx, ecx, edx;
730 int index_msb, core_bits;
731
732 cpuid(1, &eax, &ebx, &ecx, &edx);
733
734
735 if (!cpu_has(c, X86_FEATURE_HT))
736 return;
737 if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
738 goto out;
739
740 smp_num_siblings = (ebx & 0xff0000) >> 16;
741
742 if (smp_num_siblings == 1) {
743 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
744 } else if (smp_num_siblings > 1) {
745
746 if (smp_num_siblings > NR_CPUS) {
747 printk(KERN_WARNING "CPU: Unsupported number of "
748 "siblings %d", smp_num_siblings);
749 smp_num_siblings = 1;
750 return;
751 }
752
753 index_msb = get_count_order(smp_num_siblings);
754 c->phys_proc_id = phys_pkg_id(index_msb);
755
756 smp_num_siblings = smp_num_siblings / c->x86_max_cores;
757
758 index_msb = get_count_order(smp_num_siblings);
759
760 core_bits = get_count_order(c->x86_max_cores);
761
762 c->cpu_core_id = phys_pkg_id(index_msb) &
763 ((1 << core_bits) - 1);
764 }
765 out:
766 if ((c->x86_max_cores * smp_num_siblings) > 1) {
767 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
768 c->phys_proc_id);
769 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
770 c->cpu_core_id);
771 }
772
773 #endif
774 }
775
776 /*
777 * find out the number of processor cores on the die
778 */
779 static int __cpuinit intel_num_cpu_cores(struct cpuinfo_x86 *c)
780 {
781 unsigned int eax, t;
782
783 if (c->cpuid_level < 4)
784 return 1;
785
786 cpuid_count(4, 0, &eax, &t, &t, &t);
787
788 if (eax & 0x1f)
789 return ((eax >> 26) + 1);
790 else
791 return 1;
792 }
793
794 static void srat_detect_node(void)
795 {
796 #ifdef CONFIG_NUMA
797 unsigned node;
798 int cpu = smp_processor_id();
799 int apicid = hard_smp_processor_id();
800
801 /* Don't do the funky fallback heuristics the AMD version employs
802 for now. */
803 node = apicid_to_node[apicid];
804 if (node == NUMA_NO_NODE)
805 node = first_node(node_online_map);
806 numa_set_node(cpu, node);
807
808 printk(KERN_INFO "CPU %d/%x -> Node %d\n", cpu, apicid, node);
809 #endif
810 }
811
812 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
813 {
814 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
815 (c->x86 == 0x6 && c->x86_model >= 0x0e))
816 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
817 }
818
819 static void __cpuinit init_intel(struct cpuinfo_x86 *c)
820 {
821 /* Cache sizes */
822 unsigned n;
823
824 init_intel_cacheinfo(c);
825 if (c->cpuid_level > 9) {
826 unsigned eax = cpuid_eax(10);
827 /* Check for version and the number of counters */
828 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
829 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
830 }
831
832 if (cpu_has_ds) {
833 unsigned int l1, l2;
834 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
835 if (!(l1 & (1<<11)))
836 set_cpu_cap(c, X86_FEATURE_BTS);
837 if (!(l1 & (1<<12)))
838 set_cpu_cap(c, X86_FEATURE_PEBS);
839 }
840
841
842 if (cpu_has_bts)
843 ds_init_intel(c);
844
845 n = c->extended_cpuid_level;
846 if (n >= 0x80000008) {
847 unsigned eax = cpuid_eax(0x80000008);
848 c->x86_virt_bits = (eax >> 8) & 0xff;
849 c->x86_phys_bits = eax & 0xff;
850 /* CPUID workaround for Intel 0F34 CPU */
851 if (c->x86_vendor == X86_VENDOR_INTEL &&
852 c->x86 == 0xF && c->x86_model == 0x3 &&
853 c->x86_mask == 0x4)
854 c->x86_phys_bits = 36;
855 }
856
857 if (c->x86 == 15)
858 c->x86_cache_alignment = c->x86_clflush_size * 2;
859 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
860 (c->x86 == 0x6 && c->x86_model >= 0x0e))
861 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
862 if (c->x86 == 6)
863 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
864 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
865 c->x86_max_cores = intel_num_cpu_cores(c);
866
867 srat_detect_node();
868 }
869
870 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c)
871 {
872 char *v = c->x86_vendor_id;
873
874 if (!strcmp(v, "AuthenticAMD"))
875 c->x86_vendor = X86_VENDOR_AMD;
876 else if (!strcmp(v, "GenuineIntel"))
877 c->x86_vendor = X86_VENDOR_INTEL;
878 else
879 c->x86_vendor = X86_VENDOR_UNKNOWN;
880 }
881
882 /* Do some early cpuid on the boot CPU to get some parameter that are
883 needed before check_bugs. Everything advanced is in identify_cpu
884 below. */
885 static void __cpuinit early_identify_cpu(struct cpuinfo_x86 *c)
886 {
887 u32 tfms, xlvl;
888
889 c->loops_per_jiffy = loops_per_jiffy;
890 c->x86_cache_size = -1;
891 c->x86_vendor = X86_VENDOR_UNKNOWN;
892 c->x86_model = c->x86_mask = 0; /* So far unknown... */
893 c->x86_vendor_id[0] = '\0'; /* Unset */
894 c->x86_model_id[0] = '\0'; /* Unset */
895 c->x86_clflush_size = 64;
896 c->x86_cache_alignment = c->x86_clflush_size;
897 c->x86_max_cores = 1;
898 c->x86_coreid_bits = 0;
899 c->extended_cpuid_level = 0;
900 memset(&c->x86_capability, 0, sizeof c->x86_capability);
901
902 /* Get vendor name */
903 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
904 (unsigned int *)&c->x86_vendor_id[0],
905 (unsigned int *)&c->x86_vendor_id[8],
906 (unsigned int *)&c->x86_vendor_id[4]);
907
908 get_cpu_vendor(c);
909
910 /* Initialize the standard set of capabilities */
911 /* Note that the vendor-specific code below might override */
912
913 /* Intel-defined flags: level 0x00000001 */
914 if (c->cpuid_level >= 0x00000001) {
915 __u32 misc;
916 cpuid(0x00000001, &tfms, &misc, &c->x86_capability[4],
917 &c->x86_capability[0]);
918 c->x86 = (tfms >> 8) & 0xf;
919 c->x86_model = (tfms >> 4) & 0xf;
920 c->x86_mask = tfms & 0xf;
921 if (c->x86 == 0xf)
922 c->x86 += (tfms >> 20) & 0xff;
923 if (c->x86 >= 0x6)
924 c->x86_model += ((tfms >> 16) & 0xF) << 4;
925 if (c->x86_capability[0] & (1<<19))
926 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
927 } else {
928 /* Have CPUID level 0 only - unheard of */
929 c->x86 = 4;
930 }
931
932 #ifdef CONFIG_SMP
933 c->phys_proc_id = (cpuid_ebx(1) >> 24) & 0xff;
934 #endif
935 /* AMD-defined flags: level 0x80000001 */
936 xlvl = cpuid_eax(0x80000000);
937 c->extended_cpuid_level = xlvl;
938 if ((xlvl & 0xffff0000) == 0x80000000) {
939 if (xlvl >= 0x80000001) {
940 c->x86_capability[1] = cpuid_edx(0x80000001);
941 c->x86_capability[6] = cpuid_ecx(0x80000001);
942 }
943 if (xlvl >= 0x80000004)
944 get_model_name(c); /* Default name */
945 }
946
947 /* Transmeta-defined flags: level 0x80860001 */
948 xlvl = cpuid_eax(0x80860000);
949 if ((xlvl & 0xffff0000) == 0x80860000) {
950 /* Don't set x86_cpuid_level here for now to not confuse. */
951 if (xlvl >= 0x80860001)
952 c->x86_capability[2] = cpuid_edx(0x80860001);
953 }
954
955 c->extended_cpuid_level = cpuid_eax(0x80000000);
956 if (c->extended_cpuid_level >= 0x80000007)
957 c->x86_power = cpuid_edx(0x80000007);
958
959 switch (c->x86_vendor) {
960 case X86_VENDOR_AMD:
961 early_init_amd(c);
962 break;
963 case X86_VENDOR_INTEL:
964 early_init_intel(c);
965 break;
966 }
967
968 }
969
970 /*
971 * This does the hard work of actually picking apart the CPU stuff...
972 */
973 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
974 {
975 int i;
976
977 early_identify_cpu(c);
978
979 init_scattered_cpuid_features(c);
980
981 c->apicid = phys_pkg_id(0);
982
983 /*
984 * Vendor-specific initialization. In this section we
985 * canonicalize the feature flags, meaning if there are
986 * features a certain CPU supports which CPUID doesn't
987 * tell us, CPUID claiming incorrect flags, or other bugs,
988 * we handle them here.
989 *
990 * At the end of this section, c->x86_capability better
991 * indicate the features this CPU genuinely supports!
992 */
993 switch (c->x86_vendor) {
994 case X86_VENDOR_AMD:
995 init_amd(c);
996 break;
997
998 case X86_VENDOR_INTEL:
999 init_intel(c);
1000 break;
1001
1002 case X86_VENDOR_UNKNOWN:
1003 default:
1004 display_cacheinfo(c);
1005 break;
1006 }
1007
1008 detect_ht(c);
1009
1010 /*
1011 * On SMP, boot_cpu_data holds the common feature set between
1012 * all CPUs; so make sure that we indicate which features are
1013 * common between the CPUs. The first time this routine gets
1014 * executed, c == &boot_cpu_data.
1015 */
1016 if (c != &boot_cpu_data) {
1017 /* AND the already accumulated flags with these */
1018 for (i = 0; i < NCAPINTS; i++)
1019 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1020 }
1021
1022 /* Clear all flags overriden by options */
1023 for (i = 0; i < NCAPINTS; i++)
1024 c->x86_capability[i] ^= cleared_cpu_caps[i];
1025
1026 #ifdef CONFIG_X86_MCE
1027 mcheck_init(c);
1028 #endif
1029 select_idle_routine(c);
1030
1031 if (c != &boot_cpu_data)
1032 mtrr_ap_init();
1033 #ifdef CONFIG_NUMA
1034 numa_add_cpu(smp_processor_id());
1035 #endif
1036
1037 }
1038
1039 static __init int setup_noclflush(char *arg)
1040 {
1041 setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1042 return 1;
1043 }
1044 __setup("noclflush", setup_noclflush);
1045
1046 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
1047 {
1048 if (c->x86_model_id[0])
1049 printk(KERN_INFO "%s", c->x86_model_id);
1050
1051 if (c->x86_mask || c->cpuid_level >= 0)
1052 printk(KERN_CONT " stepping %02x\n", c->x86_mask);
1053 else
1054 printk(KERN_CONT "\n");
1055 }
1056
1057 static __init int setup_disablecpuid(char *arg)
1058 {
1059 int bit;
1060 if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1061 setup_clear_cpu_cap(bit);
1062 else
1063 return 0;
1064 return 1;
1065 }
1066 __setup("clearcpuid=", setup_disablecpuid);
1067
1068 /*
1069 * Get CPU information for use by the procfs.
1070 */
1071
1072 static int show_cpuinfo(struct seq_file *m, void *v)
1073 {
1074 struct cpuinfo_x86 *c = v;
1075 int cpu = 0, i;
1076
1077 #ifdef CONFIG_SMP
1078 cpu = c->cpu_index;
1079 #endif
1080
1081 seq_printf(m, "processor\t: %u\n"
1082 "vendor_id\t: %s\n"
1083 "cpu family\t: %d\n"
1084 "model\t\t: %d\n"
1085 "model name\t: %s\n",
1086 (unsigned)cpu,
1087 c->x86_vendor_id[0] ? c->x86_vendor_id : "unknown",
1088 c->x86,
1089 (int)c->x86_model,
1090 c->x86_model_id[0] ? c->x86_model_id : "unknown");
1091
1092 if (c->x86_mask || c->cpuid_level >= 0)
1093 seq_printf(m, "stepping\t: %d\n", c->x86_mask);
1094 else
1095 seq_printf(m, "stepping\t: unknown\n");
1096
1097 if (cpu_has(c, X86_FEATURE_TSC)) {
1098 unsigned int freq = cpufreq_quick_get((unsigned)cpu);
1099
1100 if (!freq)
1101 freq = cpu_khz;
1102 seq_printf(m, "cpu MHz\t\t: %u.%03u\n",
1103 freq / 1000, (freq % 1000));
1104 }
1105
1106 /* Cache size */
1107 if (c->x86_cache_size >= 0)
1108 seq_printf(m, "cache size\t: %d KB\n", c->x86_cache_size);
1109
1110 #ifdef CONFIG_SMP
1111 if (smp_num_siblings * c->x86_max_cores > 1) {
1112 seq_printf(m, "physical id\t: %d\n", c->phys_proc_id);
1113 seq_printf(m, "siblings\t: %d\n",
1114 cpus_weight(per_cpu(cpu_core_map, cpu)));
1115 seq_printf(m, "core id\t\t: %d\n", c->cpu_core_id);
1116 seq_printf(m, "cpu cores\t: %d\n", c->booted_cores);
1117 }
1118 #endif
1119
1120 seq_printf(m,
1121 "fpu\t\t: yes\n"
1122 "fpu_exception\t: yes\n"
1123 "cpuid level\t: %d\n"
1124 "wp\t\t: yes\n"
1125 "flags\t\t:",
1126 c->cpuid_level);
1127
1128 for (i = 0; i < 32*NCAPINTS; i++)
1129 if (cpu_has(c, i) && x86_cap_flags[i] != NULL)
1130 seq_printf(m, " %s", x86_cap_flags[i]);
1131
1132 seq_printf(m, "\nbogomips\t: %lu.%02lu\n",
1133 c->loops_per_jiffy/(500000/HZ),
1134 (c->loops_per_jiffy/(5000/HZ)) % 100);
1135
1136 if (c->x86_tlbsize > 0)
1137 seq_printf(m, "TLB size\t: %d 4K pages\n", c->x86_tlbsize);
1138 seq_printf(m, "clflush size\t: %d\n", c->x86_clflush_size);
1139 seq_printf(m, "cache_alignment\t: %d\n", c->x86_cache_alignment);
1140
1141 seq_printf(m, "address sizes\t: %u bits physical, %u bits virtual\n",
1142 c->x86_phys_bits, c->x86_virt_bits);
1143
1144 seq_printf(m, "power management:");
1145 for (i = 0; i < 32; i++) {
1146 if (c->x86_power & (1 << i)) {
1147 if (i < ARRAY_SIZE(x86_power_flags) &&
1148 x86_power_flags[i])
1149 seq_printf(m, "%s%s",
1150 x86_power_flags[i][0]?" ":"",
1151 x86_power_flags[i]);
1152 else
1153 seq_printf(m, " [%d]", i);
1154 }
1155 }
1156
1157 seq_printf(m, "\n\n");
1158
1159 return 0;
1160 }
1161
1162 static void *c_start(struct seq_file *m, loff_t *pos)
1163 {
1164 if (*pos == 0) /* just in case, cpu 0 is not the first */
1165 *pos = first_cpu(cpu_online_map);
1166 if ((*pos) < NR_CPUS && cpu_online(*pos))
1167 return &cpu_data(*pos);
1168 return NULL;
1169 }
1170
1171 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
1172 {
1173 *pos = next_cpu(*pos, cpu_online_map);
1174 return c_start(m, pos);
1175 }
1176
1177 static void c_stop(struct seq_file *m, void *v)
1178 {
1179 }
1180
1181 const struct seq_operations cpuinfo_op = {
1182 .start = c_start,
1183 .next = c_next,
1184 .stop = c_stop,
1185 .show = show_cpuinfo,
1186 };
WRT350N Kernel Patches