| blob | 91a689eca43d98a055afb2d329910292305b0e02 |
1 /*
2 * arch/xtensa/kernel/entry.S
3 *
4 * Low-level exception handling
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 2004-2007 by Tensilica Inc.
11 *
12 * Chris Zankel <chris@zankel.net>
13 *
14 */
16 #include <linux/linkage.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/processor.h>
19 #include <asm/thread_info.h>
20 #include <asm/uaccess.h>
21 #include <asm/unistd.h>
22 #include <asm/ptrace.h>
23 #include <asm/current.h>
24 #include <asm/pgtable.h>
25 #include <asm/page.h>
26 #include <asm/signal.h>
27 #include <asm/tlbflush.h>
29 /* Unimplemented features. */
31 #undef SIGNAL_HANDLING_IN_DOUBLE_EXCEPTION
32 #undef KERNEL_STACK_OVERFLOW_CHECK
33 #undef PREEMPTIBLE_KERNEL
34 #undef ALLOCA_EXCEPTION_IN_IRAM
36 /* Not well tested.
37 *
38 * - fast_coprocessor
39 */
41 /*
42 * Macro to find first bit set in WINDOWBASE from the left + 1
43 *
44 * 100....0 -> 1
45 * 010....0 -> 2
46 * 000....1 -> WSBITS
47 */
49 .macro ffs_ws bit mask
51 #if XCHAL_HAVE_NSA
52 nsau \bit, \mask # 32-WSBITS ... 31 (32 iff 0)
53 addi \bit, \bit, WSBITS - 32 + 1 # uppest bit set -> return 1
54 #else
55 movi \bit, WSBITS
56 #if WSBITS > 16
57 _bltui \mask, 0x10000, 99f
58 addi \bit, \bit, -16
59 extui \mask, \mask, 16, 16
60 #endif
61 #if WSBITS > 8
62 99: _bltui \mask, 0x100, 99f
63 addi \bit, \bit, -8
64 srli \mask, \mask, 8
65 #endif
66 99: _bltui \mask, 0x10, 99f
67 addi \bit, \bit, -4
68 srli \mask, \mask, 4
69 99: _bltui \mask, 0x4, 99f
70 addi \bit, \bit, -2
71 srli \mask, \mask, 2
72 99: _bltui \mask, 0x2, 99f
73 addi \bit, \bit, -1
74 99:
76 #endif
77 .endm
79 /* ----------------- DEFAULT FIRST LEVEL EXCEPTION HANDLERS ----------------- */
81 /*
82 * First-level exception handler for user exceptions.
83 * Save some special registers, extra states and all registers in the AR
84 * register file that were in use in the user task, and jump to the common
85 * exception code.
86 * We save SAR (used to calculate WMASK), and WB and WS (we don't have to
87 * save them for kernel exceptions).
88 *
89 * Entry condition for user_exception:
90 *
91 * a0: trashed, original value saved on stack (PT_AREG0)
92 * a1: a1
93 * a2: new stack pointer, original value in depc
94 * a3: dispatch table
95 * depc: a2, original value saved on stack (PT_DEPC)
96 * excsave1: a3
97 *
98 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
99 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
100 *
101 * Entry condition for _user_exception:
102 *
103 * a0-a3 and depc have been saved to PT_AREG0...PT_AREG3 and PT_DEPC
104 * excsave has been restored, and
105 * stack pointer (a1) has been set.
106 *
107 * Note: _user_exception might be at an odd adress. Don't use call0..call12
108 */
110 ENTRY(user_exception)
112 /* Save a2, a3, and depc, restore excsave_1 and set SP. */
114 xsr a3, EXCSAVE_1
115 rsr a0, DEPC
116 s32i a1, a2, PT_AREG1
117 s32i a0, a2, PT_AREG2
118 s32i a3, a2, PT_AREG3
119 mov a1, a2
121 .globl _user_exception
122 _user_exception:
124 /* Save SAR and turn off single stepping */
126 movi a2, 0
127 rsr a3, SAR
128 xsr a2, ICOUNTLEVEL
129 s32i a3, a1, PT_SAR
130 s32i a2, a1, PT_ICOUNTLEVEL
132 /* Rotate ws so that the current windowbase is at bit0. */
133 /* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */
135 rsr a2, WINDOWBASE
136 rsr a3, WINDOWSTART
137 ssr a2
138 s32i a2, a1, PT_WINDOWBASE
139 s32i a3, a1, PT_WINDOWSTART
140 slli a2, a3, 32-WSBITS
141 src a2, a3, a2
142 srli a2, a2, 32-WSBITS
143 s32i a2, a1, PT_WMASK # needed for restoring registers
145 /* Save only live registers. */
147 _bbsi.l a2, 1, 1f
148 s32i a4, a1, PT_AREG4
149 s32i a5, a1, PT_AREG5
150 s32i a6, a1, PT_AREG6
151 s32i a7, a1, PT_AREG7
152 _bbsi.l a2, 2, 1f
153 s32i a8, a1, PT_AREG8
154 s32i a9, a1, PT_AREG9
155 s32i a10, a1, PT_AREG10
156 s32i a11, a1, PT_AREG11
157 _bbsi.l a2, 3, 1f
158 s32i a12, a1, PT_AREG12
159 s32i a13, a1, PT_AREG13
160 s32i a14, a1, PT_AREG14
161 s32i a15, a1, PT_AREG15
162 _bnei a2, 1, 1f # only one valid frame?
164 /* Only one valid frame, skip saving regs. */
166 j 2f
168 /* Save the remaining registers.
169 * We have to save all registers up to the first '1' from
170 * the right, except the current frame (bit 0).
171 * Assume a2 is: 001001000110001
172 * All register frames starting from the top field to the marked '1'
173 * must be saved.
174 */
176 1: addi a3, a2, -1 # eliminate '1' in bit 0: yyyyxxww0
177 neg a3, a3 # yyyyxxww0 -> YYYYXXWW1+1
178 and a3, a3, a2 # max. only one bit is set
180 /* Find number of frames to save */
182 ffs_ws a0, a3 # number of frames to the '1' from left
184 /* Store information into WMASK:
185 * bits 0..3: xxx1 masked lower 4 bits of the rotated windowstart,
186 * bits 4...: number of valid 4-register frames
187 */
189 slli a3, a0, 4 # number of frames to save in bits 8..4
190 extui a2, a2, 0, 4 # mask for the first 16 registers
191 or a2, a3, a2
192 s32i a2, a1, PT_WMASK # needed when we restore the reg-file
194 /* Save 4 registers at a time */
196 1: rotw -1
197 s32i a0, a5, PT_AREG_END - 16
198 s32i a1, a5, PT_AREG_END - 12
199 s32i a2, a5, PT_AREG_END - 8
200 s32i a3, a5, PT_AREG_END - 4
201 addi a0, a4, -1
202 addi a1, a5, -16
203 _bnez a0, 1b
205 /* WINDOWBASE still in SAR! */
207 rsr a2, SAR # original WINDOWBASE
208 movi a3, 1
209 ssl a2
210 sll a3, a3
211 wsr a3, WINDOWSTART # set corresponding WINDOWSTART bit
212 wsr a2, WINDOWBASE # and WINDOWSTART
213 rsync
215 /* We are back to the original stack pointer (a1) */
217 2:
218 #if XCHAL_EXTRA_SA_SIZE
220 /* For user exceptions, save the extra state into the user's TCB.
221 * Note: We must assume that xchal_extra_store_funcbody destroys a2..a15
222 */
224 GET_CURRENT(a2,a1)
225 addi a2, a2, THREAD_CP_SAVE
226 xchal_extra_store_funcbody
227 #endif
229 /* Now, jump to the common exception handler. */
231 j common_exception
234 /*
235 * First-level exit handler for kernel exceptions
236 * Save special registers and the live window frame.
237 * Note: Even though we changes the stack pointer, we don't have to do a
238 * MOVSP here, as we do that when we return from the exception.
239 * (See comment in the kernel exception exit code)
240 *
241 * Entry condition for kernel_exception:
242 *
243 * a0: trashed, original value saved on stack (PT_AREG0)
244 * a1: a1
245 * a2: new stack pointer, original in DEPC
246 * a3: dispatch table
247 * depc: a2, original value saved on stack (PT_DEPC)
248 * excsave_1: a3
249 *
250 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
251 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
252 *
253 * Entry condition for _kernel_exception:
254 *
255 * a0-a3 and depc have been saved to PT_AREG0...PT_AREG3 and PT_DEPC
256 * excsave has been restored, and
257 * stack pointer (a1) has been set.
258 *
259 * Note: _kernel_exception might be at an odd adress. Don't use call0..call12
260 */
262 ENTRY(kernel_exception)
264 /* Save a0, a2, a3, DEPC and set SP. */
266 xsr a3, EXCSAVE_1 # restore a3, excsave_1
267 rsr a0, DEPC # get a2
268 s32i a1, a2, PT_AREG1
269 s32i a0, a2, PT_AREG2
270 s32i a3, a2, PT_AREG3
271 mov a1, a2
273 .globl _kernel_exception
274 _kernel_exception:
276 /* Save SAR and turn off single stepping */
278 movi a2, 0
279 rsr a3, SAR
280 xsr a2, ICOUNTLEVEL
281 s32i a3, a1, PT_SAR
282 s32i a2, a1, PT_ICOUNTLEVEL
284 /* Rotate ws so that the current windowbase is at bit0. */
285 /* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */
287 rsr a2, WINDOWBASE # don't need to save these, we only
288 rsr a3, WINDOWSTART # need shifted windowstart: windowmask
289 ssr a2
290 slli a2, a3, 32-WSBITS
291 src a2, a3, a2
292 srli a2, a2, 32-WSBITS
293 s32i a2, a1, PT_WMASK # needed for kernel_exception_exit
295 /* Save only the live window-frame */
297 _bbsi.l a2, 1, 1f
298 s32i a4, a1, PT_AREG4
299 s32i a5, a1, PT_AREG5
300 s32i a6, a1, PT_AREG6
301 s32i a7, a1, PT_AREG7
302 _bbsi.l a2, 2, 1f
303 s32i a8, a1, PT_AREG8
304 s32i a9, a1, PT_AREG9
305 s32i a10, a1, PT_AREG10
306 s32i a11, a1, PT_AREG11
307 _bbsi.l a2, 3, 1f
308 s32i a12, a1, PT_AREG12
309 s32i a13, a1, PT_AREG13
310 s32i a14, a1, PT_AREG14
311 s32i a15, a1, PT_AREG15
313 1:
315 #ifdef KERNEL_STACK_OVERFLOW_CHECK
317 /* Stack overflow check, for debugging */
318 extui a2, a1, TASK_SIZE_BITS,XX
319 movi a3, SIZE??
320 _bge a2, a3, out_of_stack_panic
322 #endif
324 /*
325 * This is the common exception handler.
326 * We get here from the user exception handler or simply by falling through
327 * from the kernel exception handler.
328 * Save the remaining special registers, switch to kernel mode, and jump
329 * to the second-level exception handler.
330 *
331 */
333 common_exception:
335 /* Save some registers, disable loops and clear the syscall flag. */
337 rsr a2, DEBUGCAUSE
338 rsr a3, EPC_1
339 s32i a2, a1, PT_DEBUGCAUSE
340 s32i a3, a1, PT_PC
342 movi a2, -1
343 rsr a3, EXCVADDR
344 s32i a2, a1, PT_SYSCALL
345 movi a2, 0
346 s32i a3, a1, PT_EXCVADDR
347 xsr a2, LCOUNT
348 s32i a2, a1, PT_LCOUNT
350 /* It is now save to restore the EXC_TABLE_FIXUP variable. */
352 rsr a0, EXCCAUSE
353 movi a3, 0
354 rsr a2, EXCSAVE_1
355 s32i a0, a1, PT_EXCCAUSE
356 s32i a3, a2, EXC_TABLE_FIXUP
358 /* All unrecoverable states are saved on stack, now, and a1 is valid,
359 * so we can allow exceptions and interrupts (*) again.
360 * Set PS(EXCM = 0, UM = 0, RING = 0, OWB = 0, WOE = 1, INTLEVEL = X)
361 *
362 * (*) We only allow interrupts if PS.INTLEVEL was not set to 1 before
363 * (interrupts disabled) and if this exception is not an interrupt.
364 */
366 rsr a3, PS
367 addi a0, a0, -4
368 movi a2, 1
369 extui a3, a3, 0, 1 # a3 = PS.INTLEVEL[0]
370 moveqz a3, a2, a0 # a3 = 1 iff interrupt exception
371 movi a2, 1 << PS_WOE_BIT
372 or a3, a3, a2
373 rsr a0, EXCCAUSE
374 xsr a3, PS
376 s32i a3, a1, PT_PS # save ps
378 /* Save LBEG, LEND */
380 rsr a2, LBEG
381 rsr a3, LEND
382 s32i a2, a1, PT_LBEG
383 s32i a3, a1, PT_LEND
385 /* Go to second-level dispatcher. Set up parameters to pass to the
386 * exception handler and call the exception handler.
387 */
389 movi a4, exc_table
390 mov a6, a1 # pass stack frame
391 mov a7, a0 # pass EXCCAUSE
392 addx4 a4, a0, a4
393 l32i a4, a4, EXC_TABLE_DEFAULT # load handler
395 /* Call the second-level handler */
397 callx4 a4
399 /* Jump here for exception exit */
401 common_exception_return:
403 /* Jump if we are returning from kernel exceptions. */
405 1: l32i a3, a1, PT_PS
406 _bbsi.l a3, PS_UM_BIT, 2f
407 j kernel_exception_exit
409 /* Specific to a user exception exit:
410 * We need to check some flags for signal handling and rescheduling,
411 * and have to restore WB and WS, extra states, and all registers
412 * in the register file that were in use in the user task.
413 */
415 2: wsr a3, PS /* disable interrupts */
417 /* Check for signals (keep interrupts disabled while we read TI_FLAGS)
418 * Note: PS.INTLEVEL = 0, PS.EXCM = 1
419 */
421 GET_THREAD_INFO(a2,a1)
422 l32i a4, a2, TI_FLAGS
424 /* Enable interrupts again.
425 * Note: When we get here, we certainly have handled any interrupts.
426 * (Hint: There is only one user exception frame on stack)
427 */
429 movi a3, 1 << PS_WOE_BIT
431 _bbsi.l a4, TIF_NEED_RESCHED, 3f
432 _bbci.l a4, TIF_SIGPENDING, 4f
434 #ifndef SIGNAL_HANDLING_IN_DOUBLE_EXCEPTION
435 l32i a4, a1, PT_DEPC
436 bgeui a4, VALID_DOUBLE_EXCEPTION_ADDRESS, 4f
437 #endif
439 /* Reenable interrupts and call do_signal() */
441 wsr a3, PS
442 movi a4, do_signal # int do_signal(struct pt_regs*, sigset_t*)
443 mov a6, a1
444 movi a7, 0
445 callx4 a4
446 j 1b
448 3: /* Reenable interrupts and reschedule */
450 wsr a3, PS
451 movi a4, schedule # void schedule (void)
452 callx4 a4
453 j 1b
455 /* Restore the state of the task and return from the exception. */
457 4: /* a2 holds GET_CURRENT(a2,a1) */
459 #if XCHAL_EXTRA_SA_SIZE
461 /* For user exceptions, restore the extra state from the user's TCB. */
463 /* Note: a2 still contains GET_CURRENT(a2,a1) */
464 addi a2, a2, THREAD_CP_SAVE
465 xchal_extra_load_funcbody
467 /* We must assume that xchal_extra_store_funcbody destroys
468 * registers a2..a15. FIXME, this list can eventually be
469 * reduced once real register requirements of the macro are
470 * finalized. */
472 #endif /* XCHAL_EXTRA_SA_SIZE */
475 /* Switch to the user thread WINDOWBASE. Save SP temporarily in DEPC */
477 l32i a2, a1, PT_WINDOWBASE
478 l32i a3, a1, PT_WINDOWSTART
479 wsr a1, DEPC # use DEPC as temp storage
480 wsr a3, WINDOWSTART # restore WINDOWSTART
481 ssr a2 # preserve user's WB in the SAR
482 wsr a2, WINDOWBASE # switch to user's saved WB
483 rsync
484 rsr a1, DEPC # restore stack pointer
485 l32i a2, a1, PT_WMASK # register frames saved (in bits 4...9)
486 rotw -1 # we restore a4..a7
487 _bltui a6, 16, 1f # only have to restore current window?
489 /* The working registers are a0 and a3. We are restoring to
490 * a4..a7. Be careful not to destroy what we have just restored.
491 * Note: wmask has the format YYYYM:
492 * Y: number of registers saved in groups of 4
493 * M: 4 bit mask of first 16 registers
494 */
496 mov a2, a6
497 mov a3, a5
499 2: rotw -1 # a0..a3 become a4..a7
500 addi a3, a7, -4*4 # next iteration
501 addi a2, a6, -16 # decrementing Y in WMASK
502 l32i a4, a3, PT_AREG_END + 0
503 l32i a5, a3, PT_AREG_END + 4
504 l32i a6, a3, PT_AREG_END + 8
505 l32i a7, a3, PT_AREG_END + 12
506 _bgeui a2, 16, 2b
508 /* Clear unrestored registers (don't leak anything to user-land */
510 1: rsr a0, WINDOWBASE
511 rsr a3, SAR
512 sub a3, a0, a3
513 beqz a3, 2f
514 extui a3, a3, 0, WBBITS
516 1: rotw -1
517 addi a3, a7, -1
518 movi a4, 0
519 movi a5, 0
520 movi a6, 0
521 movi a7, 0
522 bgei a3, 1, 1b
524 /* We are back were we were when we started.
525 * Note: a2 still contains WMASK (if we've returned to the original
526 * frame where we had loaded a2), or at least the lower 4 bits
527 * (if we have restored WSBITS-1 frames).
528 */
530 2: j common_exception_exit
532 /* This is the kernel exception exit.
533 * We avoided to do a MOVSP when we entered the exception, but we
534 * have to do it here.
535 */
537 kernel_exception_exit:
539 /* Disable interrupts (a3 holds PT_PS) */
541 wsr a3, PS
543 #ifdef PREEMPTIBLE_KERNEL
545 #ifdef CONFIG_PREEMPT
547 /*
548 * Note: We've just returned from a call4, so we have
549 * at least 4 addt'l regs.
550 */
552 /* Check current_thread_info->preempt_count */
554 GET_THREAD_INFO(a2)
555 l32i a3, a2, TI_PREEMPT
556 bnez a3, 1f
558 l32i a2, a2, TI_FLAGS
560 1:
562 #endif
564 #endif
566 /* Check if we have to do a movsp.
567 *
568 * We only have to do a movsp if the previous window-frame has
569 * been spilled to the *temporary* exception stack instead of the
570 * task's stack. This is the case if the corresponding bit in
571 * WINDOWSTART for the previous window-frame was set before
572 * (not spilled) but is zero now (spilled).
573 * If this bit is zero, all other bits except the one for the
574 * current window frame are also zero. So, we can use a simple test:
575 * 'and' WINDOWSTART and WINDOWSTART-1:
576 *
577 * (XXXXXX1[0]* - 1) AND XXXXXX1[0]* = XXXXXX0[0]*
578 *
579 * The result is zero only if one bit was set.
580 *
581 * (Note: We might have gone through several task switches before
582 * we come back to the current task, so WINDOWBASE might be
583 * different from the time the exception occurred.)
584 */
586 /* Test WINDOWSTART before and after the exception.
587 * We actually have WMASK, so we only have to test if it is 1 or not.
588 */
590 l32i a2, a1, PT_WMASK
591 _beqi a2, 1, common_exception_exit # Spilled before exception,jump
593 /* Test WINDOWSTART now. If spilled, do the movsp */
595 rsr a3, WINDOWSTART
596 addi a0, a3, -1
597 and a3, a3, a0
598 _bnez a3, common_exception_exit
600 /* Do a movsp (we returned from a call4, so we have at least a0..a7) */
602 addi a0, a1, -16
603 l32i a3, a0, 0
604 l32i a4, a0, 4
605 s32i a3, a1, PT_SIZE+0
606 s32i a4, a1, PT_SIZE+4
607 l32i a3, a0, 8
608 l32i a4, a0, 12
609 s32i a3, a1, PT_SIZE+8
610 s32i a4, a1, PT_SIZE+12
612 /* Common exception exit.
613 * We restore the special register and the current window frame, and
614 * return from the exception.
615 *
616 * Note: We expect a2 to hold PT_WMASK
617 */
619 common_exception_exit:
621 _bbsi.l a2, 1, 1f
622 l32i a4, a1, PT_AREG4
623 l32i a5, a1, PT_AREG5
624 l32i a6, a1, PT_AREG6
625 l32i a7, a1, PT_AREG7
626 _bbsi.l a2, 2, 1f
627 l32i a8, a1, PT_AREG8
628 l32i a9, a1, PT_AREG9
629 l32i a10, a1, PT_AREG10
630 l32i a11, a1, PT_AREG11
631 _bbsi.l a2, 3, 1f
632 l32i a12, a1, PT_AREG12
633 l32i a13, a1, PT_AREG13
634 l32i a14, a1, PT_AREG14
635 l32i a15, a1, PT_AREG15
637 /* Restore PC, SAR */
639 1: l32i a2, a1, PT_PC
640 l32i a3, a1, PT_SAR
641 wsr a2, EPC_1
642 wsr a3, SAR
644 /* Restore LBEG, LEND, LCOUNT */
646 l32i a2, a1, PT_LBEG
647 l32i a3, a1, PT_LEND
648 wsr a2, LBEG
649 l32i a2, a1, PT_LCOUNT
650 wsr a3, LEND
651 wsr a2, LCOUNT
653 /* We control single stepping through the ICOUNTLEVEL register. */
655 l32i a2, a1, PT_ICOUNTLEVEL
656 movi a3, -2
657 wsr a2, ICOUNTLEVEL
658 wsr a3, ICOUNT
660 /* Check if it was double exception. */
662 l32i a0, a1, PT_DEPC
663 l32i a3, a1, PT_AREG3
664 l32i a2, a1, PT_AREG2
665 _bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
667 /* Restore a0...a3 and return */
669 l32i a0, a1, PT_AREG0
670 l32i a1, a1, PT_AREG1
671 rfe
673 1: wsr a0, DEPC
674 l32i a0, a1, PT_AREG0
675 l32i a1, a1, PT_AREG1
676 rfde
678 /*
679 * Debug exception handler.
680 *
681 * Currently, we don't support KGDB, so only user application can be debugged.
682 *
683 * When we get here, a0 is trashed and saved to excsave[debuglevel]
684 */
686 ENTRY(debug_exception)
688 rsr a0, EPS + XCHAL_DEBUGLEVEL
689 bbsi.l a0, PS_EXCM_BIT, 1f # exception mode
691 /* Set EPC_1 and EXCCAUSE */
693 wsr a2, DEPC # save a2 temporarily
694 rsr a2, EPC + XCHAL_DEBUGLEVEL
695 wsr a2, EPC_1
697 movi a2, EXCCAUSE_MAPPED_DEBUG
698 wsr a2, EXCCAUSE
700 /* Restore PS to the value before the debug exc but with PS.EXCM set.*/
702 movi a2, 1 << PS_EXCM_BIT
703 or a2, a0, a2
704 movi a0, debug_exception # restore a3, debug jump vector
705 wsr a2, PS
706 xsr a0, EXCSAVE + XCHAL_DEBUGLEVEL
708 /* Switch to kernel/user stack, restore jump vector, and save a0 */
710 bbsi.l a2, PS_UM_BIT, 2f # jump if user mode
712 addi a2, a1, -16-PT_SIZE # assume kernel stack
713 s32i a0, a2, PT_AREG0
714 movi a0, 0
715 s32i a1, a2, PT_AREG1
716 s32i a0, a2, PT_DEPC # mark it as a regular exception
717 xsr a0, DEPC
718 s32i a3, a2, PT_AREG3
719 s32i a0, a2, PT_AREG2
720 mov a1, a2
721 j _kernel_exception
723 2: rsr a2, EXCSAVE_1
724 l32i a2, a2, EXC_TABLE_KSTK # load kernel stack pointer
725 s32i a0, a2, PT_AREG0
726 movi a0, 0
727 s32i a1, a2, PT_AREG1
728 s32i a0, a2, PT_DEPC
729 xsr a0, DEPC
730 s32i a3, a2, PT_AREG3
731 s32i a0, a2, PT_AREG2
732 mov a1, a2
733 j _user_exception
735 /* Debug exception while in exception mode. */
736 1: j 1b // FIXME!!
739 /*
740 * We get here in case of an unrecoverable exception.
741 * The only thing we can do is to be nice and print a panic message.
742 * We only produce a single stack frame for panic, so ???
743 *
744 *
745 * Entry conditions:
746 *
747 * - a0 contains the caller address; original value saved in excsave1.
748 * - the original a0 contains a valid return address (backtrace) or 0.
749 * - a2 contains a valid stackpointer
750 *
751 * Notes:
752 *
753 * - If the stack pointer could be invalid, the caller has to setup a
754 * dummy stack pointer (e.g. the stack of the init_task)
755 *
756 * - If the return address could be invalid, the caller has to set it
757 * to 0, so the backtrace would stop.
758 *
759 */
760 .align 4
761 unrecoverable_text:
762 .ascii "Unrecoverable error in exception handler\0"
764 ENTRY(unrecoverable_exception)
766 movi a0, 1
767 movi a1, 0
769 wsr a0, WINDOWSTART
770 wsr a1, WINDOWBASE
771 rsync
773 movi a1, (1 << PS_WOE_BIT) | 1
774 wsr a1, PS
775 rsync
777 movi a1, init_task
778 movi a0, 0
779 addi a1, a1, PT_REGS_OFFSET
781 movi a4, panic
782 movi a6, unrecoverable_text
784 callx4 a4
786 1: j 1b
789 /* -------------------------- FAST EXCEPTION HANDLERS ----------------------- */
791 /*
792 * Fast-handler for alloca exceptions
793 *
794 * The ALLOCA handler is entered when user code executes the MOVSP
795 * instruction and the caller's frame is not in the register file.
796 * In this case, the caller frame's a0..a3 are on the stack just
797 * below sp (a1), and this handler moves them.
798 *
799 * For "MOVSP <ar>,<as>" without destination register a1, this routine
800 * simply moves the value from <as> to <ar> without moving the save area.
801 *
802 * Entry condition:
803 *
804 * a0: trashed, original value saved on stack (PT_AREG0)
805 * a1: a1
806 * a2: new stack pointer, original in DEPC
807 * a3: dispatch table
808 * depc: a2, original value saved on stack (PT_DEPC)
809 * excsave_1: a3
810 *
811 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
812 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
813 */
815 #if XCHAL_HAVE_BE
816 #define _EXTUI_MOVSP_SRC(ar) extui ar, ar, 4, 4
817 #define _EXTUI_MOVSP_DST(ar) extui ar, ar, 0, 4
818 #else
819 #define _EXTUI_MOVSP_SRC(ar) extui ar, ar, 0, 4
820 #define _EXTUI_MOVSP_DST(ar) extui ar, ar, 4, 4
821 #endif
823 ENTRY(fast_alloca)
825 /* We shouldn't be in a double exception. */
827 l32i a0, a2, PT_DEPC
828 _bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, .Lunhandled_double
830 rsr a0, DEPC # get a2
831 s32i a4, a2, PT_AREG4 # save a4 and
832 s32i a0, a2, PT_AREG2 # a2 to stack
834 /* Exit critical section. */
836 movi a0, 0
837 s32i a0, a3, EXC_TABLE_FIXUP
839 /* Restore a3, excsave_1 */
841 xsr a3, EXCSAVE_1 # make sure excsave_1 is valid for dbl.
842 rsr a4, EPC_1 # get exception address
843 s32i a3, a2, PT_AREG3 # save a3 to stack
845 #ifdef ALLOCA_EXCEPTION_IN_IRAM
846 #error iram not supported
847 #else
848 /* Note: l8ui not allowed in IRAM/IROM!! */
849 l8ui a0, a4, 1 # read as(src) from MOVSP instruction
850 #endif
851 movi a3, .Lmovsp_src
852 _EXTUI_MOVSP_SRC(a0) # extract source register number
853 addx8 a3, a0, a3
854 jx a3
856 .Lunhandled_double:
857 wsr a0, EXCSAVE_1
858 movi a0, unrecoverable_exception
859 callx0 a0
861 .align 8
862 .Lmovsp_src:
863 l32i a3, a2, PT_AREG0; _j 1f; .align 8
864 mov a3, a1; _j 1f; .align 8
865 l32i a3, a2, PT_AREG2; _j 1f; .align 8
866 l32i a3, a2, PT_AREG3; _j 1f; .align 8
867 l32i a3, a2, PT_AREG4; _j 1f; .align 8
868 mov a3, a5; _j 1f; .align 8
869 mov a3, a6; _j 1f; .align 8
870 mov a3, a7; _j 1f; .align 8
871 mov a3, a8; _j 1f; .align 8
872 mov a3, a9; _j 1f; .align 8
873 mov a3, a10; _j 1f; .align 8
874 mov a3, a11; _j 1f; .align 8
875 mov a3, a12; _j 1f; .align 8
876 mov a3, a13; _j 1f; .align 8
877 mov a3, a14; _j 1f; .align 8
878 mov a3, a15; _j 1f; .align 8
880 1:
882 #ifdef ALLOCA_EXCEPTION_IN_IRAM
883 #error iram not supported
884 #else
885 l8ui a0, a4, 0 # read ar(dst) from MOVSP instruction
886 #endif
887 addi a4, a4, 3 # step over movsp
888 _EXTUI_MOVSP_DST(a0) # extract destination register
889 wsr a4, EPC_1 # save new epc_1
891 _bnei a0, 1, 1f # no 'movsp a1, ax': jump
893 /* Move the save area. This implies the use of the L32E
894 * and S32E instructions, because this move must be done with
895 * the user's PS.RING privilege levels, not with ring 0
896 * (kernel's) privileges currently active with PS.EXCM
897 * set. Note that we have stil registered a fixup routine with the
898 * double exception vector in case a double exception occurs.
899 */
901 /* a0,a4:avail a1:old user stack a2:exc. stack a3:new user stack. */
903 l32e a0, a1, -16
904 l32e a4, a1, -12
905 s32e a0, a3, -16
906 s32e a4, a3, -12
907 l32e a0, a1, -8
908 l32e a4, a1, -4
909 s32e a0, a3, -8
910 s32e a4, a3, -4
912 /* Restore stack-pointer and all the other saved registers. */
914 mov a1, a3
916 l32i a4, a2, PT_AREG4
917 l32i a3, a2, PT_AREG3
918 l32i a0, a2, PT_AREG0
919 l32i a2, a2, PT_AREG2
920 rfe
922 /* MOVSP <at>,<as> was invoked with <at> != a1.
923 * Because the stack pointer is not being modified,
924 * we should be able to just modify the pointer
925 * without moving any save area.
926 * The processor only traps these occurrences if the
927 * caller window isn't live, so unfortunately we can't
928 * use this as an alternate trap mechanism.
929 * So we just do the move. This requires that we
930 * resolve the destination register, not just the source,
931 * so there's some extra work.
932 * (PERHAPS NOT REALLY NEEDED, BUT CLEANER...)
933 */
935 /* a0 dst-reg, a1 user-stack, a2 stack, a3 value of src reg. */
937 1: movi a4, .Lmovsp_dst
938 addx8 a4, a0, a4
939 jx a4
941 .align 8
942 .Lmovsp_dst:
943 s32i a3, a2, PT_AREG0; _j 1f; .align 8
944 mov a1, a3; _j 1f; .align 8
945 s32i a3, a2, PT_AREG2; _j 1f; .align 8
946 s32i a3, a2, PT_AREG3; _j 1f; .align 8
947 s32i a3, a2, PT_AREG4; _j 1f; .align 8
948 mov a5, a3; _j 1f; .align 8
949 mov a6, a3; _j 1f; .align 8
950 mov a7, a3; _j 1f; .align 8
951 mov a8, a3; _j 1f; .align 8
952 mov a9, a3; _j 1f; .align 8
953 mov a10, a3; _j 1f; .align 8
954 mov a11, a3; _j 1f; .align 8
955 mov a12, a3; _j 1f; .align 8
956 mov a13, a3; _j 1f; .align 8
957 mov a14, a3; _j 1f; .align 8
958 mov a15, a3; _j 1f; .align 8
960 1: l32i a4, a2, PT_AREG4
961 l32i a3, a2, PT_AREG3
962 l32i a0, a2, PT_AREG0
963 l32i a2, a2, PT_AREG2
964 rfe
967 /*
968 * fast system calls.
969 *
970 * WARNING: The kernel doesn't save the entire user context before
971 * handling a fast system call. These functions are small and short,
972 * usually offering some functionality not available to user tasks.
973 *
974 * BE CAREFUL TO PRESERVE THE USER'S CONTEXT.
975 *
976 * Entry condition:
977 *
978 * a0: trashed, original value saved on stack (PT_AREG0)
979 * a1: a1
980 * a2: new stack pointer, original in DEPC
981 * a3: dispatch table
982 * depc: a2, original value saved on stack (PT_DEPC)
983 * excsave_1: a3
984 */
986 ENTRY(fast_syscall_kernel)
988 /* Skip syscall. */
990 rsr a0, EPC_1
991 addi a0, a0, 3
992 wsr a0, EPC_1
994 l32i a0, a2, PT_DEPC
995 bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, fast_syscall_unrecoverable
997 rsr a0, DEPC # get syscall-nr
998 _beqz a0, fast_syscall_spill_registers
999 _beqi a0, __NR_xtensa, fast_syscall_xtensa
1001 j kernel_exception
1003 ENTRY(fast_syscall_user)
1005 /* Skip syscall. */
1007 rsr a0, EPC_1
1008 addi a0, a0, 3
1009 wsr a0, EPC_1
1011 l32i a0, a2, PT_DEPC
1012 bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, fast_syscall_unrecoverable
1014 rsr a0, DEPC # get syscall-nr
1015 _beqz a0, fast_syscall_spill_registers
1016 _beqi a0, __NR_xtensa, fast_syscall_xtensa
1018 j user_exception
1020 ENTRY(fast_syscall_unrecoverable)
1022 /* Restore all states. */
1024 l32i a0, a2, PT_AREG0 # restore a0
1025 xsr a2, DEPC # restore a2, depc
1026 rsr a3, EXCSAVE_1
1028 wsr a0, EXCSAVE_1
1029 movi a0, unrecoverable_exception
1030 callx0 a0
1034 /*
1035 * sysxtensa syscall handler
1036 *
1037 * int sysxtensa (SYS_XTENSA_ATOMIC_SET, ptr, val, unused);
1038 * int sysxtensa (SYS_XTENSA_ATOMIC_ADD, ptr, val, unused);
1039 * int sysxtensa (SYS_XTENSA_ATOMIC_EXG_ADD, ptr, val, unused);
1040 * int sysxtensa (SYS_XTENSA_ATOMIC_CMP_SWP, ptr, oldval, newval);
1041 * a2 a6 a3 a4 a5
1042 *
1043 * Entry condition:
1044 *
1045 * a0: a2 (syscall-nr), original value saved on stack (PT_AREG0)
1046 * a1: a1
1047 * a2: new stack pointer, original in a0 and DEPC
1048 * a3: dispatch table, original in excsave_1
1049 * a4..a15: unchanged
1050 * depc: a2, original value saved on stack (PT_DEPC)
1051 * excsave_1: a3
1052 *
1053 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
1054 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
1055 *
1056 * Note: we don't have to save a2; a2 holds the return value
1057 *
1058 * We use the two macros TRY and CATCH:
1059 *
1060 * TRY adds an entry to the __ex_table fixup table for the immediately
1061 * following instruction.
1062 *
1063 * CATCH catches any exception that occurred at one of the preceeding TRY
1064 * statements and continues from there
1065 *
1066 * Usage TRY l32i a0, a1, 0
1067 * <other code>
1068 * done: rfe
1069 * CATCH <set return code>
1070 * j done
1071 */
1073 #define TRY \
1074 .section __ex_table, "a"; \
1075 .word 66f, 67f; \
1076 .text; \
1077 66:
1079 #define CATCH \
1080 67:
1082 ENTRY(fast_syscall_xtensa)
1084 xsr a3, EXCSAVE_1 # restore a3, excsave1
1086 s32i a7, a2, PT_AREG7 # we need an additional register
1087 movi a7, 4 # sizeof(unsigned int)
1088 access_ok a3, a7, a0, a2, .Leac # a0: scratch reg, a2: sp
1090 addi a6, a6, -1 # assuming SYS_XTENSA_ATOMIC_SET = 1
1091 _bgeui a6, SYS_XTENSA_COUNT - 1, .Lill
1092 _bnei a6, SYS_XTENSA_ATOMIC_CMP_SWP - 1, .Lnswp
1094 /* Fall through for ATOMIC_CMP_SWP. */
1096 .Lswp: /* Atomic compare and swap */
1098 TRY l32i a0, a3, 0 # read old value
1099 bne a0, a4, 1f # same as old value? jump
1100 TRY s32i a5, a3, 0 # different, modify value
1101 l32i a7, a2, PT_AREG7 # restore a7
1102 l32i a0, a2, PT_AREG0 # restore a0
1103 movi a2, 1 # and return 1
1104 addi a6, a6, 1 # restore a6 (really necessary?)
1105 rfe
1107 1: l32i a7, a2, PT_AREG7 # restore a7
1108 l32i a0, a2, PT_AREG0 # restore a0
1109 movi a2, 0 # return 0 (note that we cannot set
1110 addi a6, a6, 1 # restore a6 (really necessary?)
1111 rfe
1113 .Lnswp: /* Atomic set, add, and exg_add. */
1115 TRY l32i a7, a3, 0 # orig
1116 add a0, a4, a7 # + arg
1117 moveqz a0, a4, a6 # set
1118 TRY s32i a0, a3, 0 # write new value
1120 mov a0, a2
1121 mov a2, a7
1122 l32i a7, a0, PT_AREG7 # restore a7
1123 l32i a0, a0, PT_AREG0 # restore a0
1124 addi a6, a6, 1 # restore a6 (really necessary?)
1125 rfe
1127 CATCH
1128 .Leac: l32i a7, a2, PT_AREG7 # restore a7
1129 l32i a0, a2, PT_AREG0 # restore a0
1130 movi a2, -EFAULT
1131 rfe
1133 .Lill: l32i a7, a2, PT_AREG0 # restore a7
1134 l32i a0, a2, PT_AREG0 # restore a0
1135 movi a2, -EINVAL
1136 rfe
1141 /* fast_syscall_spill_registers.
1142 *
1143 * Entry condition:
1144 *
1145 * a0: trashed, original value saved on stack (PT_AREG0)
1146 * a1: a1
1147 * a2: new stack pointer, original in DEPC
1148 * a3: dispatch table
1149 * depc: a2, original value saved on stack (PT_DEPC)
1150 * excsave_1: a3
1151 *
1152 * Note: We assume the stack pointer is EXC_TABLE_KSTK in the fixup handler.
1153 * Note: We don't need to save a2 in depc (return value)
1154 */
1156 ENTRY(fast_syscall_spill_registers)
1158 /* Register a FIXUP handler (pass current wb as a parameter) */
1160 movi a0, fast_syscall_spill_registers_fixup
1161 s32i a0, a3, EXC_TABLE_FIXUP
1162 rsr a0, WINDOWBASE
1163 s32i a0, a3, EXC_TABLE_PARAM
1165 /* Save a3 and SAR on stack. */
1167 rsr a0, SAR
1168 xsr a3, EXCSAVE_1 # restore a3 and excsave_1
1169 s32i a0, a2, PT_AREG4 # store SAR to PT_AREG4
1170 s32i a3, a2, PT_AREG3
1172 /* The spill routine might clobber a7, a11, and a15. */
1174 s32i a7, a2, PT_AREG5
1175 s32i a11, a2, PT_AREG6
1176 s32i a15, a2, PT_AREG7
1178 call0 _spill_registers # destroys a3, DEPC, and SAR
1180 /* Advance PC, restore registers and SAR, and return from exception. */
1182 l32i a3, a2, PT_AREG4
1183 l32i a0, a2, PT_AREG0
1184 wsr a3, SAR
1185 l32i a3, a2, PT_AREG3
1187 /* Restore clobbered registers. */
1189 l32i a7, a2, PT_AREG5
1190 l32i a11, a2, PT_AREG6
1191 l32i a15, a2, PT_AREG7
1193 movi a2, 0
1194 rfe
1196 /* Fixup handler.
1197 *
1198 * We get here if the spill routine causes an exception, e.g. tlb miss.
1199 * We basically restore WINDOWBASE and WINDOWSTART to the condition when
1200 * we entered the spill routine and jump to the user exception handler.
1201 *
1202 * a0: value of depc, original value in depc
1203 * a2: trashed, original value in EXC_TABLE_DOUBLE_SAVE
1204 * a3: exctable, original value in excsave1
1205 */
1207 fast_syscall_spill_registers_fixup:
1209 rsr a2, WINDOWBASE # get current windowbase (a2 is saved)
1210 xsr a0, DEPC # restore depc and a0
1211 ssl a2 # set shift (32 - WB)
1213 /* We need to make sure the current registers (a0-a3) are preserved.
1214 * To do this, we simply set the bit for the current window frame
1215 * in WS, so that the exception handlers save them to the task stack.
1216 */
1218 rsr a3, EXCSAVE_1 # get spill-mask
1219 slli a2, a3, 1 # shift left by one
1221 slli a3, a2, 32-WSBITS
1222 src a2, a2, a3 # a1 = xxwww1yyxxxwww1yy......
1223 wsr a2, WINDOWSTART # set corrected windowstart
1225 movi a3, exc_table
1226 l32i a2, a3, EXC_TABLE_DOUBLE_SAVE # restore a2
1227 l32i a3, a3, EXC_TABLE_PARAM # original WB (in user task)
1229 /* Return to the original (user task) WINDOWBASE.
1230 * We leave the following frame behind:
1231 * a0, a1, a2 same
1232 * a3: trashed (saved in excsave_1)
1233 * depc: depc (we have to return to that address)
1234 * excsave_1: a3
1235 */
1237 wsr a3, WINDOWBASE
1238 rsync
1240 /* We are now in the original frame when we entered _spill_registers:
1241 * a0: return address
1242 * a1: used, stack pointer
1243 * a2: kernel stack pointer
1244 * a3: available, saved in EXCSAVE_1
1245 * depc: exception address
1246 * excsave: a3
1247 * Note: This frame might be the same as above.
1248 */
1250 #ifdef SIGNAL_HANDLING_IN_DOUBLE_EXCEPTION
1251 /* Restore registers we precautiously saved.
1252 * We have the value of the 'right' a3
1253 */
1255 l32i a7, a2, PT_AREG5
1256 l32i a11, a2, PT_AREG6
1257 l32i a15, a2, PT_AREG7
1258 #endif
1260 /* Setup stack pointer. */
1262 addi a2, a2, -PT_USER_SIZE
1263 s32i a0, a2, PT_AREG0
1265 /* Make sure we return to this fixup handler. */
1267 movi a3, fast_syscall_spill_registers_fixup_return
1268 s32i a3, a2, PT_DEPC # setup depc
1270 /* Jump to the exception handler. */
1272 movi a3, exc_table
1273 rsr a0, EXCCAUSE
1274 addx4 a0, a0, a3 # find entry in table
1275 l32i a0, a0, EXC_TABLE_FAST_USER # load handler
1276 jx a0
1278 fast_syscall_spill_registers_fixup_return:
1280 /* When we return here, all registers have been restored (a2: DEPC) */
1282 wsr a2, DEPC # exception address
1284 /* Restore fixup handler. */
1286 xsr a3, EXCSAVE_1
1287 movi a2, fast_syscall_spill_registers_fixup
1288 s32i a2, a3, EXC_TABLE_FIXUP
1289 rsr a2, WINDOWBASE
1290 s32i a2, a3, EXC_TABLE_PARAM
1291 l32i a2, a3, EXC_TABLE_KSTK
1293 #ifdef SIGNAL_HANDLING_IN_DOUBLE_EXCEPTION
1294 /* Save registers again that might be clobbered. */
1296 s32i a7, a2, PT_AREG5
1297 s32i a11, a2, PT_AREG6
1298 s32i a15, a2, PT_AREG7
1299 #endif
1301 /* Load WB at the time the exception occurred. */
1303 rsr a3, SAR # WB is still in SAR
1304 neg a3, a3
1305 wsr a3, WINDOWBASE
1306 rsync
1308 /* Restore a3 and return. */
1310 movi a3, exc_table
1311 xsr a3, EXCSAVE_1
1313 rfde
1316 /*
1317 * spill all registers.
1318 *
1319 * This is not a real function. The following conditions must be met:
1320 *
1321 * - must be called with call0.
1322 * - uses DEPC, a3 and SAR.
1323 * - the last 'valid' register of each frame are clobbered.
1324 * - the caller must have registered a fixup handler
1325 * (or be inside a critical section)
1326 * - PS_EXCM must be set (PS_WOE cleared?)
1327 */
1329 ENTRY(_spill_registers)
1331 /*
1332 * Rotate ws so that the current windowbase is at bit 0.
1333 * Assume ws = xxxwww1yy (www1 current window frame).
1334 * Rotate ws right so that a2 = yyxxxwww1.
1335 */
1337 wsr a2, DEPC # preserve a2
1338 rsr a2, WINDOWBASE
1339 rsr a3, WINDOWSTART
1340 ssr a2 # holds WB
1341 slli a2, a3, WSBITS
1342 or a3, a3, a2 # a2 = xxxwww1yyxxxwww1yy
1343 srl a3, a3
1345 /* We are done if there are no more than the current register frame. */
1347 extui a3, a3, 1, WSBITS-2 # a3 = 0yyxxxwww
1348 movi a2, (1 << (WSBITS-1))
1349 _beqz a3, .Lnospill # only one active frame? jump
1351 /* We want 1 at the top, so that we return to the current windowbase */
1353 or a3, a3, a2 # 1yyxxxwww
1355 /* Skip empty frames - get 'oldest' WINDOWSTART-bit. */
1357 wsr a3, WINDOWSTART # save shifted windowstart
1358 neg a2, a3
1359 and a3, a2, a3 # first bit set from right: 000010000
1361 ffs_ws a2, a3 # a2: shifts to skip empty frames
1362 movi a3, WSBITS
1363 sub a2, a3, a2 # WSBITS-a2:number of 0-bits from right
1364 ssr a2 # save in SAR for later.
1366 rsr a3, WINDOWBASE
1367 add a3, a3, a2
1368 rsr a2, DEPC # restore a2
1369 wsr a3, WINDOWBASE
1370 rsync
1372 rsr a3, WINDOWSTART
1373 srl a3, a3 # shift windowstart
1375 /* WB is now just one frame below the oldest frame in the register
1376 window. WS is shifted so the oldest frame is in bit 0, thus, WB
1377 and WS differ by one 4-register frame. */
1379 /* Save frames. Depending what call was used (call4, call8, call12),
1380 * we have to save 4,8. or 12 registers.
1381 */
1383 _bbsi.l a3, 1, .Lc4
1384 _bbsi.l a3, 2, .Lc8
1386 /* Special case: we have a call12-frame starting at a4. */
1388 _bbci.l a3, 3, .Lc12 # bit 3 shouldn't be zero! (Jump to Lc12 first)
1390 s32e a4, a1, -16 # a1 is valid with an empty spill area
1391 l32e a4, a5, -12
1392 s32e a8, a4, -48
1393 mov a8, a4
1394 l32e a4, a1, -16
1395 j .Lc12c
1397 .Lloop: _bbsi.l a3, 1, .Lc4
1398 _bbci.l a3, 2, .Lc12
1400 .Lc8: s32e a4, a13, -16
1401 l32e a4, a5, -12
1402 s32e a8, a4, -32
1403 s32e a5, a13, -12
1404 s32e a6, a13, -8
1405 s32e a7, a13, -4
1406 s32e a9, a4, -28
1407 s32e a10, a4, -24
1408 s32e a11, a4, -20
1410 srli a11, a3, 2 # shift windowbase by 2
1411 rotw 2
1412 _bnei a3, 1, .Lloop
1414 .Lexit: /* Done. Do the final rotation, set WS, and return. */
1416 rotw 1
1417 rsr a3, WINDOWBASE
1418 ssl a3
1419 movi a3, 1
1420 sll a3, a3
1421 wsr a3, WINDOWSTART
1423 .Lnospill:
1424 jx a0
1426 .Lc4: s32e a4, a9, -16
1427 s32e a5, a9, -12
1428 s32e a6, a9, -8
1429 s32e a7, a9, -4
1431 srli a7, a3, 1
1432 rotw 1
1433 _bnei a3, 1, .Lloop
1434 j .Lexit
1436 .Lc12: _bbci.l a3, 3, .Linvalid_mask # bit 2 shouldn't be zero!
1438 /* 12-register frame (call12) */
1440 l32e a2, a5, -12
1441 s32e a8, a2, -48
1442 mov a8, a2
1444 .Lc12c: s32e a9, a8, -44
1445 s32e a10, a8, -40
1446 s32e a11, a8, -36
1447 s32e a12, a8, -32
1448 s32e a13, a8, -28
1449 s32e a14, a8, -24
1450 s32e a15, a8, -20
1451 srli a15, a3, 3
1453 /* The stack pointer for a4..a7 is out of reach, so we rotate the
1454 * window, grab the stackpointer, and rotate back.
1455 * Alternatively, we could also use the following approach, but that
1456 * makes the fixup routine much more complicated:
1457 * rotw 1
1458 * s32e a0, a13, -16
1459 * ...
1460 * rotw 2
1461 */
1463 rotw 1
1464 mov a5, a13
1465 rotw -1
1467 s32e a4, a9, -16
1468 s32e a5, a9, -12
1469 s32e a6, a9, -8
1470 s32e a7, a9, -4
1472 rotw 3
1474 _beqi a3, 1, .Lexit
1475 j .Lloop
1477 .Linvalid_mask:
1479 /* We get here because of an unrecoverable error in the window
1480 * registers. If we are in user space, we kill the application,
1481 * however, this condition is unrecoverable in kernel space.
1482 */
1484 rsr a0, PS
1485 _bbci.l a0, PS_UM_BIT, 1f
1487 /* User space: Setup a dummy frame and kill application.
1488 * Note: We assume EXC_TABLE_KSTK contains a valid stack pointer.
1489 */
1491 movi a0, 1
1492 movi a1, 0
1494 wsr a0, WINDOWSTART
1495 wsr a1, WINDOWBASE
1496 rsync
1498 movi a0, 0
1500 movi a3, exc_table
1501 l32i a1, a3, EXC_TABLE_KSTK
1502 wsr a3, EXCSAVE_1
1504 movi a4, (1 << PS_WOE_BIT) | 1
1505 wsr a4, PS
1506 rsync
1508 movi a6, SIGSEGV
1509 movi a4, do_exit
1510 callx4 a4
1512 1: /* Kernel space: PANIC! */
1514 wsr a0, EXCSAVE_1
1515 movi a0, unrecoverable_exception
1516 callx0 a0 # should not return
1517 1: j 1b
1519 /*
1520 * We should never get here. Bail out!
1521 */
1523 ENTRY(fast_second_level_miss_double_kernel)
1525 1: movi a0, unrecoverable_exception
1526 callx0 a0 # should not return
1527 1: j 1b
1529 /* First-level entry handler for user, kernel, and double 2nd-level
1530 * TLB miss exceptions. Note that for now, user and kernel miss
1531 * exceptions share the same entry point and are handled identically.
1532 *
1533 * An old, less-efficient C version of this function used to exist.
1534 * We include it below, interleaved as comments, for reference.
1535 *
1536 * Entry condition:
1537 *
1538 * a0: trashed, original value saved on stack (PT_AREG0)
1539 * a1: a1
1540 * a2: new stack pointer, original in DEPC
1541 * a3: dispatch table
1542 * depc: a2, original value saved on stack (PT_DEPC)
1543 * excsave_1: a3
1544 *
1545 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
1546 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
1547 */
1549 ENTRY(fast_second_level_miss)
1551 /* Save a1. Note: we don't expect a double exception. */
1553 s32i a1, a2, PT_AREG1
1555 /* We need to map the page of PTEs for the user task. Find
1556 * the pointer to that page. Also, it's possible for tsk->mm
1557 * to be NULL while tsk->active_mm is nonzero if we faulted on
1558 * a vmalloc address. In that rare case, we must use
1559 * active_mm instead to avoid a fault in this handler. See
1560 *
1561 * http://mail.nl.linux.org/linux-mm/2002-08/msg00258.html
1562 * (or search Internet on "mm vs. active_mm")
1563 *
1564 * if (!mm)
1565 * mm = tsk->active_mm;
1566 * pgd = pgd_offset (mm, regs->excvaddr);
1567 * pmd = pmd_offset (pgd, regs->excvaddr);
1568 * pmdval = *pmd;
1569 */
1571 GET_CURRENT(a1,a2)
1572 l32i a0, a1, TASK_MM # tsk->mm
1573 beqz a0, 9f
1576 /* We deliberately destroy a3 that holds the exception table. */
1578 8: rsr a3, EXCVADDR # fault address
1579 _PGD_OFFSET(a0, a3, a1)
1580 l32i a0, a0, 0 # read pmdval
1581 beqz a0, 2f
1583 /* Read ptevaddr and convert to top of page-table page.
1584 *
1585 * vpnval = read_ptevaddr_register() & PAGE_MASK;
1586 * vpnval += DTLB_WAY_PGTABLE;
1587 * pteval = mk_pte (virt_to_page(pmd_val(pmdval)), PAGE_KERNEL);
1588 * write_dtlb_entry (pteval, vpnval);
1589 *
1590 * The messy computation for 'pteval' above really simplifies
1591 * into the following:
1592 *
1593 * pteval = ((pmdval - PAGE_OFFSET) & PAGE_MASK) | PAGE_DIRECTORY
1594 */
1596 movi a1, -PAGE_OFFSET
1597 add a0, a0, a1 # pmdval - PAGE_OFFSET
1598 extui a1, a0, 0, PAGE_SHIFT # ... & PAGE_MASK
1599 xor a0, a0, a1
1601 movi a1, _PAGE_DIRECTORY
1602 or a0, a0, a1 # ... | PAGE_DIRECTORY
1604 /*
1605 * We utilize all three wired-ways (7-9) to hold pmd translations.
1606 * Memory regions are mapped to the DTLBs according to bits 28 and 29.
1607 * This allows to map the three most common regions to three different
1608 * DTLBs:
1609 * 0,1 -> way 7 program (0040.0000) and virtual (c000.0000)
1610 * 2 -> way 8 shared libaries (2000.0000)
1611 * 3 -> way 0 stack (3000.0000)
1612 */
1614 extui a3, a3, 28, 2 # addr. bit 28 and 29 0,1,2,3
1615 rsr a1, PTEVADDR
1616 addx2 a3, a3, a3 # -> 0,3,6,9
1617 srli a1, a1, PAGE_SHIFT
1618 extui a3, a3, 2, 2 # -> 0,0,1,2
1619 slli a1, a1, PAGE_SHIFT # ptevaddr & PAGE_MASK
1620 addi a3, a3, DTLB_WAY_PGD
1621 add a1, a1, a3 # ... + way_number
1623 3: wdtlb a0, a1
1624 dsync
1626 /* Exit critical section. */
1628 4: movi a3, exc_table # restore a3
1629 movi a0, 0
1630 s32i a0, a3, EXC_TABLE_FIXUP
1632 /* Restore the working registers, and return. */
1634 l32i a0, a2, PT_AREG0
1635 l32i a1, a2, PT_AREG1
1636 l32i a2, a2, PT_DEPC
1637 xsr a3, EXCSAVE_1
1639 bgeui a2, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
1641 /* Restore excsave1 and return. */
1643 rsr a2, DEPC
1644 rfe
1646 /* Return from double exception. */
1648 1: xsr a2, DEPC
1649 esync
1650 rfde
1652 9: l32i a0, a1, TASK_ACTIVE_MM # unlikely case mm == 0
1653 j 8b
1655 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
1657 2: /* Special case for cache aliasing.
1658 * We (should) only get here if a clear_user_page, copy_user_page
1659 * or the aliased cache flush functions got preemptively interrupted
1660 * by another task. Re-establish temporary mapping to the
1661 * TLBTEMP_BASE areas.
1662 */
1664 /* We shouldn't be in a double exception */
1666 l32i a0, a2, PT_DEPC
1667 bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 2f
1669 /* Make sure the exception originated in the special functions */
1671 movi a0, __tlbtemp_mapping_start
1672 rsr a3, EPC_1
1673 bltu a3, a0, 2f
1674 movi a0, __tlbtemp_mapping_end
1675 bgeu a3, a0, 2f
1677 /* Check if excvaddr was in one of the TLBTEMP_BASE areas. */
1679 movi a3, TLBTEMP_BASE_1
1680 rsr a0, EXCVADDR
1681 bltu a0, a3, 2f
1683 addi a1, a0, -(2 << (DCACHE_ALIAS_ORDER + PAGE_SHIFT))
1684 bgeu a1, a3, 2f
1686 /* Check if we have to restore an ITLB mapping. */
1688 movi a1, __tlbtemp_mapping_itlb
1689 rsr a3, EPC_1
1690 sub a3, a3, a1
1692 /* Calculate VPN */
1694 movi a1, PAGE_MASK
1695 and a1, a1, a0
1697 /* Jump for ITLB entry */
1699 bgez a3, 1f
1701 /* We can use up to two TLBTEMP areas, one for src and one for dst. */
1703 extui a3, a0, PAGE_SHIFT + DCACHE_ALIAS_ORDER, 1
1704 add a1, a3, a1
1706 /* PPN is in a6 for the first TLBTEMP area and in a7 for the second. */
1708 mov a0, a6
1709 movnez a0, a7, a3
1710 j 3b
1712 /* ITLB entry. We only use dst in a6. */
1714 1: witlb a6, a1
1715 isync
1716 j 4b
1719 #endif // DCACHE_WAY_SIZE > PAGE_SIZE
1722 2: /* Invalid PGD, default exception handling */
1724 movi a3, exc_table
1725 rsr a1, DEPC
1726 xsr a3, EXCSAVE_1
1727 s32i a1, a2, PT_AREG2
1728 s32i a3, a2, PT_AREG3
1729 mov a1, a2
1731 rsr a2, PS
1732 bbsi.l a2, PS_UM_BIT, 1f
1733 j _kernel_exception
1734 1: j _user_exception
1737 /*
1738 * StoreProhibitedException
1739 *
1740 * Update the pte and invalidate the itlb mapping for this pte.
1741 *
1742 * Entry condition:
1743 *
1744 * a0: trashed, original value saved on stack (PT_AREG0)
1745 * a1: a1
1746 * a2: new stack pointer, original in DEPC
1747 * a3: dispatch table
1748 * depc: a2, original value saved on stack (PT_DEPC)
1749 * excsave_1: a3
1750 *
1751 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
1752 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
1753 */
1755 ENTRY(fast_store_prohibited)
1757 /* Save a1 and a4. */
1759 s32i a1, a2, PT_AREG1
1760 s32i a4, a2, PT_AREG4
1762 GET_CURRENT(a1,a2)
1763 l32i a0, a1, TASK_MM # tsk->mm
1764 beqz a0, 9f
1766 8: rsr a1, EXCVADDR # fault address
1767 _PGD_OFFSET(a0, a1, a4)
1768 l32i a0, a0, 0
1769 beqz a0, 2f
1771 /* Note that we assume _PAGE_WRITABLE_BIT is only set if pte is valid.*/
1773 _PTE_OFFSET(a0, a1, a4)
1774 l32i a4, a0, 0 # read pteval
1775 bbci.l a4, _PAGE_WRITABLE_BIT, 2f
1777 movi a1, _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_HW_WRITE
1778 or a4, a4, a1
1779 rsr a1, EXCVADDR
1780 s32i a4, a0, 0
1782 /* We need to flush the cache if we have page coloring. */
1783 #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
1784 dhwb a0, 0
1785 #endif
1786 pdtlb a0, a1
1787 wdtlb a4, a0
1789 /* Exit critical section. */
1791 movi a0, 0
1792 s32i a0, a3, EXC_TABLE_FIXUP
1794 /* Restore the working registers, and return. */
1796 l32i a4, a2, PT_AREG4
1797 l32i a1, a2, PT_AREG1
1798 l32i a0, a2, PT_AREG0
1799 l32i a2, a2, PT_DEPC
1801 /* Restore excsave1 and a3. */
1803 xsr a3, EXCSAVE_1
1804 bgeui a2, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
1806 rsr a2, DEPC
1807 rfe
1809 /* Double exception. Restore FIXUP handler and return. */
1811 1: xsr a2, DEPC
1812 esync
1813 rfde
1815 9: l32i a0, a1, TASK_ACTIVE_MM # unlikely case mm == 0
1816 j 8b
1818 2: /* If there was a problem, handle fault in C */
1820 rsr a4, DEPC # still holds a2
1821 xsr a3, EXCSAVE_1
1822 s32i a4, a2, PT_AREG2
1823 s32i a3, a2, PT_AREG3
1824 l32i a4, a2, PT_AREG4
1825 mov a1, a2
1827 rsr a2, PS
1828 bbsi.l a2, PS_UM_BIT, 1f
1829 j _kernel_exception
1830 1: j _user_exception
1833 #if XCHAL_EXTRA_SA_SIZE
1835 #warning fast_coprocessor untested
1837 /*
1838 * Entry condition:
1839 *
1840 * a0: trashed, original value saved on stack (PT_AREG0)
1841 * a1: a1
1842 * a2: new stack pointer, original in DEPC
1843 * a3: dispatch table
1844 * depc: a2, original value saved on stack (PT_DEPC)
1845 * excsave_1: a3
1846 *
1847 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
1848 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
1849 */
1851 ENTRY(fast_coprocessor_double)
1852 wsr a0, EXCSAVE_1
1853 movi a0, unrecoverable_exception
1854 callx0 a0
1856 ENTRY(fast_coprocessor)
1858 /* Fatal if we are in a double exception. */
1860 l32i a0, a2, PT_DEPC
1861 _bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, fast_coprocessor_double
1863 /* Save some registers a1, a3, a4, SAR */
1865 xsr a3, EXCSAVE_1
1866 s32i a3, a2, PT_AREG3
1867 rsr a3, SAR
1868 s32i a4, a2, PT_AREG4
1869 s32i a1, a2, PT_AREG1
1870 s32i a5, a1, PT_AREG5
1871 s32i a3, a2, PT_SAR
1872 mov a1, a2
1874 /* Currently, the HAL macros only guarantee saving a0 and a1.
1875 * These can and will be refined in the future, but for now,
1876 * just save the remaining registers of a2...a15.
1877 */
1878 s32i a6, a1, PT_AREG6
1879 s32i a7, a1, PT_AREG7
1880 s32i a8, a1, PT_AREG8
1881 s32i a9, a1, PT_AREG9
1882 s32i a10, a1, PT_AREG10
1883 s32i a11, a1, PT_AREG11
1884 s32i a12, a1, PT_AREG12
1885 s32i a13, a1, PT_AREG13
1886 s32i a14, a1, PT_AREG14
1887 s32i a15, a1, PT_AREG15
1889 /* Find coprocessor number. Subtract first CP EXCCAUSE from EXCCAUSE */
1891 rsr a0, EXCCAUSE
1892 addi a3, a0, -XCHAL_EXCCAUSE_COPROCESSOR0_DISABLED
1894 /* Set corresponding CPENABLE bit */
1896 movi a4, 1
1897 ssl a3 # SAR: 32 - coprocessor_number
1898 rsr a5, CPENABLE
1899 sll a4, a4
1900 or a4, a5, a4
1901 wsr a4, CPENABLE
1902 rsync
1903 movi a5, coprocessor_info # list of owner and offset into cp_save
1904 addx8 a0, a4, a5 # entry for CP
1906 bne a4, a5, .Lload # bit wasn't set before, cp not in use
1908 /* Now compare the current task with the owner of the coprocessor.
1909 * If they are the same, there is no reason to save or restore any
1910 * coprocessor state. Having already enabled the coprocessor,
1911 * branch ahead to return.
1912 */
1913 GET_CURRENT(a5,a1)
1914 l32i a4, a0, COPROCESSOR_INFO_OWNER # a4: current owner for this CP
1915 beq a4, a5, .Ldone
1917 /* Find location to dump current coprocessor state:
1918 * task_struct->task_cp_save_offset + coprocessor_offset[coprocessor]
1919 *
1920 * Note: a0 pointer to the entry in the coprocessor owner table,
1921 * a3 coprocessor number,
1922 * a4 current owner of coprocessor.
1923 */
1924 l32i a5, a0, COPROCESSOR_INFO_OFFSET
1925 addi a2, a4, THREAD_CP_SAVE
1926 add a2, a2, a5
1928 /* Store current coprocessor states. (a5 still has CP number) */
1930 xchal_cpi_store_funcbody
1932 /* The macro might have destroyed a3 (coprocessor number), but
1933 * SAR still has 32 - coprocessor_number!
1934 */
1935 movi a3, 32
1936 rsr a4, SAR
1937 sub a3, a3, a4
1939 .Lload: /* A new task now owns the corpocessors. Save its TCB pointer into
1940 * the coprocessor owner table.
1941 *
1942 * Note: a0 pointer to the entry in the coprocessor owner table,
1943 * a3 coprocessor number.
1944 */
1945 GET_CURRENT(a4,a1)
1946 s32i a4, a0, 0
1948 /* Find location from where to restore the current coprocessor state.*/
1950 l32i a5, a0, COPROCESSOR_INFO_OFFSET
1951 addi a2, a4, THREAD_CP_SAVE
1952 add a2, a2, a4
1954 xchal_cpi_load_funcbody
1956 /* We must assume that the xchal_cpi_store_funcbody macro destroyed
1957 * registers a2..a15.
1958 */
1960 .Ldone: l32i a15, a1, PT_AREG15
1961 l32i a14, a1, PT_AREG14
1962 l32i a13, a1, PT_AREG13
1963 l32i a12, a1, PT_AREG12
1964 l32i a11, a1, PT_AREG11
1965 l32i a10, a1, PT_AREG10
1966 l32i a9, a1, PT_AREG9
1967 l32i a8, a1, PT_AREG8
1968 l32i a7, a1, PT_AREG7
1969 l32i a6, a1, PT_AREG6
1970 l32i a5, a1, PT_AREG5
1971 l32i a4, a1, PT_AREG4
1972 l32i a3, a1, PT_AREG3
1973 l32i a2, a1, PT_AREG2
1974 l32i a0, a1, PT_AREG0
1975 l32i a1, a1, PT_AREG1
1977 rfe
1979 #endif /* XCHAL_EXTRA_SA_SIZE */
1981 /*
1982 * System Calls.
1983 *
1984 * void system_call (struct pt_regs* regs, int exccause)
1985 * a2 a3
1986 */
1988 ENTRY(system_call)
1989 entry a1, 32
1991 /* regs->syscall = regs->areg[2] */
1993 l32i a3, a2, PT_AREG2
1994 mov a6, a2
1995 movi a4, do_syscall_trace_enter
1996 s32i a3, a2, PT_SYSCALL
1997 callx4 a4
1999 /* syscall = sys_call_table[syscall_nr] */
2001 movi a4, sys_call_table;
2002 movi a5, __NR_syscall_count
2003 movi a6, -ENOSYS
2004 bgeu a3, a5, 1f
2006 addx4 a4, a3, a4
2007 l32i a4, a4, 0
2008 movi a5, sys_ni_syscall;
2009 beq a4, a5, 1f
2011 /* Load args: arg0 - arg5 are passed via regs. */
2013 l32i a6, a2, PT_AREG6
2014 l32i a7, a2, PT_AREG3
2015 l32i a8, a2, PT_AREG4
2016 l32i a9, a2, PT_AREG5
2017 l32i a10, a2, PT_AREG8
2018 l32i a11, a2, PT_AREG9
2020 /* Pass one additional argument to the syscall: pt_regs (on stack) */
2021 s32i a2, a1, 0
2023 callx4 a4
2025 1: /* regs->areg[2] = return_value */
2027 s32i a6, a2, PT_AREG2
2028 movi a4, do_syscall_trace_leave
2029 mov a6, a2
2030 callx4 a4
2031 retw
2034 /*
2035 * Create a kernel thread
2036 *
2037 * int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
2038 * a2 a2 a3 a4
2039 */
2041 ENTRY(kernel_thread)
2042 entry a1, 16
2044 mov a5, a2 # preserve fn over syscall
2045 mov a7, a3 # preserve args over syscall
2047 movi a3, _CLONE_VM | _CLONE_UNTRACED
2048 movi a2, __NR_clone
2049 or a6, a4, a3 # arg0: flags
2050 mov a3, a1 # arg1: sp
2051 syscall
2053 beq a3, a1, 1f # branch if parent
2054 mov a6, a7 # args
2055 callx4 a5 # fn(args)
2057 movi a2, __NR_exit
2058 syscall # return value of fn(args) still in a6
2060 1: retw
2062 /*
2063 * Do a system call from kernel instead of calling sys_execve, so we end up
2064 * with proper pt_regs.
2065 *
2066 * int kernel_execve(const char *fname, char *const argv[], charg *const envp[])
2067 * a2 a2 a3 a4
2068 */
2070 ENTRY(kernel_execve)
2071 entry a1, 16
2072 mov a6, a2 # arg0 is in a6
2073 movi a2, __NR_execve
2074 syscall
2076 retw
2078 /*
2079 * Task switch.
2080 *
2081 * struct task* _switch_to (struct task* prev, struct task* next)
2082 * a2 a2 a3
2083 */
2085 ENTRY(_switch_to)
2087 entry a1, 16
2089 mov a4, a3 # preserve a3
2091 s32i a0, a2, THREAD_RA # save return address
2092 s32i a1, a2, THREAD_SP # save stack pointer
2094 /* Disable ints while we manipulate the stack pointer; spill regs. */
2096 movi a5, (1 << PS_EXCM_BIT) | LOCKLEVEL
2097 xsr a5, PS
2098 rsr a3, EXCSAVE_1
2099 rsync
2100 s32i a3, a3, EXC_TABLE_FIXUP /* enter critical section */
2102 call0 _spill_registers
2104 /* Set kernel stack (and leave critical section)
2105 * Note: It's save to set it here. The stack will not be overwritten
2106 * because the kernel stack will only be loaded again after
2107 * we return from kernel space.
2108 */
2110 l32i a0, a4, TASK_THREAD_INFO
2111 rsr a3, EXCSAVE_1 # exc_table
2112 movi a1, 0
2113 addi a0, a0, PT_REGS_OFFSET
2114 s32i a1, a3, EXC_TABLE_FIXUP
2115 s32i a0, a3, EXC_TABLE_KSTK
2117 /* restore context of the task that 'next' addresses */
2119 l32i a0, a4, THREAD_RA /* restore return address */
2120 l32i a1, a4, THREAD_SP /* restore stack pointer */
2122 wsr a5, PS
2123 rsync
2125 retw
2128 ENTRY(ret_from_fork)
2130 /* void schedule_tail (struct task_struct *prev)
2131 * Note: prev is still in a6 (return value from fake call4 frame)
2132 */
2133 movi a4, schedule_tail
2134 callx4 a4
2136 movi a4, do_syscall_trace_leave
2137 mov a6, a1
2138 callx4 a4
2140 j common_exception_return