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Initial commit
[wrt350n-kernel.git] / sound / pci / oxygen / oxygen_lib.c
blob6eb36dd11476f7c9e5b8715dfba93273faa3b650
1 /*
2 * C-Media CMI8788 driver - main driver module
3 *
4 * Copyright (c) Clemens Ladisch <clemens@ladisch.de>
5 *
6 *
7 * This driver is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2.
9 *
10 * This driver is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this driver; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/mutex.h>
23 #include <linux/pci.h>
24 #include <sound/ac97_codec.h>
25 #include <sound/asoundef.h>
26 #include <sound/core.h>
27 #include <sound/info.h>
28 #include <sound/mpu401.h>
29 #include <sound/pcm.h>
30 #include "oxygen.h"
31 #include "cm9780.h"
32
33 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
34 MODULE_DESCRIPTION("C-Media CMI8788 helper library");
35 MODULE_LICENSE("GPL");
36
37
38 static irqreturn_t oxygen_interrupt(int dummy, void *dev_id)
39 {
40 struct oxygen *chip = dev_id;
41 unsigned int status, clear, elapsed_streams, i;
42
43 status = oxygen_read16(chip, OXYGEN_INTERRUPT_STATUS);
44 if (!status)
45 return IRQ_NONE;
46
47 spin_lock(&chip->reg_lock);
48
49 clear = status & (OXYGEN_CHANNEL_A |
50 OXYGEN_CHANNEL_B |
51 OXYGEN_CHANNEL_C |
52 OXYGEN_CHANNEL_SPDIF |
53 OXYGEN_CHANNEL_MULTICH |
54 OXYGEN_CHANNEL_AC97 |
55 OXYGEN_INT_SPDIF_IN_DETECT |
56 OXYGEN_INT_GPIO |
57 OXYGEN_INT_AC97);
58 if (clear) {
59 if (clear & OXYGEN_INT_SPDIF_IN_DETECT)
60 chip->interrupt_mask &= ~OXYGEN_INT_SPDIF_IN_DETECT;
61 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
62 chip->interrupt_mask & ~clear);
63 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
64 chip->interrupt_mask);
65 }
66
67 elapsed_streams = status & chip->pcm_running;
68
69 spin_unlock(&chip->reg_lock);
70
71 for (i = 0; i < PCM_COUNT; ++i)
72 if ((elapsed_streams & (1 << i)) && chip->streams[i])
73 snd_pcm_period_elapsed(chip->streams[i]);
74
75 if (status & OXYGEN_INT_SPDIF_IN_DETECT) {
76 spin_lock(&chip->reg_lock);
77 i = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
78 if (i & (OXYGEN_SPDIF_SENSE_INT | OXYGEN_SPDIF_LOCK_INT |
79 OXYGEN_SPDIF_RATE_INT)) {
80 /* write the interrupt bit(s) to clear */
81 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, i);
82 schedule_work(&chip->spdif_input_bits_work);
83 }
84 spin_unlock(&chip->reg_lock);
85 }
86
87 if (status & OXYGEN_INT_GPIO)
88 schedule_work(&chip->gpio_work);
89
90 if ((status & OXYGEN_INT_MIDI) && chip->midi)
91 snd_mpu401_uart_interrupt(0, chip->midi->private_data);
92
93 if (status & OXYGEN_INT_AC97)
94 wake_up(&chip->ac97_waitqueue);
95
96 return IRQ_HANDLED;
97 }
98
99 static void oxygen_spdif_input_bits_changed(struct work_struct *work)
100 {
101 struct oxygen *chip = container_of(work, struct oxygen,
102 spdif_input_bits_work);
103 u32 reg;
104
105 /*
106 * This function gets called when there is new activity on the SPDIF
107 * input, or when we lose lock on the input signal, or when the rate
108 * changes.
109 */
110 msleep(1);
111 spin_lock_irq(&chip->reg_lock);
112 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
113 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
114 OXYGEN_SPDIF_LOCK_STATUS))
115 == OXYGEN_SPDIF_SENSE_STATUS) {
116 /*
117 * If we detect activity on the SPDIF input but cannot lock to
118 * a signal, the clock bit is likely to be wrong.
119 */
120 reg ^= OXYGEN_SPDIF_IN_CLOCK_MASK;
121 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
122 spin_unlock_irq(&chip->reg_lock);
123 msleep(1);
124 spin_lock_irq(&chip->reg_lock);
125 reg = oxygen_read32(chip, OXYGEN_SPDIF_CONTROL);
126 if ((reg & (OXYGEN_SPDIF_SENSE_STATUS |
127 OXYGEN_SPDIF_LOCK_STATUS))
128 == OXYGEN_SPDIF_SENSE_STATUS) {
129 /* nothing detected with either clock; give up */
130 if ((reg & OXYGEN_SPDIF_IN_CLOCK_MASK)
131 == OXYGEN_SPDIF_IN_CLOCK_192) {
132 /*
133 * Reset clock to <= 96 kHz because this is
134 * more likely to be received next time.
135 */
136 reg &= ~OXYGEN_SPDIF_IN_CLOCK_MASK;
137 reg |= OXYGEN_SPDIF_IN_CLOCK_96;
138 oxygen_write32(chip, OXYGEN_SPDIF_CONTROL, reg);
139 }
140 }
141 }
142 spin_unlock_irq(&chip->reg_lock);
143
144 if (chip->controls[CONTROL_SPDIF_INPUT_BITS]) {
145 spin_lock_irq(&chip->reg_lock);
146 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT;
147 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK,
148 chip->interrupt_mask);
149 spin_unlock_irq(&chip->reg_lock);
150
151 /*
152 * We don't actually know that any channel status bits have
153 * changed, but let's send a notification just to be sure.
154 */
155 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
156 &chip->controls[CONTROL_SPDIF_INPUT_BITS]->id);
157 }
158 }
159
160 static void oxygen_gpio_changed(struct work_struct *work)
161 {
162 struct oxygen *chip = container_of(work, struct oxygen, gpio_work);
163
164 if (chip->model->gpio_changed)
165 chip->model->gpio_changed(chip);
166 }
167
168 #ifdef CONFIG_PROC_FS
169 static void oxygen_proc_read(struct snd_info_entry *entry,
170 struct snd_info_buffer *buffer)
171 {
172 struct oxygen *chip = entry->private_data;
173 int i, j;
174
175 snd_iprintf(buffer, "CMI8788\n\n");
176 for (i = 0; i < 0x100; i += 0x10) {
177 snd_iprintf(buffer, "%02x:", i);
178 for (j = 0; j < 0x10; ++j)
179 snd_iprintf(buffer, " %02x", oxygen_read8(chip, i + j));
180 snd_iprintf(buffer, "\n");
181 }
182 if (mutex_lock_interruptible(&chip->mutex) < 0)
183 return;
184 if (chip->has_ac97_0) {
185 snd_iprintf(buffer, "\nAC97\n");
186 for (i = 0; i < 0x80; i += 0x10) {
187 snd_iprintf(buffer, "%02x:", i);
188 for (j = 0; j < 0x10; j += 2)
189 snd_iprintf(buffer, " %04x",
190 oxygen_read_ac97(chip, 0, i + j));
191 snd_iprintf(buffer, "\n");
192 }
193 }
194 if (chip->has_ac97_1) {
195 snd_iprintf(buffer, "\nAC97 2\n");
196 for (i = 0; i < 0x80; i += 0x10) {
197 snd_iprintf(buffer, "%02x:", i);
198 for (j = 0; j < 0x10; j += 2)
199 snd_iprintf(buffer, " %04x",
200 oxygen_read_ac97(chip, 1, i + j));
201 snd_iprintf(buffer, "\n");
202 }
203 }
204 mutex_unlock(&chip->mutex);
205 }
206
207 static void __devinit oxygen_proc_init(struct oxygen *chip)
208 {
209 struct snd_info_entry *entry;
210
211 if (!snd_card_proc_new(chip->card, "cmi8788", &entry))
212 snd_info_set_text_ops(entry, chip, oxygen_proc_read);
213 }
214 #else
215 #define oxygen_proc_init(chip)
216 #endif
217
218 static void __devinit oxygen_init(struct oxygen *chip)
219 {
220 unsigned int i;
221
222 chip->dac_routing = 1;
223 for (i = 0; i < 8; ++i)
224 chip->dac_volume[i] = 0xff;
225 chip->spdif_playback_enable = 1;
226 chip->spdif_bits = OXYGEN_SPDIF_C | OXYGEN_SPDIF_ORIGINAL |
227 (IEC958_AES1_CON_PCM_CODER << OXYGEN_SPDIF_CATEGORY_SHIFT);
228 chip->spdif_pcm_bits = chip->spdif_bits;
229
230 if (oxygen_read8(chip, OXYGEN_REVISION) & OXYGEN_REVISION_2)
231 chip->revision = 2;
232 else
233 chip->revision = 1;
234
235 if (chip->revision == 1)
236 oxygen_set_bits8(chip, OXYGEN_MISC,
237 OXYGEN_MISC_PCI_MEM_W_1_CLOCK);
238
239 i = oxygen_read16(chip, OXYGEN_AC97_CONTROL);
240 chip->has_ac97_0 = (i & OXYGEN_AC97_CODEC_0) != 0;
241 chip->has_ac97_1 = (i & OXYGEN_AC97_CODEC_1) != 0;
242
243 oxygen_set_bits8(chip, OXYGEN_FUNCTION,
244 OXYGEN_FUNCTION_RESET_CODEC |
245 chip->model->function_flags);
246 oxygen_write8_masked(chip, OXYGEN_FUNCTION,
247 OXYGEN_FUNCTION_SPI,
248 OXYGEN_FUNCTION_2WIRE_SPI_MASK);
249 oxygen_write8(chip, OXYGEN_DMA_STATUS, 0);
250 oxygen_write8(chip, OXYGEN_DMA_PAUSE, 0);
251 oxygen_write8(chip, OXYGEN_PLAY_CHANNELS,
252 OXYGEN_PLAY_CHANNELS_2 |
253 OXYGEN_DMA_A_BURST_8 |
254 OXYGEN_DMA_MULTICH_BURST_8);
255 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
256 oxygen_write8_masked(chip, OXYGEN_MISC, 0,
257 OXYGEN_MISC_WRITE_PCI_SUBID |
258 OXYGEN_MISC_REC_C_FROM_SPDIF |
259 OXYGEN_MISC_REC_B_FROM_AC97 |
260 OXYGEN_MISC_REC_A_FROM_MULTICH);
261 oxygen_write8(chip, OXYGEN_REC_FORMAT,
262 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_A_SHIFT) |
263 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_B_SHIFT) |
264 (OXYGEN_FORMAT_16 << OXYGEN_REC_FORMAT_C_SHIFT));
265 oxygen_write8(chip, OXYGEN_PLAY_FORMAT,
266 (OXYGEN_FORMAT_16 << OXYGEN_SPDIF_FORMAT_SHIFT) |
267 (OXYGEN_FORMAT_16 << OXYGEN_MULTICH_FORMAT_SHIFT));
268 oxygen_write8(chip, OXYGEN_REC_CHANNELS, OXYGEN_REC_CHANNELS_2_2_2);
269 oxygen_write16(chip, OXYGEN_I2S_MULTICH_FORMAT,
270 OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
271 OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
272 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
273 oxygen_write16(chip, OXYGEN_I2S_A_FORMAT,
274 OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
275 OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
276 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
277 oxygen_write16(chip, OXYGEN_I2S_B_FORMAT,
278 OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
279 OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
280 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
281 oxygen_write16(chip, OXYGEN_I2S_C_FORMAT,
282 OXYGEN_RATE_48000 | OXYGEN_I2S_FORMAT_LJUST |
283 OXYGEN_I2S_MCLK_128 | OXYGEN_I2S_BITS_16 |
284 OXYGEN_I2S_MASTER | OXYGEN_I2S_BCLK_64);
285 oxygen_write32_masked(chip, OXYGEN_SPDIF_CONTROL,
286 OXYGEN_SPDIF_SENSE_MASK |
287 OXYGEN_SPDIF_LOCK_MASK |
288 OXYGEN_SPDIF_RATE_MASK |
289 OXYGEN_SPDIF_LOCK_PAR |
290 OXYGEN_SPDIF_IN_CLOCK_96,
291 OXYGEN_SPDIF_OUT_ENABLE |
292 OXYGEN_SPDIF_LOOPBACK |
293 OXYGEN_SPDIF_SENSE_MASK |
294 OXYGEN_SPDIF_LOCK_MASK |
295 OXYGEN_SPDIF_RATE_MASK |
296 OXYGEN_SPDIF_SENSE_PAR |
297 OXYGEN_SPDIF_LOCK_PAR |
298 OXYGEN_SPDIF_IN_CLOCK_MASK);
299 oxygen_write32(chip, OXYGEN_SPDIF_OUTPUT_BITS, chip->spdif_bits);
300 oxygen_clear_bits8(chip, OXYGEN_MPU401_CONTROL, OXYGEN_MPU401_LOOPBACK);
301 oxygen_write8(chip, OXYGEN_GPI_INTERRUPT_MASK, 0);
302 oxygen_write16(chip, OXYGEN_GPIO_INTERRUPT_MASK, 0);
303 oxygen_write16(chip, OXYGEN_PLAY_ROUTING,
304 OXYGEN_PLAY_MULTICH_I2S_DAC |
305 OXYGEN_PLAY_SPDIF_SPDIF |
306 (0 << OXYGEN_PLAY_DAC0_SOURCE_SHIFT) |
307 (1 << OXYGEN_PLAY_DAC1_SOURCE_SHIFT) |
308 (2 << OXYGEN_PLAY_DAC2_SOURCE_SHIFT) |
309 (3 << OXYGEN_PLAY_DAC3_SOURCE_SHIFT));
310 oxygen_write8(chip, OXYGEN_REC_ROUTING,
311 OXYGEN_REC_A_ROUTE_I2S_ADC_1 |
312 OXYGEN_REC_B_ROUTE_I2S_ADC_2 |
313 OXYGEN_REC_C_ROUTE_SPDIF);
314 oxygen_write8(chip, OXYGEN_ADC_MONITOR, 0);
315 oxygen_write8(chip, OXYGEN_A_MONITOR_ROUTING,
316 (0 << OXYGEN_A_MONITOR_ROUTE_0_SHIFT) |
317 (1 << OXYGEN_A_MONITOR_ROUTE_1_SHIFT) |
318 (2 << OXYGEN_A_MONITOR_ROUTE_2_SHIFT) |
319 (3 << OXYGEN_A_MONITOR_ROUTE_3_SHIFT));
320
321 oxygen_write8(chip, OXYGEN_AC97_INTERRUPT_MASK,
322 OXYGEN_AC97_INT_READ_DONE |
323 OXYGEN_AC97_INT_WRITE_DONE);
324 oxygen_write32(chip, OXYGEN_AC97_OUT_CONFIG, 0);
325 oxygen_write32(chip, OXYGEN_AC97_IN_CONFIG, 0);
326 if (!(chip->has_ac97_0 | chip->has_ac97_1))
327 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
328 OXYGEN_AC97_CLOCK_DISABLE);
329 if (!chip->has_ac97_0) {
330 oxygen_set_bits16(chip, OXYGEN_AC97_CONTROL,
331 OXYGEN_AC97_NO_CODEC_0);
332 } else {
333 oxygen_write_ac97(chip, 0, AC97_RESET, 0);
334 msleep(1);
335 oxygen_ac97_set_bits(chip, 0, CM9780_GPIO_SETUP,
336 CM9780_GPIO0IO | CM9780_GPIO1IO);
337 oxygen_ac97_set_bits(chip, 0, CM9780_MIXER,
338 CM9780_BSTSEL | CM9780_STRO_MIC |
339 CM9780_MIX2FR | CM9780_PCBSW);
340 oxygen_ac97_set_bits(chip, 0, CM9780_JACK,
341 CM9780_RSOE | CM9780_CBOE |
342 CM9780_SSOE | CM9780_FROE |
343 CM9780_MIC2MIC | CM9780_LI2LI);
344 oxygen_write_ac97(chip, 0, AC97_MASTER, 0x0000);
345 oxygen_write_ac97(chip, 0, AC97_PC_BEEP, 0x8000);
346 oxygen_write_ac97(chip, 0, AC97_MIC, 0x8808);
347 oxygen_write_ac97(chip, 0, AC97_LINE, 0x0808);
348 oxygen_write_ac97(chip, 0, AC97_CD, 0x8808);
349 oxygen_write_ac97(chip, 0, AC97_VIDEO, 0x8808);
350 oxygen_write_ac97(chip, 0, AC97_AUX, 0x8808);
351 oxygen_write_ac97(chip, 0, AC97_REC_GAIN, 0x8000);
352 oxygen_write_ac97(chip, 0, AC97_CENTER_LFE_MASTER, 0x8080);
353 oxygen_write_ac97(chip, 0, AC97_SURROUND_MASTER, 0x8080);
354 /* power down unused ADCs and DACs */
355 oxygen_ac97_set_bits(chip, 0, AC97_POWERDOWN,
356 AC97_PD_PR0 | AC97_PD_PR1);
357 oxygen_ac97_set_bits(chip, 0, AC97_EXTENDED_STATUS,
358 AC97_EA_PRI | AC97_EA_PRJ | AC97_EA_PRK);
359 }
360 if (chip->has_ac97_1) {
361 oxygen_set_bits32(chip, OXYGEN_AC97_OUT_CONFIG,
362 OXYGEN_AC97_CODEC1_SLOT3 |
363 OXYGEN_AC97_CODEC1_SLOT4);
364 oxygen_write_ac97(chip, 1, AC97_RESET, 0);
365 msleep(1);
366 oxygen_write_ac97(chip, 1, AC97_MASTER, 0x0000);
367 oxygen_write_ac97(chip, 1, AC97_HEADPHONE, 0x8000);
368 oxygen_write_ac97(chip, 1, AC97_PC_BEEP, 0x8000);
369 oxygen_write_ac97(chip, 1, AC97_MIC, 0x8808);
370 oxygen_write_ac97(chip, 1, AC97_LINE, 0x8808);
371 oxygen_write_ac97(chip, 1, AC97_CD, 0x8808);
372 oxygen_write_ac97(chip, 1, AC97_VIDEO, 0x8808);
373 oxygen_write_ac97(chip, 1, AC97_AUX, 0x8808);
374 oxygen_write_ac97(chip, 1, AC97_PCM, 0x0808);
375 oxygen_write_ac97(chip, 1, AC97_REC_SEL, 0x0000);
376 oxygen_write_ac97(chip, 1, AC97_REC_GAIN, 0x0000);
377 oxygen_ac97_set_bits(chip, 1, 0x6a, 0x0040);
378 }
379 }
380
381 static void oxygen_card_free(struct snd_card *card)
382 {
383 struct oxygen *chip = card->private_data;
384
385 spin_lock_irq(&chip->reg_lock);
386 chip->interrupt_mask = 0;
387 chip->pcm_running = 0;
388 oxygen_write16(chip, OXYGEN_DMA_STATUS, 0);
389 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, 0);
390 spin_unlock_irq(&chip->reg_lock);
391 if (chip->irq >= 0) {
392 free_irq(chip->irq, chip);
393 synchronize_irq(chip->irq);
394 }
395 flush_scheduled_work();
396 chip->model->cleanup(chip);
397 mutex_destroy(&chip->mutex);
398 pci_release_regions(chip->pci);
399 pci_disable_device(chip->pci);
400 }
401
402 int __devinit oxygen_pci_probe(struct pci_dev *pci, int index, char *id,
403 int midi, const struct oxygen_model *model)
404 {
405 struct snd_card *card;
406 struct oxygen *chip;
407 int err;
408
409 card = snd_card_new(index, id, model->owner,
410 sizeof *chip + model->model_data_size);
411 if (!card)
412 return -ENOMEM;
413
414 chip = card->private_data;
415 chip->card = card;
416 chip->pci = pci;
417 chip->irq = -1;
418 chip->model = model;
419 chip->model_data = chip + 1;
420 spin_lock_init(&chip->reg_lock);
421 mutex_init(&chip->mutex);
422 INIT_WORK(&chip->spdif_input_bits_work,
423 oxygen_spdif_input_bits_changed);
424 INIT_WORK(&chip->gpio_work, oxygen_gpio_changed);
425 init_waitqueue_head(&chip->ac97_waitqueue);
426
427 err = pci_enable_device(pci);
428 if (err < 0)
429 goto err_card;
430
431 err = pci_request_regions(pci, model->chip);
432 if (err < 0) {
433 snd_printk(KERN_ERR "cannot reserve PCI resources\n");
434 goto err_pci_enable;
435 }
436
437 if (!(pci_resource_flags(pci, 0) & IORESOURCE_IO) ||
438 pci_resource_len(pci, 0) < 0x100) {
439 snd_printk(KERN_ERR "invalid PCI I/O range\n");
440 err = -ENXIO;
441 goto err_pci_regions;
442 }
443 chip->addr = pci_resource_start(pci, 0);
444
445 pci_set_master(pci);
446 snd_card_set_dev(card, &pci->dev);
447 card->private_free = oxygen_card_free;
448
449 oxygen_init(chip);
450 model->init(chip);
451
452 err = request_irq(pci->irq, oxygen_interrupt, IRQF_SHARED,
453 model->chip, chip);
454 if (err < 0) {
455 snd_printk(KERN_ERR "cannot grab interrupt %d\n", pci->irq);
456 goto err_card;
457 }
458 chip->irq = pci->irq;
459
460 strcpy(card->driver, model->chip);
461 strcpy(card->shortname, model->shortname);
462 sprintf(card->longname, "%s (rev %u) at %#lx, irq %i",
463 model->longname, chip->revision, chip->addr, chip->irq);
464 strcpy(card->mixername, model->chip);
465 snd_component_add(card, model->chip);
466
467 err = oxygen_pcm_init(chip);
468 if (err < 0)
469 goto err_card;
470
471 err = oxygen_mixer_init(chip);
472 if (err < 0)
473 goto err_card;
474
475 oxygen_write8_masked(chip, OXYGEN_MISC,
476 midi ? OXYGEN_MISC_MIDI : 0, OXYGEN_MISC_MIDI);
477 if (midi) {
478 err = snd_mpu401_uart_new(card, 0, MPU401_HW_CMIPCI,
479 chip->addr + OXYGEN_MPU401,
480 MPU401_INFO_INTEGRATED, 0, 0,
481 &chip->midi);
482 if (err < 0)
483 goto err_card;
484 }
485
486 oxygen_proc_init(chip);
487
488 spin_lock_irq(&chip->reg_lock);
489 chip->interrupt_mask |= OXYGEN_INT_SPDIF_IN_DETECT | OXYGEN_INT_AC97;
490 oxygen_write16(chip, OXYGEN_INTERRUPT_MASK, chip->interrupt_mask);
491 spin_unlock_irq(&chip->reg_lock);
492
493 err = snd_card_register(card);
494 if (err < 0)
495 goto err_card;
496
497 pci_set_drvdata(pci, card);
498 return 0;
499
500 err_pci_regions:
501 pci_release_regions(pci);
502 err_pci_enable:
503 pci_disable_device(pci);
504 err_card:
505 snd_card_free(card);
506 return err;
507 }
508 EXPORT_SYMBOL(oxygen_pci_probe);
509
510 void __devexit oxygen_pci_remove(struct pci_dev *pci)
511 {
512 snd_card_free(pci_get_drvdata(pci));
513 pci_set_drvdata(pci, NULL);
514 }
515 EXPORT_SYMBOL(oxygen_pci_remove);
WRT350N Kernel Patches