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x86: fix bootup crash in native_read_tsc()
[wrt350n-kernel.git] / drivers / ide / pci / alim15x3.c
blob130cc6e784e552e7db3f842095e2ca9b8d83a6bd
1 /*
2 * Copyright (C) 1998-2000 Michel Aubry, Maintainer
3 * Copyright (C) 1998-2000 Andrzej Krzysztofowicz, Maintainer
4 * Copyright (C) 1999-2000 CJ, cjtsai@ali.com.tw, Maintainer
5 *
6 * Copyright (C) 1998-2000 Andre Hedrick (andre@linux-ide.org)
7 * May be copied or modified under the terms of the GNU General Public License
8 * Copyright (C) 2002 Alan Cox <alan@redhat.com>
9 * ALi (now ULi M5228) support by Clear Zhang <Clear.Zhang@ali.com.tw>
10 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
11 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
12 *
13 * (U)DMA capable version of ali 1533/1543(C), 1535(D)
14 *
15 **********************************************************************
16 * 9/7/99 --Parts from the above author are included and need to be
17 * converted into standard interface, once I finish the thought.
18 *
19 * Recent changes
20 * Don't use LBA48 mode on ALi <= 0xC4
21 * Don't poke 0x79 with a non ALi northbridge
22 * Don't flip undefined bits on newer chipsets (fix Fujitsu laptop hang)
23 * Allow UDMA6 on revisions > 0xC4
24 *
25 * Documentation
26 * Chipset documentation available under NDA only
27 *
28 */
29
30 #include <linux/module.h>
31 #include <linux/types.h>
32 #include <linux/kernel.h>
33 #include <linux/pci.h>
34 #include <linux/delay.h>
35 #include <linux/hdreg.h>
36 #include <linux/ide.h>
37 #include <linux/init.h>
38 #include <linux/dmi.h>
39
40 #include <asm/io.h>
41
42 #define DISPLAY_ALI_TIMINGS
43
44 /*
45 * ALi devices are not plug in. Otherwise these static values would
46 * need to go. They ought to go away anyway
47 */
48
49 static u8 m5229_revision;
50 static u8 chip_is_1543c_e;
51 static struct pci_dev *isa_dev;
52
53 #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
54 #include <linux/stat.h>
55 #include <linux/proc_fs.h>
56
57 static u8 ali_proc = 0;
58
59 static struct pci_dev *bmide_dev;
60
61 static char *fifo[4] = {
62 "FIFO Off",
63 "FIFO On ",
64 "DMA mode",
65 "PIO mode" };
66
67 static char *udmaT[8] = {
68 "1.5T",
69 " 2T",
70 "2.5T",
71 " 3T",
72 "3.5T",
73 " 4T",
74 " 6T",
75 " 8T"
76 };
77
78 static char *channel_status[8] = {
79 "OK ",
80 "busy ",
81 "DRQ ",
82 "DRQ busy ",
83 "error ",
84 "error busy ",
85 "error DRQ ",
86 "error DRQ busy"
87 };
88
89 /**
90 * ali_get_info - generate proc file for ALi IDE
91 * @buffer: buffer to fill
92 * @addr: address of user start in buffer
93 * @offset: offset into 'file'
94 * @count: buffer count
95 *
96 * Walks the Ali devices and outputs summary data on the tuning and
97 * anything else that will help with debugging
98 */
99
100 static int ali_get_info (char *buffer, char **addr, off_t offset, int count)
101 {
102 unsigned long bibma;
103 u8 reg53h, reg5xh, reg5yh, reg5xh1, reg5yh1, c0, c1, rev, tmp;
104 char *q, *p = buffer;
105
106 /* fetch rev. */
107 pci_read_config_byte(bmide_dev, 0x08, &rev);
108 if (rev >= 0xc1) /* M1543C or newer */
109 udmaT[7] = " ???";
110 else
111 fifo[3] = " ??? ";
112
113 /* first fetch bibma: */
114
115 bibma = pci_resource_start(bmide_dev, 4);
116
117 /*
118 * at that point bibma+0x2 et bibma+0xa are byte
119 * registers to investigate:
120 */
121 c0 = inb(bibma + 0x02);
122 c1 = inb(bibma + 0x0a);
123
124 p += sprintf(p,
125 "\n Ali M15x3 Chipset.\n");
126 p += sprintf(p,
127 " ------------------\n");
128 pci_read_config_byte(bmide_dev, 0x78, &reg53h);
129 p += sprintf(p, "PCI Clock: %d.\n", reg53h);
130
131 pci_read_config_byte(bmide_dev, 0x53, &reg53h);
132 p += sprintf(p,
133 "CD_ROM FIFO:%s, CD_ROM DMA:%s\n",
134 (reg53h & 0x02) ? "Yes" : "No ",
135 (reg53h & 0x01) ? "Yes" : "No " );
136 pci_read_config_byte(bmide_dev, 0x74, &reg53h);
137 p += sprintf(p,
138 "FIFO Status: contains %d Words, runs%s%s\n\n",
139 (reg53h & 0x3f),
140 (reg53h & 0x40) ? " OVERWR" : "",
141 (reg53h & 0x80) ? " OVERRD." : "." );
142
143 p += sprintf(p,
144 "-------------------primary channel"
145 "-------------------secondary channel"
146 "---------\n\n");
147
148 pci_read_config_byte(bmide_dev, 0x09, &reg53h);
149 p += sprintf(p,
150 "channel status: %s"
151 " %s\n",
152 (reg53h & 0x20) ? "On " : "Off",
153 (reg53h & 0x10) ? "On " : "Off" );
154
155 p += sprintf(p,
156 "both channels togth: %s"
157 " %s\n",
158 (c0&0x80) ? "No " : "Yes",
159 (c1&0x80) ? "No " : "Yes" );
160
161 pci_read_config_byte(bmide_dev, 0x76, &reg53h);
162 p += sprintf(p,
163 "Channel state: %s %s\n",
164 channel_status[reg53h & 0x07],
165 channel_status[(reg53h & 0x70) >> 4] );
166
167 pci_read_config_byte(bmide_dev, 0x58, &reg5xh);
168 pci_read_config_byte(bmide_dev, 0x5c, &reg5yh);
169 p += sprintf(p,
170 "Add. Setup Timing: %dT"
171 " %dT\n",
172 (reg5xh & 0x07) ? (reg5xh & 0x07) : 8,
173 (reg5yh & 0x07) ? (reg5yh & 0x07) : 8 );
174
175 pci_read_config_byte(bmide_dev, 0x59, &reg5xh);
176 pci_read_config_byte(bmide_dev, 0x5d, &reg5yh);
177 p += sprintf(p,
178 "Command Act. Count: %dT"
179 " %dT\n"
180 "Command Rec. Count: %dT"
181 " %dT\n\n",
182 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
183 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
184 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
185 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16 );
186
187 p += sprintf(p,
188 "----------------drive0-----------drive1"
189 "------------drive0-----------drive1------\n\n");
190 p += sprintf(p,
191 "DMA enabled: %s %s"
192 " %s %s\n",
193 (c0&0x20) ? "Yes" : "No ",
194 (c0&0x40) ? "Yes" : "No ",
195 (c1&0x20) ? "Yes" : "No ",
196 (c1&0x40) ? "Yes" : "No " );
197
198 pci_read_config_byte(bmide_dev, 0x54, &reg5xh);
199 pci_read_config_byte(bmide_dev, 0x55, &reg5yh);
200 q = "FIFO threshold: %2d Words %2d Words"
201 " %2d Words %2d Words\n";
202 if (rev < 0xc1) {
203 if ((rev == 0x20) &&
204 (pci_read_config_byte(bmide_dev, 0x4f, &tmp), (tmp &= 0x20))) {
205 p += sprintf(p, q, 8, 8, 8, 8);
206 } else {
207 p += sprintf(p, q,
208 (reg5xh & 0x03) + 12,
209 ((reg5xh & 0x30)>>4) + 12,
210 (reg5yh & 0x03) + 12,
211 ((reg5yh & 0x30)>>4) + 12 );
212 }
213 } else {
214 int t1 = (tmp = (reg5xh & 0x03)) ? (tmp << 3) : 4;
215 int t2 = (tmp = ((reg5xh & 0x30)>>4)) ? (tmp << 3) : 4;
216 int t3 = (tmp = (reg5yh & 0x03)) ? (tmp << 3) : 4;
217 int t4 = (tmp = ((reg5yh & 0x30)>>4)) ? (tmp << 3) : 4;
218 p += sprintf(p, q, t1, t2, t3, t4);
219 }
220
221 #if 0
222 p += sprintf(p,
223 "FIFO threshold: %2d Words %2d Words"
224 " %2d Words %2d Words\n",
225 (reg5xh & 0x03) + 12,
226 ((reg5xh & 0x30)>>4) + 12,
227 (reg5yh & 0x03) + 12,
228 ((reg5yh & 0x30)>>4) + 12 );
229 #endif
230
231 p += sprintf(p,
232 "FIFO mode: %s %s %s %s\n",
233 fifo[((reg5xh & 0x0c) >> 2)],
234 fifo[((reg5xh & 0xc0) >> 6)],
235 fifo[((reg5yh & 0x0c) >> 2)],
236 fifo[((reg5yh & 0xc0) >> 6)] );
237
238 pci_read_config_byte(bmide_dev, 0x5a, &reg5xh);
239 pci_read_config_byte(bmide_dev, 0x5b, &reg5xh1);
240 pci_read_config_byte(bmide_dev, 0x5e, &reg5yh);
241 pci_read_config_byte(bmide_dev, 0x5f, &reg5yh1);
242
243 p += sprintf(p,/*
244 "------------------drive0-----------drive1"
245 "------------drive0-----------drive1------\n")*/
246 "Dt RW act. Cnt %2dT %2dT"
247 " %2dT %2dT\n"
248 "Dt RW rec. Cnt %2dT %2dT"
249 " %2dT %2dT\n\n",
250 (reg5xh & 0x70) ? ((reg5xh & 0x70) >> 4) : 8,
251 (reg5xh1 & 0x70) ? ((reg5xh1 & 0x70) >> 4) : 8,
252 (reg5yh & 0x70) ? ((reg5yh & 0x70) >> 4) : 8,
253 (reg5yh1 & 0x70) ? ((reg5yh1 & 0x70) >> 4) : 8,
254 (reg5xh & 0x0f) ? (reg5xh & 0x0f) : 16,
255 (reg5xh1 & 0x0f) ? (reg5xh1 & 0x0f) : 16,
256 (reg5yh & 0x0f) ? (reg5yh & 0x0f) : 16,
257 (reg5yh1 & 0x0f) ? (reg5yh1 & 0x0f) : 16 );
258
259 p += sprintf(p,
260 "-----------------------------------UDMA Timings"
261 "--------------------------------\n\n");
262
263 pci_read_config_byte(bmide_dev, 0x56, &reg5xh);
264 pci_read_config_byte(bmide_dev, 0x57, &reg5yh);
265 p += sprintf(p,
266 "UDMA: %s %s"
267 " %s %s\n"
268 "UDMA timings: %s %s"
269 " %s %s\n\n",
270 (reg5xh & 0x08) ? "OK" : "No",
271 (reg5xh & 0x80) ? "OK" : "No",
272 (reg5yh & 0x08) ? "OK" : "No",
273 (reg5yh & 0x80) ? "OK" : "No",
274 udmaT[(reg5xh & 0x07)],
275 udmaT[(reg5xh & 0x70) >> 4],
276 udmaT[reg5yh & 0x07],
277 udmaT[(reg5yh & 0x70) >> 4] );
278
279 return p-buffer; /* => must be less than 4k! */
280 }
281 #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
282
283 /**
284 * ali_set_pio_mode - set host controller for PIO mode
285 * @drive: drive
286 * @pio: PIO mode number
287 *
288 * Program the controller for the given PIO mode.
289 */
290
291 static void ali_set_pio_mode(ide_drive_t *drive, const u8 pio)
292 {
293 ide_hwif_t *hwif = HWIF(drive);
294 struct pci_dev *dev = to_pci_dev(hwif->dev);
295 int s_time, a_time, c_time;
296 u8 s_clc, a_clc, r_clc;
297 unsigned long flags;
298 int bus_speed = system_bus_clock();
299 int port = hwif->channel ? 0x5c : 0x58;
300 int portFIFO = hwif->channel ? 0x55 : 0x54;
301 u8 cd_dma_fifo = 0;
302 int unit = drive->select.b.unit & 1;
303
304 s_time = ide_pio_timings[pio].setup_time;
305 a_time = ide_pio_timings[pio].active_time;
306 if ((s_clc = (s_time * bus_speed + 999) / 1000) >= 8)
307 s_clc = 0;
308 if ((a_clc = (a_time * bus_speed + 999) / 1000) >= 8)
309 a_clc = 0;
310 c_time = ide_pio_timings[pio].cycle_time;
311
312 #if 0
313 if ((r_clc = ((c_time - s_time - a_time) * bus_speed + 999) / 1000) >= 16)
314 r_clc = 0;
315 #endif
316
317 if (!(r_clc = (c_time * bus_speed + 999) / 1000 - a_clc - s_clc)) {
318 r_clc = 1;
319 } else {
320 if (r_clc >= 16)
321 r_clc = 0;
322 }
323 local_irq_save(flags);
324
325 /*
326 * PIO mode => ATA FIFO on, ATAPI FIFO off
327 */
328 pci_read_config_byte(dev, portFIFO, &cd_dma_fifo);
329 if (drive->media==ide_disk) {
330 if (unit) {
331 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0x0F) | 0x50);
332 } else {
333 pci_write_config_byte(dev, portFIFO, (cd_dma_fifo & 0xF0) | 0x05);
334 }
335 } else {
336 if (unit) {
337 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0x0F);
338 } else {
339 pci_write_config_byte(dev, portFIFO, cd_dma_fifo & 0xF0);
340 }
341 }
342
343 pci_write_config_byte(dev, port, s_clc);
344 pci_write_config_byte(dev, port+drive->select.b.unit+2, (a_clc << 4) | r_clc);
345 local_irq_restore(flags);
346
347 /*
348 * setup active rec
349 * { 70, 165, 365 }, PIO Mode 0
350 * { 50, 125, 208 }, PIO Mode 1
351 * { 30, 100, 110 }, PIO Mode 2
352 * { 30, 80, 70 }, PIO Mode 3 with IORDY
353 * { 25, 70, 25 }, PIO Mode 4 with IORDY ns
354 * { 20, 50, 30 } PIO Mode 5 with IORDY (nonstandard)
355 */
356 }
357
358 /**
359 * ali_udma_filter - compute UDMA mask
360 * @drive: IDE device
361 *
362 * Return available UDMA modes.
363 *
364 * The actual rules for the ALi are:
365 * No UDMA on revisions <= 0x20
366 * Disk only for revisions < 0xC2
367 * Not WDC drives for revisions < 0xC2
368 *
369 * FIXME: WDC ifdef needs to die
370 */
371
372 static u8 ali_udma_filter(ide_drive_t *drive)
373 {
374 if (m5229_revision > 0x20 && m5229_revision < 0xC2) {
375 if (drive->media != ide_disk)
376 return 0;
377 #ifndef CONFIG_WDC_ALI15X3
378 if (chip_is_1543c_e && strstr(drive->id->model, "WDC "))
379 return 0;
380 #endif
381 }
382
383 return drive->hwif->ultra_mask;
384 }
385
386 /**
387 * ali_set_dma_mode - set host controller for DMA mode
388 * @drive: drive
389 * @speed: DMA mode
390 *
391 * Configure the hardware for the desired IDE transfer mode.
392 */
393
394 static void ali_set_dma_mode(ide_drive_t *drive, const u8 speed)
395 {
396 ide_hwif_t *hwif = HWIF(drive);
397 struct pci_dev *dev = to_pci_dev(hwif->dev);
398 u8 speed1 = speed;
399 u8 unit = (drive->select.b.unit & 0x01);
400 u8 tmpbyte = 0x00;
401 int m5229_udma = (hwif->channel) ? 0x57 : 0x56;
402
403 if (speed == XFER_UDMA_6)
404 speed1 = 0x47;
405
406 if (speed < XFER_UDMA_0) {
407 u8 ultra_enable = (unit) ? 0x7f : 0xf7;
408 /*
409 * clear "ultra enable" bit
410 */
411 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
412 tmpbyte &= ultra_enable;
413 pci_write_config_byte(dev, m5229_udma, tmpbyte);
414
415 /*
416 * FIXME: Oh, my... DMA timings are never set.
417 */
418 } else {
419 pci_read_config_byte(dev, m5229_udma, &tmpbyte);
420 tmpbyte &= (0x0f << ((1-unit) << 2));
421 /*
422 * enable ultra dma and set timing
423 */
424 tmpbyte |= ((0x08 | ((4-speed1)&0x07)) << (unit << 2));
425 pci_write_config_byte(dev, m5229_udma, tmpbyte);
426 if (speed >= XFER_UDMA_3) {
427 pci_read_config_byte(dev, 0x4b, &tmpbyte);
428 tmpbyte |= 1;
429 pci_write_config_byte(dev, 0x4b, tmpbyte);
430 }
431 }
432 }
433
434 /**
435 * ali15x3_dma_setup - begin a DMA phase
436 * @drive: target device
437 *
438 * Returns 1 if the DMA cannot be performed, zero on success.
439 */
440
441 static int ali15x3_dma_setup(ide_drive_t *drive)
442 {
443 if (m5229_revision < 0xC2 && drive->media != ide_disk) {
444 if (rq_data_dir(drive->hwif->hwgroup->rq))
445 return 1; /* try PIO instead of DMA */
446 }
447 return ide_dma_setup(drive);
448 }
449
450 /**
451 * init_chipset_ali15x3 - Initialise an ALi IDE controller
452 * @dev: PCI device
453 * @name: Name of the controller
454 *
455 * This function initializes the ALI IDE controller and where
456 * appropriate also sets up the 1533 southbridge.
457 */
458
459 static unsigned int __devinit init_chipset_ali15x3 (struct pci_dev *dev, const char *name)
460 {
461 unsigned long flags;
462 u8 tmpbyte;
463 struct pci_dev *north = pci_get_slot(dev->bus, PCI_DEVFN(0,0));
464
465 m5229_revision = dev->revision;
466
467 isa_dev = pci_get_device(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, NULL);
468
469 #if defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS)
470 if (!ali_proc) {
471 ali_proc = 1;
472 bmide_dev = dev;
473 ide_pci_create_host_proc("ali", ali_get_info);
474 }
475 #endif /* defined(DISPLAY_ALI_TIMINGS) && defined(CONFIG_IDE_PROC_FS) */
476
477 local_irq_save(flags);
478
479 if (m5229_revision < 0xC2) {
480 /*
481 * revision 0x20 (1543-E, 1543-F)
482 * revision 0xC0, 0xC1 (1543C-C, 1543C-D, 1543C-E)
483 * clear CD-ROM DMA write bit, m5229, 0x4b, bit 7
484 */
485 pci_read_config_byte(dev, 0x4b, &tmpbyte);
486 /*
487 * clear bit 7
488 */
489 pci_write_config_byte(dev, 0x4b, tmpbyte & 0x7F);
490 /*
491 * check m1533, 0x5e, bit 1~4 == 1001 => & 00011110 = 00010010
492 */
493 if (m5229_revision >= 0x20 && isa_dev) {
494 pci_read_config_byte(isa_dev, 0x5e, &tmpbyte);
495 chip_is_1543c_e = ((tmpbyte & 0x1e) == 0x12) ? 1: 0;
496 }
497 goto out;
498 }
499
500 /*
501 * 1543C-B?, 1535, 1535D, 1553
502 * Note 1: not all "motherboard" support this detection
503 * Note 2: if no udma 66 device, the detection may "error".
504 * but in this case, we will not set the device to
505 * ultra 66, the detection result is not important
506 */
507
508 /*
509 * enable "Cable Detection", m5229, 0x4b, bit3
510 */
511 pci_read_config_byte(dev, 0x4b, &tmpbyte);
512 pci_write_config_byte(dev, 0x4b, tmpbyte | 0x08);
513
514 /*
515 * We should only tune the 1533 enable if we are using an ALi
516 * North bridge. We might have no north found on some zany
517 * box without a device at 0:0.0. The ALi bridge will be at
518 * 0:0.0 so if we didn't find one we know what is cooking.
519 */
520 if (north && north->vendor != PCI_VENDOR_ID_AL)
521 goto out;
522
523 if (m5229_revision < 0xC5 && isa_dev)
524 {
525 /*
526 * set south-bridge's enable bit, m1533, 0x79
527 */
528
529 pci_read_config_byte(isa_dev, 0x79, &tmpbyte);
530 if (m5229_revision == 0xC2) {
531 /*
532 * 1543C-B0 (m1533, 0x79, bit 2)
533 */
534 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x04);
535 } else if (m5229_revision >= 0xC3) {
536 /*
537 * 1553/1535 (m1533, 0x79, bit 1)
538 */
539 pci_write_config_byte(isa_dev, 0x79, tmpbyte | 0x02);
540 }
541 }
542
543 out:
544 /*
545 * CD_ROM DMA on (m5229, 0x53, bit0)
546 * Enable this bit even if we want to use PIO.
547 * PIO FIFO off (m5229, 0x53, bit1)
548 * The hardware will use 0x54h and 0x55h to control PIO FIFO.
549 * (Not on later devices it seems)
550 *
551 * 0x53 changes meaning on later revs - we must no touch
552 * bit 1 on them. Need to check if 0x20 is the right break.
553 */
554 if (m5229_revision >= 0x20) {
555 pci_read_config_byte(dev, 0x53, &tmpbyte);
556
557 if (m5229_revision <= 0x20)
558 tmpbyte = (tmpbyte & (~0x02)) | 0x01;
559 else if (m5229_revision == 0xc7 || m5229_revision == 0xc8)
560 tmpbyte |= 0x03;
561 else
562 tmpbyte |= 0x01;
563
564 pci_write_config_byte(dev, 0x53, tmpbyte);
565 }
566 pci_dev_put(north);
567 pci_dev_put(isa_dev);
568 local_irq_restore(flags);
569 return 0;
570 }
571
572 /*
573 * Cable special cases
574 */
575
576 static const struct dmi_system_id cable_dmi_table[] = {
577 {
578 .ident = "HP Pavilion N5430",
579 .matches = {
580 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
581 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"),
582 },
583 },
584 {
585 .ident = "Toshiba Satellite S1800-814",
586 .matches = {
587 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
588 DMI_MATCH(DMI_PRODUCT_NAME, "S1800-814"),
589 },
590 },
591 { }
592 };
593
594 static int ali_cable_override(struct pci_dev *pdev)
595 {
596 /* Fujitsu P2000 */
597 if (pdev->subsystem_vendor == 0x10CF &&
598 pdev->subsystem_device == 0x10AF)
599 return 1;
600
601 /* Mitac 8317 (Winbook-A) and relatives */
602 if (pdev->subsystem_vendor == 0x1071 &&
603 pdev->subsystem_device == 0x8317)
604 return 1;
605
606 /* Systems by DMI */
607 if (dmi_check_system(cable_dmi_table))
608 return 1;
609
610 return 0;
611 }
612
613 /**
614 * ata66_ali15x3 - check for UDMA 66 support
615 * @hwif: IDE interface
616 *
617 * This checks if the controller and the cable are capable
618 * of UDMA66 transfers. It doesn't check the drives.
619 * But see note 2 below!
620 *
621 * FIXME: frobs bits that are not defined on newer ALi devicea
622 */
623
624 static u8 __devinit ata66_ali15x3(ide_hwif_t *hwif)
625 {
626 struct pci_dev *dev = to_pci_dev(hwif->dev);
627 unsigned long flags;
628 u8 cbl = ATA_CBL_PATA40, tmpbyte;
629
630 local_irq_save(flags);
631
632 if (m5229_revision >= 0xC2) {
633 /*
634 * m5229 80-pin cable detection (from Host View)
635 *
636 * 0x4a bit0 is 0 => primary channel has 80-pin
637 * 0x4a bit1 is 0 => secondary channel has 80-pin
638 *
639 * Certain laptops use short but suitable cables
640 * and don't implement the detect logic.
641 */
642 if (ali_cable_override(dev))
643 cbl = ATA_CBL_PATA40_SHORT;
644 else {
645 pci_read_config_byte(dev, 0x4a, &tmpbyte);
646 if ((tmpbyte & (1 << hwif->channel)) == 0)
647 cbl = ATA_CBL_PATA80;
648 }
649 }
650
651 local_irq_restore(flags);
652
653 return cbl;
654 }
655
656 /**
657 * init_hwif_common_ali15x3 - Set up ALI IDE hardware
658 * @hwif: IDE interface
659 *
660 * Initialize the IDE structure side of the ALi 15x3 driver.
661 */
662
663 static void __devinit init_hwif_common_ali15x3 (ide_hwif_t *hwif)
664 {
665 hwif->set_pio_mode = &ali_set_pio_mode;
666 hwif->set_dma_mode = &ali_set_dma_mode;
667 hwif->udma_filter = &ali_udma_filter;
668
669 if (hwif->dma_base == 0)
670 return;
671
672 hwif->dma_setup = &ali15x3_dma_setup;
673
674 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
675 hwif->cbl = ata66_ali15x3(hwif);
676 }
677
678 /**
679 * init_hwif_ali15x3 - Initialize the ALI IDE x86 stuff
680 * @hwif: interface to configure
681 *
682 * Obtain the IRQ tables for an ALi based IDE solution on the PC
683 * class platforms. This part of the code isn't applicable to the
684 * Sparc systems
685 */
686
687 static void __devinit init_hwif_ali15x3 (ide_hwif_t *hwif)
688 {
689 struct pci_dev *dev = to_pci_dev(hwif->dev);
690 u8 ideic, inmir;
691 s8 irq_routing_table[] = { -1, 9, 3, 10, 4, 5, 7, 6,
692 1, 11, 0, 12, 0, 14, 0, 15 };
693 int irq = -1;
694
695 if (dev->device == PCI_DEVICE_ID_AL_M5229)
696 hwif->irq = hwif->channel ? 15 : 14;
697
698 if (isa_dev) {
699 /*
700 * read IDE interface control
701 */
702 pci_read_config_byte(isa_dev, 0x58, &ideic);
703
704 /* bit0, bit1 */
705 ideic = ideic & 0x03;
706
707 /* get IRQ for IDE Controller */
708 if ((hwif->channel && ideic == 0x03) ||
709 (!hwif->channel && !ideic)) {
710 /*
711 * get SIRQ1 routing table
712 */
713 pci_read_config_byte(isa_dev, 0x44, &inmir);
714 inmir = inmir & 0x0f;
715 irq = irq_routing_table[inmir];
716 } else if (hwif->channel && !(ideic & 0x01)) {
717 /*
718 * get SIRQ2 routing table
719 */
720 pci_read_config_byte(isa_dev, 0x75, &inmir);
721 inmir = inmir & 0x0f;
722 irq = irq_routing_table[inmir];
723 }
724 if(irq >= 0)
725 hwif->irq = irq;
726 }
727
728 init_hwif_common_ali15x3(hwif);
729 }
730
731 /**
732 * init_dma_ali15x3 - set up DMA on ALi15x3
733 * @hwif: IDE interface
734 * @dmabase: DMA interface base PCI address
735 *
736 * Set up the DMA functionality on the ALi 15x3. For the ALi
737 * controllers this is generic so we can let the generic code do
738 * the actual work.
739 */
740
741 static void __devinit init_dma_ali15x3 (ide_hwif_t *hwif, unsigned long dmabase)
742 {
743 if (m5229_revision < 0x20)
744 return;
745 if (!hwif->channel)
746 outb(inb(dmabase + 2) & 0x60, dmabase + 2);
747 ide_setup_dma(hwif, dmabase);
748 }
749
750 static const struct ide_port_info ali15x3_chipset __devinitdata = {
751 .name = "ALI15X3",
752 .init_chipset = init_chipset_ali15x3,
753 .init_hwif = init_hwif_ali15x3,
754 .init_dma = init_dma_ali15x3,
755 .host_flags = IDE_HFLAG_BOOTABLE,
756 .pio_mask = ATA_PIO5,
757 .swdma_mask = ATA_SWDMA2,
758 .mwdma_mask = ATA_MWDMA2,
759 };
760
761 /**
762 * alim15x3_init_one - set up an ALi15x3 IDE controller
763 * @dev: PCI device to set up
764 *
765 * Perform the actual set up for an ALi15x3 that has been found by the
766 * hot plug layer.
767 */
768
769 static int __devinit alim15x3_init_one(struct pci_dev *dev, const struct pci_device_id *id)
770 {
771 static struct pci_device_id ati_rs100[] = {
772 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100) },
773 { },
774 };
775
776 struct ide_port_info d = ali15x3_chipset;
777 u8 rev = dev->revision, idx = id->driver_data;
778
779 if (pci_dev_present(ati_rs100))
780 printk(KERN_WARNING "alim15x3: ATI Radeon IGP Northbridge is not yet fully tested.\n");
781
782 /* don't use LBA48 DMA on ALi devices before rev 0xC5 */
783 if (rev <= 0xC4)
784 d.host_flags |= IDE_HFLAG_NO_LBA48_DMA;
785
786 if (rev >= 0x20) {
787 if (rev == 0x20)
788 d.host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
789
790 if (rev < 0xC2)
791 d.udma_mask = ATA_UDMA2;
792 else if (rev == 0xC2 || rev == 0xC3)
793 d.udma_mask = ATA_UDMA4;
794 else if (rev == 0xC4)
795 d.udma_mask = ATA_UDMA5;
796 else
797 d.udma_mask = ATA_UDMA6;
798 }
799
800 if (idx == 0)
801 d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
802
803 #if defined(CONFIG_SPARC64)
804 d.init_hwif = init_hwif_common_ali15x3;
805 #endif /* CONFIG_SPARC64 */
806 return ide_setup_pci_device(dev, &d);
807 }
808
809
810 static const struct pci_device_id alim15x3_pci_tbl[] = {
811 { PCI_VDEVICE(AL, PCI_DEVICE_ID_AL_M5229), 0 },
812 { PCI_VDEVICE(AL, PCI_DEVICE_ID_AL_M5228), 1 },
813 { 0, },
814 };
815 MODULE_DEVICE_TABLE(pci, alim15x3_pci_tbl);
816
817 static struct pci_driver driver = {
818 .name = "ALI15x3_IDE",
819 .id_table = alim15x3_pci_tbl,
820 .probe = alim15x3_init_one,
821 };
822
823 static int __init ali15x3_ide_init(void)
824 {
825 return ide_pci_register_driver(&driver);
826 }
827
828 module_init(ali15x3_ide_init);
829
830 MODULE_AUTHOR("Michael Aubry, Andrzej Krzysztofowicz, CJ, Andre Hedrick, Alan Cox");
831 MODULE_DESCRIPTION("PCI driver module for ALi 15x3 IDE");
832 MODULE_LICENSE("GPL");
WRT350N Kernel Patches