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x86: fix bootup crash in native_read_tsc()
[wrt350n-kernel.git] / drivers / net / wireless / ath5k / hw.c
blob3a4bf4035a2337eb7bc0d33ea52de1db00c50e8e
1 /*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
8 *
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 *
21 */
22
23 /*
24 * HW related functions for Atheros Wireless LAN devices.
25 */
26
27 #include <linux/pci.h>
28 #include <linux/delay.h>
29
30 #include "reg.h"
31 #include "base.h"
32 #include "debug.h"
33
34 /*Rate tables*/
35 static const struct ath5k_rate_table ath5k_rt_11a = AR5K_RATES_11A;
36 static const struct ath5k_rate_table ath5k_rt_11b = AR5K_RATES_11B;
37 static const struct ath5k_rate_table ath5k_rt_11g = AR5K_RATES_11G;
38 static const struct ath5k_rate_table ath5k_rt_turbo = AR5K_RATES_TURBO;
39 static const struct ath5k_rate_table ath5k_rt_xr = AR5K_RATES_XR;
40
41 /*Prototypes*/
42 static int ath5k_hw_nic_reset(struct ath5k_hw *, u32);
43 static int ath5k_hw_nic_wakeup(struct ath5k_hw *, int, bool);
44 static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
45 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
46 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
47 unsigned int, unsigned int);
48 static bool ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
49 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
50 unsigned int);
51 static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *, struct ath5k_desc *);
52 static int ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *, struct ath5k_desc *,
53 unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
54 unsigned int, unsigned int, unsigned int, unsigned int, unsigned int,
55 unsigned int, unsigned int);
56 static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *, struct ath5k_desc *);
57 static int ath5k_hw_proc_new_rx_status(struct ath5k_hw *, struct ath5k_desc *);
58 static int ath5k_hw_proc_old_rx_status(struct ath5k_hw *, struct ath5k_desc *);
59 static int ath5k_hw_get_capabilities(struct ath5k_hw *);
60
61 static int ath5k_eeprom_init(struct ath5k_hw *);
62 static int ath5k_eeprom_read_mac(struct ath5k_hw *, u8 *);
63
64 static int ath5k_hw_enable_pspoll(struct ath5k_hw *, u8 *, u16);
65 static int ath5k_hw_disable_pspoll(struct ath5k_hw *);
66
67 /*
68 * Enable to overwrite the country code (use "00" for debug)
69 */
70 #if 0
71 #define COUNTRYCODE "00"
72 #endif
73
74 /*******************\
75 General Functions
76 \*******************/
77
78 /*
79 * Functions used internaly
80 */
81
82 static inline unsigned int ath5k_hw_htoclock(unsigned int usec, bool turbo)
83 {
84 return turbo == true ? (usec * 80) : (usec * 40);
85 }
86
87 static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, bool turbo)
88 {
89 return turbo == true ? (clock / 80) : (clock / 40);
90 }
91
92 /*
93 * Check if a register write has been completed
94 */
95 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val,
96 bool is_set)
97 {
98 int i;
99 u32 data;
100
101 for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
102 data = ath5k_hw_reg_read(ah, reg);
103 if ((is_set == true) && (data & flag))
104 break;
105 else if ((data & flag) == val)
106 break;
107 udelay(15);
108 }
109
110 return (i <= 0) ? -EAGAIN : 0;
111 }
112
113
114 /***************************************\
115 Attach/Detach Functions
116 \***************************************/
117
118 /*
119 * Check if the device is supported and initialize the needed structs
120 */
121 struct ath5k_hw *ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version)
122 {
123 struct ath5k_hw *ah;
124 u8 mac[ETH_ALEN];
125 int ret;
126 u32 srev;
127
128 /*If we passed the test malloc a ath5k_hw struct*/
129 ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
130 if (ah == NULL) {
131 ret = -ENOMEM;
132 ATH5K_ERR(sc, "out of memory\n");
133 goto err;
134 }
135
136 ah->ah_sc = sc;
137 ah->ah_iobase = sc->iobase;
138
139 /*
140 * HW information
141 */
142
143 /* Get reg domain from eeprom */
144 ath5k_get_regdomain(ah);
145
146 ah->ah_op_mode = IEEE80211_IF_TYPE_STA;
147 ah->ah_radar.r_enabled = AR5K_TUNE_RADAR_ALERT;
148 ah->ah_turbo = false;
149 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
150 ah->ah_imr = 0;
151 ah->ah_atim_window = 0;
152 ah->ah_aifs = AR5K_TUNE_AIFS;
153 ah->ah_cw_min = AR5K_TUNE_CWMIN;
154 ah->ah_limit_tx_retries = AR5K_INIT_TX_RETRY;
155 ah->ah_software_retry = false;
156 ah->ah_ant_diversity = AR5K_TUNE_ANT_DIVERSITY;
157
158 /*
159 * Set the mac revision based on the pci id
160 */
161 ah->ah_version = mac_version;
162
163 /*Fill the ath5k_hw struct with the needed functions*/
164 if (ah->ah_version == AR5K_AR5212)
165 ah->ah_magic = AR5K_EEPROM_MAGIC_5212;
166 else if (ah->ah_version == AR5K_AR5211)
167 ah->ah_magic = AR5K_EEPROM_MAGIC_5211;
168
169 if (ah->ah_version == AR5K_AR5212) {
170 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc;
171 ah->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
172 ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status;
173 } else {
174 ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc;
175 ah->ah_setup_xtx_desc = ath5k_hw_setup_xr_tx_desc;
176 ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status;
177 }
178
179 if (ah->ah_version == AR5K_AR5212)
180 ah->ah_proc_rx_desc = ath5k_hw_proc_new_rx_status;
181 else if (ah->ah_version <= AR5K_AR5211)
182 ah->ah_proc_rx_desc = ath5k_hw_proc_old_rx_status;
183
184 /* Bring device out of sleep and reset it's units */
185 ret = ath5k_hw_nic_wakeup(ah, AR5K_INIT_MODE, true);
186 if (ret)
187 goto err_free;
188
189 /* Get MAC, PHY and RADIO revisions */
190 srev = ath5k_hw_reg_read(ah, AR5K_SREV);
191 ah->ah_mac_srev = srev;
192 ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
193 ah->ah_mac_revision = AR5K_REG_MS(srev, AR5K_SREV_REV);
194 ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
195 0xffffffff;
196 ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
197 CHANNEL_5GHZ);
198
199 if (ah->ah_version == AR5K_AR5210)
200 ah->ah_radio_2ghz_revision = 0;
201 else
202 ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
203 CHANNEL_2GHZ);
204
205 /* Return on unsuported chips (unsupported eeprom etc) */
206 if(srev >= AR5K_SREV_VER_AR5416){
207 ATH5K_ERR(sc, "Device not yet supported.\n");
208 ret = -ENODEV;
209 goto err_free;
210 }
211
212 /* Identify single chip solutions */
213 if((srev <= AR5K_SREV_VER_AR5414) &&
214 (srev >= AR5K_SREV_VER_AR2424)) {
215 ah->ah_single_chip = true;
216 } else {
217 ah->ah_single_chip = false;
218 }
219
220 /* Single chip radio */
221 if (ah->ah_radio_2ghz_revision == ah->ah_radio_5ghz_revision)
222 ah->ah_radio_2ghz_revision = 0;
223
224 /* Identify the radio chip*/
225 if (ah->ah_version == AR5K_AR5210) {
226 ah->ah_radio = AR5K_RF5110;
227 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112) {
228 ah->ah_radio = AR5K_RF5111;
229 } else if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_SC1) {
230 ah->ah_radio = AR5K_RF5112;
231 } else {
232 ah->ah_radio = AR5K_RF5413;
233 }
234
235 ah->ah_phy = AR5K_PHY(0);
236
237 /*
238 * Get card capabilities, values, ...
239 */
240
241 ret = ath5k_eeprom_init(ah);
242 if (ret) {
243 ATH5K_ERR(sc, "unable to init EEPROM\n");
244 goto err_free;
245 }
246
247 /* Get misc capabilities */
248 ret = ath5k_hw_get_capabilities(ah);
249 if (ret) {
250 ATH5K_ERR(sc, "unable to get device capabilities: 0x%04x\n",
251 sc->pdev->device);
252 goto err_free;
253 }
254
255 /* Get MAC address */
256 ret = ath5k_eeprom_read_mac(ah, mac);
257 if (ret) {
258 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
259 sc->pdev->device);
260 goto err_free;
261 }
262
263 ath5k_hw_set_lladdr(ah, mac);
264 /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
265 memset(ah->ah_bssid, 0xff, ETH_ALEN);
266 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
267 ath5k_hw_set_opmode(ah);
268
269 ath5k_hw_set_rfgain_opt(ah);
270
271 return ah;
272 err_free:
273 kfree(ah);
274 err:
275 return ERR_PTR(ret);
276 }
277
278 /*
279 * Bring up MAC + PHY Chips
280 */
281 static int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
282 {
283 u32 turbo, mode, clock;
284 int ret;
285
286 turbo = 0;
287 mode = 0;
288 clock = 0;
289
290 ATH5K_TRACE(ah->ah_sc);
291
292 /* Wakeup the device */
293 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
294 if (ret) {
295 ATH5K_ERR(ah->ah_sc, "failed to wakeup the MAC Chip\n");
296 return ret;
297 }
298
299 if (ah->ah_version != AR5K_AR5210) {
300 /*
301 * Get channel mode flags
302 */
303
304 if (ah->ah_radio >= AR5K_RF5112) {
305 mode = AR5K_PHY_MODE_RAD_RF5112;
306 clock = AR5K_PHY_PLL_RF5112;
307 } else {
308 mode = AR5K_PHY_MODE_RAD_RF5111; /*Zero*/
309 clock = AR5K_PHY_PLL_RF5111; /*Zero*/
310 }
311
312 if (flags & CHANNEL_2GHZ) {
313 mode |= AR5K_PHY_MODE_FREQ_2GHZ;
314 clock |= AR5K_PHY_PLL_44MHZ;
315
316 if (flags & CHANNEL_CCK) {
317 mode |= AR5K_PHY_MODE_MOD_CCK;
318 } else if (flags & CHANNEL_OFDM) {
319 /* XXX Dynamic OFDM/CCK is not supported by the
320 * AR5211 so we set MOD_OFDM for plain g (no
321 * CCK headers) operation. We need to test
322 * this, 5211 might support ofdm-only g after
323 * all, there are also initial register values
324 * in the code for g mode (see initvals.c). */
325 if (ah->ah_version == AR5K_AR5211)
326 mode |= AR5K_PHY_MODE_MOD_OFDM;
327 else
328 mode |= AR5K_PHY_MODE_MOD_DYN;
329 } else {
330 ATH5K_ERR(ah->ah_sc,
331 "invalid radio modulation mode\n");
332 return -EINVAL;
333 }
334 } else if (flags & CHANNEL_5GHZ) {
335 mode |= AR5K_PHY_MODE_FREQ_5GHZ;
336 clock |= AR5K_PHY_PLL_40MHZ;
337
338 if (flags & CHANNEL_OFDM)
339 mode |= AR5K_PHY_MODE_MOD_OFDM;
340 else {
341 ATH5K_ERR(ah->ah_sc,
342 "invalid radio modulation mode\n");
343 return -EINVAL;
344 }
345 } else {
346 ATH5K_ERR(ah->ah_sc, "invalid radio frequency mode\n");
347 return -EINVAL;
348 }
349
350 if (flags & CHANNEL_TURBO)
351 turbo = AR5K_PHY_TURBO_MODE | AR5K_PHY_TURBO_SHORT;
352 } else { /* Reset the device */
353
354 /* ...enable Atheros turbo mode if requested */
355 if (flags & CHANNEL_TURBO)
356 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE,
357 AR5K_PHY_TURBO);
358 }
359
360 /* ...reset chipset and PCI device */
361 if (ah->ah_single_chip == false && ath5k_hw_nic_reset(ah,
362 AR5K_RESET_CTL_CHIP | AR5K_RESET_CTL_PCI)) {
363 ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip + PCI\n");
364 return -EIO;
365 }
366
367 if (ah->ah_version == AR5K_AR5210)
368 udelay(2300);
369
370 /* ...wakeup again!*/
371 ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
372 if (ret) {
373 ATH5K_ERR(ah->ah_sc, "failed to resume the MAC Chip\n");
374 return ret;
375 }
376
377 /* ...final warm reset */
378 if (ath5k_hw_nic_reset(ah, 0)) {
379 ATH5K_ERR(ah->ah_sc, "failed to warm reset the MAC Chip\n");
380 return -EIO;
381 }
382
383 if (ah->ah_version != AR5K_AR5210) {
384 /* ...set the PHY operating mode */
385 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL);
386 udelay(300);
387
388 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE);
389 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO);
390 }
391
392 return 0;
393 }
394
395 /*
396 * Get the rate table for a specific operation mode
397 */
398 const struct ath5k_rate_table *ath5k_hw_get_rate_table(struct ath5k_hw *ah,
399 unsigned int mode)
400 {
401 ATH5K_TRACE(ah->ah_sc);
402
403 if (!test_bit(mode, ah->ah_capabilities.cap_mode))
404 return NULL;
405
406 /* Get rate tables */
407 switch (mode) {
408 case MODE_IEEE80211A:
409 return &ath5k_rt_11a;
410 case MODE_ATHEROS_TURBO:
411 return &ath5k_rt_turbo;
412 case MODE_IEEE80211B:
413 return &ath5k_rt_11b;
414 case MODE_IEEE80211G:
415 return &ath5k_rt_11g;
416 case MODE_ATHEROS_TURBOG:
417 return &ath5k_rt_xr;
418 }
419
420 return NULL;
421 }
422
423 /*
424 * Free the ath5k_hw struct
425 */
426 void ath5k_hw_detach(struct ath5k_hw *ah)
427 {
428 ATH5K_TRACE(ah->ah_sc);
429
430 if (ah->ah_rf_banks != NULL)
431 kfree(ah->ah_rf_banks);
432
433 /* assume interrupts are down */
434 kfree(ah);
435 }
436
437 /****************************\
438 Reset function and helpers
439 \****************************/
440
441 /**
442 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
443 *
444 * @ah: the &struct ath5k_hw
445 * @channel: the currently set channel upon reset
446 *
447 * Write the OFDM timings for the AR5212 upon reset. This is a helper for
448 * ath5k_hw_reset(). This seems to tune the PLL a specified frequency
449 * depending on the bandwidth of the channel.
450 *
451 */
452 static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
453 struct ieee80211_channel *channel)
454 {
455 /* Get exponent and mantissa and set it */
456 u32 coef_scaled, coef_exp, coef_man,
457 ds_coef_exp, ds_coef_man, clock;
458
459 if (!(ah->ah_version == AR5K_AR5212) ||
460 !(channel->val & CHANNEL_OFDM))
461 BUG();
462
463 /* Seems there are two PLLs, one for baseband sampling and one
464 * for tuning. Tuning basebands are 40 MHz or 80MHz when in
465 * turbo. */
466 clock = channel->val & CHANNEL_TURBO ? 80 : 40;
467 coef_scaled = ((5 * (clock << 24)) / 2) /
468 channel->freq;
469
470 for (coef_exp = 31; coef_exp > 0; coef_exp--)
471 if ((coef_scaled >> coef_exp) & 0x1)
472 break;
473
474 if (!coef_exp)
475 return -EINVAL;
476
477 coef_exp = 14 - (coef_exp - 24);
478 coef_man = coef_scaled +
479 (1 << (24 - coef_exp - 1));
480 ds_coef_man = coef_man >> (24 - coef_exp);
481 ds_coef_exp = coef_exp - 16;
482
483 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
484 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
485 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
486 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
487
488 return 0;
489 }
490
491 /**
492 * ath5k_hw_write_rate_duration - set rate duration during hw resets
493 *
494 * @ah: the &struct ath5k_hw
495 * @driver_mode: one of enum ieee80211_phymode or our one of our own
496 * vendor modes
497 *
498 * Write the rate duration table for the current mode upon hw reset. This
499 * is a helper for ath5k_hw_reset(). It seems all this is doing is setting
500 * an ACK timeout for the hardware for the current mode for each rate. The
501 * rates which are capable of short preamble (802.11b rates 2Mbps, 5.5Mbps,
502 * and 11Mbps) have another register for the short preamble ACK timeout
503 * calculation.
504 *
505 */
506 static inline void ath5k_hw_write_rate_duration(struct ath5k_hw *ah,
507 unsigned int driver_mode)
508 {
509 struct ath5k_softc *sc = ah->ah_sc;
510 const struct ath5k_rate_table *rt;
511 unsigned int i;
512
513 /* Get rate table for the current operating mode */
514 rt = ath5k_hw_get_rate_table(ah,
515 driver_mode);
516
517 /* Write rate duration table */
518 for (i = 0; i < rt->rate_count; i++) {
519 const struct ath5k_rate *rate, *control_rate;
520 u32 reg;
521 u16 tx_time;
522
523 rate = &rt->rates[i];
524 control_rate = &rt->rates[rate->control_rate];
525
526 /* Set ACK timeout */
527 reg = AR5K_RATE_DUR(rate->rate_code);
528
529 /* An ACK frame consists of 10 bytes. If you add the FCS,
530 * which ieee80211_generic_frame_duration() adds,
531 * its 14 bytes. Note we use the control rate and not the
532 * actual rate for this rate. See mac80211 tx.c
533 * ieee80211_duration() for a brief description of
534 * what rate we should choose to TX ACKs. */
535 tx_time = ieee80211_generic_frame_duration(sc->hw,
536 sc->vif, 10, control_rate->rate_kbps/100);
537
538 ath5k_hw_reg_write(ah, tx_time, reg);
539
540 if (!HAS_SHPREAMBLE(i))
541 continue;
542
543 /*
544 * We're not distinguishing short preamble here,
545 * This is true, all we'll get is a longer value here
546 * which is not necessarilly bad. We could use
547 * export ieee80211_frame_duration() but that needs to be
548 * fixed first to be properly used by mac802111 drivers:
549 *
550 * - remove erp stuff and let the routine figure ofdm
551 * erp rates
552 * - remove passing argument ieee80211_local as
553 * drivers don't have access to it
554 * - move drivers using ieee80211_generic_frame_duration()
555 * to this
556 */
557 ath5k_hw_reg_write(ah, tx_time,
558 reg + (AR5K_SET_SHORT_PREAMBLE << 2));
559 }
560 }
561
562 /*
563 * Main reset function
564 */
565 int ath5k_hw_reset(struct ath5k_hw *ah, enum ieee80211_if_types op_mode,
566 struct ieee80211_channel *channel, bool change_channel)
567 {
568 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
569 u32 data, s_seq, s_ant, s_led[3];
570 unsigned int i, mode, freq, ee_mode, ant[2], driver_mode = -1;
571 int ret;
572
573 ATH5K_TRACE(ah->ah_sc);
574
575 s_seq = 0;
576 s_ant = 0;
577 ee_mode = 0;
578 freq = 0;
579 mode = 0;
580
581 /*
582 * Save some registers before a reset
583 */
584 /*DCU/Antenna selection not available on 5210*/
585 if (ah->ah_version != AR5K_AR5210) {
586 if (change_channel == true) {
587 /* Seq number for queue 0 -do this for all queues ? */
588 s_seq = ath5k_hw_reg_read(ah,
589 AR5K_QUEUE_DFS_SEQNUM(0));
590 /*Default antenna*/
591 s_ant = ath5k_hw_reg_read(ah, AR5K_DEFAULT_ANTENNA);
592 }
593 }
594
595 /*GPIOs*/
596 s_led[0] = ath5k_hw_reg_read(ah, AR5K_PCICFG) & AR5K_PCICFG_LEDSTATE;
597 s_led[1] = ath5k_hw_reg_read(ah, AR5K_GPIOCR);
598 s_led[2] = ath5k_hw_reg_read(ah, AR5K_GPIODO);
599
600 if (change_channel == true && ah->ah_rf_banks != NULL)
601 ath5k_hw_get_rf_gain(ah);
602
603
604 /*Wakeup the device*/
605 ret = ath5k_hw_nic_wakeup(ah, channel->val, false);
606 if (ret)
607 return ret;
608
609 /*
610 * Initialize operating mode
611 */
612 ah->ah_op_mode = op_mode;
613
614 /*
615 * 5111/5112 Settings
616 * 5210 only comes with RF5110
617 */
618 if (ah->ah_version != AR5K_AR5210) {
619 if (ah->ah_radio != AR5K_RF5111 &&
620 ah->ah_radio != AR5K_RF5112 &&
621 ah->ah_radio != AR5K_RF5413) {
622 ATH5K_ERR(ah->ah_sc,
623 "invalid phy radio: %u\n", ah->ah_radio);
624 return -EINVAL;
625 }
626
627 switch (channel->val & CHANNEL_MODES) {
628 case CHANNEL_A:
629 mode = AR5K_INI_VAL_11A;
630 freq = AR5K_INI_RFGAIN_5GHZ;
631 ee_mode = AR5K_EEPROM_MODE_11A;
632 driver_mode = MODE_IEEE80211A;
633 break;
634 case CHANNEL_G:
635 mode = AR5K_INI_VAL_11G;
636 freq = AR5K_INI_RFGAIN_2GHZ;
637 ee_mode = AR5K_EEPROM_MODE_11G;
638 driver_mode = MODE_IEEE80211G;
639 break;
640 case CHANNEL_B:
641 mode = AR5K_INI_VAL_11B;
642 freq = AR5K_INI_RFGAIN_2GHZ;
643 ee_mode = AR5K_EEPROM_MODE_11B;
644 driver_mode = MODE_IEEE80211B;
645 break;
646 case CHANNEL_T:
647 mode = AR5K_INI_VAL_11A_TURBO;
648 freq = AR5K_INI_RFGAIN_5GHZ;
649 ee_mode = AR5K_EEPROM_MODE_11A;
650 driver_mode = MODE_ATHEROS_TURBO;
651 break;
652 /*Is this ok on 5211 too ?*/
653 case CHANNEL_TG:
654 mode = AR5K_INI_VAL_11G_TURBO;
655 freq = AR5K_INI_RFGAIN_2GHZ;
656 ee_mode = AR5K_EEPROM_MODE_11G;
657 driver_mode = MODE_ATHEROS_TURBOG;
658 break;
659 case CHANNEL_XR:
660 if (ah->ah_version == AR5K_AR5211) {
661 ATH5K_ERR(ah->ah_sc,
662 "XR mode not available on 5211");
663 return -EINVAL;
664 }
665 mode = AR5K_INI_VAL_XR;
666 freq = AR5K_INI_RFGAIN_5GHZ;
667 ee_mode = AR5K_EEPROM_MODE_11A;
668 driver_mode = MODE_IEEE80211A;
669 break;
670 default:
671 ATH5K_ERR(ah->ah_sc,
672 "invalid channel: %d\n", channel->freq);
673 return -EINVAL;
674 }
675
676 /* PHY access enable */
677 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
678
679 }
680
681 ret = ath5k_hw_write_initvals(ah, mode, change_channel);
682 if (ret)
683 return ret;
684
685 /*
686 * 5211/5212 Specific
687 */
688 if (ah->ah_version != AR5K_AR5210) {
689 /*
690 * Write initial RF gain settings
691 * This should work for both 5111/5112
692 */
693 ret = ath5k_hw_rfgain(ah, freq);
694 if (ret)
695 return ret;
696
697 mdelay(1);
698
699 /*
700 * Write some more initial register settings
701 */
702 if (ah->ah_version > AR5K_AR5211){ /* found on 5213+ */
703 ath5k_hw_reg_write(ah, 0x0002a002, AR5K_PHY(11));
704
705 if (channel->val == CHANNEL_G)
706 ath5k_hw_reg_write(ah, 0x00f80d80, AR5K_PHY(83)); /* 0x00fc0ec0 */
707 else
708 ath5k_hw_reg_write(ah, 0x00000000, AR5K_PHY(83));
709
710 ath5k_hw_reg_write(ah, 0x000001b5, 0xa228); /* 0x000009b5 */
711 ath5k_hw_reg_write(ah, 0x000009b5, 0xa228);
712 ath5k_hw_reg_write(ah, 0x0000000f, 0x8060);
713 ath5k_hw_reg_write(ah, 0x00000000, 0xa254);
714 ath5k_hw_reg_write(ah, 0x0000000e, AR5K_PHY_SCAL);
715 }
716
717 /* Fix for first revision of the RF5112 RF chipset */
718 if (ah->ah_radio >= AR5K_RF5112 &&
719 ah->ah_radio_5ghz_revision <
720 AR5K_SREV_RAD_5112A) {
721 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD,
722 AR5K_PHY_CCKTXCTL);
723 if (channel->val & CHANNEL_5GHZ)
724 data = 0xffb81020;
725 else
726 data = 0xffb80d20;
727 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL);
728 }
729
730 /*
731 * Set TX power (FIXME)
732 */
733 ret = ath5k_hw_txpower(ah, channel, AR5K_TUNE_DEFAULT_TXPOWER);
734 if (ret)
735 return ret;
736
737 /* Write rate duration table only on AR5212 and if
738 * virtual interface has already been brought up
739 * XXX: rethink this after new mode changes to
740 * mac80211 are integrated */
741 if (ah->ah_version == AR5K_AR5212 &&
742 ah->ah_sc->vif != NULL)
743 ath5k_hw_write_rate_duration(ah, driver_mode);
744
745 /*
746 * Write RF registers
747 * TODO:Does this work on 5211 (5111) ?
748 */
749 ret = ath5k_hw_rfregs(ah, channel, mode);
750 if (ret)
751 return ret;
752
753 /*
754 * Configure additional registers
755 */
756
757 /* Write OFDM timings on 5212*/
758 if (ah->ah_version == AR5K_AR5212 &&
759 channel->val & CHANNEL_OFDM) {
760 ret = ath5k_hw_write_ofdm_timings(ah, channel);
761 if (ret)
762 return ret;
763 }
764
765 /*Enable/disable 802.11b mode on 5111
766 (enable 2111 frequency converter + CCK)*/
767 if (ah->ah_radio == AR5K_RF5111) {
768 if (driver_mode == MODE_IEEE80211B)
769 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
770 AR5K_TXCFG_B_MODE);
771 else
772 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
773 AR5K_TXCFG_B_MODE);
774 }
775
776 /*
777 * Set channel and calibrate the PHY
778 */
779 ret = ath5k_hw_channel(ah, channel);
780 if (ret)
781 return ret;
782
783 /* Set antenna mode */
784 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x44),
785 ah->ah_antenna[ee_mode][0], 0xfffffc06);
786
787 /*
788 * In case a fixed antenna was set as default
789 * write the same settings on both AR5K_PHY_ANT_SWITCH_TABLE
790 * registers.
791 */
792 if (s_ant != 0){
793 if (s_ant == AR5K_ANT_FIXED_A) /* 1 - Main */
794 ant[0] = ant[1] = AR5K_ANT_FIXED_A;
795 else /* 2 - Aux */
796 ant[0] = ant[1] = AR5K_ANT_FIXED_B;
797 } else {
798 ant[0] = AR5K_ANT_FIXED_A;
799 ant[1] = AR5K_ANT_FIXED_B;
800 }
801
802 ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[0]],
803 AR5K_PHY_ANT_SWITCH_TABLE_0);
804 ath5k_hw_reg_write(ah, ah->ah_antenna[ee_mode][ant[1]],
805 AR5K_PHY_ANT_SWITCH_TABLE_1);
806
807 /* Commit values from EEPROM */
808 if (ah->ah_radio == AR5K_RF5111)
809 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
810 AR5K_PHY_FRAME_CTL_TX_CLIP, ee->ee_tx_clip);
811
812 ath5k_hw_reg_write(ah,
813 AR5K_PHY_NF_SVAL(ee->ee_noise_floor_thr[ee_mode]),
814 AR5K_PHY(0x5a));
815
816 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x11),
817 (ee->ee_switch_settling[ee_mode] << 7) & 0x3f80,
818 0xffffc07f);
819 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x12),
820 (ee->ee_ant_tx_rx[ee_mode] << 12) & 0x3f000,
821 0xfffc0fff);
822 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x14),
823 (ee->ee_adc_desired_size[ee_mode] & 0x00ff) |
824 ((ee->ee_pga_desired_size[ee_mode] << 8) & 0xff00),
825 0xffff0000);
826
827 ath5k_hw_reg_write(ah,
828 (ee->ee_tx_end2xpa_disable[ee_mode] << 24) |
829 (ee->ee_tx_end2xpa_disable[ee_mode] << 16) |
830 (ee->ee_tx_frm2xpa_enable[ee_mode] << 8) |
831 (ee->ee_tx_frm2xpa_enable[ee_mode]), AR5K_PHY(0x0d));
832
833 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x0a),
834 ee->ee_tx_end2xlna_enable[ee_mode] << 8, 0xffff00ff);
835 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x19),
836 (ee->ee_thr_62[ee_mode] << 12) & 0x7f000, 0xfff80fff);
837 AR5K_REG_MASKED_BITS(ah, AR5K_PHY(0x49), 4, 0xffffff01);
838
839 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
840 AR5K_PHY_IQ_CORR_ENABLE |
841 (ee->ee_i_cal[ee_mode] << AR5K_PHY_IQ_CORR_Q_I_COFF_S) |
842 ee->ee_q_cal[ee_mode]);
843
844 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
845 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_GAIN_2GHZ,
846 AR5K_PHY_GAIN_2GHZ_MARGIN_TXRX,
847 ee->ee_margin_tx_rx[ee_mode]);
848
849 } else {
850 mdelay(1);
851 /* Disable phy and wait */
852 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
853 mdelay(1);
854 }
855
856 /*
857 * Restore saved values
858 */
859 /*DCU/Antenna selection not available on 5210*/
860 if (ah->ah_version != AR5K_AR5210) {
861 ath5k_hw_reg_write(ah, s_seq, AR5K_QUEUE_DFS_SEQNUM(0));
862 ath5k_hw_reg_write(ah, s_ant, AR5K_DEFAULT_ANTENNA);
863 }
864 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, s_led[0]);
865 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR);
866 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO);
867
868 /*
869 * Misc
870 */
871 /* XXX: add ah->aid once mac80211 gives this to us */
872 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
873
874 ath5k_hw_set_opmode(ah);
875 /*PISR/SISR Not available on 5210*/
876 if (ah->ah_version != AR5K_AR5210) {
877 ath5k_hw_reg_write(ah, 0xffffffff, AR5K_PISR);
878 /* If we later allow tuning for this, store into sc structure */
879 data = AR5K_TUNE_RSSI_THRES |
880 AR5K_TUNE_BMISS_THRES << AR5K_RSSI_THR_BMISS_S;
881 ath5k_hw_reg_write(ah, data, AR5K_RSSI_THR);
882 }
883
884 /*
885 * Set Rx/Tx DMA Configuration
886 *(passing dma size not available on 5210)
887 */
888 if (ah->ah_version != AR5K_AR5210) {
889 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_SDMAMR,
890 AR5K_DMASIZE_512B | AR5K_TXCFG_DMASIZE);
891 AR5K_REG_WRITE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_SDMAMW,
892 AR5K_DMASIZE_512B);
893 }
894
895 /*
896 * Enable the PHY and wait until completion
897 */
898 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
899
900 /*
901 * 5111/5112 Specific
902 */
903 if (ah->ah_version != AR5K_AR5210) {
904 data = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
905 AR5K_PHY_RX_DELAY_M;
906 data = (channel->val & CHANNEL_CCK) ?
907 ((data << 2) / 22) : (data / 10);
908
909 udelay(100 + data);
910 } else {
911 mdelay(1);
912 }
913
914 /*
915 * Enable calibration and wait until completion
916 */
917 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
918 AR5K_PHY_AGCCTL_CAL);
919
920 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
921 AR5K_PHY_AGCCTL_CAL, 0, false)) {
922 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
923 channel->freq);
924 return -EAGAIN;
925 }
926
927 ret = ath5k_hw_noise_floor_calibration(ah, channel->freq);
928 if (ret)
929 return ret;
930
931 ah->ah_calibration = false;
932
933 /* A and G modes can use QAM modulation which requires enabling
934 * I and Q calibration. Don't bother in B mode. */
935 if (!(driver_mode == MODE_IEEE80211B)) {
936 ah->ah_calibration = true;
937 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
938 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
939 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
940 AR5K_PHY_IQ_RUN);
941 }
942
943 /*
944 * Reset queues and start beacon timers at the end of the reset routine
945 */
946 for (i = 0; i < ah->ah_capabilities.cap_queues.q_tx_num; i++) {
947 /*No QCU on 5210*/
948 if (ah->ah_version != AR5K_AR5210)
949 AR5K_REG_WRITE_Q(ah, AR5K_QUEUE_QCUMASK(i), i);
950
951 ret = ath5k_hw_reset_tx_queue(ah, i);
952 if (ret) {
953 ATH5K_ERR(ah->ah_sc,
954 "failed to reset TX queue #%d\n", i);
955 return ret;
956 }
957 }
958
959 /* Pre-enable interrupts on 5211/5212*/
960 if (ah->ah_version != AR5K_AR5210)
961 ath5k_hw_set_intr(ah, AR5K_INT_RX | AR5K_INT_TX |
962 AR5K_INT_FATAL);
963
964 /*
965 * Set RF kill flags if supported by the device (read from the EEPROM)
966 * Disable gpio_intr for now since it results system hang.
967 * TODO: Handle this in ath5k_intr
968 */
969 #if 0
970 if (AR5K_EEPROM_HDR_RFKILL(ah->ah_capabilities.cap_eeprom.ee_header)) {
971 ath5k_hw_set_gpio_input(ah, 0);
972 ah->ah_gpio[0] = ath5k_hw_get_gpio(ah, 0);
973 if (ah->ah_gpio[0] == 0)
974 ath5k_hw_set_gpio_intr(ah, 0, 1);
975 else
976 ath5k_hw_set_gpio_intr(ah, 0, 0);
977 }
978 #endif
979
980 /*
981 * Set the 32MHz reference clock on 5212 phy clock sleep register
982 */
983 if (ah->ah_version == AR5K_AR5212) {
984 ath5k_hw_reg_write(ah, AR5K_PHY_SCR_32MHZ, AR5K_PHY_SCR);
985 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT);
986 ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ, AR5K_PHY_SCAL);
987 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK);
988 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY);
989 ath5k_hw_reg_write(ah, ah->ah_radio == AR5K_RF5111 ?
990 AR5K_PHY_SPENDING_RF5111 : AR5K_PHY_SPENDING_RF5112,
991 AR5K_PHY_SPENDING);
992 }
993
994 /*
995 * Disable beacons and reset the register
996 */
997 AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE |
998 AR5K_BEACON_RESET_TSF);
999
1000 return 0;
1001 }
1002
1003 /*
1004 * Reset chipset
1005 */
1006 static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
1007 {
1008 int ret;
1009 u32 mask = val ? val : ~0U;
1010
1011 ATH5K_TRACE(ah->ah_sc);
1012
1013 /* Read-and-clear RX Descriptor Pointer*/
1014 ath5k_hw_reg_read(ah, AR5K_RXDP);
1015
1016 /*
1017 * Reset the device and wait until success
1018 */
1019 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL);
1020
1021 /* Wait at least 128 PCI clocks */
1022 udelay(15);
1023
1024 if (ah->ah_version == AR5K_AR5210) {
1025 val &= AR5K_RESET_CTL_CHIP;
1026 mask &= AR5K_RESET_CTL_CHIP;
1027 } else {
1028 val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
1029 mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
1030 }
1031
1032 ret = ath5k_hw_register_timeout(ah, AR5K_RESET_CTL, mask, val, false);
1033
1034 /*
1035 * Reset configuration register (for hw byte-swap). Note that this
1036 * is only set for big endian. We do the necessary magic in
1037 * AR5K_INIT_CFG.
1038 */
1039 if ((val & AR5K_RESET_CTL_PCU) == 0)
1040 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG);
1041
1042 return ret;
1043 }
1044
1045 /*
1046 * Power management functions
1047 */
1048
1049 /*
1050 * Sleep control
1051 */
1052 int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode,
1053 bool set_chip, u16 sleep_duration)
1054 {
1055 unsigned int i;
1056 u32 staid;
1057
1058 ATH5K_TRACE(ah->ah_sc);
1059 staid = ath5k_hw_reg_read(ah, AR5K_STA_ID1);
1060
1061 switch (mode) {
1062 case AR5K_PM_AUTO:
1063 staid &= ~AR5K_STA_ID1_DEFAULT_ANTENNA;
1064 /* fallthrough */
1065 case AR5K_PM_NETWORK_SLEEP:
1066 if (set_chip == true)
1067 ath5k_hw_reg_write(ah,
1068 AR5K_SLEEP_CTL_SLE | sleep_duration,
1069 AR5K_SLEEP_CTL);
1070
1071 staid |= AR5K_STA_ID1_PWR_SV;
1072 break;
1073
1074 case AR5K_PM_FULL_SLEEP:
1075 if (set_chip == true)
1076 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP,
1077 AR5K_SLEEP_CTL);
1078
1079 staid |= AR5K_STA_ID1_PWR_SV;
1080 break;
1081
1082 case AR5K_PM_AWAKE:
1083 if (set_chip == false)
1084 goto commit;
1085
1086 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_WAKE,
1087 AR5K_SLEEP_CTL);
1088
1089 for (i = 5000; i > 0; i--) {
1090 /* Check if the chip did wake up */
1091 if ((ath5k_hw_reg_read(ah, AR5K_PCICFG) &
1092 AR5K_PCICFG_SPWR_DN) == 0)
1093 break;
1094
1095 /* Wait a bit and retry */
1096 udelay(200);
1097 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_WAKE,
1098 AR5K_SLEEP_CTL);
1099 }
1100
1101 /* Fail if the chip didn't wake up */
1102 if (i <= 0)
1103 return -EIO;
1104
1105 staid &= ~AR5K_STA_ID1_PWR_SV;
1106 break;
1107
1108 default:
1109 return -EINVAL;
1110 }
1111
1112 commit:
1113 ah->ah_power_mode = mode;
1114 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1);
1115
1116 return 0;
1117 }
1118
1119 /***********************\
1120 DMA Related Functions
1121 \***********************/
1122
1123 /*
1124 * Receive functions
1125 */
1126
1127 /*
1128 * Start DMA receive
1129 */
1130 void ath5k_hw_start_rx(struct ath5k_hw *ah)
1131 {
1132 ATH5K_TRACE(ah->ah_sc);
1133 ath5k_hw_reg_write(ah, AR5K_CR_RXE, AR5K_CR);
1134 }
1135
1136 /*
1137 * Stop DMA receive
1138 */
1139 int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah)
1140 {
1141 unsigned int i;
1142
1143 ATH5K_TRACE(ah->ah_sc);
1144 ath5k_hw_reg_write(ah, AR5K_CR_RXD, AR5K_CR);
1145
1146 /*
1147 * It may take some time to disable the DMA receive unit
1148 */
1149 for (i = 2000; i > 0 &&
1150 (ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_CR_RXE) != 0;
1151 i--)
1152 udelay(10);
1153
1154 return i ? 0 : -EBUSY;
1155 }
1156
1157 /*
1158 * Get the address of the RX Descriptor
1159 */
1160 u32 ath5k_hw_get_rx_buf(struct ath5k_hw *ah)
1161 {
1162 return ath5k_hw_reg_read(ah, AR5K_RXDP);
1163 }
1164
1165 /*
1166 * Set the address of the RX Descriptor
1167 */
1168 void ath5k_hw_put_rx_buf(struct ath5k_hw *ah, u32 phys_addr)
1169 {
1170 ATH5K_TRACE(ah->ah_sc);
1171
1172 /*TODO:Shouldn't we check if RX is enabled first ?*/
1173 ath5k_hw_reg_write(ah, phys_addr, AR5K_RXDP);
1174 }
1175
1176 /*
1177 * Transmit functions
1178 */
1179
1180 /*
1181 * Start DMA transmit for a specific queue
1182 * (see also QCU/DCU functions)
1183 */
1184 int ath5k_hw_tx_start(struct ath5k_hw *ah, unsigned int queue)
1185 {
1186 u32 tx_queue;
1187
1188 ATH5K_TRACE(ah->ah_sc);
1189 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1190
1191 /* Return if queue is declared inactive */
1192 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
1193 return -EIO;
1194
1195 if (ah->ah_version == AR5K_AR5210) {
1196 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
1197
1198 /*
1199 * Set the queue by type on 5210
1200 */
1201 switch (ah->ah_txq[queue].tqi_type) {
1202 case AR5K_TX_QUEUE_DATA:
1203 tx_queue |= AR5K_CR_TXE0 & ~AR5K_CR_TXD0;
1204 break;
1205 case AR5K_TX_QUEUE_BEACON:
1206 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
1207 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
1208 AR5K_BSR);
1209 break;
1210 case AR5K_TX_QUEUE_CAB:
1211 tx_queue |= AR5K_CR_TXE1 & ~AR5K_CR_TXD1;
1212 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1FV | AR5K_BCR_TQ1V |
1213 AR5K_BCR_BDMAE, AR5K_BSR);
1214 break;
1215 default:
1216 return -EINVAL;
1217 }
1218 /* Start queue */
1219 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
1220 } else {
1221 /* Return if queue is disabled */
1222 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXD, queue))
1223 return -EIO;
1224
1225 /* Start queue */
1226 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXE, queue);
1227 }
1228
1229 return 0;
1230 }
1231
1232 /*
1233 * Stop DMA transmit for a specific queue
1234 * (see also QCU/DCU functions)
1235 */
1236 int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue)
1237 {
1238 unsigned int i = 100;
1239 u32 tx_queue, pending;
1240
1241 ATH5K_TRACE(ah->ah_sc);
1242 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1243
1244 /* Return if queue is declared inactive */
1245 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
1246 return -EIO;
1247
1248 if (ah->ah_version == AR5K_AR5210) {
1249 tx_queue = ath5k_hw_reg_read(ah, AR5K_CR);
1250
1251 /*
1252 * Set by queue type
1253 */
1254 switch (ah->ah_txq[queue].tqi_type) {
1255 case AR5K_TX_QUEUE_DATA:
1256 tx_queue |= AR5K_CR_TXD0 & ~AR5K_CR_TXE0;
1257 break;
1258 case AR5K_TX_QUEUE_BEACON:
1259 case AR5K_TX_QUEUE_CAB:
1260 /* XXX Fix me... */
1261 tx_queue |= AR5K_CR_TXD1 & ~AR5K_CR_TXD1;
1262 ath5k_hw_reg_write(ah, 0, AR5K_BSR);
1263 break;
1264 default:
1265 return -EINVAL;
1266 }
1267
1268 /* Stop queue */
1269 ath5k_hw_reg_write(ah, tx_queue, AR5K_CR);
1270 } else {
1271 /*
1272 * Schedule TX disable and wait until queue is empty
1273 */
1274 AR5K_REG_WRITE_Q(ah, AR5K_QCU_TXD, queue);
1275
1276 /*Check for pending frames*/
1277 do {
1278 pending = ath5k_hw_reg_read(ah,
1279 AR5K_QUEUE_STATUS(queue)) &
1280 AR5K_QCU_STS_FRMPENDCNT;
1281 udelay(100);
1282 } while (--i && pending);
1283
1284 /* Clear register */
1285 ath5k_hw_reg_write(ah, 0, AR5K_QCU_TXD);
1286 }
1287
1288 /* TODO: Check for success else return error */
1289 return 0;
1290 }
1291
1292 /*
1293 * Get the address of the TX Descriptor for a specific queue
1294 * (see also QCU/DCU functions)
1295 */
1296 u32 ath5k_hw_get_tx_buf(struct ath5k_hw *ah, unsigned int queue)
1297 {
1298 u16 tx_reg;
1299
1300 ATH5K_TRACE(ah->ah_sc);
1301 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1302
1303 /*
1304 * Get the transmit queue descriptor pointer from the selected queue
1305 */
1306 /*5210 doesn't have QCU*/
1307 if (ah->ah_version == AR5K_AR5210) {
1308 switch (ah->ah_txq[queue].tqi_type) {
1309 case AR5K_TX_QUEUE_DATA:
1310 tx_reg = AR5K_NOQCU_TXDP0;
1311 break;
1312 case AR5K_TX_QUEUE_BEACON:
1313 case AR5K_TX_QUEUE_CAB:
1314 tx_reg = AR5K_NOQCU_TXDP1;
1315 break;
1316 default:
1317 return 0xffffffff;
1318 }
1319 } else {
1320 tx_reg = AR5K_QUEUE_TXDP(queue);
1321 }
1322
1323 return ath5k_hw_reg_read(ah, tx_reg);
1324 }
1325
1326 /*
1327 * Set the address of the TX Descriptor for a specific queue
1328 * (see also QCU/DCU functions)
1329 */
1330 int ath5k_hw_put_tx_buf(struct ath5k_hw *ah, unsigned int queue, u32 phys_addr)
1331 {
1332 u16 tx_reg;
1333
1334 ATH5K_TRACE(ah->ah_sc);
1335 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
1336
1337 /*
1338 * Set the transmit queue descriptor pointer register by type
1339 * on 5210
1340 */
1341 if (ah->ah_version == AR5K_AR5210) {
1342 switch (ah->ah_txq[queue].tqi_type) {
1343 case AR5K_TX_QUEUE_DATA:
1344 tx_reg = AR5K_NOQCU_TXDP0;
1345 break;
1346 case AR5K_TX_QUEUE_BEACON:
1347 case AR5K_TX_QUEUE_CAB:
1348 tx_reg = AR5K_NOQCU_TXDP1;
1349 break;
1350 default:
1351 return -EINVAL;
1352 }
1353 } else {
1354 /*
1355 * Set the transmit queue descriptor pointer for
1356 * the selected queue on QCU for 5211+
1357 * (this won't work if the queue is still active)
1358 */
1359 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, queue))
1360 return -EIO;
1361
1362 tx_reg = AR5K_QUEUE_TXDP(queue);
1363 }
1364
1365 /* Set descriptor pointer */
1366 ath5k_hw_reg_write(ah, phys_addr, tx_reg);
1367
1368 return 0;
1369 }
1370
1371 /*
1372 * Update tx trigger level
1373 */
1374 int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase)
1375 {
1376 u32 trigger_level, imr;
1377 int ret = -EIO;
1378
1379 ATH5K_TRACE(ah->ah_sc);
1380
1381 /*
1382 * Disable interrupts by setting the mask
1383 */
1384 imr = ath5k_hw_set_intr(ah, ah->ah_imr & ~AR5K_INT_GLOBAL);
1385
1386 /*TODO: Boundary check on trigger_level*/
1387 trigger_level = AR5K_REG_MS(ath5k_hw_reg_read(ah, AR5K_TXCFG),
1388 AR5K_TXCFG_TXFULL);
1389
1390 if (increase == false) {
1391 if (--trigger_level < AR5K_TUNE_MIN_TX_FIFO_THRES)
1392 goto done;
1393 } else
1394 trigger_level +=
1395 ((AR5K_TUNE_MAX_TX_FIFO_THRES - trigger_level) / 2);
1396
1397 /*
1398 * Update trigger level on success
1399 */
1400 if (ah->ah_version == AR5K_AR5210)
1401 ath5k_hw_reg_write(ah, trigger_level, AR5K_TRIG_LVL);
1402 else
1403 AR5K_REG_WRITE_BITS(ah, AR5K_TXCFG,
1404 AR5K_TXCFG_TXFULL, trigger_level);
1405
1406 ret = 0;
1407
1408 done:
1409 /*
1410 * Restore interrupt mask
1411 */
1412 ath5k_hw_set_intr(ah, imr);
1413
1414 return ret;
1415 }
1416
1417 /*
1418 * Interrupt handling
1419 */
1420
1421 /*
1422 * Check if we have pending interrupts
1423 */
1424 bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah)
1425 {
1426 ATH5K_TRACE(ah->ah_sc);
1427 return ath5k_hw_reg_read(ah, AR5K_INTPEND);
1428 }
1429
1430 /*
1431 * Get interrupt mask (ISR)
1432 */
1433 int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask)
1434 {
1435 u32 data;
1436
1437 ATH5K_TRACE(ah->ah_sc);
1438
1439 /*
1440 * Read interrupt status from the Interrupt Status register
1441 * on 5210
1442 */
1443 if (ah->ah_version == AR5K_AR5210) {
1444 data = ath5k_hw_reg_read(ah, AR5K_ISR);
1445 if (unlikely(data == AR5K_INT_NOCARD)) {
1446 *interrupt_mask = data;
1447 return -ENODEV;
1448 }
1449 } else {
1450 /*
1451 * Read interrupt status from the Read-And-Clear shadow register
1452 * Note: PISR/SISR Not available on 5210
1453 */
1454 data = ath5k_hw_reg_read(ah, AR5K_RAC_PISR);
1455 }
1456
1457 /*
1458 * Get abstract interrupt mask (driver-compatible)
1459 */
1460 *interrupt_mask = (data & AR5K_INT_COMMON) & ah->ah_imr;
1461
1462 if (unlikely(data == AR5K_INT_NOCARD))
1463 return -ENODEV;
1464
1465 if (data & (AR5K_ISR_RXOK | AR5K_ISR_RXERR))
1466 *interrupt_mask |= AR5K_INT_RX;
1467
1468 if (data & (AR5K_ISR_TXOK | AR5K_ISR_TXERR
1469 | AR5K_ISR_TXDESC | AR5K_ISR_TXEOL))
1470 *interrupt_mask |= AR5K_INT_TX;
1471
1472 if (ah->ah_version != AR5K_AR5210) {
1473 /*HIU = Host Interface Unit (PCI etc)*/
1474 if (unlikely(data & (AR5K_ISR_HIUERR)))
1475 *interrupt_mask |= AR5K_INT_FATAL;
1476
1477 /*Beacon Not Ready*/
1478 if (unlikely(data & (AR5K_ISR_BNR)))
1479 *interrupt_mask |= AR5K_INT_BNR;
1480 }
1481
1482 /*
1483 * XXX: BMISS interrupts may occur after association.
1484 * I found this on 5210 code but it needs testing. If this is
1485 * true we should disable them before assoc and re-enable them
1486 * after a successfull assoc + some jiffies.
1487 */
1488 #if 0
1489 interrupt_mask &= ~AR5K_INT_BMISS;
1490 #endif
1491
1492 /*
1493 * In case we didn't handle anything,
1494 * print the register value.
1495 */
1496 if (unlikely(*interrupt_mask == 0 && net_ratelimit()))
1497 ATH5K_PRINTF("0x%08x\n", data);
1498
1499 return 0;
1500 }
1501
1502 /*
1503 * Set interrupt mask
1504 */
1505 enum ath5k_int ath5k_hw_set_intr(struct ath5k_hw *ah, enum ath5k_int new_mask)
1506 {
1507 enum ath5k_int old_mask, int_mask;
1508
1509 /*
1510 * Disable card interrupts to prevent any race conditions
1511 * (they will be re-enabled afterwards).
1512 */
1513 ath5k_hw_reg_write(ah, AR5K_IER_DISABLE, AR5K_IER);
1514
1515 old_mask = ah->ah_imr;
1516
1517 /*
1518 * Add additional, chipset-dependent interrupt mask flags
1519 * and write them to the IMR (interrupt mask register).
1520 */
1521 int_mask = new_mask & AR5K_INT_COMMON;
1522
1523 if (new_mask & AR5K_INT_RX)
1524 int_mask |= AR5K_IMR_RXOK | AR5K_IMR_RXERR | AR5K_IMR_RXORN |
1525 AR5K_IMR_RXDESC;
1526
1527 if (new_mask & AR5K_INT_TX)
1528 int_mask |= AR5K_IMR_TXOK | AR5K_IMR_TXERR | AR5K_IMR_TXDESC |
1529 AR5K_IMR_TXURN;
1530
1531 if (ah->ah_version != AR5K_AR5210) {
1532 if (new_mask & AR5K_INT_FATAL) {
1533 int_mask |= AR5K_IMR_HIUERR;
1534 AR5K_REG_ENABLE_BITS(ah, AR5K_SIMR2, AR5K_SIMR2_MCABT |
1535 AR5K_SIMR2_SSERR | AR5K_SIMR2_DPERR);
1536 }
1537 }
1538
1539 ath5k_hw_reg_write(ah, int_mask, AR5K_PIMR);
1540
1541 /* Store new interrupt mask */
1542 ah->ah_imr = new_mask;
1543
1544 /* ..re-enable interrupts */
1545 ath5k_hw_reg_write(ah, AR5K_IER_ENABLE, AR5K_IER);
1546
1547 return old_mask;
1548 }
1549
1550
1551 /*************************\
1552 EEPROM access functions
1553 \*************************/
1554
1555 /*
1556 * Read from eeprom
1557 */
1558 static int ath5k_hw_eeprom_read(struct ath5k_hw *ah, u32 offset, u16 *data)
1559 {
1560 u32 status, timeout;
1561
1562 ATH5K_TRACE(ah->ah_sc);
1563 /*
1564 * Initialize EEPROM access
1565 */
1566 if (ah->ah_version == AR5K_AR5210) {
1567 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
1568 (void)ath5k_hw_reg_read(ah, AR5K_EEPROM_BASE + (4 * offset));
1569 } else {
1570 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
1571 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1572 AR5K_EEPROM_CMD_READ);
1573 }
1574
1575 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
1576 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
1577 if (status & AR5K_EEPROM_STAT_RDDONE) {
1578 if (status & AR5K_EEPROM_STAT_RDERR)
1579 return -EIO;
1580 *data = (u16)(ath5k_hw_reg_read(ah, AR5K_EEPROM_DATA) &
1581 0xffff);
1582 return 0;
1583 }
1584 udelay(15);
1585 }
1586
1587 return -ETIMEDOUT;
1588 }
1589
1590 /*
1591 * Write to eeprom - currently disabled, use at your own risk
1592 */
1593 static int ath5k_hw_eeprom_write(struct ath5k_hw *ah, u32 offset, u16 data)
1594 {
1595 #if 0
1596 u32 status, timeout;
1597
1598 ATH5K_TRACE(ah->ah_sc);
1599
1600 /*
1601 * Initialize eeprom access
1602 */
1603
1604 if (ah->ah_version == AR5K_AR5210) {
1605 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_EEAE);
1606 } else {
1607 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1608 AR5K_EEPROM_CMD_RESET);
1609 }
1610
1611 /*
1612 * Write data to data register
1613 */
1614
1615 if (ah->ah_version == AR5K_AR5210) {
1616 ath5k_hw_reg_write(ah, data, AR5K_EEPROM_BASE + (4 * offset));
1617 } else {
1618 ath5k_hw_reg_write(ah, offset, AR5K_EEPROM_BASE);
1619 ath5k_hw_reg_write(ah, data, AR5K_EEPROM_DATA);
1620 AR5K_REG_ENABLE_BITS(ah, AR5K_EEPROM_CMD,
1621 AR5K_EEPROM_CMD_WRITE);
1622 }
1623
1624 /*
1625 * Check status
1626 */
1627
1628 for (timeout = AR5K_TUNE_REGISTER_TIMEOUT; timeout > 0; timeout--) {
1629 status = ath5k_hw_reg_read(ah, AR5K_EEPROM_STATUS);
1630 if (status & AR5K_EEPROM_STAT_WRDONE) {
1631 if (status & AR5K_EEPROM_STAT_WRERR)
1632 return EIO;
1633 return 0;
1634 }
1635 udelay(15);
1636 }
1637 #endif
1638 ATH5K_ERR(ah->ah_sc, "EEPROM Write is disabled!");
1639 return -EIO;
1640 }
1641
1642 /*
1643 * Translate binary channel representation in EEPROM to frequency
1644 */
1645 static u16 ath5k_eeprom_bin2freq(struct ath5k_hw *ah, u16 bin, unsigned int mode)
1646 {
1647 u16 val;
1648
1649 if (bin == AR5K_EEPROM_CHANNEL_DIS)
1650 return bin;
1651
1652 if (mode == AR5K_EEPROM_MODE_11A) {
1653 if (ah->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
1654 val = (5 * bin) + 4800;
1655 else
1656 val = bin > 62 ? (10 * 62) + (5 * (bin - 62)) + 5100 :
1657 (bin * 10) + 5100;
1658 } else {
1659 if (ah->ah_ee_version > AR5K_EEPROM_VERSION_3_2)
1660 val = bin + 2300;
1661 else
1662 val = bin + 2400;
1663 }
1664
1665 return val;
1666 }
1667
1668 /*
1669 * Read antenna infos from eeprom
1670 */
1671 static int ath5k_eeprom_read_ants(struct ath5k_hw *ah, u32 *offset,
1672 unsigned int mode)
1673 {
1674 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1675 u32 o = *offset;
1676 u16 val;
1677 int ret, i = 0;
1678
1679 AR5K_EEPROM_READ(o++, val);
1680 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f;
1681 ee->ee_ant_tx_rx[mode] = (val >> 2) & 0x3f;
1682 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
1683
1684 AR5K_EEPROM_READ(o++, val);
1685 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
1686 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
1687 ee->ee_ant_control[mode][i++] = val & 0x3f;
1688
1689 AR5K_EEPROM_READ(o++, val);
1690 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f;
1691 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f;
1692 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f;
1693
1694 AR5K_EEPROM_READ(o++, val);
1695 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3;
1696 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f;
1697 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f;
1698 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f;
1699
1700 AR5K_EEPROM_READ(o++, val);
1701 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf;
1702 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f;
1703 ee->ee_ant_control[mode][i++] = val & 0x3f;
1704
1705 /* Get antenna modes */
1706 ah->ah_antenna[mode][0] =
1707 (ee->ee_ant_control[mode][0] << 4) | 0x1;
1708 ah->ah_antenna[mode][AR5K_ANT_FIXED_A] =
1709 ee->ee_ant_control[mode][1] |
1710 (ee->ee_ant_control[mode][2] << 6) |
1711 (ee->ee_ant_control[mode][3] << 12) |
1712 (ee->ee_ant_control[mode][4] << 18) |
1713 (ee->ee_ant_control[mode][5] << 24);
1714 ah->ah_antenna[mode][AR5K_ANT_FIXED_B] =
1715 ee->ee_ant_control[mode][6] |
1716 (ee->ee_ant_control[mode][7] << 6) |
1717 (ee->ee_ant_control[mode][8] << 12) |
1718 (ee->ee_ant_control[mode][9] << 18) |
1719 (ee->ee_ant_control[mode][10] << 24);
1720
1721 /* return new offset */
1722 *offset = o;
1723
1724 return 0;
1725 }
1726
1727 /*
1728 * Read supported modes from eeprom
1729 */
1730 static int ath5k_eeprom_read_modes(struct ath5k_hw *ah, u32 *offset,
1731 unsigned int mode)
1732 {
1733 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1734 u32 o = *offset;
1735 u16 val;
1736 int ret;
1737
1738 AR5K_EEPROM_READ(o++, val);
1739 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff;
1740 ee->ee_thr_62[mode] = val & 0xff;
1741
1742 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
1743 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28;
1744
1745 AR5K_EEPROM_READ(o++, val);
1746 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff;
1747 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff;
1748
1749 AR5K_EEPROM_READ(o++, val);
1750 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff;
1751
1752 if ((val & 0xff) & 0x80)
1753 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1);
1754 else
1755 ee->ee_noise_floor_thr[mode] = val & 0xff;
1756
1757 if (ah->ah_ee_version <= AR5K_EEPROM_VERSION_3_2)
1758 ee->ee_noise_floor_thr[mode] =
1759 mode == AR5K_EEPROM_MODE_11A ? -54 : -1;
1760
1761 AR5K_EEPROM_READ(o++, val);
1762 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff;
1763 ee->ee_x_gain[mode] = (val >> 1) & 0xf;
1764 ee->ee_xpd[mode] = val & 0x1;
1765
1766 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0)
1767 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1;
1768
1769 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_3_3) {
1770 AR5K_EEPROM_READ(o++, val);
1771 ee->ee_false_detect[mode] = (val >> 6) & 0x7f;
1772
1773 if (mode == AR5K_EEPROM_MODE_11A)
1774 ee->ee_xr_power[mode] = val & 0x3f;
1775 else {
1776 ee->ee_ob[mode][0] = val & 0x7;
1777 ee->ee_db[mode][0] = (val >> 3) & 0x7;
1778 }
1779 }
1780
1781 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_4) {
1782 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN;
1783 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA;
1784 } else {
1785 ee->ee_i_gain[mode] = (val >> 13) & 0x7;
1786
1787 AR5K_EEPROM_READ(o++, val);
1788 ee->ee_i_gain[mode] |= (val << 3) & 0x38;
1789
1790 if (mode == AR5K_EEPROM_MODE_11G)
1791 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff;
1792 }
1793
1794 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0 &&
1795 mode == AR5K_EEPROM_MODE_11A) {
1796 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
1797 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
1798 }
1799
1800 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_6 &&
1801 mode == AR5K_EEPROM_MODE_11G)
1802 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f;
1803
1804 /* return new offset */
1805 *offset = o;
1806
1807 return 0;
1808 }
1809
1810 /*
1811 * Initialize eeprom & capabilities structs
1812 */
1813 static int ath5k_eeprom_init(struct ath5k_hw *ah)
1814 {
1815 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1816 unsigned int mode, i;
1817 int ret;
1818 u32 offset;
1819 u16 val;
1820
1821 /* Initial TX thermal adjustment values */
1822 ee->ee_tx_clip = 4;
1823 ee->ee_pwd_84 = ee->ee_pwd_90 = 1;
1824 ee->ee_gain_select = 1;
1825
1826 /*
1827 * Read values from EEPROM and store them in the capability structure
1828 */
1829 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MAGIC, ee_magic);
1830 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_PROTECT, ee_protect);
1831 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_REG_DOMAIN, ee_regdomain);
1832 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_VERSION, ee_version);
1833 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_HDR, ee_header);
1834
1835 /* Return if we have an old EEPROM */
1836 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_0)
1837 return 0;
1838
1839 #ifdef notyet
1840 /*
1841 * Validate the checksum of the EEPROM date. There are some
1842 * devices with invalid EEPROMs.
1843 */
1844 for (cksum = 0, offset = 0; offset < AR5K_EEPROM_INFO_MAX; offset++) {
1845 AR5K_EEPROM_READ(AR5K_EEPROM_INFO(offset), val);
1846 cksum ^= val;
1847 }
1848 if (cksum != AR5K_EEPROM_INFO_CKSUM) {
1849 ATH5K_ERR(ah->ah_sc, "Invalid EEPROM checksum 0x%04x\n", cksum);
1850 return -EIO;
1851 }
1852 #endif
1853
1854 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_ANT_GAIN(ah->ah_ee_version),
1855 ee_ant_gain);
1856
1857 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
1858 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC0, ee_misc0);
1859 AR5K_EEPROM_READ_HDR(AR5K_EEPROM_MISC1, ee_misc1);
1860 }
1861
1862 if (ah->ah_ee_version < AR5K_EEPROM_VERSION_3_3) {
1863 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB0_2GHZ, val);
1864 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7;
1865 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7;
1866
1867 AR5K_EEPROM_READ(AR5K_EEPROM_OBDB1_2GHZ, val);
1868 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7;
1869 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7;
1870 }
1871
1872 /*
1873 * Get conformance test limit values
1874 */
1875 offset = AR5K_EEPROM_CTL(ah->ah_ee_version);
1876 ee->ee_ctls = AR5K_EEPROM_N_CTLS(ah->ah_ee_version);
1877
1878 for (i = 0; i < ee->ee_ctls; i++) {
1879 AR5K_EEPROM_READ(offset++, val);
1880 ee->ee_ctl[i] = (val >> 8) & 0xff;
1881 ee->ee_ctl[i + 1] = val & 0xff;
1882 }
1883
1884 /*
1885 * Get values for 802.11a (5GHz)
1886 */
1887 mode = AR5K_EEPROM_MODE_11A;
1888
1889 ee->ee_turbo_max_power[mode] =
1890 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header);
1891
1892 offset = AR5K_EEPROM_MODES_11A(ah->ah_ee_version);
1893
1894 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
1895 if (ret)
1896 return ret;
1897
1898 AR5K_EEPROM_READ(offset++, val);
1899 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
1900 ee->ee_ob[mode][3] = (val >> 5) & 0x7;
1901 ee->ee_db[mode][3] = (val >> 2) & 0x7;
1902 ee->ee_ob[mode][2] = (val << 1) & 0x7;
1903
1904 AR5K_EEPROM_READ(offset++, val);
1905 ee->ee_ob[mode][2] |= (val >> 15) & 0x1;
1906 ee->ee_db[mode][2] = (val >> 12) & 0x7;
1907 ee->ee_ob[mode][1] = (val >> 9) & 0x7;
1908 ee->ee_db[mode][1] = (val >> 6) & 0x7;
1909 ee->ee_ob[mode][0] = (val >> 3) & 0x7;
1910 ee->ee_db[mode][0] = val & 0x7;
1911
1912 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
1913 if (ret)
1914 return ret;
1915
1916 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1) {
1917 AR5K_EEPROM_READ(offset++, val);
1918 ee->ee_margin_tx_rx[mode] = val & 0x3f;
1919 }
1920
1921 /*
1922 * Get values for 802.11b (2.4GHz)
1923 */
1924 mode = AR5K_EEPROM_MODE_11B;
1925 offset = AR5K_EEPROM_MODES_11B(ah->ah_ee_version);
1926
1927 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
1928 if (ret)
1929 return ret;
1930
1931 AR5K_EEPROM_READ(offset++, val);
1932 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
1933 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
1934 ee->ee_db[mode][1] = val & 0x7;
1935
1936 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
1937 if (ret)
1938 return ret;
1939
1940 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
1941 AR5K_EEPROM_READ(offset++, val);
1942 ee->ee_cal_pier[mode][0] =
1943 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
1944 ee->ee_cal_pier[mode][1] =
1945 ath5k_eeprom_bin2freq(ah, (val >> 8) & 0xff, mode);
1946
1947 AR5K_EEPROM_READ(offset++, val);
1948 ee->ee_cal_pier[mode][2] =
1949 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
1950 }
1951
1952 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
1953 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
1954
1955 /*
1956 * Get values for 802.11g (2.4GHz)
1957 */
1958 mode = AR5K_EEPROM_MODE_11G;
1959 offset = AR5K_EEPROM_MODES_11G(ah->ah_ee_version);
1960
1961 ret = ath5k_eeprom_read_ants(ah, &offset, mode);
1962 if (ret)
1963 return ret;
1964
1965 AR5K_EEPROM_READ(offset++, val);
1966 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff);
1967 ee->ee_ob[mode][1] = (val >> 4) & 0x7;
1968 ee->ee_db[mode][1] = val & 0x7;
1969
1970 ret = ath5k_eeprom_read_modes(ah, &offset, mode);
1971 if (ret)
1972 return ret;
1973
1974 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_0) {
1975 AR5K_EEPROM_READ(offset++, val);
1976 ee->ee_cal_pier[mode][0] =
1977 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
1978 ee->ee_cal_pier[mode][1] =
1979 ath5k_eeprom_bin2freq(ah, (val >> 8) & 0xff, mode);
1980
1981 AR5K_EEPROM_READ(offset++, val);
1982 ee->ee_turbo_max_power[mode] = val & 0x7f;
1983 ee->ee_xr_power[mode] = (val >> 7) & 0x3f;
1984
1985 AR5K_EEPROM_READ(offset++, val);
1986 ee->ee_cal_pier[mode][2] =
1987 ath5k_eeprom_bin2freq(ah, val & 0xff, mode);
1988
1989 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_1)
1990 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f;
1991
1992 AR5K_EEPROM_READ(offset++, val);
1993 ee->ee_i_cal[mode] = (val >> 8) & 0x3f;
1994 ee->ee_q_cal[mode] = (val >> 3) & 0x1f;
1995
1996 if (ah->ah_ee_version >= AR5K_EEPROM_VERSION_4_2) {
1997 AR5K_EEPROM_READ(offset++, val);
1998 ee->ee_cck_ofdm_gain_delta = val & 0xff;
1999 }
2000 }
2001
2002 /*
2003 * Read 5GHz EEPROM channels
2004 */
2005
2006 return 0;
2007 }
2008
2009 /*
2010 * Read the MAC address from eeprom
2011 */
2012 static int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac)
2013 {
2014 u8 mac_d[ETH_ALEN];
2015 u32 total, offset;
2016 u16 data;
2017 int octet, ret;
2018
2019 memset(mac, 0, ETH_ALEN);
2020 memset(mac_d, 0, ETH_ALEN);
2021
2022 ret = ath5k_hw_eeprom_read(ah, 0x20, &data);
2023 if (ret)
2024 return ret;
2025
2026 for (offset = 0x1f, octet = 0, total = 0; offset >= 0x1d; offset--) {
2027 ret = ath5k_hw_eeprom_read(ah, offset, &data);
2028 if (ret)
2029 return ret;
2030
2031 total += data;
2032 mac_d[octet + 1] = data & 0xff;
2033 mac_d[octet] = data >> 8;
2034 octet += 2;
2035 }
2036
2037 memcpy(mac, mac_d, ETH_ALEN);
2038
2039 if (!total || total == 3 * 0xffff)
2040 return -EINVAL;
2041
2042 return 0;
2043 }
2044
2045 /*
2046 * Read/Write regulatory domain
2047 */
2048 static bool ath5k_eeprom_regulation_domain(struct ath5k_hw *ah, bool write,
2049 enum ath5k_regdom *regdomain)
2050 {
2051 u16 ee_regdomain;
2052
2053 /* Read current value */
2054 if (write != true) {
2055 ee_regdomain = ah->ah_capabilities.cap_eeprom.ee_regdomain;
2056 *regdomain = ath5k_regdom_to_ieee(ee_regdomain);
2057 return true;
2058 }
2059
2060 ee_regdomain = ath5k_regdom_from_ieee(*regdomain);
2061
2062 /* Try to write a new value */
2063 if (ah->ah_capabilities.cap_eeprom.ee_protect &
2064 AR5K_EEPROM_PROTECT_WR_128_191)
2065 return false;
2066 if (ath5k_hw_eeprom_write(ah, AR5K_EEPROM_REG_DOMAIN, ee_regdomain)!=0)
2067 return false;
2068
2069 ah->ah_capabilities.cap_eeprom.ee_regdomain = ee_regdomain;
2070
2071 return true;
2072 }
2073
2074 /*
2075 * Use the above to write a new regulatory domain
2076 */
2077 int ath5k_hw_set_regdomain(struct ath5k_hw *ah, u16 regdomain)
2078 {
2079 enum ath5k_regdom ieee_regdomain;
2080
2081 ieee_regdomain = ath5k_regdom_to_ieee(regdomain);
2082
2083 if (ath5k_eeprom_regulation_domain(ah, true, &ieee_regdomain) == true)
2084 return 0;
2085
2086 return -EIO;
2087 }
2088
2089 /*
2090 * Fill the capabilities struct
2091 */
2092 static int ath5k_hw_get_capabilities(struct ath5k_hw *ah)
2093 {
2094 u16 ee_header;
2095
2096 ATH5K_TRACE(ah->ah_sc);
2097 /* Capabilities stored in the EEPROM */
2098 ee_header = ah->ah_capabilities.cap_eeprom.ee_header;
2099
2100 if (ah->ah_version == AR5K_AR5210) {
2101 /*
2102 * Set radio capabilities
2103 * (The AR5110 only supports the middle 5GHz band)
2104 */
2105 ah->ah_capabilities.cap_range.range_5ghz_min = 5120;
2106 ah->ah_capabilities.cap_range.range_5ghz_max = 5430;
2107 ah->ah_capabilities.cap_range.range_2ghz_min = 0;
2108 ah->ah_capabilities.cap_range.range_2ghz_max = 0;
2109
2110 /* Set supported modes */
2111 __set_bit(MODE_IEEE80211A, ah->ah_capabilities.cap_mode);
2112 __set_bit(MODE_ATHEROS_TURBO, ah->ah_capabilities.cap_mode);
2113 } else {
2114 /*
2115 * XXX The tranceiver supports frequencies from 4920 to 6100GHz
2116 * XXX and from 2312 to 2732GHz. There are problems with the
2117 * XXX current ieee80211 implementation because the IEEE
2118 * XXX channel mapping does not support negative channel
2119 * XXX numbers (2312MHz is channel -19). Of course, this
2120 * XXX doesn't matter because these channels are out of range
2121 * XXX but some regulation domains like MKK (Japan) will
2122 * XXX support frequencies somewhere around 4.8GHz.
2123 */
2124
2125 /*
2126 * Set radio capabilities
2127 */
2128
2129 if (AR5K_EEPROM_HDR_11A(ee_header)) {
2130 ah->ah_capabilities.cap_range.range_5ghz_min = 5005; /* 4920 */
2131 ah->ah_capabilities.cap_range.range_5ghz_max = 6100;
2132
2133 /* Set supported modes */
2134 __set_bit(MODE_IEEE80211A,
2135 ah->ah_capabilities.cap_mode);
2136 __set_bit(MODE_ATHEROS_TURBO,
2137 ah->ah_capabilities.cap_mode);
2138 if (ah->ah_version == AR5K_AR5212)
2139 __set_bit(MODE_ATHEROS_TURBOG,
2140 ah->ah_capabilities.cap_mode);
2141 }
2142
2143 /* Enable 802.11b if a 2GHz capable radio (2111/5112) is
2144 * connected */
2145 if (AR5K_EEPROM_HDR_11B(ee_header) ||
2146 AR5K_EEPROM_HDR_11G(ee_header)) {
2147 ah->ah_capabilities.cap_range.range_2ghz_min = 2412; /* 2312 */
2148 ah->ah_capabilities.cap_range.range_2ghz_max = 2732;
2149
2150 if (AR5K_EEPROM_HDR_11B(ee_header))
2151 __set_bit(MODE_IEEE80211B,
2152 ah->ah_capabilities.cap_mode);
2153
2154 if (AR5K_EEPROM_HDR_11G(ee_header))
2155 __set_bit(MODE_IEEE80211G,
2156 ah->ah_capabilities.cap_mode);
2157 }
2158 }
2159
2160 /* GPIO */
2161 ah->ah_gpio_npins = AR5K_NUM_GPIO;
2162
2163 /* Set number of supported TX queues */
2164 if (ah->ah_version == AR5K_AR5210)
2165 ah->ah_capabilities.cap_queues.q_tx_num =
2166 AR5K_NUM_TX_QUEUES_NOQCU;
2167 else
2168 ah->ah_capabilities.cap_queues.q_tx_num = AR5K_NUM_TX_QUEUES;
2169
2170 return 0;
2171 }
2172
2173 /*********************************\
2174 Protocol Control Unit Functions
2175 \*********************************/
2176
2177 /*
2178 * Set Operation mode
2179 */
2180 int ath5k_hw_set_opmode(struct ath5k_hw *ah)
2181 {
2182 u32 pcu_reg, beacon_reg, low_id, high_id;
2183
2184 pcu_reg = 0;
2185 beacon_reg = 0;
2186
2187 ATH5K_TRACE(ah->ah_sc);
2188
2189 switch (ah->ah_op_mode) {
2190 case IEEE80211_IF_TYPE_IBSS:
2191 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_DESC_ANTENNA |
2192 (ah->ah_version == AR5K_AR5210 ?
2193 AR5K_STA_ID1_NO_PSPOLL : 0);
2194 beacon_reg |= AR5K_BCR_ADHOC;
2195 break;
2196
2197 case IEEE80211_IF_TYPE_AP:
2198 pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_RTS_DEF_ANTENNA |
2199 (ah->ah_version == AR5K_AR5210 ?
2200 AR5K_STA_ID1_NO_PSPOLL : 0);
2201 beacon_reg |= AR5K_BCR_AP;
2202 break;
2203
2204 case IEEE80211_IF_TYPE_STA:
2205 pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
2206 (ah->ah_version == AR5K_AR5210 ?
2207 AR5K_STA_ID1_PWR_SV : 0);
2208 case IEEE80211_IF_TYPE_MNTR:
2209 pcu_reg |= AR5K_STA_ID1_DEFAULT_ANTENNA |
2210 (ah->ah_version == AR5K_AR5210 ?
2211 AR5K_STA_ID1_NO_PSPOLL : 0);
2212 break;
2213
2214 default:
2215 return -EINVAL;
2216 }
2217
2218 /*
2219 * Set PCU registers
2220 */
2221 low_id = AR5K_LOW_ID(ah->ah_sta_id);
2222 high_id = AR5K_HIGH_ID(ah->ah_sta_id);
2223 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
2224 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
2225
2226 /*
2227 * Set Beacon Control Register on 5210
2228 */
2229 if (ah->ah_version == AR5K_AR5210)
2230 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
2231
2232 return 0;
2233 }
2234
2235 /*
2236 * BSSID Functions
2237 */
2238
2239 /*
2240 * Get station id
2241 */
2242 void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac)
2243 {
2244 ATH5K_TRACE(ah->ah_sc);
2245 memcpy(mac, ah->ah_sta_id, ETH_ALEN);
2246 }
2247
2248 /*
2249 * Set station id
2250 */
2251 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
2252 {
2253 u32 low_id, high_id;
2254
2255 ATH5K_TRACE(ah->ah_sc);
2256 /* Set new station ID */
2257 memcpy(ah->ah_sta_id, mac, ETH_ALEN);
2258
2259 low_id = AR5K_LOW_ID(mac);
2260 high_id = AR5K_HIGH_ID(mac);
2261
2262 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
2263 ath5k_hw_reg_write(ah, high_id, AR5K_STA_ID1);
2264
2265 return 0;
2266 }
2267
2268 /*
2269 * Set BSSID
2270 */
2271 void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id)
2272 {
2273 u32 low_id, high_id;
2274 u16 tim_offset = 0;
2275
2276 /*
2277 * Set simple BSSID mask on 5212
2278 */
2279 if (ah->ah_version == AR5K_AR5212) {
2280 ath5k_hw_reg_write(ah, 0xfffffff, AR5K_BSS_IDM0);
2281 ath5k_hw_reg_write(ah, 0xfffffff, AR5K_BSS_IDM1);
2282 }
2283
2284 /*
2285 * Set BSSID which triggers the "SME Join" operation
2286 */
2287 low_id = AR5K_LOW_ID(bssid);
2288 high_id = AR5K_HIGH_ID(bssid);
2289 ath5k_hw_reg_write(ah, low_id, AR5K_BSS_ID0);
2290 ath5k_hw_reg_write(ah, high_id | ((assoc_id & 0x3fff) <<
2291 AR5K_BSS_ID1_AID_S), AR5K_BSS_ID1);
2292
2293 if (assoc_id == 0) {
2294 ath5k_hw_disable_pspoll(ah);
2295 return;
2296 }
2297
2298 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM,
2299 tim_offset ? tim_offset + 4 : 0);
2300
2301 ath5k_hw_enable_pspoll(ah, NULL, 0);
2302 }
2303 /**
2304 * ath5k_hw_set_bssid_mask - set common bits we should listen to
2305 *
2306 * The bssid_mask is a utility used by AR5212 hardware to inform the hardware
2307 * which bits of the interface's MAC address should be looked at when trying
2308 * to decide which packets to ACK. In station mode every bit matters. In AP
2309 * mode with a single BSS every bit matters as well. In AP mode with
2310 * multiple BSSes not every bit matters.
2311 *
2312 * @ah: the &struct ath5k_hw
2313 * @mask: the bssid_mask, a u8 array of size ETH_ALEN
2314 *
2315 * Note that this is a simple filter and *does* not filter out all
2316 * relevant frames. Some non-relevant frames will get through, probability
2317 * jocks are welcomed to compute.
2318 *
2319 * When handling multiple BSSes (or VAPs) you can get the BSSID mask by
2320 * computing the set of:
2321 *
2322 * ~ ( MAC XOR BSSID )
2323 *
2324 * When you do this you are essentially computing the common bits. Later it
2325 * is assumed the harware will "and" (&) the BSSID mask with the MAC address
2326 * to obtain the relevant bits which should match on the destination frame.
2327 *
2328 * Simple example: on your card you have have two BSSes you have created with
2329 * BSSID-01 and BSSID-02. Lets assume BSSID-01 will not use the MAC address.
2330 * There is another BSSID-03 but you are not part of it. For simplicity's sake,
2331 * assuming only 4 bits for a mac address and for BSSIDs you can then have:
2332 *
2333 * \
2334 * MAC: 0001 |
2335 * BSSID-01: 0100 | --> Belongs to us
2336 * BSSID-02: 1001 |
2337 * /
2338 * -------------------
2339 * BSSID-03: 0110 | --> External
2340 * -------------------
2341 *
2342 * Our bssid_mask would then be:
2343 *
2344 * On loop iteration for BSSID-01:
2345 * ~(0001 ^ 0100) -> ~(0101)
2346 * -> 1010
2347 * bssid_mask = 1010
2348 *
2349 * On loop iteration for BSSID-02:
2350 * bssid_mask &= ~(0001 ^ 1001)
2351 * bssid_mask = (1010) & ~(0001 ^ 1001)
2352 * bssid_mask = (1010) & ~(1001)
2353 * bssid_mask = (1010) & (0110)
2354 * bssid_mask = 0010
2355 *
2356 * A bssid_mask of 0010 means "only pay attention to the second least
2357 * significant bit". This is because its the only bit common
2358 * amongst the MAC and all BSSIDs we support. To findout what the real
2359 * common bit is we can simply "&" the bssid_mask now with any BSSID we have
2360 * or our MAC address (we assume the hardware uses the MAC address).
2361 *
2362 * Now, suppose there's an incoming frame for BSSID-03:
2363 *
2364 * IFRAME-01: 0110
2365 *
2366 * An easy eye-inspeciton of this already should tell you that this frame
2367 * will not pass our check. This is beacuse the bssid_mask tells the
2368 * hardware to only look at the second least significant bit and the
2369 * common bit amongst the MAC and BSSIDs is 0, this frame has the 2nd LSB
2370 * as 1, which does not match 0.
2371 *
2372 * So with IFRAME-01 we *assume* the hardware will do:
2373 *
2374 * allow = (IFRAME-01 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
2375 * --> allow = (0110 & 0010) == (0010 & 0001) ? 1 : 0;
2376 * --> allow = (0010) == 0000 ? 1 : 0;
2377 * --> allow = 0
2378 *
2379 * Lets now test a frame that should work:
2380 *
2381 * IFRAME-02: 0001 (we should allow)
2382 *
2383 * allow = (0001 & 1010) == 1010
2384 *
2385 * allow = (IFRAME-02 & bssid_mask) == (bssid_mask & MAC) ? 1 : 0;
2386 * --> allow = (0001 & 0010) == (0010 & 0001) ? 1 :0;
2387 * --> allow = (0010) == (0010)
2388 * --> allow = 1
2389 *
2390 * Other examples:
2391 *
2392 * IFRAME-03: 0100 --> allowed
2393 * IFRAME-04: 1001 --> allowed
2394 * IFRAME-05: 1101 --> allowed but its not for us!!!
2395 *
2396 */
2397 int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
2398 {
2399 u32 low_id, high_id;
2400 ATH5K_TRACE(ah->ah_sc);
2401
2402 if (ah->ah_version == AR5K_AR5212) {
2403 low_id = AR5K_LOW_ID(mask);
2404 high_id = AR5K_HIGH_ID(mask);
2405
2406 ath5k_hw_reg_write(ah, low_id, AR5K_BSS_IDM0);
2407 ath5k_hw_reg_write(ah, high_id, AR5K_BSS_IDM1);
2408
2409 return 0;
2410 }
2411
2412 return -EIO;
2413 }
2414
2415 /*
2416 * Receive start/stop functions
2417 */
2418
2419 /*
2420 * Start receive on PCU
2421 */
2422 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
2423 {
2424 ATH5K_TRACE(ah->ah_sc);
2425 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
2426 }
2427
2428 /*
2429 * Stop receive on PCU
2430 */
2431 void ath5k_hw_stop_pcu_recv(struct ath5k_hw *ah)
2432 {
2433 ATH5K_TRACE(ah->ah_sc);
2434 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
2435 }
2436
2437 /*
2438 * RX Filter functions
2439 */
2440
2441 /*
2442 * Set multicast filter
2443 */
2444 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
2445 {
2446 ATH5K_TRACE(ah->ah_sc);
2447 /* Set the multicat filter */
2448 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
2449 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
2450 }
2451
2452 /*
2453 * Set multicast filter by index
2454 */
2455 int ath5k_hw_set_mcast_filterindex(struct ath5k_hw *ah, u32 index)
2456 {
2457
2458 ATH5K_TRACE(ah->ah_sc);
2459 if (index >= 64)
2460 return -EINVAL;
2461 else if (index >= 32)
2462 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER1,
2463 (1 << (index - 32)));
2464 else
2465 AR5K_REG_ENABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index));
2466
2467 return 0;
2468 }
2469
2470 /*
2471 * Clear Multicast filter by index
2472 */
2473 int ath5k_hw_clear_mcast_filter_idx(struct ath5k_hw *ah, u32 index)
2474 {
2475
2476 ATH5K_TRACE(ah->ah_sc);
2477 if (index >= 64)
2478 return -EINVAL;
2479 else if (index >= 32)
2480 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER1,
2481 (1 << (index - 32)));
2482 else
2483 AR5K_REG_DISABLE_BITS(ah, AR5K_MCAST_FILTER0, (1 << index));
2484
2485 return 0;
2486 }
2487
2488 /*
2489 * Get current rx filter
2490 */
2491 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
2492 {
2493 u32 data, filter = 0;
2494
2495 ATH5K_TRACE(ah->ah_sc);
2496 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
2497
2498 /*Radar detection for 5212*/
2499 if (ah->ah_version == AR5K_AR5212) {
2500 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
2501
2502 if (data & AR5K_PHY_ERR_FIL_RADAR)
2503 filter |= AR5K_RX_FILTER_RADARERR;
2504 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK))
2505 filter |= AR5K_RX_FILTER_PHYERR;
2506 }
2507
2508 return filter;
2509 }
2510
2511 /*
2512 * Set rx filter
2513 */
2514 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
2515 {
2516 u32 data = 0;
2517
2518 ATH5K_TRACE(ah->ah_sc);
2519
2520 /* Set PHY error filter register on 5212*/
2521 if (ah->ah_version == AR5K_AR5212) {
2522 if (filter & AR5K_RX_FILTER_RADARERR)
2523 data |= AR5K_PHY_ERR_FIL_RADAR;
2524 if (filter & AR5K_RX_FILTER_PHYERR)
2525 data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK;
2526 }
2527
2528 /*
2529 * The AR5210 uses promiscous mode to detect radar activity
2530 */
2531 if (ah->ah_version == AR5K_AR5210 &&
2532 (filter & AR5K_RX_FILTER_RADARERR)) {
2533 filter &= ~AR5K_RX_FILTER_RADARERR;
2534 filter |= AR5K_RX_FILTER_PROM;
2535 }
2536
2537 /*Zero length DMA*/
2538 if (data)
2539 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
2540 else
2541 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
2542
2543 /*Write RX Filter register*/
2544 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER);
2545
2546 /*Write PHY error filter register on 5212*/
2547 if (ah->ah_version == AR5K_AR5212)
2548 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL);
2549
2550 }
2551
2552 /*
2553 * Beacon related functions
2554 */
2555
2556 /*
2557 * Get a 32bit TSF
2558 */
2559 u32 ath5k_hw_get_tsf32(struct ath5k_hw *ah)
2560 {
2561 ATH5K_TRACE(ah->ah_sc);
2562 return ath5k_hw_reg_read(ah, AR5K_TSF_L32);
2563 }
2564
2565 /*
2566 * Get the full 64bit TSF
2567 */
2568 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
2569 {
2570 u64 tsf = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
2571 ATH5K_TRACE(ah->ah_sc);
2572
2573 return ath5k_hw_reg_read(ah, AR5K_TSF_L32) | (tsf << 32);
2574 }
2575
2576 /*
2577 * Force a TSF reset
2578 */
2579 void ath5k_hw_reset_tsf(struct ath5k_hw *ah)
2580 {
2581 ATH5K_TRACE(ah->ah_sc);
2582 AR5K_REG_ENABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_RESET_TSF);
2583 }
2584
2585 /*
2586 * Initialize beacon timers
2587 */
2588 void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
2589 {
2590 u32 timer1, timer2, timer3;
2591
2592 ATH5K_TRACE(ah->ah_sc);
2593 /*
2594 * Set the additional timers by mode
2595 */
2596 switch (ah->ah_op_mode) {
2597 case IEEE80211_IF_TYPE_STA:
2598 if (ah->ah_version == AR5K_AR5210) {
2599 timer1 = 0xffffffff;
2600 timer2 = 0xffffffff;
2601 } else {
2602 timer1 = 0x0000ffff;
2603 timer2 = 0x0007ffff;
2604 }
2605 break;
2606
2607 default:
2608 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3;
2609 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3;
2610 }
2611
2612 timer3 = next_beacon + (ah->ah_atim_window ? ah->ah_atim_window : 1);
2613
2614 /*
2615 * Set the beacon register and enable all timers.
2616 * (next beacon, DMA beacon, software beacon, ATIM window time)
2617 */
2618 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
2619 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1);
2620 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2);
2621 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3);
2622
2623 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD |
2624 AR5K_BEACON_RESET_TSF | AR5K_BEACON_ENABLE),
2625 AR5K_BEACON);
2626 }
2627
2628 #if 0
2629 /*
2630 * Set beacon timers
2631 */
2632 int ath5k_hw_set_beacon_timers(struct ath5k_hw *ah,
2633 const struct ath5k_beacon_state *state)
2634 {
2635 u32 cfp_period, next_cfp, dtim, interval, next_beacon;
2636
2637 /*
2638 * TODO: should be changed through *state
2639 * review struct ath5k_beacon_state struct
2640 *
2641 * XXX: These are used for cfp period bellow, are they
2642 * ok ? Is it O.K. for tsf here to be 0 or should we use
2643 * get_tsf ?
2644 */
2645 u32 dtim_count = 0; /* XXX */
2646 u32 cfp_count = 0; /* XXX */
2647 u32 tsf = 0; /* XXX */
2648
2649 ATH5K_TRACE(ah->ah_sc);
2650 /* Return on an invalid beacon state */
2651 if (state->bs_interval < 1)
2652 return -EINVAL;
2653
2654 interval = state->bs_interval;
2655 dtim = state->bs_dtim_period;
2656
2657 /*
2658 * PCF support?
2659 */
2660 if (state->bs_cfp_period > 0) {
2661 /*
2662 * Enable PCF mode and set the CFP
2663 * (Contention Free Period) and timer registers
2664 */
2665 cfp_period = state->bs_cfp_period * state->bs_dtim_period *
2666 state->bs_interval;
2667 next_cfp = (cfp_count * state->bs_dtim_period + dtim_count) *
2668 state->bs_interval;
2669
2670 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
2671 AR5K_STA_ID1_DEFAULT_ANTENNA |
2672 AR5K_STA_ID1_PCF);
2673 ath5k_hw_reg_write(ah, cfp_period, AR5K_CFP_PERIOD);
2674 ath5k_hw_reg_write(ah, state->bs_cfp_max_duration,
2675 AR5K_CFP_DUR);
2676 ath5k_hw_reg_write(ah, (tsf + (next_cfp == 0 ? cfp_period :
2677 next_cfp)) << 3, AR5K_TIMER2);
2678 } else {
2679 /* Disable PCF mode */
2680 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
2681 AR5K_STA_ID1_DEFAULT_ANTENNA |
2682 AR5K_STA_ID1_PCF);
2683 }
2684
2685 /*
2686 * Enable the beacon timer register
2687 */
2688 ath5k_hw_reg_write(ah, state->bs_next_beacon, AR5K_TIMER0);
2689
2690 /*
2691 * Start the beacon timers
2692 */
2693 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_BEACON) &~
2694 (AR5K_BEACON_PERIOD | AR5K_BEACON_TIM)) |
2695 AR5K_REG_SM(state->bs_tim_offset ? state->bs_tim_offset + 4 : 0,
2696 AR5K_BEACON_TIM) | AR5K_REG_SM(state->bs_interval,
2697 AR5K_BEACON_PERIOD), AR5K_BEACON);
2698
2699 /*
2700 * Write new beacon miss threshold, if it appears to be valid
2701 * XXX: Figure out right values for min <= bs_bmiss_threshold <= max
2702 * and return if its not in range. We can test this by reading value and
2703 * setting value to a largest value and seeing which values register.
2704 */
2705
2706 AR5K_REG_WRITE_BITS(ah, AR5K_RSSI_THR, AR5K_RSSI_THR_BMISS,
2707 state->bs_bmiss_threshold);
2708
2709 /*
2710 * Set sleep control register
2711 * XXX: Didn't find this in 5210 code but since this register
2712 * exists also in ar5k's 5210 headers i leave it as common code.
2713 */
2714 AR5K_REG_WRITE_BITS(ah, AR5K_SLEEP_CTL, AR5K_SLEEP_CTL_SLDUR,
2715 (state->bs_sleep_duration - 3) << 3);
2716
2717 /*
2718 * Set enhanced sleep registers on 5212
2719 */
2720 if (ah->ah_version == AR5K_AR5212) {
2721 if (state->bs_sleep_duration > state->bs_interval &&
2722 roundup(state->bs_sleep_duration, interval) ==
2723 state->bs_sleep_duration)
2724 interval = state->bs_sleep_duration;
2725
2726 if (state->bs_sleep_duration > dtim && (dtim == 0 ||
2727 roundup(state->bs_sleep_duration, dtim) ==
2728 state->bs_sleep_duration))
2729 dtim = state->bs_sleep_duration;
2730
2731 if (interval > dtim)
2732 return -EINVAL;
2733
2734 next_beacon = interval == dtim ? state->bs_next_dtim :
2735 state->bs_next_beacon;
2736
2737 ath5k_hw_reg_write(ah,
2738 AR5K_REG_SM((state->bs_next_dtim - 3) << 3,
2739 AR5K_SLEEP0_NEXT_DTIM) |
2740 AR5K_REG_SM(10, AR5K_SLEEP0_CABTO) |
2741 AR5K_SLEEP0_ENH_SLEEP_EN |
2742 AR5K_SLEEP0_ASSUME_DTIM, AR5K_SLEEP0);
2743
2744 ath5k_hw_reg_write(ah, AR5K_REG_SM((next_beacon - 3) << 3,
2745 AR5K_SLEEP1_NEXT_TIM) |
2746 AR5K_REG_SM(10, AR5K_SLEEP1_BEACON_TO), AR5K_SLEEP1);
2747
2748 ath5k_hw_reg_write(ah,
2749 AR5K_REG_SM(interval, AR5K_SLEEP2_TIM_PER) |
2750 AR5K_REG_SM(dtim, AR5K_SLEEP2_DTIM_PER), AR5K_SLEEP2);
2751 }
2752
2753 return 0;
2754 }
2755
2756 /*
2757 * Reset beacon timers
2758 */
2759 void ath5k_hw_reset_beacon(struct ath5k_hw *ah)
2760 {
2761 ATH5K_TRACE(ah->ah_sc);
2762 /*
2763 * Disable beacon timer
2764 */
2765 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
2766
2767 /*
2768 * Disable some beacon register values
2769 */
2770 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
2771 AR5K_STA_ID1_DEFAULT_ANTENNA | AR5K_STA_ID1_PCF);
2772 ath5k_hw_reg_write(ah, AR5K_BEACON_PERIOD, AR5K_BEACON);
2773 }
2774
2775 /*
2776 * Wait for beacon queue to finish
2777 */
2778 int ath5k_hw_beaconq_finish(struct ath5k_hw *ah, unsigned long phys_addr)
2779 {
2780 unsigned int i;
2781 int ret;
2782
2783 ATH5K_TRACE(ah->ah_sc);
2784
2785 /* 5210 doesn't have QCU*/
2786 if (ah->ah_version == AR5K_AR5210) {
2787 /*
2788 * Wait for beaconn queue to finish by checking
2789 * Control Register and Beacon Status Register.
2790 */
2791 for (i = AR5K_TUNE_BEACON_INTERVAL / 2; i > 0; i--) {
2792 if (!(ath5k_hw_reg_read(ah, AR5K_BSR) & AR5K_BSR_TXQ1F)
2793 ||
2794 !(ath5k_hw_reg_read(ah, AR5K_CR) & AR5K_BSR_TXQ1F))
2795 break;
2796 udelay(10);
2797 }
2798
2799 /* Timeout... */
2800 if (i <= 0) {
2801 /*
2802 * Re-schedule the beacon queue
2803 */
2804 ath5k_hw_reg_write(ah, phys_addr, AR5K_NOQCU_TXDP1);
2805 ath5k_hw_reg_write(ah, AR5K_BCR_TQ1V | AR5K_BCR_BDMAE,
2806 AR5K_BCR);
2807
2808 return -EIO;
2809 }
2810 ret = 0;
2811 } else {
2812 /*5211/5212*/
2813 ret = ath5k_hw_register_timeout(ah,
2814 AR5K_QUEUE_STATUS(AR5K_TX_QUEUE_ID_BEACON),
2815 AR5K_QCU_STS_FRMPENDCNT, 0, false);
2816
2817 if (AR5K_REG_READ_Q(ah, AR5K_QCU_TXE, AR5K_TX_QUEUE_ID_BEACON))
2818 return -EIO;
2819 }
2820
2821 return ret;
2822 }
2823 #endif
2824
2825 /*
2826 * Update mib counters (statistics)
2827 */
2828 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah,
2829 struct ath5k_mib_stats *statistics)
2830 {
2831 ATH5K_TRACE(ah->ah_sc);
2832 /* Read-And-Clear */
2833 statistics->ackrcv_bad += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
2834 statistics->rts_bad += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
2835 statistics->rts_good += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
2836 statistics->fcs_bad += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
2837 statistics->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
2838
2839 /* Reset profile count registers on 5212*/
2840 if (ah->ah_version == AR5K_AR5212) {
2841 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_TX);
2842 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RX);
2843 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_RXCLR);
2844 ath5k_hw_reg_write(ah, 0, AR5K_PROFCNT_CYCLE);
2845 }
2846 }
2847
2848 /** ath5k_hw_set_ack_bitrate - set bitrate for ACKs
2849 *
2850 * @ah: the &struct ath5k_hw
2851 * @high: determines if to use low bit rate or now
2852 */
2853 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high)
2854 {
2855 if (ah->ah_version != AR5K_AR5212)
2856 return;
2857 else {
2858 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB;
2859 if (high)
2860 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);
2861 else
2862 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);
2863 }
2864 }
2865
2866
2867 /*
2868 * ACK/CTS Timeouts
2869 */
2870
2871 /*
2872 * Set ACK timeout on PCU
2873 */
2874 int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
2875 {
2876 ATH5K_TRACE(ah->ah_sc);
2877 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK),
2878 ah->ah_turbo) <= timeout)
2879 return -EINVAL;
2880
2881 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
2882 ath5k_hw_htoclock(timeout, ah->ah_turbo));
2883
2884 return 0;
2885 }
2886
2887 /*
2888 * Read the ACK timeout from PCU
2889 */
2890 unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah)
2891 {
2892 ATH5K_TRACE(ah->ah_sc);
2893
2894 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah,
2895 AR5K_TIME_OUT), AR5K_TIME_OUT_ACK), ah->ah_turbo);
2896 }
2897
2898 /*
2899 * Set CTS timeout on PCU
2900 */
2901 int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
2902 {
2903 ATH5K_TRACE(ah->ah_sc);
2904 if (ath5k_hw_clocktoh(AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS),
2905 ah->ah_turbo) <= timeout)
2906 return -EINVAL;
2907
2908 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
2909 ath5k_hw_htoclock(timeout, ah->ah_turbo));
2910
2911 return 0;
2912 }
2913
2914 /*
2915 * Read CTS timeout from PCU
2916 */
2917 unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah)
2918 {
2919 ATH5K_TRACE(ah->ah_sc);
2920 return ath5k_hw_clocktoh(AR5K_REG_MS(ath5k_hw_reg_read(ah,
2921 AR5K_TIME_OUT), AR5K_TIME_OUT_CTS), ah->ah_turbo);
2922 }
2923
2924 /*
2925 * Key table (WEP) functions
2926 */
2927
2928 int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
2929 {
2930 unsigned int i;
2931
2932 ATH5K_TRACE(ah->ah_sc);
2933 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
2934
2935 for (i = 0; i < AR5K_KEYCACHE_SIZE; i++)
2936 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i));
2937
2938 /* Set NULL encryption on non-5210*/
2939 if (ah->ah_version != AR5K_AR5210)
2940 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
2941 AR5K_KEYTABLE_TYPE(entry));
2942
2943 return 0;
2944 }
2945
2946 int ath5k_hw_is_key_valid(struct ath5k_hw *ah, u16 entry)
2947 {
2948 ATH5K_TRACE(ah->ah_sc);
2949 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
2950
2951 /* Check the validation flag at the end of the entry */
2952 return ath5k_hw_reg_read(ah, AR5K_KEYTABLE_MAC1(entry)) &
2953 AR5K_KEYTABLE_VALID;
2954 }
2955
2956 int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry,
2957 const struct ieee80211_key_conf *key, const u8 *mac)
2958 {
2959 unsigned int i;
2960 __le32 key_v[5] = {};
2961 u32 keytype;
2962
2963 ATH5K_TRACE(ah->ah_sc);
2964
2965 /* key->keylen comes in from mac80211 in bytes */
2966
2967 if (key->keylen > AR5K_KEYTABLE_SIZE / 8)
2968 return -EOPNOTSUPP;
2969
2970 switch (key->keylen) {
2971 /* WEP 40-bit = 40-bit entered key + 24 bit IV = 64-bit */
2972 case 40 / 8:
2973 memcpy(&key_v[0], key->key, 5);
2974 keytype = AR5K_KEYTABLE_TYPE_40;
2975 break;
2976
2977 /* WEP 104-bit = 104-bit entered key + 24-bit IV = 128-bit */
2978 case 104 / 8:
2979 memcpy(&key_v[0], &key->key[0], 6);
2980 memcpy(&key_v[2], &key->key[6], 6);
2981 memcpy(&key_v[4], &key->key[12], 1);
2982 keytype = AR5K_KEYTABLE_TYPE_104;
2983 break;
2984 /* WEP 128-bit = 128-bit entered key + 24 bit IV = 152-bit */
2985 case 128 / 8:
2986 memcpy(&key_v[0], &key->key[0], 6);
2987 memcpy(&key_v[2], &key->key[6], 6);
2988 memcpy(&key_v[4], &key->key[12], 4);
2989 keytype = AR5K_KEYTABLE_TYPE_128;
2990 break;
2991
2992 default:
2993 return -EINVAL; /* shouldn't happen */
2994 }
2995
2996 for (i = 0; i < ARRAY_SIZE(key_v); i++)
2997 ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]),
2998 AR5K_KEYTABLE_OFF(entry, i));
2999
3000 ath5k_hw_reg_write(ah, keytype, AR5K_KEYTABLE_TYPE(entry));
3001
3002 return ath5k_hw_set_key_lladdr(ah, entry, mac);
3003 }
3004
3005 int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac)
3006 {
3007 u32 low_id, high_id;
3008
3009 ATH5K_TRACE(ah->ah_sc);
3010 /* Invalid entry (key table overflow) */
3011 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
3012
3013 /* MAC may be NULL if it's a broadcast key. In this case no need to
3014 * to compute AR5K_LOW_ID and AR5K_HIGH_ID as we already know it. */
3015 if (unlikely(mac == NULL)) {
3016 low_id = 0xffffffff;
3017 high_id = 0xffff | AR5K_KEYTABLE_VALID;
3018 } else {
3019 low_id = AR5K_LOW_ID(mac);
3020 high_id = AR5K_HIGH_ID(mac) | AR5K_KEYTABLE_VALID;
3021 }
3022
3023 ath5k_hw_reg_write(ah, low_id, AR5K_KEYTABLE_MAC0(entry));
3024 ath5k_hw_reg_write(ah, high_id, AR5K_KEYTABLE_MAC1(entry));
3025
3026 return 0;
3027 }
3028
3029
3030 /********************************************\
3031 Queue Control Unit, DFS Control Unit Functions
3032 \********************************************/
3033
3034 /*
3035 * Initialize a transmit queue
3036 */
3037 int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, enum ath5k_tx_queue queue_type,
3038 struct ath5k_txq_info *queue_info)
3039 {
3040 unsigned int queue;
3041 int ret;
3042
3043 ATH5K_TRACE(ah->ah_sc);
3044
3045 /*
3046 * Get queue by type
3047 */
3048 /*5210 only has 2 queues*/
3049 if (ah->ah_version == AR5K_AR5210) {
3050 switch (queue_type) {
3051 case AR5K_TX_QUEUE_DATA:
3052 queue = AR5K_TX_QUEUE_ID_NOQCU_DATA;
3053 break;
3054 case AR5K_TX_QUEUE_BEACON:
3055 case AR5K_TX_QUEUE_CAB:
3056 queue = AR5K_TX_QUEUE_ID_NOQCU_BEACON;
3057 break;
3058 default:
3059 return -EINVAL;
3060 }
3061 } else {
3062 switch (queue_type) {
3063 case AR5K_TX_QUEUE_DATA:
3064 for (queue = AR5K_TX_QUEUE_ID_DATA_MIN;
3065 ah->ah_txq[queue].tqi_type !=
3066 AR5K_TX_QUEUE_INACTIVE; queue++) {
3067
3068 if (queue > AR5K_TX_QUEUE_ID_DATA_MAX)
3069 return -EINVAL;
3070 }
3071 break;
3072 case AR5K_TX_QUEUE_UAPSD:
3073 queue = AR5K_TX_QUEUE_ID_UAPSD;
3074 break;
3075 case AR5K_TX_QUEUE_BEACON:
3076 queue = AR5K_TX_QUEUE_ID_BEACON;
3077 break;
3078 case AR5K_TX_QUEUE_CAB:
3079 queue = AR5K_TX_QUEUE_ID_CAB;
3080 break;
3081 case AR5K_TX_QUEUE_XR_DATA:
3082 if (ah->ah_version != AR5K_AR5212)
3083 ATH5K_ERR(ah->ah_sc,
3084 "XR data queues only supported in"
3085 " 5212!\n");
3086 queue = AR5K_TX_QUEUE_ID_XR_DATA;
3087 break;
3088 default:
3089 return -EINVAL;
3090 }
3091 }
3092
3093 /*
3094 * Setup internal queue structure
3095 */
3096 memset(&ah->ah_txq[queue], 0, sizeof(struct ath5k_txq_info));
3097 ah->ah_txq[queue].tqi_type = queue_type;
3098
3099 if (queue_info != NULL) {
3100 queue_info->tqi_type = queue_type;
3101 ret = ath5k_hw_setup_tx_queueprops(ah, queue, queue_info);
3102 if (ret)
3103 return ret;
3104 }
3105 /*
3106 * We use ah_txq_status to hold a temp value for
3107 * the Secondary interrupt mask registers on 5211+
3108 * check out ath5k_hw_reset_tx_queue
3109 */
3110 AR5K_Q_ENABLE_BITS(ah->ah_txq_status, queue);
3111
3112 return queue;
3113 }
3114
3115 /*
3116 * Setup a transmit queue
3117 */
3118 int ath5k_hw_setup_tx_queueprops(struct ath5k_hw *ah, int queue,
3119 const struct ath5k_txq_info *queue_info)
3120 {
3121 ATH5K_TRACE(ah->ah_sc);
3122 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3123
3124 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
3125 return -EIO;
3126
3127 memcpy(&ah->ah_txq[queue], queue_info, sizeof(struct ath5k_txq_info));
3128
3129 /*XXX: Is this supported on 5210 ?*/
3130 if ((queue_info->tqi_type == AR5K_TX_QUEUE_DATA &&
3131 ((queue_info->tqi_subtype == AR5K_WME_AC_VI) ||
3132 (queue_info->tqi_subtype == AR5K_WME_AC_VO))) ||
3133 queue_info->tqi_type == AR5K_TX_QUEUE_UAPSD)
3134 ah->ah_txq[queue].tqi_flags |= AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS;
3135
3136 return 0;
3137 }
3138
3139 /*
3140 * Get properties for a specific transmit queue
3141 */
3142 int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue,
3143 struct ath5k_txq_info *queue_info)
3144 {
3145 ATH5K_TRACE(ah->ah_sc);
3146 memcpy(queue_info, &ah->ah_txq[queue], sizeof(struct ath5k_txq_info));
3147 return 0;
3148 }
3149
3150 /*
3151 * Set a transmit queue inactive
3152 */
3153 void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3154 {
3155 ATH5K_TRACE(ah->ah_sc);
3156 if (WARN_ON(queue >= ah->ah_capabilities.cap_queues.q_tx_num))
3157 return;
3158
3159 /* This queue will be skipped in further operations */
3160 ah->ah_txq[queue].tqi_type = AR5K_TX_QUEUE_INACTIVE;
3161 /*For SIMR setup*/
3162 AR5K_Q_DISABLE_BITS(ah->ah_txq_status, queue);
3163 }
3164
3165 /*
3166 * Set DFS params for a transmit queue
3167 */
3168 int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue)
3169 {
3170 u32 cw_min, cw_max, retry_lg, retry_sh;
3171 struct ath5k_txq_info *tq = &ah->ah_txq[queue];
3172
3173 ATH5K_TRACE(ah->ah_sc);
3174 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3175
3176 tq = &ah->ah_txq[queue];
3177
3178 if (tq->tqi_type == AR5K_TX_QUEUE_INACTIVE)
3179 return 0;
3180
3181 if (ah->ah_version == AR5K_AR5210) {
3182 /* Only handle data queues, others will be ignored */
3183 if (tq->tqi_type != AR5K_TX_QUEUE_DATA)
3184 return 0;
3185
3186 /* Set Slot time */
3187 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3188 AR5K_INIT_SLOT_TIME_TURBO : AR5K_INIT_SLOT_TIME,
3189 AR5K_SLOT_TIME);
3190 /* Set ACK_CTS timeout */
3191 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3192 AR5K_INIT_ACK_CTS_TIMEOUT_TURBO :
3193 AR5K_INIT_ACK_CTS_TIMEOUT, AR5K_SLOT_TIME);
3194 /* Set Transmit Latency */
3195 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3196 AR5K_INIT_TRANSMIT_LATENCY_TURBO :
3197 AR5K_INIT_TRANSMIT_LATENCY, AR5K_USEC_5210);
3198 /* Set IFS0 */
3199 if (ah->ah_turbo == true)
3200 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS_TURBO +
3201 (ah->ah_aifs + tq->tqi_aifs) *
3202 AR5K_INIT_SLOT_TIME_TURBO) <<
3203 AR5K_IFS0_DIFS_S) | AR5K_INIT_SIFS_TURBO,
3204 AR5K_IFS0);
3205 else
3206 ath5k_hw_reg_write(ah, ((AR5K_INIT_SIFS +
3207 (ah->ah_aifs + tq->tqi_aifs) *
3208 AR5K_INIT_SLOT_TIME) << AR5K_IFS0_DIFS_S) |
3209 AR5K_INIT_SIFS, AR5K_IFS0);
3210
3211 /* Set IFS1 */
3212 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3213 AR5K_INIT_PROTO_TIME_CNTRL_TURBO :
3214 AR5K_INIT_PROTO_TIME_CNTRL, AR5K_IFS1);
3215 /* Set PHY register 0x9844 (??) */
3216 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3217 (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x38 :
3218 (ath5k_hw_reg_read(ah, AR5K_PHY(17)) & ~0x7F) | 0x1C,
3219 AR5K_PHY(17));
3220 /* Set Frame Control Register */
3221 ath5k_hw_reg_write(ah, ah->ah_turbo == true ?
3222 (AR5K_PHY_FRAME_CTL_INI | AR5K_PHY_TURBO_MODE |
3223 AR5K_PHY_TURBO_SHORT | 0x2020) :
3224 (AR5K_PHY_FRAME_CTL_INI | 0x1020),
3225 AR5K_PHY_FRAME_CTL_5210);
3226 }
3227
3228 /*
3229 * Calculate cwmin/max by channel mode
3230 */
3231 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN;
3232 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX;
3233 ah->ah_aifs = AR5K_TUNE_AIFS;
3234 /*XR is only supported on 5212*/
3235 if (IS_CHAN_XR(ah->ah_current_channel) &&
3236 ah->ah_version == AR5K_AR5212) {
3237 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_XR;
3238 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_XR;
3239 ah->ah_aifs = AR5K_TUNE_AIFS_XR;
3240 /*B mode is not supported on 5210*/
3241 } else if (IS_CHAN_B(ah->ah_current_channel) &&
3242 ah->ah_version != AR5K_AR5210) {
3243 cw_min = ah->ah_cw_min = AR5K_TUNE_CWMIN_11B;
3244 cw_max = ah->ah_cw_max = AR5K_TUNE_CWMAX_11B;
3245 ah->ah_aifs = AR5K_TUNE_AIFS_11B;
3246 }
3247
3248 cw_min = 1;
3249 while (cw_min < ah->ah_cw_min)
3250 cw_min = (cw_min << 1) | 1;
3251
3252 cw_min = tq->tqi_cw_min < 0 ? (cw_min >> (-tq->tqi_cw_min)) :
3253 ((cw_min << tq->tqi_cw_min) + (1 << tq->tqi_cw_min) - 1);
3254 cw_max = tq->tqi_cw_max < 0 ? (cw_max >> (-tq->tqi_cw_max)) :
3255 ((cw_max << tq->tqi_cw_max) + (1 << tq->tqi_cw_max) - 1);
3256
3257 /*
3258 * Calculate and set retry limits
3259 */
3260 if (ah->ah_software_retry == true) {
3261 /* XXX Need to test this */
3262 retry_lg = ah->ah_limit_tx_retries;
3263 retry_sh = retry_lg = retry_lg > AR5K_DCU_RETRY_LMT_SH_RETRY ?
3264 AR5K_DCU_RETRY_LMT_SH_RETRY : retry_lg;
3265 } else {
3266 retry_lg = AR5K_INIT_LG_RETRY;
3267 retry_sh = AR5K_INIT_SH_RETRY;
3268 }
3269
3270 /*No QCU/DCU [5210]*/
3271 if (ah->ah_version == AR5K_AR5210) {
3272 ath5k_hw_reg_write(ah,
3273 (cw_min << AR5K_NODCU_RETRY_LMT_CW_MIN_S)
3274 | AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
3275 AR5K_NODCU_RETRY_LMT_SLG_RETRY)
3276 | AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
3277 AR5K_NODCU_RETRY_LMT_SSH_RETRY)
3278 | AR5K_REG_SM(retry_lg, AR5K_NODCU_RETRY_LMT_LG_RETRY)
3279 | AR5K_REG_SM(retry_sh, AR5K_NODCU_RETRY_LMT_SH_RETRY),
3280 AR5K_NODCU_RETRY_LMT);
3281 } else {
3282 /*QCU/DCU [5211+]*/
3283 ath5k_hw_reg_write(ah,
3284 AR5K_REG_SM(AR5K_INIT_SLG_RETRY,
3285 AR5K_DCU_RETRY_LMT_SLG_RETRY) |
3286 AR5K_REG_SM(AR5K_INIT_SSH_RETRY,
3287 AR5K_DCU_RETRY_LMT_SSH_RETRY) |
3288 AR5K_REG_SM(retry_lg, AR5K_DCU_RETRY_LMT_LG_RETRY) |
3289 AR5K_REG_SM(retry_sh, AR5K_DCU_RETRY_LMT_SH_RETRY),
3290 AR5K_QUEUE_DFS_RETRY_LIMIT(queue));
3291
3292 /*===Rest is also for QCU/DCU only [5211+]===*/
3293
3294 /*
3295 * Set initial content window (cw_min/cw_max)
3296 * and arbitrated interframe space (aifs)...
3297 */
3298 ath5k_hw_reg_write(ah,
3299 AR5K_REG_SM(cw_min, AR5K_DCU_LCL_IFS_CW_MIN) |
3300 AR5K_REG_SM(cw_max, AR5K_DCU_LCL_IFS_CW_MAX) |
3301 AR5K_REG_SM(ah->ah_aifs + tq->tqi_aifs,
3302 AR5K_DCU_LCL_IFS_AIFS),
3303 AR5K_QUEUE_DFS_LOCAL_IFS(queue));
3304
3305 /*
3306 * Set misc registers
3307 */
3308 ath5k_hw_reg_write(ah, AR5K_QCU_MISC_DCU_EARLY,
3309 AR5K_QUEUE_MISC(queue));
3310
3311 if (tq->tqi_cbr_period) {
3312 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_cbr_period,
3313 AR5K_QCU_CBRCFG_INTVAL) |
3314 AR5K_REG_SM(tq->tqi_cbr_overflow_limit,
3315 AR5K_QCU_CBRCFG_ORN_THRES),
3316 AR5K_QUEUE_CBRCFG(queue));
3317 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3318 AR5K_QCU_MISC_FRSHED_CBR);
3319 if (tq->tqi_cbr_overflow_limit)
3320 AR5K_REG_ENABLE_BITS(ah,
3321 AR5K_QUEUE_MISC(queue),
3322 AR5K_QCU_MISC_CBR_THRES_ENABLE);
3323 }
3324
3325 if (tq->tqi_ready_time)
3326 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_ready_time,
3327 AR5K_QCU_RDYTIMECFG_INTVAL) |
3328 AR5K_QCU_RDYTIMECFG_ENABLE,
3329 AR5K_QUEUE_RDYTIMECFG(queue));
3330
3331 if (tq->tqi_burst_time) {
3332 ath5k_hw_reg_write(ah, AR5K_REG_SM(tq->tqi_burst_time,
3333 AR5K_DCU_CHAN_TIME_DUR) |
3334 AR5K_DCU_CHAN_TIME_ENABLE,
3335 AR5K_QUEUE_DFS_CHANNEL_TIME(queue));
3336
3337 if (tq->tqi_flags & AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)
3338 AR5K_REG_ENABLE_BITS(ah,
3339 AR5K_QUEUE_MISC(queue),
3340 AR5K_QCU_MISC_TXE);
3341 }
3342
3343 if (tq->tqi_flags & AR5K_TXQ_FLAG_BACKOFF_DISABLE)
3344 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_POST_FR_BKOFF_DIS,
3345 AR5K_QUEUE_DFS_MISC(queue));
3346
3347 if (tq->tqi_flags & AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
3348 ath5k_hw_reg_write(ah, AR5K_DCU_MISC_BACKOFF_FRAG,
3349 AR5K_QUEUE_DFS_MISC(queue));
3350
3351 /*
3352 * Set registers by queue type
3353 */
3354 switch (tq->tqi_type) {
3355 case AR5K_TX_QUEUE_BEACON:
3356 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3357 AR5K_QCU_MISC_FRSHED_DBA_GT |
3358 AR5K_QCU_MISC_CBREXP_BCN |
3359 AR5K_QCU_MISC_BCN_ENABLE);
3360
3361 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
3362 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
3363 AR5K_DCU_MISC_ARBLOCK_CTL_S) |
3364 AR5K_DCU_MISC_POST_FR_BKOFF_DIS |
3365 AR5K_DCU_MISC_BCN_ENABLE);
3366
3367 ath5k_hw_reg_write(ah, ((AR5K_TUNE_BEACON_INTERVAL -
3368 (AR5K_TUNE_SW_BEACON_RESP -
3369 AR5K_TUNE_DMA_BEACON_RESP) -
3370 AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF) * 1024) |
3371 AR5K_QCU_RDYTIMECFG_ENABLE,
3372 AR5K_QUEUE_RDYTIMECFG(queue));
3373 break;
3374
3375 case AR5K_TX_QUEUE_CAB:
3376 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3377 AR5K_QCU_MISC_FRSHED_DBA_GT |
3378 AR5K_QCU_MISC_CBREXP |
3379 AR5K_QCU_MISC_CBREXP_BCN);
3380
3381 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_DFS_MISC(queue),
3382 (AR5K_DCU_MISC_ARBLOCK_CTL_GLOBAL <<
3383 AR5K_DCU_MISC_ARBLOCK_CTL_S));
3384 break;
3385
3386 case AR5K_TX_QUEUE_UAPSD:
3387 AR5K_REG_ENABLE_BITS(ah, AR5K_QUEUE_MISC(queue),
3388 AR5K_QCU_MISC_CBREXP);
3389 break;
3390
3391 case AR5K_TX_QUEUE_DATA:
3392 default:
3393 break;
3394 }
3395
3396 /*
3397 * Enable interrupts for this tx queue
3398 * in the secondary interrupt mask registers
3399 */
3400 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXOKINT_ENABLE)
3401 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txok, queue);
3402
3403 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXERRINT_ENABLE)
3404 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txerr, queue);
3405
3406 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXURNINT_ENABLE)
3407 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txurn, queue);
3408
3409 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXDESCINT_ENABLE)
3410 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txdesc, queue);
3411
3412 if (tq->tqi_flags & AR5K_TXQ_FLAG_TXEOLINT_ENABLE)
3413 AR5K_Q_ENABLE_BITS(ah->ah_txq_imr_txeol, queue);
3414
3415
3416 /* Update secondary interrupt mask registers */
3417 ah->ah_txq_imr_txok &= ah->ah_txq_status;
3418 ah->ah_txq_imr_txerr &= ah->ah_txq_status;
3419 ah->ah_txq_imr_txurn &= ah->ah_txq_status;
3420 ah->ah_txq_imr_txdesc &= ah->ah_txq_status;
3421 ah->ah_txq_imr_txeol &= ah->ah_txq_status;
3422
3423 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txok,
3424 AR5K_SIMR0_QCU_TXOK) |
3425 AR5K_REG_SM(ah->ah_txq_imr_txdesc,
3426 AR5K_SIMR0_QCU_TXDESC), AR5K_SIMR0);
3427 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txerr,
3428 AR5K_SIMR1_QCU_TXERR) |
3429 AR5K_REG_SM(ah->ah_txq_imr_txeol,
3430 AR5K_SIMR1_QCU_TXEOL), AR5K_SIMR1);
3431 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txq_imr_txurn,
3432 AR5K_SIMR2_QCU_TXURN), AR5K_SIMR2);
3433 }
3434
3435 return 0;
3436 }
3437
3438 /*
3439 * Get number of pending frames
3440 * for a specific queue [5211+]
3441 */
3442 u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue) {
3443 ATH5K_TRACE(ah->ah_sc);
3444 AR5K_ASSERT_ENTRY(queue, ah->ah_capabilities.cap_queues.q_tx_num);
3445
3446 /* Return if queue is declared inactive */
3447 if (ah->ah_txq[queue].tqi_type == AR5K_TX_QUEUE_INACTIVE)
3448 return false;
3449
3450 /* XXX: How about AR5K_CFG_TXCNT ? */
3451 if (ah->ah_version == AR5K_AR5210)
3452 return false;
3453
3454 return AR5K_QUEUE_STATUS(queue) & AR5K_QCU_STS_FRMPENDCNT;
3455 }
3456
3457 /*
3458 * Set slot time
3459 */
3460 int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time)
3461 {
3462 ATH5K_TRACE(ah->ah_sc);
3463 if (slot_time < AR5K_SLOT_TIME_9 || slot_time > AR5K_SLOT_TIME_MAX)
3464 return -EINVAL;
3465
3466 if (ah->ah_version == AR5K_AR5210)
3467 ath5k_hw_reg_write(ah, ath5k_hw_htoclock(slot_time,
3468 ah->ah_turbo), AR5K_SLOT_TIME);
3469 else
3470 ath5k_hw_reg_write(ah, slot_time, AR5K_DCU_GBL_IFS_SLOT);
3471
3472 return 0;
3473 }
3474
3475 /*
3476 * Get slot time
3477 */
3478 unsigned int ath5k_hw_get_slot_time(struct ath5k_hw *ah)
3479 {
3480 ATH5K_TRACE(ah->ah_sc);
3481 if (ah->ah_version == AR5K_AR5210)
3482 return ath5k_hw_clocktoh(ath5k_hw_reg_read(ah,
3483 AR5K_SLOT_TIME) & 0xffff, ah->ah_turbo);
3484 else
3485 return ath5k_hw_reg_read(ah, AR5K_DCU_GBL_IFS_SLOT) & 0xffff;
3486 }
3487
3488
3489 /******************************\
3490 Hardware Descriptor Functions
3491 \******************************/
3492
3493 /*
3494 * TX Descriptor
3495 */
3496
3497 /*
3498 * Initialize the 2-word tx descriptor on 5210/5211
3499 */
3500 static int
3501 ath5k_hw_setup_2word_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3502 unsigned int pkt_len, unsigned int hdr_len, enum ath5k_pkt_type type,
3503 unsigned int tx_power, unsigned int tx_rate0, unsigned int tx_tries0,
3504 unsigned int key_index, unsigned int antenna_mode, unsigned int flags,
3505 unsigned int rtscts_rate, unsigned int rtscts_duration)
3506 {
3507 u32 frame_type;
3508 struct ath5k_hw_2w_tx_desc *tx_desc;
3509 unsigned int buff_len;
3510
3511 tx_desc = (struct ath5k_hw_2w_tx_desc *)&desc->ds_ctl0;
3512
3513 /*
3514 * Validate input
3515 * - Zero retries don't make sense.
3516 * - A zero rate will put the HW into a mode where it continously sends
3517 * noise on the channel, so it is important to avoid this.
3518 */
3519 if (unlikely(tx_tries0 == 0)) {
3520 ATH5K_ERR(ah->ah_sc, "zero retries\n");
3521 WARN_ON(1);
3522 return -EINVAL;
3523 }
3524 if (unlikely(tx_rate0 == 0)) {
3525 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3526 WARN_ON(1);
3527 return -EINVAL;
3528 }
3529
3530 /* Clear status descriptor */
3531 memset(desc->ds_hw, 0, sizeof(struct ath5k_hw_tx_status));
3532
3533 /* Initialize control descriptor */
3534 tx_desc->tx_control_0 = 0;
3535 tx_desc->tx_control_1 = 0;
3536
3537 /* Setup control descriptor */
3538
3539 /* Verify and set frame length */
3540 if (pkt_len & ~AR5K_2W_TX_DESC_CTL0_FRAME_LEN)
3541 return -EINVAL;
3542
3543 tx_desc->tx_control_0 = pkt_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN;
3544
3545 /* Verify and set buffer length */
3546 buff_len = pkt_len - FCS_LEN;
3547
3548 /* NB: beacon's BufLen must be a multiple of 4 bytes */
3549 if(type == AR5K_PKT_TYPE_BEACON)
3550 buff_len = roundup(buff_len, 4);
3551
3552 if (buff_len & ~AR5K_2W_TX_DESC_CTL1_BUF_LEN)
3553 return -EINVAL;
3554
3555 tx_desc->tx_control_1 = buff_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN;
3556
3557 /*
3558 * Verify and set header length
3559 * XXX: I only found that on 5210 code, does it work on 5211 ?
3560 */
3561 if (ah->ah_version == AR5K_AR5210) {
3562 if (hdr_len & ~AR5K_2W_TX_DESC_CTL0_HEADER_LEN)
3563 return -EINVAL;
3564 tx_desc->tx_control_0 |=
3565 AR5K_REG_SM(hdr_len, AR5K_2W_TX_DESC_CTL0_HEADER_LEN);
3566 }
3567
3568 /*Diferences between 5210-5211*/
3569 if (ah->ah_version == AR5K_AR5210) {
3570 switch (type) {
3571 case AR5K_PKT_TYPE_BEACON:
3572 case AR5K_PKT_TYPE_PROBE_RESP:
3573 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY;
3574 case AR5K_PKT_TYPE_PIFS:
3575 frame_type = AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS;
3576 default:
3577 frame_type = type /*<< 2 ?*/;
3578 }
3579
3580 tx_desc->tx_control_0 |=
3581 AR5K_REG_SM(frame_type, AR5K_2W_TX_DESC_CTL0_FRAME_TYPE) |
3582 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
3583 } else {
3584 tx_desc->tx_control_0 |=
3585 AR5K_REG_SM(tx_rate0, AR5K_2W_TX_DESC_CTL0_XMIT_RATE) |
3586 AR5K_REG_SM(antenna_mode, AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT);
3587 tx_desc->tx_control_1 |=
3588 AR5K_REG_SM(type, AR5K_2W_TX_DESC_CTL1_FRAME_TYPE);
3589 }
3590 #define _TX_FLAGS(_c, _flag) \
3591 if (flags & AR5K_TXDESC_##_flag) \
3592 tx_desc->tx_control_##_c |= \
3593 AR5K_2W_TX_DESC_CTL##_c##_##_flag
3594
3595 _TX_FLAGS(0, CLRDMASK);
3596 _TX_FLAGS(0, VEOL);
3597 _TX_FLAGS(0, INTREQ);
3598 _TX_FLAGS(0, RTSENA);
3599 _TX_FLAGS(1, NOACK);
3600
3601 #undef _TX_FLAGS
3602
3603 /*
3604 * WEP crap
3605 */
3606 if (key_index != AR5K_TXKEYIX_INVALID) {
3607 tx_desc->tx_control_0 |=
3608 AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
3609 tx_desc->tx_control_1 |=
3610 AR5K_REG_SM(key_index,
3611 AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
3612 }
3613
3614 /*
3615 * RTS/CTS Duration [5210 ?]
3616 */
3617 if ((ah->ah_version == AR5K_AR5210) &&
3618 (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)))
3619 tx_desc->tx_control_1 |= rtscts_duration &
3620 AR5K_2W_TX_DESC_CTL1_RTS_DURATION;
3621
3622 return 0;
3623 }
3624
3625 /*
3626 * Initialize the 4-word tx descriptor on 5212
3627 */
3628 static int ath5k_hw_setup_4word_tx_desc(struct ath5k_hw *ah,
3629 struct ath5k_desc *desc, unsigned int pkt_len, unsigned int hdr_len,
3630 enum ath5k_pkt_type type, unsigned int tx_power, unsigned int tx_rate0,
3631 unsigned int tx_tries0, unsigned int key_index,
3632 unsigned int antenna_mode, unsigned int flags, unsigned int rtscts_rate,
3633 unsigned int rtscts_duration)
3634 {
3635 struct ath5k_hw_4w_tx_desc *tx_desc;
3636 struct ath5k_hw_tx_status *tx_status;
3637 unsigned int buff_len;
3638
3639 ATH5K_TRACE(ah->ah_sc);
3640 tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0;
3641 tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[2];
3642
3643 /*
3644 * Validate input
3645 * - Zero retries don't make sense.
3646 * - A zero rate will put the HW into a mode where it continously sends
3647 * noise on the channel, so it is important to avoid this.
3648 */
3649 if (unlikely(tx_tries0 == 0)) {
3650 ATH5K_ERR(ah->ah_sc, "zero retries\n");
3651 WARN_ON(1);
3652 return -EINVAL;
3653 }
3654 if (unlikely(tx_rate0 == 0)) {
3655 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3656 WARN_ON(1);
3657 return -EINVAL;
3658 }
3659
3660 /* Clear status descriptor */
3661 memset(tx_status, 0, sizeof(struct ath5k_hw_tx_status));
3662
3663 /* Initialize control descriptor */
3664 tx_desc->tx_control_0 = 0;
3665 tx_desc->tx_control_1 = 0;
3666 tx_desc->tx_control_2 = 0;
3667 tx_desc->tx_control_3 = 0;
3668
3669 /* Setup control descriptor */
3670
3671 /* Verify and set frame length */
3672 if (pkt_len & ~AR5K_4W_TX_DESC_CTL0_FRAME_LEN)
3673 return -EINVAL;
3674
3675 tx_desc->tx_control_0 = pkt_len & AR5K_4W_TX_DESC_CTL0_FRAME_LEN;
3676
3677 /* Verify and set buffer length */
3678 buff_len = pkt_len - FCS_LEN;
3679
3680 /* NB: beacon's BufLen must be a multiple of 4 bytes */
3681 if(type == AR5K_PKT_TYPE_BEACON)
3682 buff_len = roundup(buff_len, 4);
3683
3684 if (buff_len & ~AR5K_4W_TX_DESC_CTL1_BUF_LEN)
3685 return -EINVAL;
3686
3687 tx_desc->tx_control_1 = buff_len & AR5K_4W_TX_DESC_CTL1_BUF_LEN;
3688
3689 tx_desc->tx_control_0 |=
3690 AR5K_REG_SM(tx_power, AR5K_4W_TX_DESC_CTL0_XMIT_POWER) |
3691 AR5K_REG_SM(antenna_mode, AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT);
3692 tx_desc->tx_control_1 |= AR5K_REG_SM(type,
3693 AR5K_4W_TX_DESC_CTL1_FRAME_TYPE);
3694 tx_desc->tx_control_2 = AR5K_REG_SM(tx_tries0 + AR5K_TUNE_HWTXTRIES,
3695 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0);
3696 tx_desc->tx_control_3 = tx_rate0 & AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
3697
3698 #define _TX_FLAGS(_c, _flag) \
3699 if (flags & AR5K_TXDESC_##_flag) \
3700 tx_desc->tx_control_##_c |= \
3701 AR5K_4W_TX_DESC_CTL##_c##_##_flag
3702
3703 _TX_FLAGS(0, CLRDMASK);
3704 _TX_FLAGS(0, VEOL);
3705 _TX_FLAGS(0, INTREQ);
3706 _TX_FLAGS(0, RTSENA);
3707 _TX_FLAGS(0, CTSENA);
3708 _TX_FLAGS(1, NOACK);
3709
3710 #undef _TX_FLAGS
3711
3712 /*
3713 * WEP crap
3714 */
3715 if (key_index != AR5K_TXKEYIX_INVALID) {
3716 tx_desc->tx_control_0 |= AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID;
3717 tx_desc->tx_control_1 |= AR5K_REG_SM(key_index,
3718 AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX);
3719 }
3720
3721 /*
3722 * RTS/CTS
3723 */
3724 if (flags & (AR5K_TXDESC_RTSENA | AR5K_TXDESC_CTSENA)) {
3725 if ((flags & AR5K_TXDESC_RTSENA) &&
3726 (flags & AR5K_TXDESC_CTSENA))
3727 return -EINVAL;
3728 tx_desc->tx_control_2 |= rtscts_duration &
3729 AR5K_4W_TX_DESC_CTL2_RTS_DURATION;
3730 tx_desc->tx_control_3 |= AR5K_REG_SM(rtscts_rate,
3731 AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE);
3732 }
3733
3734 return 0;
3735 }
3736
3737 /*
3738 * Initialize a 4-word multirate tx descriptor on 5212
3739 */
3740 static bool
3741 ath5k_hw_setup_xr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3742 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, u_int tx_tries2,
3743 unsigned int tx_rate3, u_int tx_tries3)
3744 {
3745 struct ath5k_hw_4w_tx_desc *tx_desc;
3746
3747 /*
3748 * Rates can be 0 as long as the retry count is 0 too.
3749 * A zero rate and nonzero retry count will put the HW into a mode where
3750 * it continously sends noise on the channel, so it is important to
3751 * avoid this.
3752 */
3753 if (unlikely((tx_rate1 == 0 && tx_tries1 != 0) ||
3754 (tx_rate2 == 0 && tx_tries2 != 0) ||
3755 (tx_rate3 == 0 && tx_tries3 != 0))) {
3756 ATH5K_ERR(ah->ah_sc, "zero rate\n");
3757 WARN_ON(1);
3758 return -EINVAL;
3759 }
3760
3761 if (ah->ah_version == AR5K_AR5212) {
3762 tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0;
3763
3764 #define _XTX_TRIES(_n) \
3765 if (tx_tries##_n) { \
3766 tx_desc->tx_control_2 |= \
3767 AR5K_REG_SM(tx_tries##_n, \
3768 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES##_n); \
3769 tx_desc->tx_control_3 |= \
3770 AR5K_REG_SM(tx_rate##_n, \
3771 AR5K_4W_TX_DESC_CTL3_XMIT_RATE##_n); \
3772 }
3773
3774 _XTX_TRIES(1);
3775 _XTX_TRIES(2);
3776 _XTX_TRIES(3);
3777
3778 #undef _XTX_TRIES
3779
3780 return true;
3781 }
3782
3783 return false;
3784 }
3785
3786 /*
3787 * Proccess the tx status descriptor on 5210/5211
3788 */
3789 static int ath5k_hw_proc_2word_tx_status(struct ath5k_hw *ah,
3790 struct ath5k_desc *desc)
3791 {
3792 struct ath5k_hw_tx_status *tx_status;
3793 struct ath5k_hw_2w_tx_desc *tx_desc;
3794
3795 tx_desc = (struct ath5k_hw_2w_tx_desc *)&desc->ds_ctl0;
3796 tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[0];
3797
3798 /* No frame has been send or error */
3799 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
3800 return -EINPROGRESS;
3801
3802 /*
3803 * Get descriptor status
3804 */
3805 desc->ds_us.tx.ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
3806 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
3807 desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
3808 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
3809 desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
3810 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
3811 /*TODO: desc->ds_us.tx.ts_virtcol + test*/
3812 desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
3813 AR5K_DESC_TX_STATUS1_SEQ_NUM);
3814 desc->ds_us.tx.ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
3815 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
3816 desc->ds_us.tx.ts_antenna = 1;
3817 desc->ds_us.tx.ts_status = 0;
3818 desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_0,
3819 AR5K_2W_TX_DESC_CTL0_XMIT_RATE);
3820
3821 if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){
3822 if (tx_status->tx_status_0 &
3823 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
3824 desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY;
3825
3826 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
3827 desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO;
3828
3829 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
3830 desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT;
3831 }
3832
3833 return 0;
3834 }
3835
3836 /*
3837 * Proccess a tx descriptor on 5212
3838 */
3839 static int ath5k_hw_proc_4word_tx_status(struct ath5k_hw *ah,
3840 struct ath5k_desc *desc)
3841 {
3842 struct ath5k_hw_tx_status *tx_status;
3843 struct ath5k_hw_4w_tx_desc *tx_desc;
3844
3845 ATH5K_TRACE(ah->ah_sc);
3846 tx_desc = (struct ath5k_hw_4w_tx_desc *)&desc->ds_ctl0;
3847 tx_status = (struct ath5k_hw_tx_status *)&desc->ds_hw[2];
3848
3849 /* No frame has been send or error */
3850 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0))
3851 return -EINPROGRESS;
3852
3853 /*
3854 * Get descriptor status
3855 */
3856 desc->ds_us.tx.ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0,
3857 AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP);
3858 desc->ds_us.tx.ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0,
3859 AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT);
3860 desc->ds_us.tx.ts_longretry = AR5K_REG_MS(tx_status->tx_status_0,
3861 AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT);
3862 desc->ds_us.tx.ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1,
3863 AR5K_DESC_TX_STATUS1_SEQ_NUM);
3864 desc->ds_us.tx.ts_rssi = AR5K_REG_MS(tx_status->tx_status_1,
3865 AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH);
3866 desc->ds_us.tx.ts_antenna = (tx_status->tx_status_1 &
3867 AR5K_DESC_TX_STATUS1_XMIT_ANTENNA) ? 2 : 1;
3868 desc->ds_us.tx.ts_status = 0;
3869
3870 switch (AR5K_REG_MS(tx_status->tx_status_1,
3871 AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX)) {
3872 case 0:
3873 desc->ds_us.tx.ts_rate = tx_desc->tx_control_3 &
3874 AR5K_4W_TX_DESC_CTL3_XMIT_RATE0;
3875 break;
3876 case 1:
3877 desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3,
3878 AR5K_4W_TX_DESC_CTL3_XMIT_RATE1);
3879 desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2,
3880 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1);
3881 break;
3882 case 2:
3883 desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3,
3884 AR5K_4W_TX_DESC_CTL3_XMIT_RATE2);
3885 desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2,
3886 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2);
3887 break;
3888 case 3:
3889 desc->ds_us.tx.ts_rate = AR5K_REG_MS(tx_desc->tx_control_3,
3890 AR5K_4W_TX_DESC_CTL3_XMIT_RATE3);
3891 desc->ds_us.tx.ts_longretry +=AR5K_REG_MS(tx_desc->tx_control_2,
3892 AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3);
3893 break;
3894 }
3895
3896 if ((tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK) == 0){
3897 if (tx_status->tx_status_0 &
3898 AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES)
3899 desc->ds_us.tx.ts_status |= AR5K_TXERR_XRETRY;
3900
3901 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN)
3902 desc->ds_us.tx.ts_status |= AR5K_TXERR_FIFO;
3903
3904 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED)
3905 desc->ds_us.tx.ts_status |= AR5K_TXERR_FILT;
3906 }
3907
3908 return 0;
3909 }
3910
3911 /*
3912 * RX Descriptor
3913 */
3914
3915 /*
3916 * Initialize an rx descriptor
3917 */
3918 int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc,
3919 u32 size, unsigned int flags)
3920 {
3921 struct ath5k_rx_desc *rx_desc;
3922
3923 ATH5K_TRACE(ah->ah_sc);
3924 rx_desc = (struct ath5k_rx_desc *)&desc->ds_ctl0;
3925
3926 /*
3927 *Clear ds_hw
3928 * If we don't clean the status descriptor,
3929 * while scanning we get too many results,
3930 * most of them virtual, after some secs
3931 * of scanning system hangs. M.F.
3932 */
3933 memset(desc->ds_hw, 0, sizeof(desc->ds_hw));
3934
3935 /*Initialize rx descriptor*/
3936 rx_desc->rx_control_0 = 0;
3937 rx_desc->rx_control_1 = 0;
3938
3939 /* Setup descriptor */
3940 rx_desc->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN;
3941 if (unlikely(rx_desc->rx_control_1 != size))
3942 return -EINVAL;
3943
3944 if (flags & AR5K_RXDESC_INTREQ)
3945 rx_desc->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ;
3946
3947 return 0;
3948 }
3949
3950 /*
3951 * Proccess the rx status descriptor on 5210/5211
3952 */
3953 static int ath5k_hw_proc_old_rx_status(struct ath5k_hw *ah,
3954 struct ath5k_desc *desc)
3955 {
3956 struct ath5k_hw_old_rx_status *rx_status;
3957
3958 rx_status = (struct ath5k_hw_old_rx_status *)&desc->ds_hw[0];
3959
3960 /* No frame received / not ready */
3961 if (unlikely((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_DONE)
3962 == 0))
3963 return -EINPROGRESS;
3964
3965 /*
3966 * Frame receive status
3967 */
3968 desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 &
3969 AR5K_OLD_RX_DESC_STATUS0_DATA_LEN;
3970 desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
3971 AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL);
3972 desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
3973 AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE);
3974 desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 &
3975 AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA;
3976 desc->ds_us.rx.rs_more = rx_status->rx_status_0 &
3977 AR5K_OLD_RX_DESC_STATUS0_MORE;
3978 desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
3979 AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
3980 desc->ds_us.rx.rs_status = 0;
3981
3982 /*
3983 * Key table status
3984 */
3985 if (rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID)
3986 desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
3987 AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX);
3988 else
3989 desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID;
3990
3991 /*
3992 * Receive/descriptor errors
3993 */
3994 if ((rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK)
3995 == 0) {
3996 if (rx_status->rx_status_1 & AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR)
3997 desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC;
3998
3999 if (rx_status->rx_status_1 &
4000 AR5K_OLD_RX_DESC_STATUS1_FIFO_OVERRUN)
4001 desc->ds_us.rx.rs_status |= AR5K_RXERR_FIFO;
4002
4003 if (rx_status->rx_status_1 &
4004 AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR) {
4005 desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY;
4006 desc->ds_us.rx.rs_phyerr =
4007 AR5K_REG_MS(rx_status->rx_status_1,
4008 AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR);
4009 }
4010
4011 if (rx_status->rx_status_1 &
4012 AR5K_OLD_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
4013 desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT;
4014 }
4015
4016 return 0;
4017 }
4018
4019 /*
4020 * Proccess the rx status descriptor on 5212
4021 */
4022 static int ath5k_hw_proc_new_rx_status(struct ath5k_hw *ah,
4023 struct ath5k_desc *desc)
4024 {
4025 struct ath5k_hw_new_rx_status *rx_status;
4026 struct ath5k_hw_rx_error *rx_err;
4027
4028 ATH5K_TRACE(ah->ah_sc);
4029 rx_status = (struct ath5k_hw_new_rx_status *)&desc->ds_hw[0];
4030
4031 /* Overlay on error */
4032 rx_err = (struct ath5k_hw_rx_error *)&desc->ds_hw[0];
4033
4034 /* No frame received / not ready */
4035 if (unlikely((rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_DONE)
4036 == 0))
4037 return -EINPROGRESS;
4038
4039 /*
4040 * Frame receive status
4041 */
4042 desc->ds_us.rx.rs_datalen = rx_status->rx_status_0 &
4043 AR5K_NEW_RX_DESC_STATUS0_DATA_LEN;
4044 desc->ds_us.rx.rs_rssi = AR5K_REG_MS(rx_status->rx_status_0,
4045 AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL);
4046 desc->ds_us.rx.rs_rate = AR5K_REG_MS(rx_status->rx_status_0,
4047 AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE);
4048 desc->ds_us.rx.rs_antenna = rx_status->rx_status_0 &
4049 AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA;
4050 desc->ds_us.rx.rs_more = rx_status->rx_status_0 &
4051 AR5K_NEW_RX_DESC_STATUS0_MORE;
4052 desc->ds_us.rx.rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1,
4053 AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP);
4054 desc->ds_us.rx.rs_status = 0;
4055
4056 /*
4057 * Key table status
4058 */
4059 if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_VALID)
4060 desc->ds_us.rx.rs_keyix = AR5K_REG_MS(rx_status->rx_status_1,
4061 AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX);
4062 else
4063 desc->ds_us.rx.rs_keyix = AR5K_RXKEYIX_INVALID;
4064
4065 /*
4066 * Receive/descriptor errors
4067 */
4068 if ((rx_status->rx_status_1 &
4069 AR5K_NEW_RX_DESC_STATUS1_FRAME_RECEIVE_OK) == 0) {
4070 if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR)
4071 desc->ds_us.rx.rs_status |= AR5K_RXERR_CRC;
4072
4073 if (rx_status->rx_status_1 &
4074 AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR) {
4075 desc->ds_us.rx.rs_status |= AR5K_RXERR_PHY;
4076 desc->ds_us.rx.rs_phyerr =
4077 AR5K_REG_MS(rx_err->rx_error_1,
4078 AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE);
4079 }
4080
4081 if (rx_status->rx_status_1 &
4082 AR5K_NEW_RX_DESC_STATUS1_DECRYPT_CRC_ERROR)
4083 desc->ds_us.rx.rs_status |= AR5K_RXERR_DECRYPT;
4084
4085 if (rx_status->rx_status_1 & AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR)
4086 desc->ds_us.rx.rs_status |= AR5K_RXERR_MIC;
4087 }
4088
4089 return 0;
4090 }
4091
4092
4093 /****************\
4094 GPIO Functions
4095 \****************/
4096
4097 /*
4098 * Set led state
4099 */
4100 void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state)
4101 {
4102 u32 led;
4103 /*5210 has different led mode handling*/
4104 u32 led_5210;
4105
4106 ATH5K_TRACE(ah->ah_sc);
4107
4108 /*Reset led status*/
4109 if (ah->ah_version != AR5K_AR5210)
4110 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG,
4111 AR5K_PCICFG_LEDMODE | AR5K_PCICFG_LED);
4112 else
4113 AR5K_REG_DISABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_LED);
4114
4115 /*
4116 * Some blinking values, define at your wish
4117 */
4118 switch (state) {
4119 case AR5K_LED_SCAN:
4120 case AR5K_LED_AUTH:
4121 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_PEND;
4122 led_5210 = AR5K_PCICFG_LED_PEND | AR5K_PCICFG_LED_BCTL;
4123 break;
4124
4125 case AR5K_LED_INIT:
4126 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_NONE;
4127 led_5210 = AR5K_PCICFG_LED_PEND;
4128 break;
4129
4130 case AR5K_LED_ASSOC:
4131 case AR5K_LED_RUN:
4132 led = AR5K_PCICFG_LEDMODE_PROP | AR5K_PCICFG_LED_ASSOC;
4133 led_5210 = AR5K_PCICFG_LED_ASSOC;
4134 break;
4135
4136 default:
4137 led = AR5K_PCICFG_LEDMODE_PROM | AR5K_PCICFG_LED_NONE;
4138 led_5210 = AR5K_PCICFG_LED_PEND;
4139 break;
4140 }
4141
4142 /*Write new status to the register*/
4143 if (ah->ah_version != AR5K_AR5210)
4144 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led);
4145 else
4146 AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, led_5210);
4147 }
4148
4149 /*
4150 * Set GPIO outputs
4151 */
4152 int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio)
4153 {
4154 ATH5K_TRACE(ah->ah_sc);
4155 if (gpio > AR5K_NUM_GPIO)
4156 return -EINVAL;
4157
4158 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &~
4159 AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_OUT(gpio), AR5K_GPIOCR);
4160
4161 return 0;
4162 }
4163
4164 /*
4165 * Set GPIO inputs
4166 */
4167 int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio)
4168 {
4169 ATH5K_TRACE(ah->ah_sc);
4170 if (gpio > AR5K_NUM_GPIO)
4171 return -EINVAL;
4172
4173 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &~
4174 AR5K_GPIOCR_OUT(gpio)) | AR5K_GPIOCR_IN(gpio), AR5K_GPIOCR);
4175
4176 return 0;
4177 }
4178
4179 /*
4180 * Get GPIO state
4181 */
4182 u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio)
4183 {
4184 ATH5K_TRACE(ah->ah_sc);
4185 if (gpio > AR5K_NUM_GPIO)
4186 return 0xffffffff;
4187
4188 /* GPIO input magic */
4189 return ((ath5k_hw_reg_read(ah, AR5K_GPIODI) & AR5K_GPIODI_M) >> gpio) &
4190 0x1;
4191 }
4192
4193 /*
4194 * Set GPIO state
4195 */
4196 int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val)
4197 {
4198 u32 data;
4199 ATH5K_TRACE(ah->ah_sc);
4200
4201 if (gpio > AR5K_NUM_GPIO)
4202 return -EINVAL;
4203
4204 /* GPIO output magic */
4205 data = ath5k_hw_reg_read(ah, AR5K_GPIODO);
4206
4207 data &= ~(1 << gpio);
4208 data |= (val & 1) << gpio;
4209
4210 ath5k_hw_reg_write(ah, data, AR5K_GPIODO);
4211
4212 return 0;
4213 }
4214
4215 /*
4216 * Initialize the GPIO interrupt (RFKill switch)
4217 */
4218 void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio,
4219 u32 interrupt_level)
4220 {
4221 u32 data;
4222
4223 ATH5K_TRACE(ah->ah_sc);
4224 if (gpio > AR5K_NUM_GPIO)
4225 return;
4226
4227 /*
4228 * Set the GPIO interrupt
4229 */
4230 data = (ath5k_hw_reg_read(ah, AR5K_GPIOCR) &
4231 ~(AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_SELH |
4232 AR5K_GPIOCR_INT_ENA | AR5K_GPIOCR_OUT(gpio))) |
4233 (AR5K_GPIOCR_INT_SEL(gpio) | AR5K_GPIOCR_INT_ENA);
4234
4235 ath5k_hw_reg_write(ah, interrupt_level ? data :
4236 (data | AR5K_GPIOCR_INT_SELH), AR5K_GPIOCR);
4237
4238 ah->ah_imr |= AR5K_IMR_GPIO;
4239
4240 /* Enable GPIO interrupts */
4241 AR5K_REG_ENABLE_BITS(ah, AR5K_PIMR, AR5K_IMR_GPIO);
4242 }
4243
4244
4245 /*********************************\
4246 Regulatory Domain/Channels Setup
4247 \*********************************/
4248
4249 u16 ath5k_get_regdomain(struct ath5k_hw *ah)
4250 {
4251 u16 regdomain;
4252 enum ath5k_regdom ieee_regdomain;
4253 #ifdef COUNTRYCODE
4254 u16 code;
4255 #endif
4256
4257 ath5k_eeprom_regulation_domain(ah, false, &ieee_regdomain);
4258 ah->ah_capabilities.cap_regdomain.reg_hw = ieee_regdomain;
4259
4260 #ifdef COUNTRYCODE
4261 /*
4262 * Get the regulation domain by country code. This will ignore
4263 * the settings found in the EEPROM.
4264 */
4265 code = ieee80211_name2countrycode(COUNTRYCODE);
4266 ieee_regdomain = ieee80211_countrycode2regdomain(code);
4267 #endif
4268
4269 regdomain = ath5k_regdom_from_ieee(ieee_regdomain);
4270 ah->ah_capabilities.cap_regdomain.reg_current = regdomain;
4271
4272 return regdomain;
4273 }
4274
4275
4276 /****************\
4277 Misc functions
4278 \****************/
4279
4280 int ath5k_hw_get_capability(struct ath5k_hw *ah,
4281 enum ath5k_capability_type cap_type,
4282 u32 capability, u32 *result)
4283 {
4284 ATH5K_TRACE(ah->ah_sc);
4285
4286 switch (cap_type) {
4287 case AR5K_CAP_NUM_TXQUEUES:
4288 if (result) {
4289 if (ah->ah_version == AR5K_AR5210)
4290 *result = AR5K_NUM_TX_QUEUES_NOQCU;
4291 else
4292 *result = AR5K_NUM_TX_QUEUES;
4293 goto yes;
4294 }
4295 case AR5K_CAP_VEOL:
4296 goto yes;
4297 case AR5K_CAP_COMPRESSION:
4298 if (ah->ah_version == AR5K_AR5212)
4299 goto yes;
4300 else
4301 goto no;
4302 case AR5K_CAP_BURST:
4303 goto yes;
4304 case AR5K_CAP_TPC:
4305 goto yes;
4306 case AR5K_CAP_BSSIDMASK:
4307 if (ah->ah_version == AR5K_AR5212)
4308 goto yes;
4309 else
4310 goto no;
4311 case AR5K_CAP_XR:
4312 if (ah->ah_version == AR5K_AR5212)
4313 goto yes;
4314 else
4315 goto no;
4316 default:
4317 goto no;
4318 }
4319
4320 no:
4321 return -EINVAL;
4322 yes:
4323 return 0;
4324 }
4325
4326 static int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid,
4327 u16 assoc_id)
4328 {
4329 ATH5K_TRACE(ah->ah_sc);
4330
4331 if (ah->ah_version == AR5K_AR5210) {
4332 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1,
4333 AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
4334 return 0;
4335 }
4336
4337 return -EIO;
4338 }
4339
4340 static int ath5k_hw_disable_pspoll(struct ath5k_hw *ah)
4341 {
4342 ATH5K_TRACE(ah->ah_sc);
4343
4344 if (ah->ah_version == AR5K_AR5210) {
4345 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1,
4346 AR5K_STA_ID1_NO_PSPOLL | AR5K_STA_ID1_DEFAULT_ANTENNA);
4347 return 0;
4348 }
4349
4350 return -EIO;
4351 }
WRT350N Kernel Patches