drivers/usb/host/ehci-pci.c

   1 /*
   2  * EHCI HCD (Host Controller Driver) PCI Bus Glue.
   3  *
   4  * Copyright (c) 2000-2004 by David Brownell
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2 of the License, or (at your
   9  * option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  14  * for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20
  21 #ifndef CONFIG_PCI
  22 #error "This file is PCI bus glue.  CONFIG_PCI must be defined."
  23 #endif
  24
  25 /*-------------------------------------------------------------------------*/
  26
  27 /* EHCI 0.96 (and later) section 5.1 says how to kick BIOS/SMM/...
  28  * off the controller (maybe it can boot from highspeed USB disks).
  29  */
  30 static int bios_handoff(struct ehci_hcd *ehci, int where, u32 cap)
  31 {
  32         struct pci_dev *pdev = to_pci_dev(ehci_to_hcd(ehci)->self.controller);
  33
  34         /* always say Linux will own the hardware */
  35         pci_write_config_byte(pdev, where + 3, 1);
  36
  37         /* maybe wait a while for BIOS to respond */
  38         if (cap & (1 << 16)) {
  39                 int msec = 5000;
  40
  41                 do {
  42                         msleep(10);
  43                         msec -= 10;
  44                         pci_read_config_dword(pdev, where, &cap);
  45                 } while ((cap & (1 << 16)) && msec);
  46                 if (cap & (1 << 16)) {
  47                         ehci_err(ehci, "BIOS handoff failed (%d, %08x)\n",
  48                                 where, cap);
  49                         // some BIOS versions seem buggy...
  50                         // return 1;
  51                         ehci_warn(ehci, "continuing after BIOS bug...\n");
  52                         /* disable all SMIs, and clear "BIOS owns" flag */
  53                         pci_write_config_dword(pdev, where + 4, 0);
  54                         pci_write_config_byte(pdev, where + 2, 0);
  55                 } else
  56                         ehci_dbg(ehci, "BIOS handoff succeeded\n");
  57         }
  58         return 0;
  59 }
  60
  61 /* called after powerup, by probe or system-pm "wakeup" */
  62 static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
  63 {
  64         u32                     temp;
  65         int                     retval;
  66         unsigned                count = 256/4;
  67
  68         /* optional debug port, normally in the first BAR */
  69         temp = pci_find_capability(pdev, 0x0a);
  70         if (temp) {
  71                 pci_read_config_dword(pdev, temp, &temp);
  72                 temp >>= 16;
  73                 if ((temp & (3 << 13)) == (1 << 13)) {
  74                         temp &= 0x1fff;
  75                         ehci->debug = ehci_to_hcd(ehci)->regs + temp;
  76                         temp = readl(&ehci->debug->control);
  77                         ehci_info(ehci, "debug port %d%s\n",
  78                                 HCS_DEBUG_PORT(ehci->hcs_params),
  79                                 (temp & DBGP_ENABLED)
  80                                         ? " IN USE"
  81                                         : "");
  82                         if (!(temp & DBGP_ENABLED))
  83                                 ehci->debug = NULL;
  84                 }
  85         }
  86
  87         temp = HCC_EXT_CAPS(readl(&ehci->caps->hcc_params));
  88
  89         /* EHCI 0.96 and later may have "extended capabilities" */
  90         while (temp && count--) {
  91                 u32             cap;
  92
  93                 pci_read_config_dword(pdev, temp, &cap);
  94                 ehci_dbg(ehci, "capability %04x at %02x\n", cap, temp);
  95                 switch (cap & 0xff) {
  96                 case 1:                 /* BIOS/SMM/... handoff */
  97                         if (bios_handoff(ehci, temp, cap) != 0)
  98                                 return -EOPNOTSUPP;
  99                         break;
 100                 case 0:                 /* illegal reserved capability */
 101                         ehci_dbg(ehci, "illegal capability!\n");
 102                         cap = 0;
 103                         /* FALLTHROUGH */
 104                 default:                /* unknown */
 105                         break;
 106                 }
 107                 temp = (cap >> 8) & 0xff;
 108         }
 109         if (!count) {
 110                 ehci_err(ehci, "bogus capabilities ... PCI problems!\n");
 111                 return -EIO;
 112         }
 113
 114         /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
 115         retval = pci_set_mwi(pdev);
 116         if (!retval)
 117                 ehci_dbg(ehci, "MWI active\n");
 118
 119         ehci_port_power(ehci, 0);
 120
 121         return 0;
 122 }
 123
 124 /* called during probe() after chip reset completes */
 125 static int ehci_pci_setup(struct usb_hcd *hcd)
 126 {
 127         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 128         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 129         u32                     temp;
 130         int                     retval;
 131
 132         ehci->caps = hcd->regs;
 133         ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase));
 134         dbg_hcs_params(ehci, "reset");
 135         dbg_hcc_params(ehci, "reset");
 136
 137         /* cache this readonly data; minimize chip reads */
 138         ehci->hcs_params = readl(&ehci->caps->hcs_params);
 139
 140         retval = ehci_halt(ehci);
 141         if (retval)
 142                 return retval;
 143
 144         /* data structure init */
 145         retval = ehci_init(hcd);
 146         if (retval)
 147                 return retval;
 148
 149         /* NOTE:  only the parts below this line are PCI-specific */
 150
 151         switch (pdev->vendor) {
 152         case PCI_VENDOR_ID_TDI:
 153                 if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
 154                         ehci->is_tdi_rh_tt = 1;
 155                         tdi_reset(ehci);
 156                 }
 157                 break;
 158         case PCI_VENDOR_ID_AMD:
 159                 /* AMD8111 EHCI doesn't work, according to AMD errata */
 160                 if (pdev->device == 0x7463) {
 161                         ehci_info(ehci, "ignoring AMD8111 (errata)\n");
 162                         retval = -EIO;
 163                         goto done;
 164                 }
 165                 break;
 166         case PCI_VENDOR_ID_NVIDIA:
 167                 /* NVidia reports that certain chips don't handle
 168                  * QH, ITD, or SITD addresses above 2GB.  (But TD,
 169                  * data buffer, and periodic schedule are normal.)
 170                  */
 171                 switch (pdev->device) {
 172                 case 0x003c:    /* MCP04 */
 173                 case 0x005b:    /* CK804 */
 174                 case 0x00d8:    /* CK8 */
 175                 case 0x00e8:    /* CK8S */
 176                         if (pci_set_consistent_dma_mask(pdev,
 177                                                 DMA_31BIT_MASK) < 0)
 178                                 ehci_warn(ehci, "can't enable NVidia "
 179                                         "workaround for >2GB RAM\n");
 180                         break;
 181                 }
 182                 break;
 183         }
 184
 185         if (ehci_is_TDI(ehci))
 186                 ehci_reset(ehci);
 187
 188         /* at least the Genesys GL880S needs fixup here */
 189         temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
 190         temp &= 0x0f;
 191         if (temp && HCS_N_PORTS(ehci->hcs_params) > temp) {
 192                 ehci_dbg(ehci, "bogus port configuration: "
 193                         "cc=%d x pcc=%d < ports=%d\n",
 194                         HCS_N_CC(ehci->hcs_params),
 195                         HCS_N_PCC(ehci->hcs_params),
 196                         HCS_N_PORTS(ehci->hcs_params));
 197
 198                 switch (pdev->vendor) {
 199                 case 0x17a0:            /* GENESYS */
 200                         /* GL880S: should be PORTS=2 */
 201                         temp |= (ehci->hcs_params & ~0xf);
 202                         ehci->hcs_params = temp;
 203                         break;
 204                 case PCI_VENDOR_ID_NVIDIA:
 205                         /* NF4: should be PCC=10 */
 206                         break;
 207                 }
 208         }
 209
 210         /* Serial Bus Release Number is at PCI 0x60 offset */
 211         pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
 212
 213         /* Workaround current PCI init glitch:  wakeup bits aren't
 214          * being set from PCI PM capability.
 215          */
 216         if (!device_can_wakeup(&pdev->dev)) {
 217                 u16     port_wake;
 218
 219                 pci_read_config_word(pdev, 0x62, &port_wake);
 220                 if (port_wake & 0x0001)
 221                         device_init_wakeup(&pdev->dev, 1);
 222         }
 223
 224         retval = ehci_pci_reinit(ehci, pdev);
 225 done:
 226         return retval;
 227 }
 228
 229 /*-------------------------------------------------------------------------*/
 230
 231 #ifdef  CONFIG_PM
 232
 233 /* suspend/resume, section 4.3 */
 234
 235 /* These routines rely on the PCI bus glue
 236  * to handle powerdown and wakeup, and currently also on
 237  * transceivers that don't need any software attention to set up
 238  * the right sort of wakeup.
 239  * Also they depend on separate root hub suspend/resume.
 240  */
 241
 242 static int ehci_pci_suspend(struct usb_hcd *hcd, pm_message_t message)
 243 {
 244         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 245         unsigned long           flags;
 246         int                     rc = 0;
 247
 248         if (time_before(jiffies, ehci->next_statechange))
 249                 msleep(10);
 250
 251         /* Root hub was already suspended. Disable irq emission and
 252          * mark HW unaccessible, bail out if RH has been resumed. Use
 253          * the spinlock to properly synchronize with possible pending
 254          * RH suspend or resume activity.
 255          *
 256          * This is still racy as hcd->state is manipulated outside of
 257          * any locks =P But that will be a different fix.
 258          */
 259         spin_lock_irqsave (&ehci->lock, flags);
 260         if (hcd->state != HC_STATE_SUSPENDED) {
 261                 rc = -EINVAL;
 262                 goto bail;
 263         }
 264         writel (0, &ehci->regs->intr_enable);
 265         (void)readl(&ehci->regs->intr_enable);
 266
 267         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 268  bail:
 269         spin_unlock_irqrestore (&ehci->lock, flags);
 270
 271         // could save FLADJ in case of Vaux power loss
 272         // ... we'd only use it to handle clock skew
 273
 274         return rc;
 275 }
 276
 277 static int ehci_pci_resume(struct usb_hcd *hcd)
 278 {
 279         struct ehci_hcd         *ehci = hcd_to_ehci(hcd);
 280         unsigned                port;
 281         struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
 282         int                     retval = -EINVAL;
 283
 284         // maybe restore FLADJ
 285
 286         if (time_before(jiffies, ehci->next_statechange))
 287                 msleep(100);
 288
 289         /* Mark hardware accessible again as we are out of D3 state by now */
 290         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 291
 292         /* If CF is clear, we lost PCI Vaux power and need to restart.  */
 293         if (readl(&ehci->regs->configured_flag) != FLAG_CF)
 294                 goto restart;
 295
 296         /* If any port is suspended (or owned by the companion),
 297          * we know we can/must resume the HC (and mustn't reset it).
 298          * We just defer that to the root hub code.
 299          */
 300         for (port = HCS_N_PORTS(ehci->hcs_params); port > 0; ) {
 301                 u32     status;
 302                 port--;
 303                 status = readl(&ehci->regs->port_status [port]);
 304                 if (!(status & PORT_POWER))
 305                         continue;
 306                 if (status & (PORT_SUSPEND | PORT_RESUME | PORT_OWNER)) {
 307                         usb_hcd_resume_root_hub(hcd);
 308                         return 0;
 309                 }
 310         }
 311
 312 restart:
 313         ehci_dbg(ehci, "lost power, restarting\n");
 314         usb_root_hub_lost_power(hcd->self.root_hub);
 315
 316         /* Else reset, to cope with power loss or flush-to-storage
 317          * style "resume" having let BIOS kick in during reboot.
 318          */
 319         (void) ehci_halt(ehci);
 320         (void) ehci_reset(ehci);
 321         (void) ehci_pci_reinit(ehci, pdev);
 322
 323         /* emptying the schedule aborts any urbs */
 324         spin_lock_irq(&ehci->lock);
 325         if (ehci->reclaim)
 326                 ehci->reclaim_ready = 1;
 327         ehci_work(ehci, NULL);
 328         spin_unlock_irq(&ehci->lock);
 329
 330         /* restart; khubd will disconnect devices */
 331         retval = ehci_run(hcd);
 332
 333         /* here we "know" root ports should always stay powered */
 334         ehci_port_power(ehci, 1);
 335
 336         return retval;
 337 }
 338 #endif
 339
 340 static const struct hc_driver ehci_pci_hc_driver = {
 341         .description =          hcd_name,
 342         .product_desc =         "EHCI Host Controller",
 343         .hcd_priv_size =        sizeof(struct ehci_hcd),
 344
 345         /*
 346          * generic hardware linkage
 347          */
 348         .irq =                  ehci_irq,
 349         .flags =                HCD_MEMORY | HCD_USB2,
 350
 351         /*
 352          * basic lifecycle operations
 353          */
 354         .reset =                ehci_pci_setup,
 355         .start =                ehci_run,
 356 #ifdef  CONFIG_PM
 357         .suspend =              ehci_pci_suspend,
 358         .resume =               ehci_pci_resume,
 359 #endif
 360         .stop =                 ehci_stop,
 361
 362         /*
 363          * managing i/o requests and associated device resources
 364          */
 365         .urb_enqueue =          ehci_urb_enqueue,
 366         .urb_dequeue =          ehci_urb_dequeue,
 367         .endpoint_disable =     ehci_endpoint_disable,
 368
 369         /*
 370          * scheduling support
 371          */
 372         .get_frame_number =     ehci_get_frame,
 373
 374         /*
 375          * root hub support
 376          */
 377         .hub_status_data =      ehci_hub_status_data,
 378         .hub_control =          ehci_hub_control,
 379         .bus_suspend =          ehci_bus_suspend,
 380         .bus_resume =           ehci_bus_resume,
 381 };
 382
 383 /*-------------------------------------------------------------------------*/
 384
 385 /* PCI driver selection metadata; PCI hotplugging uses this */
 386 static const struct pci_device_id pci_ids [] = { {
 387         /* handle any USB 2.0 EHCI controller */
 388         PCI_DEVICE_CLASS(((PCI_CLASS_SERIAL_USB << 8) | 0x20), ~0),
 389         .driver_data =  (unsigned long) &ehci_pci_hc_driver,
 390         },
 391         { /* end: all zeroes */ }
 392 };
 393 MODULE_DEVICE_TABLE(pci, pci_ids);
 394
 395 /* pci driver glue; this is a "new style" PCI driver module */
 396 static struct pci_driver ehci_pci_driver = {
 397         .name =         (char *) hcd_name,
 398         .id_table =     pci_ids,
 399
 400         .probe =        usb_hcd_pci_probe,
 401         .remove =       usb_hcd_pci_remove,
 402
 403 #ifdef  CONFIG_PM
 404         .suspend =      usb_hcd_pci_suspend,
 405         .resume =       usb_hcd_pci_resume,
 406 #endif
 407 };
 408
 409 static int __init ehci_hcd_pci_init(void)
 410 {
 411         if (usb_disabled())
 412                 return -ENODEV;
 413
 414         pr_debug("%s: block sizes: qh %Zd qtd %Zd itd %Zd sitd %Zd\n",
 415                 hcd_name,
 416                 sizeof(struct ehci_qh), sizeof(struct ehci_qtd),
 417                 sizeof(struct ehci_itd), sizeof(struct ehci_sitd));
 418
 419         return pci_register_driver(&ehci_pci_driver);
 420 }
 421 module_init(ehci_hcd_pci_init);
 422
 423 static void __exit ehci_hcd_pci_cleanup(void)
 424 {
 425         pci_unregister_driver(&ehci_pci_driver);
 426 }
 427 module_exit(ehci_hcd_pci_cleanup);