arch/powerpc/boot/dts/mpc8610_hpcd.dts

   1 /*
   2  * MPC8610 HPCD Device Tree Source
   3  *
   4  * Copyright 2007 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under the terms of the GNU General Public License Version 2 as published
   8  * by the Free Software Foundation.
   9  */
  10
  11
  12 / {
  13         model = "MPC8610HPCD";
  14         compatible = "fsl,MPC8610HPCD";
  15         #address-cells = <1>;
  16         #size-cells = <1>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 PowerPC,8610@0 {
  23                         device_type = "cpu";
  24                         reg = <0>;
  25                         d-cache-line-size = <d# 32>;    // bytes
  26                         i-cache-line-size = <d# 32>;    // bytes
  27                         d-cache-size = <8000>;          // L1, 32K
  28                         i-cache-size = <8000>;          // L1, 32K
  29                         timebase-frequency = <0>;       // 33 MHz, from uboot
  30                         bus-frequency = <0>;            // From uboot
  31                         clock-frequency = <0>;          // From uboot
  32                 };
  33         };
  34
  35         memory {
  36                 device_type = "memory";
  37                 reg = <00000000 20000000>;      // 512M at 0x0
  38         };
  39
  40         soc@e0000000 {
  41                 #address-cells = <1>;
  42                 #size-cells = <1>;
  43                 #interrupt-cells = <2>;
  44                 device_type = "soc";
  45                 ranges = <0 e0000000 00100000>;
  46                 reg = <e0000000 1000>;
  47                 bus-frequency = <0>;
  48
  49                 i2c@3000 {
  50                         device_type = "i2c";
  51                         compatible = "fsl-i2c";
  52                         #address-cells = <1>;
  53                         #size-cells = <0>;
  54                         reg = <3000 100>;
  55                         interrupts = <2b 2>;
  56                         interrupt-parent = <&mpic>;
  57                         dfsrr;
  58                 };
  59
  60                 i2c@3100 {
  61                         device_type = "i2c";
  62                         compatible = "fsl-i2c";
  63                         #address-cells = <1>;
  64                         #size-cells = <0>;
  65                         reg = <3100 100>;
  66                         interrupts = <2b 2>;
  67                         interrupt-parent = <&mpic>;
  68                         dfsrr;
  69                 };
  70
  71                 serial@4500 {
  72                         device_type = "serial";
  73                         compatible = "ns16550";
  74                         reg = <4500 100>;
  75                         clock-frequency = <0>;
  76                         interrupts = <2a 2>;
  77                         interrupt-parent = <&mpic>;
  78                 };
  79
  80                 serial@4600 {
  81                         device_type = "serial";
  82                         compatible = "ns16550";
  83                         reg = <4600 100>;
  84                         clock-frequency = <0>;
  85                         interrupts = <1c 2>;
  86                         interrupt-parent = <&mpic>;
  87                 };
  88
  89
  90                 mpic: interrupt-controller@40000 {
  91                         clock-frequency = <0>;
  92                         interrupt-controller;
  93                         #address-cells = <0>;
  94                         #interrupt-cells = <2>;
  95                         reg = <40000 40000>;
  96                         compatible = "chrp,open-pic";
  97                         device_type = "open-pic";
  98                         big-endian;
  99                 };
 100
 101                 global-utilities@e0000 {
 102                         compatible = "fsl,mpc8610-guts";
 103                         reg = <e0000 1000>;
 104                         fsl,has-rstcr;
 105                 };
 106         };
 107
 108         pci@e0008000 {
 109                 compatible = "fsl,mpc8610-pci";
 110                 device_type = "pci";
 111                 #interrupt-cells = <1>;
 112                 #size-cells = <2>;
 113                 #address-cells = <3>;
 114                 reg = <e0008000 1000>;
 115                 bus-range = <0 0>;
 116                 ranges = <02000000 0 80000000 80000000 0 10000000
 117                           01000000 0 00000000 e1000000 0 00100000>;
 118                 clock-frequency = <1fca055>;
 119                 interrupt-parent = <&mpic>;
 120                 interrupts = <18 2>;
 121                 interrupt-map-mask = <f800 0 0 7>;
 122                 interrupt-map = <
 123                         /* IDSEL 0x11 */
 124                         8800 0 0 1 &mpic 4 1
 125                         8800 0 0 2 &mpic 5 1
 126                         8800 0 0 3 &mpic 6 1
 127                         8800 0 0 4 &mpic 7 1
 128
 129                         /* IDSEL 0x12 */
 130                         9000 0 0 1 &mpic 5 1
 131                         9000 0 0 2 &mpic 6 1
 132                         9000 0 0 3 &mpic 7 1
 133                         9000 0 0 4 &mpic 4 1
 134                         >;
 135         };
 136
 137         pcie@e000a000 {
 138                 compatible = "fsl,mpc8641-pcie";
 139                 device_type = "pci";
 140                 #interrupt-cells = <1>;
 141                 #size-cells = <2>;
 142                 #address-cells = <3>;
 143                 reg = <e000a000 1000>;
 144                 bus-range = <1 3>;
 145                 ranges = <02000000 0 a0000000 a0000000 0 10000000
 146                           01000000 0 00000000 e3000000 0 00100000>;
 147                 clock-frequency = <1fca055>;
 148                 interrupt-parent = <&mpic>;
 149                 interrupts = <1a 2>;
 150                 interrupt-map-mask = <f800 0 0 7>;
 151
 152                 interrupt-map = <
 153                         /* IDSEL 0x1b */
 154                         d800 0 0 1 &mpic 2 1
 155
 156                         /* IDSEL 0x1c*/
 157                         e000 0 0 1 &mpic 1 1
 158                         e000 0 0 2 &mpic 1 1
 159                         e000 0 0 3 &mpic 1 1
 160                         e000 0 0 4 &mpic 1 1
 161
 162                         /* IDSEL 0x1f */
 163                         f800 0 0 1 &mpic 3 0
 164                         f800 0 0 2 &mpic 0 1
 165                 >;
 166
 167                 pcie@0 {
 168                         reg = <0 0 0 0 0>;
 169                         #size-cells = <2>;
 170                         #address-cells = <3>;
 171                         device_type = "pci";
 172                         ranges = <02000000 0 a0000000
 173                                   02000000 0 a0000000
 174                                   0 10000000
 175                                   01000000 0 00000000
 176                                   01000000 0 00000000
 177                                   0 00100000>;
 178                         uli1575@0 {
 179                                 reg = <0 0 0 0 0>;
 180                                 #size-cells = <2>;
 181                                 #address-cells = <3>;
 182                                 ranges = <02000000 0 a0000000
 183                                           02000000 0 a0000000
 184                                           0 10000000
 185                                           01000000 0 00000000
 186                                           01000000 0 00000000
 187                                           0 00100000>;
 188                         };
 189                 };
 190         };
 191 };