drivers/char/agp/sworks-agp.c

   1 /*
   2  * Serverworks AGPGART routines.
   3  */
   4
   5 #include <linux/module.h>
   6 #include <linux/pci.h>
   7 #include <linux/init.h>
   8 #include <linux/string.h>
   9 #include <linux/slab.h>
  10 #include <linux/jiffies.h>
  11 #include <linux/agp_backend.h>
  12 #include "agp.h"
  13
  14 #define SVWRKS_COMMAND          0x04
  15 #define SVWRKS_APSIZE           0x10
  16 #define SVWRKS_MMBASE           0x14
  17 #define SVWRKS_CACHING          0x4b
  18 #define SVWRKS_AGP_ENABLE       0x60
  19 #define SVWRKS_FEATURE          0x68
  20
  21 #define SVWRKS_SIZE_MASK        0xfe000000
  22
  23 /* Memory mapped registers */
  24 #define SVWRKS_GART_CACHE       0x02
  25 #define SVWRKS_GATTBASE         0x04
  26 #define SVWRKS_TLBFLUSH         0x10
  27 #define SVWRKS_POSTFLUSH        0x14
  28 #define SVWRKS_DIRFLUSH         0x0c
  29
  30
  31 struct serverworks_page_map {
  32         unsigned long *real;
  33         unsigned long __iomem *remapped;
  34 };
  35
  36 static struct _serverworks_private {
  37         struct pci_dev *svrwrks_dev;    /* device one */
  38         volatile u8 __iomem *registers;
  39         struct serverworks_page_map **gatt_pages;
  40         int num_tables;
  41         struct serverworks_page_map scratch_dir;
  42
  43         int gart_addr_ofs;
  44         int mm_addr_ofs;
  45 } serverworks_private;
  46
  47 static int serverworks_create_page_map(struct serverworks_page_map *page_map)
  48 {
  49         int i;
  50
  51         page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
  52         if (page_map->real == NULL) {
  53                 return -ENOMEM;
  54         }
  55         SetPageReserved(virt_to_page(page_map->real));
  56         global_cache_flush();
  57         page_map->remapped = ioremap_nocache(virt_to_gart(page_map->real),
  58                                             PAGE_SIZE);
  59         if (page_map->remapped == NULL) {
  60                 ClearPageReserved(virt_to_page(page_map->real));
  61                 free_page((unsigned long) page_map->real);
  62                 page_map->real = NULL;
  63                 return -ENOMEM;
  64         }
  65         global_cache_flush();
  66
  67         for (i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++)
  68                 writel(agp_bridge->scratch_page, page_map->remapped+i);
  69
  70         return 0;
  71 }
  72
  73 static void serverworks_free_page_map(struct serverworks_page_map *page_map)
  74 {
  75         iounmap(page_map->remapped);
  76         ClearPageReserved(virt_to_page(page_map->real));
  77         free_page((unsigned long) page_map->real);
  78 }
  79
  80 static void serverworks_free_gatt_pages(void)
  81 {
  82         int i;
  83         struct serverworks_page_map **tables;
  84         struct serverworks_page_map *entry;
  85
  86         tables = serverworks_private.gatt_pages;
  87         for (i = 0; i < serverworks_private.num_tables; i++) {
  88                 entry = tables[i];
  89                 if (entry != NULL) {
  90                         if (entry->real != NULL) {
  91                                 serverworks_free_page_map(entry);
  92                         }
  93                         kfree(entry);
  94                 }
  95         }
  96         kfree(tables);
  97 }
  98
  99 static int serverworks_create_gatt_pages(int nr_tables)
 100 {
 101         struct serverworks_page_map **tables;
 102         struct serverworks_page_map *entry;
 103         int retval = 0;
 104         int i;
 105
 106         tables = kzalloc((nr_tables + 1) * sizeof(struct serverworks_page_map *),
 107                          GFP_KERNEL);
 108         if (tables == NULL)
 109                 return -ENOMEM;
 110
 111         for (i = 0; i < nr_tables; i++) {
 112                 entry = kzalloc(sizeof(struct serverworks_page_map), GFP_KERNEL);
 113                 if (entry == NULL) {
 114                         retval = -ENOMEM;
 115                         break;
 116                 }
 117                 tables[i] = entry;
 118                 retval = serverworks_create_page_map(entry);
 119                 if (retval != 0) break;
 120         }
 121         serverworks_private.num_tables = nr_tables;
 122         serverworks_private.gatt_pages = tables;
 123
 124         if (retval != 0) serverworks_free_gatt_pages();
 125
 126         return retval;
 127 }
 128
 129 #define SVRWRKS_GET_GATT(addr) (serverworks_private.gatt_pages[\
 130         GET_PAGE_DIR_IDX(addr)]->remapped)
 131
 132 #ifndef GET_PAGE_DIR_OFF
 133 #define GET_PAGE_DIR_OFF(addr) (addr >> 22)
 134 #endif
 135
 136 #ifndef GET_PAGE_DIR_IDX
 137 #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
 138         GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
 139 #endif
 140
 141 #ifndef GET_GATT_OFF
 142 #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
 143 #endif
 144
 145 static int serverworks_create_gatt_table(struct agp_bridge_data *bridge)
 146 {
 147         struct aper_size_info_lvl2 *value;
 148         struct serverworks_page_map page_dir;
 149         int retval;
 150         u32 temp;
 151         int i;
 152
 153         value = A_SIZE_LVL2(agp_bridge->current_size);
 154         retval = serverworks_create_page_map(&page_dir);
 155         if (retval != 0) {
 156                 return retval;
 157         }
 158         retval = serverworks_create_page_map(&serverworks_private.scratch_dir);
 159         if (retval != 0) {
 160                 serverworks_free_page_map(&page_dir);
 161                 return retval;
 162         }
 163         /* Create a fake scratch directory */
 164         for (i = 0; i < 1024; i++) {
 165                 writel(agp_bridge->scratch_page, serverworks_private.scratch_dir.remapped+i);
 166                 writel(virt_to_gart(serverworks_private.scratch_dir.real) | 1, page_dir.remapped+i);
 167         }
 168
 169         retval = serverworks_create_gatt_pages(value->num_entries / 1024);
 170         if (retval != 0) {
 171                 serverworks_free_page_map(&page_dir);
 172                 serverworks_free_page_map(&serverworks_private.scratch_dir);
 173                 return retval;
 174         }
 175
 176         agp_bridge->gatt_table_real = (u32 *)page_dir.real;
 177         agp_bridge->gatt_table = (u32 __iomem *)page_dir.remapped;
 178         agp_bridge->gatt_bus_addr = virt_to_gart(page_dir.real);
 179
 180         /* Get the address for the gart region.
 181          * This is a bus address even on the alpha, b/c its
 182          * used to program the agp master not the cpu
 183          */
 184
 185         pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
 186         agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 187
 188         /* Calculate the agp offset */
 189         for (i = 0; i < value->num_entries / 1024; i++)
 190                 writel(virt_to_gart(serverworks_private.gatt_pages[i]->real)|1, page_dir.remapped+i);
 191
 192         return 0;
 193 }
 194
 195 static int serverworks_free_gatt_table(struct agp_bridge_data *bridge)
 196 {
 197         struct serverworks_page_map page_dir;
 198
 199         page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
 200         page_dir.remapped = (unsigned long __iomem *)agp_bridge->gatt_table;
 201
 202         serverworks_free_gatt_pages();
 203         serverworks_free_page_map(&page_dir);
 204         serverworks_free_page_map(&serverworks_private.scratch_dir);
 205         return 0;
 206 }
 207
 208 static int serverworks_fetch_size(void)
 209 {
 210         int i;
 211         u32 temp;
 212         u32 temp2;
 213         struct aper_size_info_lvl2 *values;
 214
 215         values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
 216         pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
 217         pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,
 218                                         SVWRKS_SIZE_MASK);
 219         pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp2);
 220         pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,temp);
 221         temp2 &= SVWRKS_SIZE_MASK;
 222
 223         for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
 224                 if (temp2 == values[i].size_value) {
 225                         agp_bridge->previous_size =
 226                             agp_bridge->current_size = (void *) (values + i);
 227
 228                         agp_bridge->aperture_size_idx = i;
 229                         return values[i].size;
 230                 }
 231         }
 232
 233         return 0;
 234 }
 235
 236 /*
 237  * This routine could be implemented by taking the addresses
 238  * written to the GATT, and flushing them individually.  However
 239  * currently it just flushes the whole table.  Which is probably
 240  * more efficent, since agp_memory blocks can be a large number of
 241  * entries.
 242  */
 243 static void serverworks_tlbflush(struct agp_memory *temp)
 244 {
 245         unsigned long timeout;
 246
 247         writeb(1, serverworks_private.registers+SVWRKS_POSTFLUSH);
 248         timeout = jiffies + 3*HZ;
 249         while (readb(serverworks_private.registers+SVWRKS_POSTFLUSH) == 1) {
 250                 cpu_relax();
 251                 if (time_after(jiffies, timeout)) {
 252                         printk(KERN_ERR PFX "TLB post flush took more than 3 seconds\n");
 253                         break;
 254                 }
 255         }
 256
 257         writel(1, serverworks_private.registers+SVWRKS_DIRFLUSH);
 258         timeout = jiffies + 3*HZ;
 259         while (readl(serverworks_private.registers+SVWRKS_DIRFLUSH) == 1) {
 260                 cpu_relax();
 261                 if (time_after(jiffies, timeout)) {
 262                         printk(KERN_ERR PFX "TLB Dir flush took more than 3 seconds\n");
 263                         break;
 264                 }
 265         }
 266 }
 267
 268 static int serverworks_configure(void)
 269 {
 270         struct aper_size_info_lvl2 *current_size;
 271         u32 temp;
 272         u8 enable_reg;
 273         u16 cap_reg;
 274
 275         current_size = A_SIZE_LVL2(agp_bridge->current_size);
 276
 277         /* Get the memory mapped registers */
 278         pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp);
 279         temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
 280         serverworks_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096);
 281         if (!serverworks_private.registers) {
 282                 printk (KERN_ERR PFX "Unable to ioremap() memory.\n");
 283                 return -ENOMEM;
 284         }
 285
 286         writeb(0xA, serverworks_private.registers+SVWRKS_GART_CACHE);
 287         readb(serverworks_private.registers+SVWRKS_GART_CACHE); /* PCI Posting. */
 288
 289         writel(agp_bridge->gatt_bus_addr, serverworks_private.registers+SVWRKS_GATTBASE);
 290         readl(serverworks_private.registers+SVWRKS_GATTBASE);   /* PCI Posting. */
 291
 292         cap_reg = readw(serverworks_private.registers+SVWRKS_COMMAND);
 293         cap_reg &= ~0x0007;
 294         cap_reg |= 0x4;
 295         writew(cap_reg, serverworks_private.registers+SVWRKS_COMMAND);
 296         readw(serverworks_private.registers+SVWRKS_COMMAND);
 297
 298         pci_read_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, &enable_reg);
 299         enable_reg |= 0x1; /* Agp Enable bit */
 300         pci_write_config_byte(serverworks_private.svrwrks_dev,SVWRKS_AGP_ENABLE, enable_reg);
 301         serverworks_tlbflush(NULL);
 302
 303         agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);
 304
 305         /* Fill in the mode register */
 306         pci_read_config_dword(serverworks_private.svrwrks_dev,
 307                               agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
 308
 309         pci_read_config_byte(agp_bridge->dev, SVWRKS_CACHING, &enable_reg);
 310         enable_reg &= ~0x3;
 311         pci_write_config_byte(agp_bridge->dev, SVWRKS_CACHING, enable_reg);
 312
 313         pci_read_config_byte(agp_bridge->dev, SVWRKS_FEATURE, &enable_reg);
 314         enable_reg |= (1<<6);
 315         pci_write_config_byte(agp_bridge->dev,SVWRKS_FEATURE, enable_reg);
 316
 317         return 0;
 318 }
 319
 320 static void serverworks_cleanup(void)
 321 {
 322         iounmap((void __iomem *) serverworks_private.registers);
 323 }
 324
 325 static int serverworks_insert_memory(struct agp_memory *mem,
 326                              off_t pg_start, int type)
 327 {
 328         int i, j, num_entries;
 329         unsigned long __iomem *cur_gatt;
 330         unsigned long addr;
 331
 332         num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
 333
 334         if (type != 0 || mem->type != 0) {
 335                 return -EINVAL;
 336         }
 337         if ((pg_start + mem->page_count) > num_entries) {
 338                 return -EINVAL;
 339         }
 340
 341         j = pg_start;
 342         while (j < (pg_start + mem->page_count)) {
 343                 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 344                 cur_gatt = SVRWRKS_GET_GATT(addr);
 345                 if (!PGE_EMPTY(agp_bridge, readl(cur_gatt+GET_GATT_OFF(addr))))
 346                         return -EBUSY;
 347                 j++;
 348         }
 349
 350         if (mem->is_flushed == FALSE) {
 351                 global_cache_flush();
 352                 mem->is_flushed = TRUE;
 353         }
 354
 355         for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
 356                 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 357                 cur_gatt = SVRWRKS_GET_GATT(addr);
 358                 writel(agp_bridge->driver->mask_memory(agp_bridge, mem->memory[i], mem->type), cur_gatt+GET_GATT_OFF(addr));
 359         }
 360         serverworks_tlbflush(mem);
 361         return 0;
 362 }
 363
 364 static int serverworks_remove_memory(struct agp_memory *mem, off_t pg_start,
 365                              int type)
 366 {
 367         int i;
 368         unsigned long __iomem *cur_gatt;
 369         unsigned long addr;
 370
 371         if (type != 0 || mem->type != 0) {
 372                 return -EINVAL;
 373         }
 374
 375         global_cache_flush();
 376         serverworks_tlbflush(mem);
 377
 378         for (i = pg_start; i < (mem->page_count + pg_start); i++) {
 379                 addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
 380                 cur_gatt = SVRWRKS_GET_GATT(addr);
 381                 writel(agp_bridge->scratch_page, cur_gatt+GET_GATT_OFF(addr));
 382         }
 383
 384         serverworks_tlbflush(mem);
 385         return 0;
 386 }
 387
 388 static const struct gatt_mask serverworks_masks[] =
 389 {
 390         {.mask = 1, .type = 0}
 391 };
 392
 393 static const struct aper_size_info_lvl2 serverworks_sizes[7] =
 394 {
 395         {2048, 524288, 0x80000000},
 396         {1024, 262144, 0xc0000000},
 397         {512, 131072, 0xe0000000},
 398         {256, 65536, 0xf0000000},
 399         {128, 32768, 0xf8000000},
 400         {64, 16384, 0xfc000000},
 401         {32, 8192, 0xfe000000}
 402 };
 403
 404 static void serverworks_agp_enable(struct agp_bridge_data *bridge, u32 mode)
 405 {
 406         u32 command;
 407
 408         pci_read_config_dword(serverworks_private.svrwrks_dev,
 409                               bridge->capndx + PCI_AGP_STATUS,
 410                               &command);
 411
 412         command = agp_collect_device_status(bridge, mode, command);
 413
 414         command &= ~0x10;       /* disable FW */
 415         command &= ~0x08;
 416
 417         command |= 0x100;
 418
 419         pci_write_config_dword(serverworks_private.svrwrks_dev,
 420                                bridge->capndx + PCI_AGP_COMMAND,
 421                                command);
 422
 423         agp_device_command(command, 0);
 424 }
 425
 426 static const struct agp_bridge_driver sworks_driver = {
 427         .owner                  = THIS_MODULE,
 428         .aperture_sizes         = serverworks_sizes,
 429         .size_type              = LVL2_APER_SIZE,
 430         .num_aperture_sizes     = 7,
 431         .configure              = serverworks_configure,
 432         .fetch_size             = serverworks_fetch_size,
 433         .cleanup                = serverworks_cleanup,
 434         .tlb_flush              = serverworks_tlbflush,
 435         .mask_memory            = agp_generic_mask_memory,
 436         .masks                  = serverworks_masks,
 437         .agp_enable             = serverworks_agp_enable,
 438         .cache_flush            = global_cache_flush,
 439         .create_gatt_table      = serverworks_create_gatt_table,
 440         .free_gatt_table        = serverworks_free_gatt_table,
 441         .insert_memory          = serverworks_insert_memory,
 442         .remove_memory          = serverworks_remove_memory,
 443         .alloc_by_type          = agp_generic_alloc_by_type,
 444         .free_by_type           = agp_generic_free_by_type,
 445         .agp_alloc_page         = agp_generic_alloc_page,
 446         .agp_destroy_page       = agp_generic_destroy_page,
 447         .agp_type_to_mask_type  = agp_generic_type_to_mask_type,
 448 };
 449
 450 static int __devinit agp_serverworks_probe(struct pci_dev *pdev,
 451                                            const struct pci_device_id *ent)
 452 {
 453         struct agp_bridge_data *bridge;
 454         struct pci_dev *bridge_dev;
 455         u32 temp, temp2;
 456         u8 cap_ptr = 0;
 457
 458         cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
 459
 460         switch (pdev->device) {
 461         case 0x0006:
 462                 printk (KERN_ERR PFX "ServerWorks CNB20HE is unsupported due to lack of documentation.\n");
 463                 return -ENODEV;
 464
 465         case PCI_DEVICE_ID_SERVERWORKS_HE:
 466         case PCI_DEVICE_ID_SERVERWORKS_LE:
 467         case 0x0007:
 468                 break;
 469
 470         default:
 471                 if (cap_ptr)
 472                         printk(KERN_ERR PFX "Unsupported Serverworks chipset "
 473                                         "(device id: %04x)\n", pdev->device);
 474                 return -ENODEV;
 475         }
 476
 477         /* Everything is on func 1 here so we are hardcoding function one */
 478         bridge_dev = pci_get_bus_and_slot((unsigned int)pdev->bus->number,
 479                         PCI_DEVFN(0, 1));
 480         if (!bridge_dev) {
 481                 printk(KERN_INFO PFX "Detected a Serverworks chipset "
 482                        "but could not find the secondary device.\n");
 483                 return -ENODEV;
 484         }
 485
 486         serverworks_private.svrwrks_dev = bridge_dev;
 487         serverworks_private.gart_addr_ofs = 0x10;
 488
 489         pci_read_config_dword(pdev, SVWRKS_APSIZE, &temp);
 490         if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 491                 pci_read_config_dword(pdev, SVWRKS_APSIZE + 4, &temp2);
 492                 if (temp2 != 0) {
 493                         printk(KERN_INFO PFX "Detected 64 bit aperture address, "
 494                                "but top bits are not zero.  Disabling agp\n");
 495                         return -ENODEV;
 496                 }
 497                 serverworks_private.mm_addr_ofs = 0x18;
 498         } else
 499                 serverworks_private.mm_addr_ofs = 0x14;
 500
 501         pci_read_config_dword(pdev, serverworks_private.mm_addr_ofs, &temp);
 502         if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
 503                 pci_read_config_dword(pdev,
 504                                 serverworks_private.mm_addr_ofs + 4, &temp2);
 505                 if (temp2 != 0) {
 506                         printk(KERN_INFO PFX "Detected 64 bit MMIO address, "
 507                                "but top bits are not zero.  Disabling agp\n");
 508                         return -ENODEV;
 509                 }
 510         }
 511
 512         bridge = agp_alloc_bridge();
 513         if (!bridge)
 514                 return -ENOMEM;
 515
 516         bridge->driver = &sworks_driver;
 517         bridge->dev_private_data = &serverworks_private,
 518         bridge->dev = pci_dev_get(pdev);
 519
 520         pci_set_drvdata(pdev, bridge);
 521         return agp_add_bridge(bridge);
 522 }
 523
 524 static void __devexit agp_serverworks_remove(struct pci_dev *pdev)
 525 {
 526         struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
 527
 528         pci_dev_put(bridge->dev);
 529         agp_remove_bridge(bridge);
 530         agp_put_bridge(bridge);
 531         pci_dev_put(serverworks_private.svrwrks_dev);
 532         serverworks_private.svrwrks_dev = NULL;
 533 }
 534
 535 static struct pci_device_id agp_serverworks_pci_table[] = {
 536         {
 537         .class          = (PCI_CLASS_BRIDGE_HOST << 8),
 538         .class_mask     = ~0,
 539         .vendor         = PCI_VENDOR_ID_SERVERWORKS,
 540         .device         = PCI_ANY_ID,
 541         .subvendor      = PCI_ANY_ID,
 542         .subdevice      = PCI_ANY_ID,
 543         },
 544         { }
 545 };
 546
 547 MODULE_DEVICE_TABLE(pci, agp_serverworks_pci_table);
 548
 549 static struct pci_driver agp_serverworks_pci_driver = {
 550         .name           = "agpgart-serverworks",
 551         .id_table       = agp_serverworks_pci_table,
 552         .probe          = agp_serverworks_probe,
 553         .remove         = agp_serverworks_remove,
 554 };
 555
 556 static int __init agp_serverworks_init(void)
 557 {
 558         if (agp_off)
 559                 return -EINVAL;
 560         return pci_register_driver(&agp_serverworks_pci_driver);
 561 }
 562
 563 static void __exit agp_serverworks_cleanup(void)
 564 {
 565         pci_unregister_driver(&agp_serverworks_pci_driver);
 566 }
 567
 568 module_init(agp_serverworks_init);
 569 module_exit(agp_serverworks_cleanup);
 570
 571 MODULE_LICENSE("GPL and additional rights");
 572