?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
x86: cpa: move clflush_cache_range()
[wrt350n-kernel.git] / drivers / net / e1000e / phy.c
blobfc6fee112f1c191231f64e23a98dd9ce19d7f574
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2007 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 #include <linux/delay.h>
30
31 #include "e1000.h"
32
33 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw);
34 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw);
35 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active);
36 static s32 e1000_wait_autoneg(struct e1000_hw *hw);
37
38 /* Cable length tables */
39 static const u16 e1000_m88_cable_length_table[] =
40 { 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
41
42 static const u16 e1000_igp_2_cable_length_table[] =
43 { 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
44 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
45 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
46 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
47 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
48 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
49 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
50 124};
51 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
52 ARRAY_SIZE(e1000_igp_2_cable_length_table)
53
54 /**
55 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
56 * @hw: pointer to the HW structure
57 *
58 * Read the PHY management control register and check whether a PHY reset
59 * is blocked. If a reset is not blocked return 0, otherwise
60 * return E1000_BLK_PHY_RESET (12).
61 **/
62 s32 e1000e_check_reset_block_generic(struct e1000_hw *hw)
63 {
64 u32 manc;
65
66 manc = er32(MANC);
67
68 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
69 E1000_BLK_PHY_RESET : 0;
70 }
71
72 /**
73 * e1000e_get_phy_id - Retrieve the PHY ID and revision
74 * @hw: pointer to the HW structure
75 *
76 * Reads the PHY registers and stores the PHY ID and possibly the PHY
77 * revision in the hardware structure.
78 **/
79 s32 e1000e_get_phy_id(struct e1000_hw *hw)
80 {
81 struct e1000_phy_info *phy = &hw->phy;
82 s32 ret_val;
83 u16 phy_id;
84
85 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
86 if (ret_val)
87 return ret_val;
88
89 phy->id = (u32)(phy_id << 16);
90 udelay(20);
91 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
92 if (ret_val)
93 return ret_val;
94
95 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
96 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
97
98 return 0;
99 }
100
101 /**
102 * e1000e_phy_reset_dsp - Reset PHY DSP
103 * @hw: pointer to the HW structure
104 *
105 * Reset the digital signal processor.
106 **/
107 s32 e1000e_phy_reset_dsp(struct e1000_hw *hw)
108 {
109 s32 ret_val;
110
111 ret_val = e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
112 if (ret_val)
113 return ret_val;
114
115 return e1e_wphy(hw, M88E1000_PHY_GEN_CONTROL, 0);
116 }
117
118 /**
119 * e1000_read_phy_reg_mdic - Read MDI control register
120 * @hw: pointer to the HW structure
121 * @offset: register offset to be read
122 * @data: pointer to the read data
123 *
124 * Reads the MDI control regsiter in the PHY at offset and stores the
125 * information read to data.
126 **/
127 static s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
128 {
129 struct e1000_phy_info *phy = &hw->phy;
130 u32 i, mdic = 0;
131
132 if (offset > MAX_PHY_REG_ADDRESS) {
133 hw_dbg(hw, "PHY Address %d is out of range\n", offset);
134 return -E1000_ERR_PARAM;
135 }
136
137 /* Set up Op-code, Phy Address, and register offset in the MDI
138 * Control register. The MAC will take care of interfacing with the
139 * PHY to retrieve the desired data.
140 */
141 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
142 (phy->addr << E1000_MDIC_PHY_SHIFT) |
143 (E1000_MDIC_OP_READ));
144
145 ew32(MDIC, mdic);
146
147 /* Poll the ready bit to see if the MDI read completed */
148 for (i = 0; i < 64; i++) {
149 udelay(50);
150 mdic = er32(MDIC);
151 if (mdic & E1000_MDIC_READY)
152 break;
153 }
154 if (!(mdic & E1000_MDIC_READY)) {
155 hw_dbg(hw, "MDI Read did not complete\n");
156 return -E1000_ERR_PHY;
157 }
158 if (mdic & E1000_MDIC_ERROR) {
159 hw_dbg(hw, "MDI Error\n");
160 return -E1000_ERR_PHY;
161 }
162 *data = (u16) mdic;
163
164 return 0;
165 }
166
167 /**
168 * e1000_write_phy_reg_mdic - Write MDI control register
169 * @hw: pointer to the HW structure
170 * @offset: register offset to write to
171 * @data: data to write to register at offset
172 *
173 * Writes data to MDI control register in the PHY at offset.
174 **/
175 static s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
176 {
177 struct e1000_phy_info *phy = &hw->phy;
178 u32 i, mdic = 0;
179
180 if (offset > MAX_PHY_REG_ADDRESS) {
181 hw_dbg(hw, "PHY Address %d is out of range\n", offset);
182 return -E1000_ERR_PARAM;
183 }
184
185 /* Set up Op-code, Phy Address, and register offset in the MDI
186 * Control register. The MAC will take care of interfacing with the
187 * PHY to retrieve the desired data.
188 */
189 mdic = (((u32)data) |
190 (offset << E1000_MDIC_REG_SHIFT) |
191 (phy->addr << E1000_MDIC_PHY_SHIFT) |
192 (E1000_MDIC_OP_WRITE));
193
194 ew32(MDIC, mdic);
195
196 /* Poll the ready bit to see if the MDI read completed */
197 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
198 udelay(5);
199 mdic = er32(MDIC);
200 if (mdic & E1000_MDIC_READY)
201 break;
202 }
203 if (!(mdic & E1000_MDIC_READY)) {
204 hw_dbg(hw, "MDI Write did not complete\n");
205 return -E1000_ERR_PHY;
206 }
207
208 return 0;
209 }
210
211 /**
212 * e1000e_read_phy_reg_m88 - Read m88 PHY register
213 * @hw: pointer to the HW structure
214 * @offset: register offset to be read
215 * @data: pointer to the read data
216 *
217 * Acquires semaphore, if necessary, then reads the PHY register at offset
218 * and storing the retrieved information in data. Release any acquired
219 * semaphores before exiting.
220 **/
221 s32 e1000e_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
222 {
223 s32 ret_val;
224
225 ret_val = hw->phy.ops.acquire_phy(hw);
226 if (ret_val)
227 return ret_val;
228
229 ret_val = e1000_read_phy_reg_mdic(hw,
230 MAX_PHY_REG_ADDRESS & offset,
231 data);
232
233 hw->phy.ops.release_phy(hw);
234
235 return ret_val;
236 }
237
238 /**
239 * e1000e_write_phy_reg_m88 - Write m88 PHY register
240 * @hw: pointer to the HW structure
241 * @offset: register offset to write to
242 * @data: data to write at register offset
243 *
244 * Acquires semaphore, if necessary, then writes the data to PHY register
245 * at the offset. Release any acquired semaphores before exiting.
246 **/
247 s32 e1000e_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
248 {
249 s32 ret_val;
250
251 ret_val = hw->phy.ops.acquire_phy(hw);
252 if (ret_val)
253 return ret_val;
254
255 ret_val = e1000_write_phy_reg_mdic(hw,
256 MAX_PHY_REG_ADDRESS & offset,
257 data);
258
259 hw->phy.ops.release_phy(hw);
260
261 return ret_val;
262 }
263
264 /**
265 * e1000e_read_phy_reg_igp - Read igp PHY register
266 * @hw: pointer to the HW structure
267 * @offset: register offset to be read
268 * @data: pointer to the read data
269 *
270 * Acquires semaphore, if necessary, then reads the PHY register at offset
271 * and storing the retrieved information in data. Release any acquired
272 * semaphores before exiting.
273 **/
274 s32 e1000e_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
275 {
276 s32 ret_val;
277
278 ret_val = hw->phy.ops.acquire_phy(hw);
279 if (ret_val)
280 return ret_val;
281
282 if (offset > MAX_PHY_MULTI_PAGE_REG) {
283 ret_val = e1000_write_phy_reg_mdic(hw,
284 IGP01E1000_PHY_PAGE_SELECT,
285 (u16)offset);
286 if (ret_val) {
287 hw->phy.ops.release_phy(hw);
288 return ret_val;
289 }
290 }
291
292 ret_val = e1000_read_phy_reg_mdic(hw,
293 MAX_PHY_REG_ADDRESS & offset,
294 data);
295
296 hw->phy.ops.release_phy(hw);
297
298 return ret_val;
299 }
300
301 /**
302 * e1000e_write_phy_reg_igp - Write igp PHY register
303 * @hw: pointer to the HW structure
304 * @offset: register offset to write to
305 * @data: data to write at register offset
306 *
307 * Acquires semaphore, if necessary, then writes the data to PHY register
308 * at the offset. Release any acquired semaphores before exiting.
309 **/
310 s32 e1000e_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
311 {
312 s32 ret_val;
313
314 ret_val = hw->phy.ops.acquire_phy(hw);
315 if (ret_val)
316 return ret_val;
317
318 if (offset > MAX_PHY_MULTI_PAGE_REG) {
319 ret_val = e1000_write_phy_reg_mdic(hw,
320 IGP01E1000_PHY_PAGE_SELECT,
321 (u16)offset);
322 if (ret_val) {
323 hw->phy.ops.release_phy(hw);
324 return ret_val;
325 }
326 }
327
328 ret_val = e1000_write_phy_reg_mdic(hw,
329 MAX_PHY_REG_ADDRESS & offset,
330 data);
331
332 hw->phy.ops.release_phy(hw);
333
334 return ret_val;
335 }
336
337 /**
338 * e1000e_read_kmrn_reg - Read kumeran register
339 * @hw: pointer to the HW structure
340 * @offset: register offset to be read
341 * @data: pointer to the read data
342 *
343 * Acquires semaphore, if necessary. Then reads the PHY register at offset
344 * using the kumeran interface. The information retrieved is stored in data.
345 * Release any acquired semaphores before exiting.
346 **/
347 s32 e1000e_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data)
348 {
349 u32 kmrnctrlsta;
350 s32 ret_val;
351
352 ret_val = hw->phy.ops.acquire_phy(hw);
353 if (ret_val)
354 return ret_val;
355
356 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
357 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
358 ew32(KMRNCTRLSTA, kmrnctrlsta);
359
360 udelay(2);
361
362 kmrnctrlsta = er32(KMRNCTRLSTA);
363 *data = (u16)kmrnctrlsta;
364
365 hw->phy.ops.release_phy(hw);
366
367 return ret_val;
368 }
369
370 /**
371 * e1000e_write_kmrn_reg - Write kumeran register
372 * @hw: pointer to the HW structure
373 * @offset: register offset to write to
374 * @data: data to write at register offset
375 *
376 * Acquires semaphore, if necessary. Then write the data to PHY register
377 * at the offset using the kumeran interface. Release any acquired semaphores
378 * before exiting.
379 **/
380 s32 e1000e_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data)
381 {
382 u32 kmrnctrlsta;
383 s32 ret_val;
384
385 ret_val = hw->phy.ops.acquire_phy(hw);
386 if (ret_val)
387 return ret_val;
388
389 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
390 E1000_KMRNCTRLSTA_OFFSET) | data;
391 ew32(KMRNCTRLSTA, kmrnctrlsta);
392
393 udelay(2);
394 hw->phy.ops.release_phy(hw);
395
396 return ret_val;
397 }
398
399 /**
400 * e1000e_copper_link_setup_m88 - Setup m88 PHY's for copper link
401 * @hw: pointer to the HW structure
402 *
403 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
404 * and downshift values are set also.
405 **/
406 s32 e1000e_copper_link_setup_m88(struct e1000_hw *hw)
407 {
408 struct e1000_phy_info *phy = &hw->phy;
409 s32 ret_val;
410 u16 phy_data;
411
412 /* Enable CRS on TX. This must be set for half-duplex operation. */
413 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
414 if (ret_val)
415 return ret_val;
416
417 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
418
419 /* Options:
420 * MDI/MDI-X = 0 (default)
421 * 0 - Auto for all speeds
422 * 1 - MDI mode
423 * 2 - MDI-X mode
424 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
425 */
426 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
427
428 switch (phy->mdix) {
429 case 1:
430 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
431 break;
432 case 2:
433 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
434 break;
435 case 3:
436 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
437 break;
438 case 0:
439 default:
440 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
441 break;
442 }
443
444 /* Options:
445 * disable_polarity_correction = 0 (default)
446 * Automatic Correction for Reversed Cable Polarity
447 * 0 - Disabled
448 * 1 - Enabled
449 */
450 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
451 if (phy->disable_polarity_correction == 1)
452 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
453
454 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
455 if (ret_val)
456 return ret_val;
457
458 if (phy->revision < 4) {
459 /* Force TX_CLK in the Extended PHY Specific Control Register
460 * to 25MHz clock.
461 */
462 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
463 if (ret_val)
464 return ret_val;
465
466 phy_data |= M88E1000_EPSCR_TX_CLK_25;
467
468 if ((phy->revision == 2) &&
469 (phy->id == M88E1111_I_PHY_ID)) {
470 /* 82573L PHY - set the downshift counter to 5x. */
471 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
472 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
473 } else {
474 /* Configure Master and Slave downshift values */
475 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
476 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
477 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
478 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
479 }
480 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
481 if (ret_val)
482 return ret_val;
483 }
484
485 /* Commit the changes. */
486 ret_val = e1000e_commit_phy(hw);
487 if (ret_val)
488 hw_dbg(hw, "Error committing the PHY changes\n");
489
490 return ret_val;
491 }
492
493 /**
494 * e1000e_copper_link_setup_igp - Setup igp PHY's for copper link
495 * @hw: pointer to the HW structure
496 *
497 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
498 * igp PHY's.
499 **/
500 s32 e1000e_copper_link_setup_igp(struct e1000_hw *hw)
501 {
502 struct e1000_phy_info *phy = &hw->phy;
503 s32 ret_val;
504 u16 data;
505
506 ret_val = e1000_phy_hw_reset(hw);
507 if (ret_val) {
508 hw_dbg(hw, "Error resetting the PHY.\n");
509 return ret_val;
510 }
511
512 /* Wait 15ms for MAC to configure PHY from NVM settings. */
513 msleep(15);
514
515 /* disable lplu d0 during driver init */
516 ret_val = e1000_set_d0_lplu_state(hw, 0);
517 if (ret_val) {
518 hw_dbg(hw, "Error Disabling LPLU D0\n");
519 return ret_val;
520 }
521 /* Configure mdi-mdix settings */
522 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &data);
523 if (ret_val)
524 return ret_val;
525
526 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
527
528 switch (phy->mdix) {
529 case 1:
530 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
531 break;
532 case 2:
533 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
534 break;
535 case 0:
536 default:
537 data |= IGP01E1000_PSCR_AUTO_MDIX;
538 break;
539 }
540 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, data);
541 if (ret_val)
542 return ret_val;
543
544 /* set auto-master slave resolution settings */
545 if (hw->mac.autoneg) {
546 /* when autonegotiation advertisement is only 1000Mbps then we
547 * should disable SmartSpeed and enable Auto MasterSlave
548 * resolution as hardware default. */
549 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
550 /* Disable SmartSpeed */
551 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
552 &data);
553 if (ret_val)
554 return ret_val;
555
556 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
557 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
558 data);
559 if (ret_val)
560 return ret_val;
561
562 /* Set auto Master/Slave resolution process */
563 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
564 if (ret_val)
565 return ret_val;
566
567 data &= ~CR_1000T_MS_ENABLE;
568 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
569 if (ret_val)
570 return ret_val;
571 }
572
573 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &data);
574 if (ret_val)
575 return ret_val;
576
577 /* load defaults for future use */
578 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
579 ((data & CR_1000T_MS_VALUE) ?
580 e1000_ms_force_master :
581 e1000_ms_force_slave) :
582 e1000_ms_auto;
583
584 switch (phy->ms_type) {
585 case e1000_ms_force_master:
586 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
587 break;
588 case e1000_ms_force_slave:
589 data |= CR_1000T_MS_ENABLE;
590 data &= ~(CR_1000T_MS_VALUE);
591 break;
592 case e1000_ms_auto:
593 data &= ~CR_1000T_MS_ENABLE;
594 default:
595 break;
596 }
597 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, data);
598 }
599
600 return ret_val;
601 }
602
603 /**
604 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
605 * @hw: pointer to the HW structure
606 *
607 * Reads the MII auto-neg advertisement register and/or the 1000T control
608 * register and if the PHY is already setup for auto-negotiation, then
609 * return successful. Otherwise, setup advertisement and flow control to
610 * the appropriate values for the wanted auto-negotiation.
611 **/
612 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
613 {
614 struct e1000_phy_info *phy = &hw->phy;
615 s32 ret_val;
616 u16 mii_autoneg_adv_reg;
617 u16 mii_1000t_ctrl_reg = 0;
618
619 phy->autoneg_advertised &= phy->autoneg_mask;
620
621 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
622 ret_val = e1e_rphy(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
623 if (ret_val)
624 return ret_val;
625
626 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
627 /* Read the MII 1000Base-T Control Register (Address 9). */
628 ret_val = e1e_rphy(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
629 if (ret_val)
630 return ret_val;
631 }
632
633 /* Need to parse both autoneg_advertised and fc and set up
634 * the appropriate PHY registers. First we will parse for
635 * autoneg_advertised software override. Since we can advertise
636 * a plethora of combinations, we need to check each bit
637 * individually.
638 */
639
640 /* First we clear all the 10/100 mb speed bits in the Auto-Neg
641 * Advertisement Register (Address 4) and the 1000 mb speed bits in
642 * the 1000Base-T Control Register (Address 9).
643 */
644 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
645 NWAY_AR_100TX_HD_CAPS |
646 NWAY_AR_10T_FD_CAPS |
647 NWAY_AR_10T_HD_CAPS);
648 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
649
650 hw_dbg(hw, "autoneg_advertised %x\n", phy->autoneg_advertised);
651
652 /* Do we want to advertise 10 Mb Half Duplex? */
653 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
654 hw_dbg(hw, "Advertise 10mb Half duplex\n");
655 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
656 }
657
658 /* Do we want to advertise 10 Mb Full Duplex? */
659 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
660 hw_dbg(hw, "Advertise 10mb Full duplex\n");
661 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
662 }
663
664 /* Do we want to advertise 100 Mb Half Duplex? */
665 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
666 hw_dbg(hw, "Advertise 100mb Half duplex\n");
667 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
668 }
669
670 /* Do we want to advertise 100 Mb Full Duplex? */
671 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
672 hw_dbg(hw, "Advertise 100mb Full duplex\n");
673 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
674 }
675
676 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
677 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
678 hw_dbg(hw, "Advertise 1000mb Half duplex request denied!\n");
679
680 /* Do we want to advertise 1000 Mb Full Duplex? */
681 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
682 hw_dbg(hw, "Advertise 1000mb Full duplex\n");
683 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
684 }
685
686 /* Check for a software override of the flow control settings, and
687 * setup the PHY advertisement registers accordingly. If
688 * auto-negotiation is enabled, then software will have to set the
689 * "PAUSE" bits to the correct value in the Auto-Negotiation
690 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
691 * negotiation.
692 *
693 * The possible values of the "fc" parameter are:
694 * 0: Flow control is completely disabled
695 * 1: Rx flow control is enabled (we can receive pause frames
696 * but not send pause frames).
697 * 2: Tx flow control is enabled (we can send pause frames
698 * but we do not support receiving pause frames).
699 * 3: Both Rx and TX flow control (symmetric) are enabled.
700 * other: No software override. The flow control configuration
701 * in the EEPROM is used.
702 */
703 switch (hw->mac.fc) {
704 case e1000_fc_none:
705 /* Flow control (RX & TX) is completely disabled by a
706 * software over-ride.
707 */
708 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
709 break;
710 case e1000_fc_rx_pause:
711 /* RX Flow control is enabled, and TX Flow control is
712 * disabled, by a software over-ride.
713 */
714 /* Since there really isn't a way to advertise that we are
715 * capable of RX Pause ONLY, we will advertise that we
716 * support both symmetric and asymmetric RX PAUSE. Later
717 * (in e1000e_config_fc_after_link_up) we will disable the
718 * hw's ability to send PAUSE frames.
719 */
720 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
721 break;
722 case e1000_fc_tx_pause:
723 /* TX Flow control is enabled, and RX Flow control is
724 * disabled, by a software over-ride.
725 */
726 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
727 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
728 break;
729 case e1000_fc_full:
730 /* Flow control (both RX and TX) is enabled by a software
731 * over-ride.
732 */
733 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
734 break;
735 default:
736 hw_dbg(hw, "Flow control param set incorrectly\n");
737 ret_val = -E1000_ERR_CONFIG;
738 return ret_val;
739 }
740
741 ret_val = e1e_wphy(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
742 if (ret_val)
743 return ret_val;
744
745 hw_dbg(hw, "Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
746
747 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
748 ret_val = e1e_wphy(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
749 }
750
751 return ret_val;
752 }
753
754 /**
755 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
756 * @hw: pointer to the HW structure
757 *
758 * Performs initial bounds checking on autoneg advertisement parameter, then
759 * configure to advertise the full capability. Setup the PHY to autoneg
760 * and restart the negotiation process between the link partner. If
761 * wait_for_link, then wait for autoneg to complete before exiting.
762 **/
763 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
764 {
765 struct e1000_phy_info *phy = &hw->phy;
766 s32 ret_val;
767 u16 phy_ctrl;
768
769 /* Perform some bounds checking on the autoneg advertisement
770 * parameter.
771 */
772 phy->autoneg_advertised &= phy->autoneg_mask;
773
774 /* If autoneg_advertised is zero, we assume it was not defaulted
775 * by the calling code so we set to advertise full capability.
776 */
777 if (phy->autoneg_advertised == 0)
778 phy->autoneg_advertised = phy->autoneg_mask;
779
780 hw_dbg(hw, "Reconfiguring auto-neg advertisement params\n");
781 ret_val = e1000_phy_setup_autoneg(hw);
782 if (ret_val) {
783 hw_dbg(hw, "Error Setting up Auto-Negotiation\n");
784 return ret_val;
785 }
786 hw_dbg(hw, "Restarting Auto-Neg\n");
787
788 /* Restart auto-negotiation by setting the Auto Neg Enable bit and
789 * the Auto Neg Restart bit in the PHY control register.
790 */
791 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
792 if (ret_val)
793 return ret_val;
794
795 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
796 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
797 if (ret_val)
798 return ret_val;
799
800 /* Does the user want to wait for Auto-Neg to complete here, or
801 * check at a later time (for example, callback routine).
802 */
803 if (phy->wait_for_link) {
804 ret_val = e1000_wait_autoneg(hw);
805 if (ret_val) {
806 hw_dbg(hw, "Error while waiting for "
807 "autoneg to complete\n");
808 return ret_val;
809 }
810 }
811
812 hw->mac.get_link_status = 1;
813
814 return ret_val;
815 }
816
817 /**
818 * e1000e_setup_copper_link - Configure copper link settings
819 * @hw: pointer to the HW structure
820 *
821 * Calls the appropriate function to configure the link for auto-neg or forced
822 * speed and duplex. Then we check for link, once link is established calls
823 * to configure collision distance and flow control are called. If link is
824 * not established, we return -E1000_ERR_PHY (-2).
825 **/
826 s32 e1000e_setup_copper_link(struct e1000_hw *hw)
827 {
828 s32 ret_val;
829 bool link;
830
831 if (hw->mac.autoneg) {
832 /* Setup autoneg and flow control advertisement and perform
833 * autonegotiation. */
834 ret_val = e1000_copper_link_autoneg(hw);
835 if (ret_val)
836 return ret_val;
837 } else {
838 /* PHY will be set to 10H, 10F, 100H or 100F
839 * depending on user settings. */
840 hw_dbg(hw, "Forcing Speed and Duplex\n");
841 ret_val = e1000_phy_force_speed_duplex(hw);
842 if (ret_val) {
843 hw_dbg(hw, "Error Forcing Speed and Duplex\n");
844 return ret_val;
845 }
846 }
847
848 /* Check link status. Wait up to 100 microseconds for link to become
849 * valid.
850 */
851 ret_val = e1000e_phy_has_link_generic(hw,
852 COPPER_LINK_UP_LIMIT,
853 10,
854 &link);
855 if (ret_val)
856 return ret_val;
857
858 if (link) {
859 hw_dbg(hw, "Valid link established!!!\n");
860 e1000e_config_collision_dist(hw);
861 ret_val = e1000e_config_fc_after_link_up(hw);
862 } else {
863 hw_dbg(hw, "Unable to establish link!!!\n");
864 }
865
866 return ret_val;
867 }
868
869 /**
870 * e1000e_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
871 * @hw: pointer to the HW structure
872 *
873 * Calls the PHY setup function to force speed and duplex. Clears the
874 * auto-crossover to force MDI manually. Waits for link and returns
875 * successful if link up is successful, else -E1000_ERR_PHY (-2).
876 **/
877 s32 e1000e_phy_force_speed_duplex_igp(struct e1000_hw *hw)
878 {
879 struct e1000_phy_info *phy = &hw->phy;
880 s32 ret_val;
881 u16 phy_data;
882 bool link;
883
884 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
885 if (ret_val)
886 return ret_val;
887
888 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
889
890 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
891 if (ret_val)
892 return ret_val;
893
894 /* Clear Auto-Crossover to force MDI manually. IGP requires MDI
895 * forced whenever speed and duplex are forced.
896 */
897 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
898 if (ret_val)
899 return ret_val;
900
901 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
902 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
903
904 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
905 if (ret_val)
906 return ret_val;
907
908 hw_dbg(hw, "IGP PSCR: %X\n", phy_data);
909
910 udelay(1);
911
912 if (phy->wait_for_link) {
913 hw_dbg(hw, "Waiting for forced speed/duplex link on IGP phy.\n");
914
915 ret_val = e1000e_phy_has_link_generic(hw,
916 PHY_FORCE_LIMIT,
917 100000,
918 &link);
919 if (ret_val)
920 return ret_val;
921
922 if (!link)
923 hw_dbg(hw, "Link taking longer than expected.\n");
924
925 /* Try once more */
926 ret_val = e1000e_phy_has_link_generic(hw,
927 PHY_FORCE_LIMIT,
928 100000,
929 &link);
930 if (ret_val)
931 return ret_val;
932 }
933
934 return ret_val;
935 }
936
937 /**
938 * e1000e_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
939 * @hw: pointer to the HW structure
940 *
941 * Calls the PHY setup function to force speed and duplex. Clears the
942 * auto-crossover to force MDI manually. Resets the PHY to commit the
943 * changes. If time expires while waiting for link up, we reset the DSP.
944 * After reset, TX_CLK and CRS on TX must be set. Return successful upon
945 * successful completion, else return corresponding error code.
946 **/
947 s32 e1000e_phy_force_speed_duplex_m88(struct e1000_hw *hw)
948 {
949 struct e1000_phy_info *phy = &hw->phy;
950 s32 ret_val;
951 u16 phy_data;
952 bool link;
953
954 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
955 * forced whenever speed and duplex are forced.
956 */
957 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
958 if (ret_val)
959 return ret_val;
960
961 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
962 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
963 if (ret_val)
964 return ret_val;
965
966 hw_dbg(hw, "M88E1000 PSCR: %X\n", phy_data);
967
968 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_data);
969 if (ret_val)
970 return ret_val;
971
972 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
973
974 /* Reset the phy to commit changes. */
975 phy_data |= MII_CR_RESET;
976
977 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_data);
978 if (ret_val)
979 return ret_val;
980
981 udelay(1);
982
983 if (phy->wait_for_link) {
984 hw_dbg(hw, "Waiting for forced speed/duplex link on M88 phy.\n");
985
986 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
987 100000, &link);
988 if (ret_val)
989 return ret_val;
990
991 if (!link) {
992 /* We didn't get link.
993 * Reset the DSP and cross our fingers.
994 */
995 ret_val = e1e_wphy(hw, M88E1000_PHY_PAGE_SELECT, 0x001d);
996 if (ret_val)
997 return ret_val;
998 ret_val = e1000e_phy_reset_dsp(hw);
999 if (ret_val)
1000 return ret_val;
1001 }
1002
1003 /* Try once more */
1004 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1005 100000, &link);
1006 if (ret_val)
1007 return ret_val;
1008 }
1009
1010 ret_val = e1e_rphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1011 if (ret_val)
1012 return ret_val;
1013
1014 /* Resetting the phy means we need to re-force TX_CLK in the
1015 * Extended PHY Specific Control Register to 25MHz clock from
1016 * the reset value of 2.5MHz.
1017 */
1018 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1019 ret_val = e1e_wphy(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1020 if (ret_val)
1021 return ret_val;
1022
1023 /* In addition, we must re-enable CRS on Tx for both half and full
1024 * duplex.
1025 */
1026 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1027 if (ret_val)
1028 return ret_val;
1029
1030 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1031 ret_val = e1e_wphy(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1032
1033 return ret_val;
1034 }
1035
1036 /**
1037 * e1000e_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1038 * @hw: pointer to the HW structure
1039 * @phy_ctrl: pointer to current value of PHY_CONTROL
1040 *
1041 * Forces speed and duplex on the PHY by doing the following: disable flow
1042 * control, force speed/duplex on the MAC, disable auto speed detection,
1043 * disable auto-negotiation, configure duplex, configure speed, configure
1044 * the collision distance, write configuration to CTRL register. The
1045 * caller must write to the PHY_CONTROL register for these settings to
1046 * take affect.
1047 **/
1048 void e1000e_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1049 {
1050 struct e1000_mac_info *mac = &hw->mac;
1051 u32 ctrl;
1052
1053 /* Turn off flow control when forcing speed/duplex */
1054 mac->fc = e1000_fc_none;
1055
1056 /* Force speed/duplex on the mac */
1057 ctrl = er32(CTRL);
1058 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1059 ctrl &= ~E1000_CTRL_SPD_SEL;
1060
1061 /* Disable Auto Speed Detection */
1062 ctrl &= ~E1000_CTRL_ASDE;
1063
1064 /* Disable autoneg on the phy */
1065 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1066
1067 /* Forcing Full or Half Duplex? */
1068 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1069 ctrl &= ~E1000_CTRL_FD;
1070 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1071 hw_dbg(hw, "Half Duplex\n");
1072 } else {
1073 ctrl |= E1000_CTRL_FD;
1074 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1075 hw_dbg(hw, "Full Duplex\n");
1076 }
1077
1078 /* Forcing 10mb or 100mb? */
1079 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1080 ctrl |= E1000_CTRL_SPD_100;
1081 *phy_ctrl |= MII_CR_SPEED_100;
1082 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1083 hw_dbg(hw, "Forcing 100mb\n");
1084 } else {
1085 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1086 *phy_ctrl |= MII_CR_SPEED_10;
1087 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1088 hw_dbg(hw, "Forcing 10mb\n");
1089 }
1090
1091 e1000e_config_collision_dist(hw);
1092
1093 ew32(CTRL, ctrl);
1094 }
1095
1096 /**
1097 * e1000e_set_d3_lplu_state - Sets low power link up state for D3
1098 * @hw: pointer to the HW structure
1099 * @active: boolean used to enable/disable lplu
1100 *
1101 * Success returns 0, Failure returns 1
1102 *
1103 * The low power link up (lplu) state is set to the power management level D3
1104 * and SmartSpeed is disabled when active is true, else clear lplu for D3
1105 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1106 * is used during Dx states where the power conservation is most important.
1107 * During driver activity, SmartSpeed should be enabled so performance is
1108 * maintained.
1109 **/
1110 s32 e1000e_set_d3_lplu_state(struct e1000_hw *hw, bool active)
1111 {
1112 struct e1000_phy_info *phy = &hw->phy;
1113 s32 ret_val;
1114 u16 data;
1115
1116 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1117 if (ret_val)
1118 return ret_val;
1119
1120 if (!active) {
1121 data &= ~IGP02E1000_PM_D3_LPLU;
1122 ret_val = e1e_wphy(hw,
1123 IGP02E1000_PHY_POWER_MGMT,
1124 data);
1125 if (ret_val)
1126 return ret_val;
1127 /* LPLU and SmartSpeed are mutually exclusive. LPLU is used
1128 * during Dx states where the power conservation is most
1129 * important. During driver activity we should enable
1130 * SmartSpeed, so performance is maintained. */
1131 if (phy->smart_speed == e1000_smart_speed_on) {
1132 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1133 &data);
1134 if (ret_val)
1135 return ret_val;
1136
1137 data |= IGP01E1000_PSCFR_SMART_SPEED;
1138 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1139 data);
1140 if (ret_val)
1141 return ret_val;
1142 } else if (phy->smart_speed == e1000_smart_speed_off) {
1143 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1144 &data);
1145 if (ret_val)
1146 return ret_val;
1147
1148 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1149 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
1150 data);
1151 if (ret_val)
1152 return ret_val;
1153 }
1154 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1155 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1156 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1157 data |= IGP02E1000_PM_D3_LPLU;
1158 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
1159 if (ret_val)
1160 return ret_val;
1161
1162 /* When LPLU is enabled, we should disable SmartSpeed */
1163 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
1164 if (ret_val)
1165 return ret_val;
1166
1167 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1168 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
1169 }
1170
1171 return ret_val;
1172 }
1173
1174 /**
1175 * e1000e_check_downshift - Checks whether a downshift in speed occured
1176 * @hw: pointer to the HW structure
1177 *
1178 * Success returns 0, Failure returns 1
1179 *
1180 * A downshift is detected by querying the PHY link health.
1181 **/
1182 s32 e1000e_check_downshift(struct e1000_hw *hw)
1183 {
1184 struct e1000_phy_info *phy = &hw->phy;
1185 s32 ret_val;
1186 u16 phy_data, offset, mask;
1187
1188 switch (phy->type) {
1189 case e1000_phy_m88:
1190 case e1000_phy_gg82563:
1191 offset = M88E1000_PHY_SPEC_STATUS;
1192 mask = M88E1000_PSSR_DOWNSHIFT;
1193 break;
1194 case e1000_phy_igp_2:
1195 case e1000_phy_igp_3:
1196 offset = IGP01E1000_PHY_LINK_HEALTH;
1197 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1198 break;
1199 default:
1200 /* speed downshift not supported */
1201 phy->speed_downgraded = 0;
1202 return 0;
1203 }
1204
1205 ret_val = e1e_rphy(hw, offset, &phy_data);
1206
1207 if (!ret_val)
1208 phy->speed_downgraded = (phy_data & mask);
1209
1210 return ret_val;
1211 }
1212
1213 /**
1214 * e1000_check_polarity_m88 - Checks the polarity.
1215 * @hw: pointer to the HW structure
1216 *
1217 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1218 *
1219 * Polarity is determined based on the PHY specific status register.
1220 **/
1221 static s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1222 {
1223 struct e1000_phy_info *phy = &hw->phy;
1224 s32 ret_val;
1225 u16 data;
1226
1227 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &data);
1228
1229 if (!ret_val)
1230 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1231 ? e1000_rev_polarity_reversed
1232 : e1000_rev_polarity_normal;
1233
1234 return ret_val;
1235 }
1236
1237 /**
1238 * e1000_check_polarity_igp - Checks the polarity.
1239 * @hw: pointer to the HW structure
1240 *
1241 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1242 *
1243 * Polarity is determined based on the PHY port status register, and the
1244 * current speed (since there is no polarity at 100Mbps).
1245 **/
1246 static s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1247 {
1248 struct e1000_phy_info *phy = &hw->phy;
1249 s32 ret_val;
1250 u16 data, offset, mask;
1251
1252 /* Polarity is determined based on the speed of
1253 * our connection. */
1254 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1255 if (ret_val)
1256 return ret_val;
1257
1258 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1259 IGP01E1000_PSSR_SPEED_1000MBPS) {
1260 offset = IGP01E1000_PHY_PCS_INIT_REG;
1261 mask = IGP01E1000_PHY_POLARITY_MASK;
1262 } else {
1263 /* This really only applies to 10Mbps since
1264 * there is no polarity for 100Mbps (always 0).
1265 */
1266 offset = IGP01E1000_PHY_PORT_STATUS;
1267 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1268 }
1269
1270 ret_val = e1e_rphy(hw, offset, &data);
1271
1272 if (!ret_val)
1273 phy->cable_polarity = (data & mask)
1274 ? e1000_rev_polarity_reversed
1275 : e1000_rev_polarity_normal;
1276
1277 return ret_val;
1278 }
1279
1280 /**
1281 * e1000_wait_autoneg - Wait for auto-neg compeletion
1282 * @hw: pointer to the HW structure
1283 *
1284 * Waits for auto-negotiation to complete or for the auto-negotiation time
1285 * limit to expire, which ever happens first.
1286 **/
1287 static s32 e1000_wait_autoneg(struct e1000_hw *hw)
1288 {
1289 s32 ret_val = 0;
1290 u16 i, phy_status;
1291
1292 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
1293 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
1294 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1295 if (ret_val)
1296 break;
1297 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1298 if (ret_val)
1299 break;
1300 if (phy_status & MII_SR_AUTONEG_COMPLETE)
1301 break;
1302 msleep(100);
1303 }
1304
1305 /* PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
1306 * has completed.
1307 */
1308 return ret_val;
1309 }
1310
1311 /**
1312 * e1000e_phy_has_link_generic - Polls PHY for link
1313 * @hw: pointer to the HW structure
1314 * @iterations: number of times to poll for link
1315 * @usec_interval: delay between polling attempts
1316 * @success: pointer to whether polling was successful or not
1317 *
1318 * Polls the PHY status register for link, 'iterations' number of times.
1319 **/
1320 s32 e1000e_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
1321 u32 usec_interval, bool *success)
1322 {
1323 s32 ret_val = 0;
1324 u16 i, phy_status;
1325
1326 for (i = 0; i < iterations; i++) {
1327 /* Some PHYs require the PHY_STATUS register to be read
1328 * twice due to the link bit being sticky. No harm doing
1329 * it across the board.
1330 */
1331 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1332 if (ret_val)
1333 break;
1334 ret_val = e1e_rphy(hw, PHY_STATUS, &phy_status);
1335 if (ret_val)
1336 break;
1337 if (phy_status & MII_SR_LINK_STATUS)
1338 break;
1339 if (usec_interval >= 1000)
1340 mdelay(usec_interval/1000);
1341 else
1342 udelay(usec_interval);
1343 }
1344
1345 *success = (i < iterations);
1346
1347 return ret_val;
1348 }
1349
1350 /**
1351 * e1000e_get_cable_length_m88 - Determine cable length for m88 PHY
1352 * @hw: pointer to the HW structure
1353 *
1354 * Reads the PHY specific status register to retrieve the cable length
1355 * information. The cable length is determined by averaging the minimum and
1356 * maximum values to get the "average" cable length. The m88 PHY has four
1357 * possible cable length values, which are:
1358 * Register Value Cable Length
1359 * 0 < 50 meters
1360 * 1 50 - 80 meters
1361 * 2 80 - 110 meters
1362 * 3 110 - 140 meters
1363 * 4 > 140 meters
1364 **/
1365 s32 e1000e_get_cable_length_m88(struct e1000_hw *hw)
1366 {
1367 struct e1000_phy_info *phy = &hw->phy;
1368 s32 ret_val;
1369 u16 phy_data, index;
1370
1371 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1372 if (ret_val)
1373 return ret_val;
1374
1375 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
1376 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
1377 phy->min_cable_length = e1000_m88_cable_length_table[index];
1378 phy->max_cable_length = e1000_m88_cable_length_table[index+1];
1379
1380 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1381
1382 return ret_val;
1383 }
1384
1385 /**
1386 * e1000e_get_cable_length_igp_2 - Determine cable length for igp2 PHY
1387 * @hw: pointer to the HW structure
1388 *
1389 * The automatic gain control (agc) normalizes the amplitude of the
1390 * received signal, adjusting for the attenuation produced by the
1391 * cable. By reading the AGC registers, which reperesent the
1392 * cobination of course and fine gain value, the value can be put
1393 * into a lookup table to obtain the approximate cable length
1394 * for each channel.
1395 **/
1396 s32 e1000e_get_cable_length_igp_2(struct e1000_hw *hw)
1397 {
1398 struct e1000_phy_info *phy = &hw->phy;
1399 s32 ret_val;
1400 u16 phy_data, i, agc_value = 0;
1401 u16 cur_agc_index, max_agc_index = 0;
1402 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
1403 u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
1404 {IGP02E1000_PHY_AGC_A,
1405 IGP02E1000_PHY_AGC_B,
1406 IGP02E1000_PHY_AGC_C,
1407 IGP02E1000_PHY_AGC_D};
1408
1409 /* Read the AGC registers for all channels */
1410 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
1411 ret_val = e1e_rphy(hw, agc_reg_array[i], &phy_data);
1412 if (ret_val)
1413 return ret_val;
1414
1415 /* Getting bits 15:9, which represent the combination of
1416 * course and fine gain values. The result is a number
1417 * that can be put into the lookup table to obtain the
1418 * approximate cable length. */
1419 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
1420 IGP02E1000_AGC_LENGTH_MASK;
1421
1422 /* Array index bound check. */
1423 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
1424 (cur_agc_index == 0))
1425 return -E1000_ERR_PHY;
1426
1427 /* Remove min & max AGC values from calculation. */
1428 if (e1000_igp_2_cable_length_table[min_agc_index] >
1429 e1000_igp_2_cable_length_table[cur_agc_index])
1430 min_agc_index = cur_agc_index;
1431 if (e1000_igp_2_cable_length_table[max_agc_index] <
1432 e1000_igp_2_cable_length_table[cur_agc_index])
1433 max_agc_index = cur_agc_index;
1434
1435 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
1436 }
1437
1438 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
1439 e1000_igp_2_cable_length_table[max_agc_index]);
1440 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
1441
1442 /* Calculate cable length with the error range of +/- 10 meters. */
1443 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
1444 (agc_value - IGP02E1000_AGC_RANGE) : 0;
1445 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
1446
1447 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
1448
1449 return ret_val;
1450 }
1451
1452 /**
1453 * e1000e_get_phy_info_m88 - Retrieve PHY information
1454 * @hw: pointer to the HW structure
1455 *
1456 * Valid for only copper links. Read the PHY status register (sticky read)
1457 * to verify that link is up. Read the PHY special control register to
1458 * determine the polarity and 10base-T extended distance. Read the PHY
1459 * special status register to determine MDI/MDIx and current speed. If
1460 * speed is 1000, then determine cable length, local and remote receiver.
1461 **/
1462 s32 e1000e_get_phy_info_m88(struct e1000_hw *hw)
1463 {
1464 struct e1000_phy_info *phy = &hw->phy;
1465 s32 ret_val;
1466 u16 phy_data;
1467 bool link;
1468
1469 if (hw->media_type != e1000_media_type_copper) {
1470 hw_dbg(hw, "Phy info is only valid for copper media\n");
1471 return -E1000_ERR_CONFIG;
1472 }
1473
1474 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1475 if (ret_val)
1476 return ret_val;
1477
1478 if (!link) {
1479 hw_dbg(hw, "Phy info is only valid if link is up\n");
1480 return -E1000_ERR_CONFIG;
1481 }
1482
1483 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1484 if (ret_val)
1485 return ret_val;
1486
1487 phy->polarity_correction = (phy_data &
1488 M88E1000_PSCR_POLARITY_REVERSAL);
1489
1490 ret_val = e1000_check_polarity_m88(hw);
1491 if (ret_val)
1492 return ret_val;
1493
1494 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1495 if (ret_val)
1496 return ret_val;
1497
1498 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX);
1499
1500 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
1501 ret_val = e1000_get_cable_length(hw);
1502 if (ret_val)
1503 return ret_val;
1504
1505 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &phy_data);
1506 if (ret_val)
1507 return ret_val;
1508
1509 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
1510 ? e1000_1000t_rx_status_ok
1511 : e1000_1000t_rx_status_not_ok;
1512
1513 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
1514 ? e1000_1000t_rx_status_ok
1515 : e1000_1000t_rx_status_not_ok;
1516 } else {
1517 /* Set values to "undefined" */
1518 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1519 phy->local_rx = e1000_1000t_rx_status_undefined;
1520 phy->remote_rx = e1000_1000t_rx_status_undefined;
1521 }
1522
1523 return ret_val;
1524 }
1525
1526 /**
1527 * e1000e_get_phy_info_igp - Retrieve igp PHY information
1528 * @hw: pointer to the HW structure
1529 *
1530 * Read PHY status to determine if link is up. If link is up, then
1531 * set/determine 10base-T extended distance and polarity correction. Read
1532 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
1533 * determine on the cable length, local and remote receiver.
1534 **/
1535 s32 e1000e_get_phy_info_igp(struct e1000_hw *hw)
1536 {
1537 struct e1000_phy_info *phy = &hw->phy;
1538 s32 ret_val;
1539 u16 data;
1540 bool link;
1541
1542 ret_val = e1000e_phy_has_link_generic(hw, 1, 0, &link);
1543 if (ret_val)
1544 return ret_val;
1545
1546 if (!link) {
1547 hw_dbg(hw, "Phy info is only valid if link is up\n");
1548 return -E1000_ERR_CONFIG;
1549 }
1550
1551 phy->polarity_correction = 1;
1552
1553 ret_val = e1000_check_polarity_igp(hw);
1554 if (ret_val)
1555 return ret_val;
1556
1557 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1558 if (ret_val)
1559 return ret_val;
1560
1561 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX);
1562
1563 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1564 IGP01E1000_PSSR_SPEED_1000MBPS) {
1565 ret_val = e1000_get_cable_length(hw);
1566 if (ret_val)
1567 return ret_val;
1568
1569 ret_val = e1e_rphy(hw, PHY_1000T_STATUS, &data);
1570 if (ret_val)
1571 return ret_val;
1572
1573 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
1574 ? e1000_1000t_rx_status_ok
1575 : e1000_1000t_rx_status_not_ok;
1576
1577 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
1578 ? e1000_1000t_rx_status_ok
1579 : e1000_1000t_rx_status_not_ok;
1580 } else {
1581 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
1582 phy->local_rx = e1000_1000t_rx_status_undefined;
1583 phy->remote_rx = e1000_1000t_rx_status_undefined;
1584 }
1585
1586 return ret_val;
1587 }
1588
1589 /**
1590 * e1000e_phy_sw_reset - PHY software reset
1591 * @hw: pointer to the HW structure
1592 *
1593 * Does a software reset of the PHY by reading the PHY control register and
1594 * setting/write the control register reset bit to the PHY.
1595 **/
1596 s32 e1000e_phy_sw_reset(struct e1000_hw *hw)
1597 {
1598 s32 ret_val;
1599 u16 phy_ctrl;
1600
1601 ret_val = e1e_rphy(hw, PHY_CONTROL, &phy_ctrl);
1602 if (ret_val)
1603 return ret_val;
1604
1605 phy_ctrl |= MII_CR_RESET;
1606 ret_val = e1e_wphy(hw, PHY_CONTROL, phy_ctrl);
1607 if (ret_val)
1608 return ret_val;
1609
1610 udelay(1);
1611
1612 return ret_val;
1613 }
1614
1615 /**
1616 * e1000e_phy_hw_reset_generic - PHY hardware reset
1617 * @hw: pointer to the HW structure
1618 *
1619 * Verify the reset block is not blocking us from resetting. Acquire
1620 * semaphore (if necessary) and read/set/write the device control reset
1621 * bit in the PHY. Wait the appropriate delay time for the device to
1622 * reset and relase the semaphore (if necessary).
1623 **/
1624 s32 e1000e_phy_hw_reset_generic(struct e1000_hw *hw)
1625 {
1626 struct e1000_phy_info *phy = &hw->phy;
1627 s32 ret_val;
1628 u32 ctrl;
1629
1630 ret_val = e1000_check_reset_block(hw);
1631 if (ret_val)
1632 return 0;
1633
1634 ret_val = phy->ops.acquire_phy(hw);
1635 if (ret_val)
1636 return ret_val;
1637
1638 ctrl = er32(CTRL);
1639 ew32(CTRL, ctrl | E1000_CTRL_PHY_RST);
1640 e1e_flush();
1641
1642 udelay(phy->reset_delay_us);
1643
1644 ew32(CTRL, ctrl);
1645 e1e_flush();
1646
1647 udelay(150);
1648
1649 phy->ops.release_phy(hw);
1650
1651 return e1000_get_phy_cfg_done(hw);
1652 }
1653
1654 /**
1655 * e1000e_get_cfg_done - Generic configuration done
1656 * @hw: pointer to the HW structure
1657 *
1658 * Generic function to wait 10 milli-seconds for configuration to complete
1659 * and return success.
1660 **/
1661 s32 e1000e_get_cfg_done(struct e1000_hw *hw)
1662 {
1663 mdelay(10);
1664 return 0;
1665 }
1666
1667 /* Internal function pointers */
1668
1669 /**
1670 * e1000_get_phy_cfg_done - Generic PHY configuration done
1671 * @hw: pointer to the HW structure
1672 *
1673 * Return success if silicon family did not implement a family specific
1674 * get_cfg_done function.
1675 **/
1676 static s32 e1000_get_phy_cfg_done(struct e1000_hw *hw)
1677 {
1678 if (hw->phy.ops.get_cfg_done)
1679 return hw->phy.ops.get_cfg_done(hw);
1680
1681 return 0;
1682 }
1683
1684 /**
1685 * e1000_phy_force_speed_duplex - Generic force PHY speed/duplex
1686 * @hw: pointer to the HW structure
1687 *
1688 * When the silicon family has not implemented a forced speed/duplex
1689 * function for the PHY, simply return 0.
1690 **/
1691 static s32 e1000_phy_force_speed_duplex(struct e1000_hw *hw)
1692 {
1693 if (hw->phy.ops.force_speed_duplex)
1694 return hw->phy.ops.force_speed_duplex(hw);
1695
1696 return 0;
1697 }
1698
1699 /**
1700 * e1000e_get_phy_type_from_id - Get PHY type from id
1701 * @phy_id: phy_id read from the phy
1702 *
1703 * Returns the phy type from the id.
1704 **/
1705 enum e1000_phy_type e1000e_get_phy_type_from_id(u32 phy_id)
1706 {
1707 enum e1000_phy_type phy_type = e1000_phy_unknown;
1708
1709 switch (phy_id) {
1710 case M88E1000_I_PHY_ID:
1711 case M88E1000_E_PHY_ID:
1712 case M88E1111_I_PHY_ID:
1713 case M88E1011_I_PHY_ID:
1714 phy_type = e1000_phy_m88;
1715 break;
1716 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
1717 phy_type = e1000_phy_igp_2;
1718 break;
1719 case GG82563_E_PHY_ID:
1720 phy_type = e1000_phy_gg82563;
1721 break;
1722 case IGP03E1000_E_PHY_ID:
1723 phy_type = e1000_phy_igp_3;
1724 break;
1725 case IFE_E_PHY_ID:
1726 case IFE_PLUS_E_PHY_ID:
1727 case IFE_C_E_PHY_ID:
1728 phy_type = e1000_phy_ife;
1729 break;
1730 default:
1731 phy_type = e1000_phy_unknown;
1732 break;
1733 }
1734 return phy_type;
1735 }
1736
1737 /**
1738 * e1000e_commit_phy - Soft PHY reset
1739 * @hw: pointer to the HW structure
1740 *
1741 * Performs a soft PHY reset on those that apply. This is a function pointer
1742 * entry point called by drivers.
1743 **/
1744 s32 e1000e_commit_phy(struct e1000_hw *hw)
1745 {
1746 if (hw->phy.ops.commit_phy)
1747 return hw->phy.ops.commit_phy(hw);
1748
1749 return 0;
1750 }
1751
1752 /**
1753 * e1000_set_d0_lplu_state - Sets low power link up state for D0
1754 * @hw: pointer to the HW structure
1755 * @active: boolean used to enable/disable lplu
1756 *
1757 * Success returns 0, Failure returns 1
1758 *
1759 * The low power link up (lplu) state is set to the power management level D0
1760 * and SmartSpeed is disabled when active is true, else clear lplu for D0
1761 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1762 * is used during Dx states where the power conservation is most important.
1763 * During driver activity, SmartSpeed should be enabled so performance is
1764 * maintained. This is a function pointer entry point called by drivers.
1765 **/
1766 static s32 e1000_set_d0_lplu_state(struct e1000_hw *hw, bool active)
1767 {
1768 if (hw->phy.ops.set_d0_lplu_state)
1769 return hw->phy.ops.set_d0_lplu_state(hw, active);
1770
1771 return 0;
1772 }
WRT350N Kernel Patches