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omap3evm: fix broken build due to missing raise and abort functions
[x-load.git] / board / omap3evm / omap3evm.c
blob9f63caae4da96316130d344e0ddea764bd7f3cc1
1 /*
2 * (C) Copyright 2006
3 * Texas Instruments, <www.ti.com>
4 * Jian Zhang <jzhang@ti.com>
5 * Richard Woodruff <r-woodruff2@ti.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25 #include <common.h>
26 #include <command.h>
27 #include <part.h>
28 #include <fat.h>
29 #include <asm/arch/cpu.h>
30 #include <asm/arch/bits.h>
31 #include <asm/arch/mux.h>
32 #include <asm/arch/sys_proto.h>
33 #include <asm/arch/sys_info.h>
34 #include <asm/arch/clocks.h>
35 #include <asm/arch/mem.h>
36
37 /* Used to index into DPLL parameter tables */
38 struct dpll_param {
39 unsigned int m;
40 unsigned int n;
41 unsigned int fsel;
42 unsigned int m2;
43 };
44
45 typedef struct dpll_param dpll_param;
46
47 /* Following functions are exported from lowlevel_init.S */
48 extern dpll_param * get_mpu_dpll_param();
49 extern dpll_param * get_iva_dpll_param();
50 extern dpll_param * get_core_dpll_param();
51 extern dpll_param * get_per_dpll_param();
52
53 #define __raw_readl(a) (*(volatile unsigned int *)(a))
54 #define __raw_writel(v,a) (*(volatile unsigned int *)(a) = (v))
55 #define __raw_readw(a) (*(volatile unsigned short *)(a))
56 #define __raw_writew(v,a) (*(volatile unsigned short *)(a) = (v))
57
58 /*******************************************************
59 * Routine: delay
60 * Description: spinning delay to use before udelay works
61 ******************************************************/
62 static inline void delay(unsigned long loops)
63 {
64 __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
65 "bne 1b":"=r" (loops):"0"(loops));
66 }
67
68 /*****************************************
69 * Routine: board_init
70 * Description: Early hardware init.
71 *****************************************/
72 int board_init (void)
73 {
74 return 0;
75 }
76
77 /*************************************************************
78 * get_device_type(): tell if GP/HS/EMU/TST
79 *************************************************************/
80 u32 get_device_type(void)
81 {
82 int mode;
83 mode = __raw_readl(CONTROL_STATUS) & (DEVICE_MASK);
84 return(mode >>= 8);
85 }
86
87 /************************************************
88 * get_sysboot_value(void) - return SYS_BOOT[4:0]
89 ************************************************/
90 u32 get_sysboot_value(void)
91 {
92 int mode;
93 mode = __raw_readl(CONTROL_STATUS) & (SYSBOOT_MASK);
94 return mode;
95 }
96 /*************************************************************
97 * Routine: get_mem_type(void) - returns the kind of memory connected
98 * to GPMC that we are trying to boot form. Uses SYS BOOT settings.
99 *************************************************************/
100 u32 get_mem_type(void)
101 {
102 u32 mem_type = get_sysboot_value();
103 switch (mem_type){
104 case 0:
105 case 2:
106 case 4:
107 case 16:
108 case 22: return GPMC_ONENAND;
109
110 case 1:
111 case 12:
112 case 15:
113 case 21:
114 case 27: return GPMC_NAND;
115
116 case 3:
117 case 6: return MMC_ONENAND;
118
119 case 8:
120 case 11:
121 case 14:
122 case 20:
123 case 26: return GPMC_MDOC;
124
125 case 17:
126 case 18:
127 case 24: return MMC_NAND;
128
129 case 7:
130 case 10:
131 case 13:
132 case 19:
133 case 25:
134 default: return GPMC_NOR;
135 }
136 }
137
138 /******************************************
139 * get_cpu_rev(void) - extract version info
140 ******************************************/
141 u32 get_cpu_rev(void)
142 {
143 u32 cpuid=0;
144 /* On ES1.0 the IDCODE register is not exposed on L4
145 * so using CPU ID to differentiate
146 * between ES2.0 and ES1.0.
147 */
148 __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 0":"=r" (cpuid));
149 if((cpuid & 0xf) == 0x0)
150 return CPU_3430_ES1;
151 else
152 return CPU_3430_ES2;
153
154 }
155
156 /******************************************
157 * cpu_is_3410(void) - returns true for 3410
158 ******************************************/
159 u32 cpu_is_3410(void)
160 {
161 int status;
162 if(get_cpu_rev() < CPU_3430_ES2) {
163 return 0;
164 } else {
165 /* read scalability status and return 1 for 3410*/
166 status = __raw_readl(CONTROL_SCALABLE_OMAP_STATUS);
167 /* Check whether MPU frequency is set to 266 MHz which
168 * is nominal for 3410. If yes return true else false
169 */
170 if (((status >> 8) & 0x3) == 0x2)
171 return 1;
172 else
173 return 0;
174 }
175 }
176
177 /*****************************************************************
178 * sr32 - clear & set a value in a bit range for a 32 bit address
179 *****************************************************************/
180 void sr32(u32 addr, u32 start_bit, u32 num_bits, u32 value)
181 {
182 u32 tmp, msk = 0;
183 msk = 1 << num_bits;
184 --msk;
185 tmp = __raw_readl(addr) & ~(msk << start_bit);
186 tmp |= value << start_bit;
187 __raw_writel(tmp, addr);
188 }
189
190 /*********************************************************************
191 * wait_on_value() - common routine to allow waiting for changes in
192 * volatile regs.
193 *********************************************************************/
194 u32 wait_on_value(u32 read_bit_mask, u32 match_value, u32 read_addr, u32 bound)
195 {
196 u32 i = 0, val;
197 do {
198 ++i;
199 val = __raw_readl(read_addr) & read_bit_mask;
200 if (val == match_value)
201 return (1);
202 if (i == bound)
203 return (0);
204 } while (1);
205 }
206
207 #ifdef CFG_3430SDRAM_DDR
208 /*********************************************************************
209 * config_3430sdram_ddr() - Init DDR on 3430SDP dev board.
210 *********************************************************************/
211 void config_3430sdram_ddr(void)
212 {
213 /* reset sdrc controller */
214 __raw_writel(SOFTRESET, SDRC_SYSCONFIG);
215 wait_on_value(BIT0, BIT0, SDRC_STATUS, 12000000);
216 __raw_writel(0, SDRC_SYSCONFIG);
217
218 /* setup sdrc to ball mux */
219 __raw_writel(SDP_SDRC_SHARING, SDRC_SHARING);
220
221 /* set mdcfg */
222 __raw_writel(SDP_SDRC_MDCFG_0_DDR, SDRC_MCFG_0);
223
224 /* set timing */
225 if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)){
226 __raw_writel(INFINEON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
227 __raw_writel(INFINEON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
228 }
229 if ((get_mem_type() == GPMC_NAND) ||(get_mem_type() == MMC_NAND)){
230 __raw_writel(MICRON_SDRC_ACTIM_CTRLA_0, SDRC_ACTIM_CTRLA_0);
231 __raw_writel(MICRON_SDRC_ACTIM_CTRLB_0, SDRC_ACTIM_CTRLB_0);
232 }
233
234 __raw_writel(SDP_SDRC_RFR_CTRL, SDRC_RFR_CTRL);
235 __raw_writel(SDP_SDRC_POWER_POP, SDRC_POWER);
236
237 /* init sequence for mDDR/mSDR using manual commands (DDR is different) */
238 __raw_writel(CMD_NOP, SDRC_MANUAL_0);
239 delay(5000);
240 __raw_writel(CMD_PRECHARGE, SDRC_MANUAL_0);
241 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
242 __raw_writel(CMD_AUTOREFRESH, SDRC_MANUAL_0);
243
244 /* set mr0 */
245 __raw_writel(SDP_SDRC_MR_0_DDR, SDRC_MR_0);
246
247 /* set up dll */
248 __raw_writel(SDP_SDRC_DLLAB_CTRL, SDRC_DLLA_CTRL);
249 delay(0x2000); /* give time to lock */
250
251 }
252 #endif // CFG_3430SDRAM_DDR
253
254 /*************************************************************
255 * get_sys_clk_speed - determine reference oscillator speed
256 * based on known 32kHz clock and gptimer.
257 *************************************************************/
258 u32 get_osc_clk_speed(void)
259 {
260 u32 start, cstart, cend, cdiff, val;
261
262 val = __raw_readl(PRM_CLKSRC_CTRL);
263 /* If SYS_CLK is being divided by 2, remove for now */
264 val = (val & (~BIT7)) | BIT6;
265 __raw_writel(val, PRM_CLKSRC_CTRL);
266
267 /* enable timer2 */
268 val = __raw_readl(CM_CLKSEL_WKUP) | BIT0;
269 __raw_writel(val, CM_CLKSEL_WKUP); /* select sys_clk for GPT1 */
270
271 /* Enable I and F Clocks for GPT1 */
272 val = __raw_readl(CM_ICLKEN_WKUP) | BIT0 | BIT2;
273 __raw_writel(val, CM_ICLKEN_WKUP);
274 val = __raw_readl(CM_FCLKEN_WKUP) | BIT0;
275 __raw_writel(val, CM_FCLKEN_WKUP);
276
277 __raw_writel(0, OMAP34XX_GPT1 + TLDR); /* start counting at 0 */
278 __raw_writel(GPT_EN, OMAP34XX_GPT1 + TCLR); /* enable clock */
279 /* enable 32kHz source *//* enabled out of reset */
280 /* determine sys_clk via gauging */
281
282 start = 20 + __raw_readl(S32K_CR); /* start time in 20 cycles */
283 while (__raw_readl(S32K_CR) < start); /* dead loop till start time */
284 cstart = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get start sys_clk count */
285 while (__raw_readl(S32K_CR) < (start + 20)); /* wait for 40 cycles */
286 cend = __raw_readl(OMAP34XX_GPT1 + TCRR); /* get end sys_clk count */
287 cdiff = cend - cstart; /* get elapsed ticks */
288
289 /* based on number of ticks assign speed */
290 if (cdiff > 19000)
291 return (S38_4M);
292 else if (cdiff > 15200)
293 return (S26M);
294 else if (cdiff > 13000)
295 return (S24M);
296 else if (cdiff > 9000)
297 return (S19_2M);
298 else if (cdiff > 7600)
299 return (S13M);
300 else
301 return (S12M);
302 }
303
304 /******************************************************************************
305 * get_sys_clkin_sel() - returns the sys_clkin_sel field value based on
306 * -- input oscillator clock frequency.
307 *
308 *****************************************************************************/
309 void get_sys_clkin_sel(u32 osc_clk, u32 *sys_clkin_sel)
310 {
311 if(osc_clk == S38_4M)
312 *sys_clkin_sel= 4;
313 else if(osc_clk == S26M)
314 *sys_clkin_sel = 3;
315 else if(osc_clk == S19_2M)
316 *sys_clkin_sel = 2;
317 else if(osc_clk == S13M)
318 *sys_clkin_sel = 1;
319 else if(osc_clk == S12M)
320 *sys_clkin_sel = 0;
321 }
322
323 /******************************************************************************
324 * prcm_init() - inits clocks for PRCM as defined in clocks.h
325 * -- called from SRAM, or Flash (using temp SRAM stack).
326 *****************************************************************************/
327 void prcm_init(void)
328 {
329 u32 osc_clk=0, sys_clkin_sel;
330 dpll_param *dpll_param_p;
331 u32 clk_index, sil_index;
332
333 /* Gauge the input clock speed and find out the sys_clkin_sel
334 * value corresponding to the input clock.
335 */
336 osc_clk = get_osc_clk_speed();
337 get_sys_clkin_sel(osc_clk, &sys_clkin_sel);
338
339 sr32(PRM_CLKSEL, 0, 3, sys_clkin_sel); /* set input crystal speed */
340
341 /* If the input clock is greater than 19.2M always divide/2 */
342 if(sys_clkin_sel > 2) {
343 sr32(PRM_CLKSRC_CTRL, 6, 2, 2);/* input clock divider */
344 clk_index = sys_clkin_sel/2;
345 } else {
346 sr32(PRM_CLKSRC_CTRL, 6, 2, 1);/* input clock divider */
347 clk_index = sys_clkin_sel;
348 }
349
350 /* The DPLL tables are defined according to sysclk value and
351 * silicon revision. The clk_index value will be used to get
352 * the values for that input sysclk from the DPLL param table
353 * and sil_index will get the values for that SysClk for the
354 * appropriate silicon rev.
355 */
356 sil_index = get_cpu_rev() - 1;
357
358 /* Unlock MPU DPLL (slows things down, and needed later) */
359 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOW_POWER_BYPASS);
360 wait_on_value(BIT0, 0, CM_IDLEST_PLL_MPU, LDELAY);
361
362 /* Getting the base address of Core DPLL param table*/
363 dpll_param_p = (dpll_param *)get_core_dpll_param();
364 /* Moving it to the right sysclk and ES rev base */
365 dpll_param_p = dpll_param_p + 2*clk_index + sil_index;
366 /* CORE DPLL */
367 /* sr32(CM_CLKSEL2_EMU) set override to work when asleep */
368 sr32(CM_CLKEN_PLL, 0, 3, PLL_FAST_RELOCK_BYPASS);
369 wait_on_value(BIT0, 0, CM_IDLEST_CKGEN, LDELAY);
370 sr32(CM_CLKSEL1_EMU, 16, 5, CORE_M3X2); /* m3x2 */
371 sr32(CM_CLKSEL1_PLL, 27, 2, dpll_param_p->m2); /* Set M2 */
372 sr32(CM_CLKSEL1_PLL, 16, 11, dpll_param_p->m); /* Set M */
373 sr32(CM_CLKSEL1_PLL, 8, 7, dpll_param_p->n); /* Set N */
374 sr32(CM_CLKSEL1_PLL, 6, 1, 0); /* 96M Src */
375 sr32(CM_CLKSEL_CORE, 8, 4, CORE_SSI_DIV); /* ssi */
376 sr32(CM_CLKSEL_CORE, 4, 2, CORE_FUSB_DIV); /* fsusb */
377 sr32(CM_CLKSEL_CORE, 2, 2, CORE_L4_DIV); /* l4 */
378 sr32(CM_CLKSEL_CORE, 0, 2, CORE_L3_DIV); /* l3 */
379 sr32(CM_CLKSEL_GFX, 0, 3, GFX_DIV); /* gfx */
380 sr32(CM_CLKSEL_WKUP, 1, 2, WKUP_RSM); /* reset mgr */
381 sr32(CM_CLKEN_PLL, 4, 4, dpll_param_p->fsel); /* FREQSEL */
382 sr32(CM_CLKEN_PLL, 0, 3, PLL_LOCK); /* lock mode */
383 wait_on_value(BIT0, 1, CM_IDLEST_CKGEN, LDELAY);
384
385 /* Getting the base address to PER DPLL param table*/
386 dpll_param_p = (dpll_param *)get_per_dpll_param();
387 /* Moving it to the right sysclk base */
388 dpll_param_p = dpll_param_p + clk_index;
389 /* PER DPLL */
390 sr32(CM_CLKEN_PLL, 16, 3, PLL_STOP);
391 wait_on_value(BIT1, 0, CM_IDLEST_CKGEN, LDELAY);
392 sr32(CM_CLKSEL1_EMU, 24, 5, PER_M6X2); /* set M6 */
393 sr32(CM_CLKSEL_CAM, 0, 5, PER_M5X2); /* set M5 */
394 sr32(CM_CLKSEL_DSS, 0, 5, PER_M4X2); /* set M4 */
395 sr32(CM_CLKSEL_DSS, 8, 5, PER_M3X2); /* set M3 */
396 sr32(CM_CLKSEL3_PLL, 0, 5, dpll_param_p->m2); /* set M2 */
397 sr32(CM_CLKSEL2_PLL, 8, 11, dpll_param_p->m); /* set m */
398 sr32(CM_CLKSEL2_PLL, 0, 7, dpll_param_p->n); /* set n */
399 sr32(CM_CLKEN_PLL, 20, 4, dpll_param_p->fsel);/* FREQSEL */
400 sr32(CM_CLKEN_PLL, 16, 3, PLL_LOCK); /* lock mode */
401 wait_on_value(BIT1, 2, CM_IDLEST_CKGEN, LDELAY);
402
403 /* Getting the base address to MPU DPLL param table*/
404 dpll_param_p = (dpll_param *)get_mpu_dpll_param();
405 /* Moving it to the right sysclk and ES rev base */
406 dpll_param_p = dpll_param_p + 2*clk_index + sil_index;
407 /* MPU DPLL (unlocked already) */
408 sr32(CM_CLKSEL2_PLL_MPU, 0, 5, dpll_param_p->m2); /* Set M2 */
409 sr32(CM_CLKSEL1_PLL_MPU, 8, 11, dpll_param_p->m); /* Set M */
410 sr32(CM_CLKSEL1_PLL_MPU, 0, 7, dpll_param_p->n); /* Set N */
411 sr32(CM_CLKEN_PLL_MPU, 4, 4, dpll_param_p->fsel); /* FREQSEL */
412 sr32(CM_CLKEN_PLL_MPU, 0, 3, PLL_LOCK); /* lock mode */
413 wait_on_value(BIT0, 1, CM_IDLEST_PLL_MPU, LDELAY);
414
415 /* Getting the base address to IVA DPLL param table*/
416 dpll_param_p = (dpll_param *)get_iva_dpll_param();
417 /* Moving it to the right sysclk and ES rev base */
418 dpll_param_p = dpll_param_p + 2*clk_index + sil_index;
419 /* IVA DPLL (set to 12*20=240MHz) */
420 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_STOP);
421 wait_on_value(BIT0, 0, CM_IDLEST_PLL_IVA2, LDELAY);
422 sr32(CM_CLKSEL2_PLL_IVA2, 0, 5, dpll_param_p->m2); /* set M2 */
423 sr32(CM_CLKSEL1_PLL_IVA2, 8, 11, dpll_param_p->m); /* set M */
424 sr32(CM_CLKSEL1_PLL_IVA2, 0, 7, dpll_param_p->n); /* set N */
425 sr32(CM_CLKEN_PLL_IVA2, 4, 4, dpll_param_p->fsel); /* FREQSEL */
426 sr32(CM_CLKEN_PLL_IVA2, 0, 3, PLL_LOCK); /* lock mode */
427 wait_on_value(BIT0, 1, CM_IDLEST_PLL_IVA2, LDELAY);
428
429 /* Set up GPTimers to sys_clk source only */
430 sr32(CM_CLKSEL_PER, 0, 8, 0xff);
431 sr32(CM_CLKSEL_WKUP, 0, 1, 1);
432
433 delay(5000);
434 }
435
436 /*****************************************
437 * Routine: secure_unlock
438 * Description: Setup security registers for access
439 * (GP Device only)
440 *****************************************/
441 void secure_unlock(void)
442 {
443 /* Permission values for registers -Full fledged permissions to all */
444 #define UNLOCK_1 0xFFFFFFFF
445 #define UNLOCK_2 0x00000000
446 #define UNLOCK_3 0x0000FFFF
447 /* Protection Module Register Target APE (PM_RT)*/
448 __raw_writel(UNLOCK_1, RT_REQ_INFO_PERMISSION_1);
449 __raw_writel(UNLOCK_1, RT_READ_PERMISSION_0);
450 __raw_writel(UNLOCK_1, RT_WRITE_PERMISSION_0);
451 __raw_writel(UNLOCK_2, RT_ADDR_MATCH_1);
452
453 __raw_writel(UNLOCK_3, GPMC_REQ_INFO_PERMISSION_0);
454 __raw_writel(UNLOCK_3, GPMC_READ_PERMISSION_0);
455 __raw_writel(UNLOCK_3, GPMC_WRITE_PERMISSION_0);
456
457 __raw_writel(UNLOCK_3, OCM_REQ_INFO_PERMISSION_0);
458 __raw_writel(UNLOCK_3, OCM_READ_PERMISSION_0);
459 __raw_writel(UNLOCK_3, OCM_WRITE_PERMISSION_0);
460 __raw_writel(UNLOCK_2, OCM_ADDR_MATCH_2);
461
462 /* IVA Changes */
463 __raw_writel(UNLOCK_3, IVA2_REQ_INFO_PERMISSION_0);
464 __raw_writel(UNLOCK_3, IVA2_READ_PERMISSION_0);
465 __raw_writel(UNLOCK_3, IVA2_WRITE_PERMISSION_0);
466
467 __raw_writel(UNLOCK_1, SMS_RG_ATT0); /* SDRC region 0 public */
468 }
469
470 /**********************************************************
471 * Routine: try_unlock_sram()
472 * Description: If chip is GP type, unlock the SRAM for
473 * general use.
474 ***********************************************************/
475 void try_unlock_memory(void)
476 {
477 int mode;
478
479 /* if GP device unlock device SRAM for general use */
480 /* secure code breaks for Secure/Emulation device - HS/E/T*/
481 mode = get_device_type();
482 if (mode == GP_DEVICE) {
483 secure_unlock();
484 }
485 return;
486 }
487
488 /**********************************************************
489 * Routine: s_init
490 * Description: Does early system init of muxing and clocks.
491 * - Called at time when only stack is available.
492 **********************************************************/
493
494 void s_init(void)
495 {
496 watchdog_init();
497 #ifdef CONFIG_3430_AS_3410
498 /* setup the scalability control register for
499 * 3430 to work in 3410 mode
500 */
501 __raw_writel(0x5ABF,CONTROL_SCALABLE_OMAP_OCP);
502 #endif
503 try_unlock_memory();
504 set_muxconf_regs();
505 delay(100);
506 prcm_init();
507 per_clocks_enable();
508 config_3430sdram_ddr();
509 }
510
511 /*******************************************************
512 * Routine: misc_init_r
513 * Description: Init ethernet (done here so udelay works)
514 ********************************************************/
515 int misc_init_r (void)
516 {
517 return(0);
518 }
519
520 /******************************************************
521 * Routine: wait_for_command_complete
522 * Description: Wait for posting to finish on watchdog
523 ******************************************************/
524 void wait_for_command_complete(unsigned int wd_base)
525 {
526 int pending = 1;
527 do {
528 pending = __raw_readl(wd_base + WWPS);
529 } while (pending);
530 }
531
532 /****************************************
533 * Routine: watchdog_init
534 * Description: Shut down watch dogs
535 *****************************************/
536 void watchdog_init(void)
537 {
538 /* There are 3 watch dogs WD1=Secure, WD2=MPU, WD3=IVA. WD1 is
539 * either taken care of by ROM (HS/EMU) or not accessible (GP).
540 * We need to take care of WD2-MPU or take a PRCM reset. WD3
541 * should not be running and does not generate a PRCM reset.
542 */
543 sr32(CM_FCLKEN_WKUP, 5, 1, 1);
544 sr32(CM_ICLKEN_WKUP, 5, 1, 1);
545 wait_on_value(BIT5, 0x20, CM_IDLEST_WKUP, 5); /* some issue here */
546
547 __raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
548 wait_for_command_complete(WD2_BASE);
549 __raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
550 }
551
552 /**********************************************
553 * Routine: dram_init
554 * Description: sets uboots idea of sdram size
555 **********************************************/
556 int dram_init (void)
557 {
558 return 0;
559 }
560
561 /*****************************************************************
562 * Routine: peripheral_enable
563 * Description: Enable the clks & power for perifs (GPT2, UART1,...)
564 ******************************************************************/
565 void per_clocks_enable(void)
566 {
567 /* Enable GP2 timer. */
568 sr32(CM_CLKSEL_PER, 0, 1, 0x1); /* GPT2 = sys clk */
569 sr32(CM_ICLKEN_PER, 3, 1, 0x1); /* ICKen GPT2 */
570 sr32(CM_FCLKEN_PER, 3, 1, 0x1); /* FCKen GPT2 */
571
572 #ifdef CFG_NS16550
573 /* Enable UART1 clocks */
574 sr32(CM_FCLKEN1_CORE, 13, 1, 0x1);
575 sr32(CM_ICLKEN1_CORE, 13, 1, 0x1);
576 #endif
577 delay(1000);
578 }
579
580 /* Set MUX for UART, GPMC, SDRC, GPIO */
581
582 #define MUX_VAL(OFFSET,VALUE)\
583 __raw_writew((VALUE), OMAP34XX_CTRL_BASE + (OFFSET));
584
585 #define CP(x) (CONTROL_PADCONF_##x)
586 /*
587 * IEN - Input Enable
588 * IDIS - Input Disable
589 * PTD - Pull type Down
590 * PTU - Pull type Up
591 * DIS - Pull type selection is inactive
592 * EN - Pull type selection is active
593 * M0 - Mode 0
594 * The commented string gives the final mux configuration for that pin
595 */
596 #define MUX_DEFAULT()\
597 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\
598 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\
599 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\
600 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\
601 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\
602 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\
603 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\
604 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\
605 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\
606 MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\
607 MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\
608 MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\
609 MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\
610 MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\
611 MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\
612 MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\
613 MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\
614 MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\
615 MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\
616 MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\
617 MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\
618 MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\
619 MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\
620 MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\
621 MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\
622 MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\
623 MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\
624 MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\
625 MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\
626 MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\
627 MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\
628 MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\
629 MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\
630 MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\
631 MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\
632 MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\
633 MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\
634 MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\
635 MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\
636 MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\
637 MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\
638 MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\
639 MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\
640 MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\
641 MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\
642 MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\
643 MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\
644 MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\
645 MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\
646 MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\
647 MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\
648 MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\
649 MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\
650 MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\
651 MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\
652 MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\
653 MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\
654 MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\
655 MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\
656 MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\
657 MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\
658 MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\
659 MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\
660 MUX_VAL(CP(GPMC_nCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\
661 MUX_VAL(CP(GPMC_nCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\
662 MUX_VAL(CP(GPMC_nCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\
663 MUX_VAL(CP(GPMC_nCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\
664 MUX_VAL(CP(GPMC_nCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\
665 MUX_VAL(CP(GPMC_nCS5), (IDIS | PTU | EN | M0)) /*GPMC_nCS5*/\
666 MUX_VAL(CP(GPMC_nCS6), (IDIS | PTU | EN | M0)) /*GPMC_nCS6*/\
667 MUX_VAL(CP(GPMC_nCS7), (IDIS | PTU | EN | M0)) /*GPMC_nCS7*/\
668 MUX_VAL(CP(GPMC_CLK), (IDIS | PTD | DIS | M0)) /*GPMC_CLK*/\
669 MUX_VAL(CP(GPMC_nADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
670 MUX_VAL(CP(GPMC_nOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
671 MUX_VAL(CP(GPMC_nWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
672 MUX_VAL(CP(GPMC_nBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
673 MUX_VAL(CP(GPMC_nBE1), (IDIS | PTD | DIS | M4)) /*GPIO_61*/\
674 MUX_VAL(CP(GPMC_nWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\
675 MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\
676 MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\
677 MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M4)) /*GPIO_64*/\
678 MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)) /*GPIO_65*/\
679 MUX_VAL(CP(DSS_DATA18), (IEN | PTD | DIS | M4)) /*GPIO_88*/\
680 MUX_VAL(CP(DSS_DATA19), (IEN | PTD | DIS | M4)) /*GPIO_89*/\
681 MUX_VAL(CP(DSS_DATA20), (IEN | PTD | DIS | M4)) /*GPIO_90*/\
682 MUX_VAL(CP(DSS_DATA21), (IEN | PTD | DIS | M4)) /*GPIO_91*/\
683 MUX_VAL(CP(CAM_WEN), (IEN | PTD | DIS | M4)) /*GPIO_167*/\
684 MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
685 MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*UART1_RTS*/\
686 MUX_VAL(CP(UART1_CTS), (IEN | PTU | DIS | M0)) /*UART1_CTS*/\
687 MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\
688 MUX_VAL(CP(McBSP1_DX), (IEN | PTD | DIS | M4)) /*GPIO_158*/\
689 MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\
690 MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M4)) /*GPIO_2 */\
691 MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M4)) /*GPIO_3 */\
692 MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M4)) /*GPIO_4 */\
693 MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M4)) /*GPIO_5 */\
694 MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M4)) /*GPIO_6 */\
695 MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M4)) /*GPIO_7 */\
696 MUX_VAL(CP(SYS_BOOT6), (IEN | PTD | DIS | M4)) /*GPIO_8 */\
697 MUX_VAL(CP(SYS_CLKOUT2), (IEN | PTU | EN | M4)) /*GPIO_186*/\
698 MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0)) /*JTAG_nTRST*/\
699 MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0)) /*JTAG_TCK*/\
700 MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0)) /*JTAG_TMS*/\
701 MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0)) /*JTAG_TDI*/\
702 MUX_VAL(CP(JTAG_EMU0), (IEN | PTD | DIS | M0)) /*JTAG_EMU0*/\
703 MUX_VAL(CP(JTAG_EMU1), (IEN | PTD | DIS | M0)) /*JTAG_EMU1*/\
704 MUX_VAL(CP(ETK_CLK), (IEN | PTD | DIS | M4)) /*GPIO_12*/\
705 MUX_VAL(CP(ETK_CTL), (IEN | PTD | DIS | M4)) /*GPIO_13*/\
706 MUX_VAL(CP(ETK_D0 ), (IEN | PTD | DIS | M4)) /*GPIO_14*/\
707 MUX_VAL(CP(ETK_D1 ), (IEN | PTD | DIS | M4)) /*GPIO_15*/\
708 MUX_VAL(CP(ETK_D2 ), (IEN | PTD | DIS | M4)) /*GPIO_16*/\
709 MUX_VAL(CP(ETK_D10), (IEN | PTD | DIS | M4)) /*GPIO_24*/\
710 MUX_VAL(CP(ETK_D11), (IEN | PTD | DIS | M4)) /*GPIO_25*/\
711 MUX_VAL(CP(ETK_D12), (IEN | PTD | DIS | M4)) /*GPIO_26*/\
712 MUX_VAL(CP(ETK_D13), (IEN | PTD | DIS | M4)) /*GPIO_27*/\
713 MUX_VAL(CP(ETK_D14), (IEN | PTD | DIS | M4)) /*GPIO_28*/\
714 MUX_VAL(CP(ETK_D15), (IEN | PTD | DIS | M4)) /*GPIO_29*/
715
716 /**********************************************************
717 * Routine: set_muxconf_regs
718 * Description: Setting up the configuration Mux registers
719 * specific to the hardware. Many pins need
720 * to be moved from protect to primary mode.
721 *********************************************************/
722 void set_muxconf_regs(void)
723 {
724 MUX_DEFAULT();
725 }
726
727 /**********************************************************
728 * Routine: nand+_init
729 * Description: Set up nand for nand and jffs2 commands
730 *********************************************************/
731
732 int nand_init(void)
733 {
734 /* global settings */
735 __raw_writel(0x10, GPMC_SYSCONFIG); /* smart idle */
736 __raw_writel(0x0, GPMC_IRQENABLE); /* isr's sources masked */
737 __raw_writel(0, GPMC_TIMEOUT_CONTROL);/* timeout disable */
738
739 /* Set the GPMC Vals . For NAND boot on 3430SDP, NAND is mapped at CS0
740 * , NOR at CS1 and MPDB at CS3. And oneNAND boot, we map oneNAND at CS0.
741 * We configure only GPMC CS0 with required values. Configiring other devices
742 * at other CS in done in u-boot anyway. So we don't have to bother doing it here.
743 */
744 __raw_writel(0 , GPMC_CONFIG7 + GPMC_CONFIG_CS0);
745 delay(1000);
746
747 if ((get_mem_type() == GPMC_NAND) || (get_mem_type() == MMC_NAND)){
748 __raw_writel( M_NAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
749 __raw_writel( M_NAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
750 __raw_writel( M_NAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
751 __raw_writel( M_NAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
752 __raw_writel( M_NAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
753 __raw_writel( M_NAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
754
755 /* Enable the GPMC Mapping */
756 __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
757 ((NAND_BASE_ADR>>24) & 0x3F) |
758 (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
759 delay(2000);
760
761 if (nand_chip()){
762 #ifdef CFG_PRINTF
763 printf("Unsupported Chip!\n");
764 #endif
765 return 1;
766 }
767
768 }
769
770 if ((get_mem_type() == GPMC_ONENAND) || (get_mem_type() == MMC_ONENAND)){
771 __raw_writel( ONENAND_GPMC_CONFIG1, GPMC_CONFIG1 + GPMC_CONFIG_CS0);
772 __raw_writel( ONENAND_GPMC_CONFIG2, GPMC_CONFIG2 + GPMC_CONFIG_CS0);
773 __raw_writel( ONENAND_GPMC_CONFIG3, GPMC_CONFIG3 + GPMC_CONFIG_CS0);
774 __raw_writel( ONENAND_GPMC_CONFIG4, GPMC_CONFIG4 + GPMC_CONFIG_CS0);
775 __raw_writel( ONENAND_GPMC_CONFIG5, GPMC_CONFIG5 + GPMC_CONFIG_CS0);
776 __raw_writel( ONENAND_GPMC_CONFIG6, GPMC_CONFIG6 + GPMC_CONFIG_CS0);
777
778 /* Enable the GPMC Mapping */
779 __raw_writel(( ((OMAP34XX_GPMC_CS0_SIZE & 0xF)<<8) |
780 ((ONENAND_BASE>>24) & 0x3F) |
781 (1<<6) ), (GPMC_CONFIG7 + GPMC_CONFIG_CS0));
782 delay(2000);
783
784 if (onenand_chip()){
785 #ifdef CFG_PRINTF
786 printf("OneNAND Unsupported !\n");
787 #endif
788 return 1;
789 }
790 }
791 return 0;
792 }
793
794 /* optionally do something like blinking LED */
795 void board_hang (void)
796 { while (0) {};}
797
798 /******************************************************************************
799 * Dummy function to handle errors for EABI incompatibility
800 *****************************************************************************/
801 void raise(void)
802 {
803 }
804
805 /******************************************************************************
806 * Dummy function to handle errors for EABI incompatibility
807 *****************************************************************************/
808 void abort(void)
809 {
810 }
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