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spi-topcliff-pch: supports a spi mode setup and bit order setup by IO control
[zen-stable.git] / drivers / mmc / host / atmel-mci.c
blob3a57964b5e145630e6898fe8a0ba38b4ee08f61c
1 /*
2 * Atmel MultiMedia Card Interface driver
3 *
4 * Copyright (C) 2004-2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10 #include <linux/blkdev.h>
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
13 #include <linux/device.h>
14 #include <linux/dmaengine.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/err.h>
17 #include <linux/gpio.h>
18 #include <linux/init.h>
19 #include <linux/interrupt.h>
20 #include <linux/ioport.h>
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/scatterlist.h>
24 #include <linux/seq_file.h>
25 #include <linux/slab.h>
26 #include <linux/stat.h>
27
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/sdio.h>
30
31 #include <mach/atmel-mci.h>
32 #include <linux/atmel-mci.h>
33 #include <linux/atmel_pdc.h>
34
35 #include <asm/io.h>
36 #include <asm/unaligned.h>
37
38 #include <mach/cpu.h>
39 #include <mach/board.h>
40
41 #include "atmel-mci-regs.h"
42
43 #define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
44 #define ATMCI_DMA_THRESHOLD 16
45
46 enum {
47 EVENT_CMD_COMPLETE = 0,
48 EVENT_XFER_COMPLETE,
49 EVENT_DATA_COMPLETE,
50 EVENT_DATA_ERROR,
51 };
52
53 enum atmel_mci_state {
54 STATE_IDLE = 0,
55 STATE_SENDING_CMD,
56 STATE_SENDING_DATA,
57 STATE_DATA_BUSY,
58 STATE_SENDING_STOP,
59 STATE_DATA_ERROR,
60 };
61
62 enum atmci_xfer_dir {
63 XFER_RECEIVE = 0,
64 XFER_TRANSMIT,
65 };
66
67 enum atmci_pdc_buf {
68 PDC_FIRST_BUF = 0,
69 PDC_SECOND_BUF,
70 };
71
72 struct atmel_mci_caps {
73 bool has_dma;
74 bool has_pdc;
75 bool has_cfg_reg;
76 bool has_cstor_reg;
77 bool has_highspeed;
78 bool has_rwproof;
79 };
80
81 struct atmel_mci_dma {
82 struct dma_chan *chan;
83 struct dma_async_tx_descriptor *data_desc;
84 };
85
86 /**
87 * struct atmel_mci - MMC controller state shared between all slots
88 * @lock: Spinlock protecting the queue and associated data.
89 * @regs: Pointer to MMIO registers.
90 * @sg: Scatterlist entry currently being processed by PIO or PDC code.
91 * @pio_offset: Offset into the current scatterlist entry.
92 * @cur_slot: The slot which is currently using the controller.
93 * @mrq: The request currently being processed on @cur_slot,
94 * or NULL if the controller is idle.
95 * @cmd: The command currently being sent to the card, or NULL.
96 * @data: The data currently being transferred, or NULL if no data
97 * transfer is in progress.
98 * @data_size: just data->blocks * data->blksz.
99 * @dma: DMA client state.
100 * @data_chan: DMA channel being used for the current data transfer.
101 * @cmd_status: Snapshot of SR taken upon completion of the current
102 * command. Only valid when EVENT_CMD_COMPLETE is pending.
103 * @data_status: Snapshot of SR taken upon completion of the current
104 * data transfer. Only valid when EVENT_DATA_COMPLETE or
105 * EVENT_DATA_ERROR is pending.
106 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
107 * to be sent.
108 * @tasklet: Tasklet running the request state machine.
109 * @pending_events: Bitmask of events flagged by the interrupt handler
110 * to be processed by the tasklet.
111 * @completed_events: Bitmask of events which the state machine has
112 * processed.
113 * @state: Tasklet state.
114 * @queue: List of slots waiting for access to the controller.
115 * @need_clock_update: Update the clock rate before the next request.
116 * @need_reset: Reset controller before next request.
117 * @mode_reg: Value of the MR register.
118 * @cfg_reg: Value of the CFG register.
119 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
120 * rate and timeout calculations.
121 * @mapbase: Physical address of the MMIO registers.
122 * @mck: The peripheral bus clock hooked up to the MMC controller.
123 * @pdev: Platform device associated with the MMC controller.
124 * @slot: Slots sharing this MMC controller.
125 * @caps: MCI capabilities depending on MCI version.
126 * @prepare_data: function to setup MCI before data transfer which
127 * depends on MCI capabilities.
128 * @submit_data: function to start data transfer which depends on MCI
129 * capabilities.
130 * @stop_transfer: function to stop data transfer which depends on MCI
131 * capabilities.
132 *
133 * Locking
134 * =======
135 *
136 * @lock is a softirq-safe spinlock protecting @queue as well as
137 * @cur_slot, @mrq and @state. These must always be updated
138 * at the same time while holding @lock.
139 *
140 * @lock also protects mode_reg and need_clock_update since these are
141 * used to synchronize mode register updates with the queue
142 * processing.
143 *
144 * The @mrq field of struct atmel_mci_slot is also protected by @lock,
145 * and must always be written at the same time as the slot is added to
146 * @queue.
147 *
148 * @pending_events and @completed_events are accessed using atomic bit
149 * operations, so they don't need any locking.
150 *
151 * None of the fields touched by the interrupt handler need any
152 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
153 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
154 * interrupts must be disabled and @data_status updated with a
155 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
156 * CMDRDY interrupt must be disabled and @cmd_status updated with a
157 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
158 * bytes_xfered field of @data must be written. This is ensured by
159 * using barriers.
160 */
161 struct atmel_mci {
162 spinlock_t lock;
163 void __iomem *regs;
164
165 struct scatterlist *sg;
166 unsigned int pio_offset;
167
168 struct atmel_mci_slot *cur_slot;
169 struct mmc_request *mrq;
170 struct mmc_command *cmd;
171 struct mmc_data *data;
172 unsigned int data_size;
173
174 struct atmel_mci_dma dma;
175 struct dma_chan *data_chan;
176
177 u32 cmd_status;
178 u32 data_status;
179 u32 stop_cmdr;
180
181 struct tasklet_struct tasklet;
182 unsigned long pending_events;
183 unsigned long completed_events;
184 enum atmel_mci_state state;
185 struct list_head queue;
186
187 bool need_clock_update;
188 bool need_reset;
189 u32 mode_reg;
190 u32 cfg_reg;
191 unsigned long bus_hz;
192 unsigned long mapbase;
193 struct clk *mck;
194 struct platform_device *pdev;
195
196 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
197
198 struct atmel_mci_caps caps;
199
200 u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
201 void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
202 void (*stop_transfer)(struct atmel_mci *host);
203 };
204
205 /**
206 * struct atmel_mci_slot - MMC slot state
207 * @mmc: The mmc_host representing this slot.
208 * @host: The MMC controller this slot is using.
209 * @sdc_reg: Value of SDCR to be written before using this slot.
210 * @sdio_irq: SDIO irq mask for this slot.
211 * @mrq: mmc_request currently being processed or waiting to be
212 * processed, or NULL when the slot is idle.
213 * @queue_node: List node for placing this node in the @queue list of
214 * &struct atmel_mci.
215 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
216 * @flags: Random state bits associated with the slot.
217 * @detect_pin: GPIO pin used for card detection, or negative if not
218 * available.
219 * @wp_pin: GPIO pin used for card write protect sending, or negative
220 * if not available.
221 * @detect_is_active_high: The state of the detect pin when it is active.
222 * @detect_timer: Timer used for debouncing @detect_pin interrupts.
223 */
224 struct atmel_mci_slot {
225 struct mmc_host *mmc;
226 struct atmel_mci *host;
227
228 u32 sdc_reg;
229 u32 sdio_irq;
230
231 struct mmc_request *mrq;
232 struct list_head queue_node;
233
234 unsigned int clock;
235 unsigned long flags;
236 #define ATMCI_CARD_PRESENT 0
237 #define ATMCI_CARD_NEED_INIT 1
238 #define ATMCI_SHUTDOWN 2
239 #define ATMCI_SUSPENDED 3
240
241 int detect_pin;
242 int wp_pin;
243 bool detect_is_active_high;
244
245 struct timer_list detect_timer;
246 };
247
248 #define atmci_test_and_clear_pending(host, event) \
249 test_and_clear_bit(event, &host->pending_events)
250 #define atmci_set_completed(host, event) \
251 set_bit(event, &host->completed_events)
252 #define atmci_set_pending(host, event) \
253 set_bit(event, &host->pending_events)
254
255 /*
256 * The debugfs stuff below is mostly optimized away when
257 * CONFIG_DEBUG_FS is not set.
258 */
259 static int atmci_req_show(struct seq_file *s, void *v)
260 {
261 struct atmel_mci_slot *slot = s->private;
262 struct mmc_request *mrq;
263 struct mmc_command *cmd;
264 struct mmc_command *stop;
265 struct mmc_data *data;
266
267 /* Make sure we get a consistent snapshot */
268 spin_lock_bh(&slot->host->lock);
269 mrq = slot->mrq;
270
271 if (mrq) {
272 cmd = mrq->cmd;
273 data = mrq->data;
274 stop = mrq->stop;
275
276 if (cmd)
277 seq_printf(s,
278 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
279 cmd->opcode, cmd->arg, cmd->flags,
280 cmd->resp[0], cmd->resp[1], cmd->resp[2],
281 cmd->resp[3], cmd->error);
282 if (data)
283 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
284 data->bytes_xfered, data->blocks,
285 data->blksz, data->flags, data->error);
286 if (stop)
287 seq_printf(s,
288 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
289 stop->opcode, stop->arg, stop->flags,
290 stop->resp[0], stop->resp[1], stop->resp[2],
291 stop->resp[3], stop->error);
292 }
293
294 spin_unlock_bh(&slot->host->lock);
295
296 return 0;
297 }
298
299 static int atmci_req_open(struct inode *inode, struct file *file)
300 {
301 return single_open(file, atmci_req_show, inode->i_private);
302 }
303
304 static const struct file_operations atmci_req_fops = {
305 .owner = THIS_MODULE,
306 .open = atmci_req_open,
307 .read = seq_read,
308 .llseek = seq_lseek,
309 .release = single_release,
310 };
311
312 static void atmci_show_status_reg(struct seq_file *s,
313 const char *regname, u32 value)
314 {
315 static const char *sr_bit[] = {
316 [0] = "CMDRDY",
317 [1] = "RXRDY",
318 [2] = "TXRDY",
319 [3] = "BLKE",
320 [4] = "DTIP",
321 [5] = "NOTBUSY",
322 [6] = "ENDRX",
323 [7] = "ENDTX",
324 [8] = "SDIOIRQA",
325 [9] = "SDIOIRQB",
326 [12] = "SDIOWAIT",
327 [14] = "RXBUFF",
328 [15] = "TXBUFE",
329 [16] = "RINDE",
330 [17] = "RDIRE",
331 [18] = "RCRCE",
332 [19] = "RENDE",
333 [20] = "RTOE",
334 [21] = "DCRCE",
335 [22] = "DTOE",
336 [23] = "CSTOE",
337 [24] = "BLKOVRE",
338 [25] = "DMADONE",
339 [26] = "FIFOEMPTY",
340 [27] = "XFRDONE",
341 [30] = "OVRE",
342 [31] = "UNRE",
343 };
344 unsigned int i;
345
346 seq_printf(s, "%s:\t0x%08x", regname, value);
347 for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
348 if (value & (1 << i)) {
349 if (sr_bit[i])
350 seq_printf(s, " %s", sr_bit[i]);
351 else
352 seq_puts(s, " UNKNOWN");
353 }
354 }
355 seq_putc(s, '\n');
356 }
357
358 static int atmci_regs_show(struct seq_file *s, void *v)
359 {
360 struct atmel_mci *host = s->private;
361 u32 *buf;
362
363 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
364 if (!buf)
365 return -ENOMEM;
366
367 /*
368 * Grab a more or less consistent snapshot. Note that we're
369 * not disabling interrupts, so IMR and SR may not be
370 * consistent.
371 */
372 spin_lock_bh(&host->lock);
373 clk_enable(host->mck);
374 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
375 clk_disable(host->mck);
376 spin_unlock_bh(&host->lock);
377
378 seq_printf(s, "MR:\t0x%08x%s%s CLKDIV=%u\n",
379 buf[ATMCI_MR / 4],
380 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
381 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "",
382 buf[ATMCI_MR / 4] & 0xff);
383 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
384 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
385 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
386 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
387 buf[ATMCI_BLKR / 4],
388 buf[ATMCI_BLKR / 4] & 0xffff,
389 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
390 if (host->caps.has_cstor_reg)
391 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
392
393 /* Don't read RSPR and RDR; it will consume the data there */
394
395 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
396 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
397
398 if (host->caps.has_dma) {
399 u32 val;
400
401 val = buf[ATMCI_DMA / 4];
402 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
403 val, val & 3,
404 ((val >> 4) & 3) ?
405 1 << (((val >> 4) & 3) + 1) : 1,
406 val & ATMCI_DMAEN ? " DMAEN" : "");
407 }
408 if (host->caps.has_cfg_reg) {
409 u32 val;
410
411 val = buf[ATMCI_CFG / 4];
412 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
413 val,
414 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
415 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
416 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
417 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
418 }
419
420 kfree(buf);
421
422 return 0;
423 }
424
425 static int atmci_regs_open(struct inode *inode, struct file *file)
426 {
427 return single_open(file, atmci_regs_show, inode->i_private);
428 }
429
430 static const struct file_operations atmci_regs_fops = {
431 .owner = THIS_MODULE,
432 .open = atmci_regs_open,
433 .read = seq_read,
434 .llseek = seq_lseek,
435 .release = single_release,
436 };
437
438 static void atmci_init_debugfs(struct atmel_mci_slot *slot)
439 {
440 struct mmc_host *mmc = slot->mmc;
441 struct atmel_mci *host = slot->host;
442 struct dentry *root;
443 struct dentry *node;
444
445 root = mmc->debugfs_root;
446 if (!root)
447 return;
448
449 node = debugfs_create_file("regs", S_IRUSR, root, host,
450 &atmci_regs_fops);
451 if (IS_ERR(node))
452 return;
453 if (!node)
454 goto err;
455
456 node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
457 if (!node)
458 goto err;
459
460 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
461 if (!node)
462 goto err;
463
464 node = debugfs_create_x32("pending_events", S_IRUSR, root,
465 (u32 *)&host->pending_events);
466 if (!node)
467 goto err;
468
469 node = debugfs_create_x32("completed_events", S_IRUSR, root,
470 (u32 *)&host->completed_events);
471 if (!node)
472 goto err;
473
474 return;
475
476 err:
477 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
478 }
479
480 static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
481 unsigned int ns)
482 {
483 /*
484 * It is easier here to use us instead of ns for the timeout,
485 * it prevents from overflows during calculation.
486 */
487 unsigned int us = DIV_ROUND_UP(ns, 1000);
488
489 /* Maximum clock frequency is host->bus_hz/2 */
490 return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
491 }
492
493 static void atmci_set_timeout(struct atmel_mci *host,
494 struct atmel_mci_slot *slot, struct mmc_data *data)
495 {
496 static unsigned dtomul_to_shift[] = {
497 0, 4, 7, 8, 10, 12, 16, 20
498 };
499 unsigned timeout;
500 unsigned dtocyc;
501 unsigned dtomul;
502
503 timeout = atmci_ns_to_clocks(host, data->timeout_ns)
504 + data->timeout_clks;
505
506 for (dtomul = 0; dtomul < 8; dtomul++) {
507 unsigned shift = dtomul_to_shift[dtomul];
508 dtocyc = (timeout + (1 << shift) - 1) >> shift;
509 if (dtocyc < 15)
510 break;
511 }
512
513 if (dtomul >= 8) {
514 dtomul = 7;
515 dtocyc = 15;
516 }
517
518 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
519 dtocyc << dtomul_to_shift[dtomul]);
520 atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
521 }
522
523 /*
524 * Return mask with command flags to be enabled for this command.
525 */
526 static u32 atmci_prepare_command(struct mmc_host *mmc,
527 struct mmc_command *cmd)
528 {
529 struct mmc_data *data;
530 u32 cmdr;
531
532 cmd->error = -EINPROGRESS;
533
534 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
535
536 if (cmd->flags & MMC_RSP_PRESENT) {
537 if (cmd->flags & MMC_RSP_136)
538 cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
539 else
540 cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
541 }
542
543 /*
544 * This should really be MAXLAT_5 for CMD2 and ACMD41, but
545 * it's too difficult to determine whether this is an ACMD or
546 * not. Better make it 64.
547 */
548 cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
549
550 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
551 cmdr |= ATMCI_CMDR_OPDCMD;
552
553 data = cmd->data;
554 if (data) {
555 cmdr |= ATMCI_CMDR_START_XFER;
556
557 if (cmd->opcode == SD_IO_RW_EXTENDED) {
558 cmdr |= ATMCI_CMDR_SDIO_BLOCK;
559 } else {
560 if (data->flags & MMC_DATA_STREAM)
561 cmdr |= ATMCI_CMDR_STREAM;
562 else if (data->blocks > 1)
563 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
564 else
565 cmdr |= ATMCI_CMDR_BLOCK;
566 }
567
568 if (data->flags & MMC_DATA_READ)
569 cmdr |= ATMCI_CMDR_TRDIR_READ;
570 }
571
572 return cmdr;
573 }
574
575 static void atmci_send_command(struct atmel_mci *host,
576 struct mmc_command *cmd, u32 cmd_flags)
577 {
578 WARN_ON(host->cmd);
579 host->cmd = cmd;
580
581 dev_vdbg(&host->pdev->dev,
582 "start command: ARGR=0x%08x CMDR=0x%08x\n",
583 cmd->arg, cmd_flags);
584
585 atmci_writel(host, ATMCI_ARGR, cmd->arg);
586 atmci_writel(host, ATMCI_CMDR, cmd_flags);
587 }
588
589 static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
590 {
591 atmci_send_command(host, data->stop, host->stop_cmdr);
592 atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
593 }
594
595 /*
596 * Configure given PDC buffer taking care of alignement issues.
597 * Update host->data_size and host->sg.
598 */
599 static void atmci_pdc_set_single_buf(struct atmel_mci *host,
600 enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
601 {
602 u32 pointer_reg, counter_reg;
603
604 if (dir == XFER_RECEIVE) {
605 pointer_reg = ATMEL_PDC_RPR;
606 counter_reg = ATMEL_PDC_RCR;
607 } else {
608 pointer_reg = ATMEL_PDC_TPR;
609 counter_reg = ATMEL_PDC_TCR;
610 }
611
612 if (buf_nb == PDC_SECOND_BUF) {
613 pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
614 counter_reg += ATMEL_PDC_SCND_BUF_OFF;
615 }
616
617 atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
618 if (host->data_size <= sg_dma_len(host->sg)) {
619 if (host->data_size & 0x3) {
620 /* If size is different from modulo 4, transfer bytes */
621 atmci_writel(host, counter_reg, host->data_size);
622 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
623 } else {
624 /* Else transfer 32-bits words */
625 atmci_writel(host, counter_reg, host->data_size / 4);
626 }
627 host->data_size = 0;
628 } else {
629 /* We assume the size of a page is 32-bits aligned */
630 atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
631 host->data_size -= sg_dma_len(host->sg);
632 if (host->data_size)
633 host->sg = sg_next(host->sg);
634 }
635 }
636
637 /*
638 * Configure PDC buffer according to the data size ie configuring one or two
639 * buffers. Don't use this function if you want to configure only the second
640 * buffer. In this case, use atmci_pdc_set_single_buf.
641 */
642 static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
643 {
644 atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
645 if (host->data_size)
646 atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
647 }
648
649 /*
650 * Unmap sg lists, called when transfer is finished.
651 */
652 static void atmci_pdc_cleanup(struct atmel_mci *host)
653 {
654 struct mmc_data *data = host->data;
655
656 if (data)
657 dma_unmap_sg(&host->pdev->dev,
658 data->sg, data->sg_len,
659 ((data->flags & MMC_DATA_WRITE)
660 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
661 }
662
663 /*
664 * Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
665 * having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
666 * interrupt needed for both transfer directions.
667 */
668 static void atmci_pdc_complete(struct atmel_mci *host)
669 {
670 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
671 atmci_pdc_cleanup(host);
672
673 /*
674 * If the card was removed, data will be NULL. No point trying
675 * to send the stop command or waiting for NBUSY in this case.
676 */
677 if (host->data) {
678 atmci_set_pending(host, EVENT_XFER_COMPLETE);
679 tasklet_schedule(&host->tasklet);
680 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
681 }
682 }
683
684 static void atmci_dma_cleanup(struct atmel_mci *host)
685 {
686 struct mmc_data *data = host->data;
687
688 if (data)
689 dma_unmap_sg(host->dma.chan->device->dev,
690 data->sg, data->sg_len,
691 ((data->flags & MMC_DATA_WRITE)
692 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
693 }
694
695 /*
696 * This function is called by the DMA driver from tasklet context.
697 */
698 static void atmci_dma_complete(void *arg)
699 {
700 struct atmel_mci *host = arg;
701 struct mmc_data *data = host->data;
702
703 dev_vdbg(&host->pdev->dev, "DMA complete\n");
704
705 if (host->caps.has_dma)
706 /* Disable DMA hardware handshaking on MCI */
707 atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
708
709 atmci_dma_cleanup(host);
710
711 /*
712 * If the card was removed, data will be NULL. No point trying
713 * to send the stop command or waiting for NBUSY in this case.
714 */
715 if (data) {
716 atmci_set_pending(host, EVENT_XFER_COMPLETE);
717 tasklet_schedule(&host->tasklet);
718
719 /*
720 * Regardless of what the documentation says, we have
721 * to wait for NOTBUSY even after block read
722 * operations.
723 *
724 * When the DMA transfer is complete, the controller
725 * may still be reading the CRC from the card, i.e.
726 * the data transfer is still in progress and we
727 * haven't seen all the potential error bits yet.
728 *
729 * The interrupt handler will schedule a different
730 * tasklet to finish things up when the data transfer
731 * is completely done.
732 *
733 * We may not complete the mmc request here anyway
734 * because the mmc layer may call back and cause us to
735 * violate the "don't submit new operations from the
736 * completion callback" rule of the dma engine
737 * framework.
738 */
739 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
740 }
741 }
742
743 /*
744 * Returns a mask of interrupt flags to be enabled after the whole
745 * request has been prepared.
746 */
747 static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
748 {
749 u32 iflags;
750
751 data->error = -EINPROGRESS;
752
753 host->sg = data->sg;
754 host->data = data;
755 host->data_chan = NULL;
756
757 iflags = ATMCI_DATA_ERROR_FLAGS;
758
759 /*
760 * Errata: MMC data write operation with less than 12
761 * bytes is impossible.
762 *
763 * Errata: MCI Transmit Data Register (TDR) FIFO
764 * corruption when length is not multiple of 4.
765 */
766 if (data->blocks * data->blksz < 12
767 || (data->blocks * data->blksz) & 3)
768 host->need_reset = true;
769
770 host->pio_offset = 0;
771 if (data->flags & MMC_DATA_READ)
772 iflags |= ATMCI_RXRDY;
773 else
774 iflags |= ATMCI_TXRDY;
775
776 return iflags;
777 }
778
779 /*
780 * Set interrupt flags and set block length into the MCI mode register even
781 * if this value is also accessible in the MCI block register. It seems to be
782 * necessary before the High Speed MCI version. It also map sg and configure
783 * PDC registers.
784 */
785 static u32
786 atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
787 {
788 u32 iflags, tmp;
789 unsigned int sg_len;
790 enum dma_data_direction dir;
791
792 data->error = -EINPROGRESS;
793
794 host->data = data;
795 host->sg = data->sg;
796 iflags = ATMCI_DATA_ERROR_FLAGS;
797
798 /* Enable pdc mode */
799 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
800
801 if (data->flags & MMC_DATA_READ) {
802 dir = DMA_FROM_DEVICE;
803 iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
804 } else {
805 dir = DMA_TO_DEVICE;
806 iflags |= ATMCI_ENDTX | ATMCI_TXBUFE;
807 }
808
809 /* Set BLKLEN */
810 tmp = atmci_readl(host, ATMCI_MR);
811 tmp &= 0x0000ffff;
812 tmp |= ATMCI_BLKLEN(data->blksz);
813 atmci_writel(host, ATMCI_MR, tmp);
814
815 /* Configure PDC */
816 host->data_size = data->blocks * data->blksz;
817 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, dir);
818 if (host->data_size)
819 atmci_pdc_set_both_buf(host,
820 ((dir == DMA_FROM_DEVICE) ? XFER_RECEIVE : XFER_TRANSMIT));
821
822 return iflags;
823 }
824
825 static u32
826 atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
827 {
828 struct dma_chan *chan;
829 struct dma_async_tx_descriptor *desc;
830 struct scatterlist *sg;
831 unsigned int i;
832 enum dma_data_direction direction;
833 enum dma_transfer_direction slave_dirn;
834 unsigned int sglen;
835 u32 iflags;
836
837 data->error = -EINPROGRESS;
838
839 WARN_ON(host->data);
840 host->sg = NULL;
841 host->data = data;
842
843 iflags = ATMCI_DATA_ERROR_FLAGS;
844
845 /*
846 * We don't do DMA on "complex" transfers, i.e. with
847 * non-word-aligned buffers or lengths. Also, we don't bother
848 * with all the DMA setup overhead for short transfers.
849 */
850 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
851 return atmci_prepare_data(host, data);
852 if (data->blksz & 3)
853 return atmci_prepare_data(host, data);
854
855 for_each_sg(data->sg, sg, data->sg_len, i) {
856 if (sg->offset & 3 || sg->length & 3)
857 return atmci_prepare_data(host, data);
858 }
859
860 /* If we don't have a channel, we can't do DMA */
861 chan = host->dma.chan;
862 if (chan)
863 host->data_chan = chan;
864
865 if (!chan)
866 return -ENODEV;
867
868 if (host->caps.has_dma)
869 atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(3) | ATMCI_DMAEN);
870
871 if (data->flags & MMC_DATA_READ) {
872 direction = DMA_FROM_DEVICE;
873 slave_dirn = DMA_DEV_TO_MEM;
874 } else {
875 direction = DMA_TO_DEVICE;
876 slave_dirn = DMA_MEM_TO_DEV;
877 }
878
879 sglen = dma_map_sg(chan->device->dev, data->sg,
880 data->sg_len, direction);
881
882 desc = chan->device->device_prep_slave_sg(chan,
883 data->sg, sglen, slave_dirn,
884 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
885 if (!desc)
886 goto unmap_exit;
887
888 host->dma.data_desc = desc;
889 desc->callback = atmci_dma_complete;
890 desc->callback_param = host;
891
892 return iflags;
893 unmap_exit:
894 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, direction);
895 return -ENOMEM;
896 }
897
898 static void
899 atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
900 {
901 return;
902 }
903
904 /*
905 * Start PDC according to transfer direction.
906 */
907 static void
908 atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
909 {
910 if (data->flags & MMC_DATA_READ)
911 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
912 else
913 atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
914 }
915
916 static void
917 atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
918 {
919 struct dma_chan *chan = host->data_chan;
920 struct dma_async_tx_descriptor *desc = host->dma.data_desc;
921
922 if (chan) {
923 dmaengine_submit(desc);
924 dma_async_issue_pending(chan);
925 }
926 }
927
928 static void atmci_stop_transfer(struct atmel_mci *host)
929 {
930 atmci_set_pending(host, EVENT_XFER_COMPLETE);
931 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
932 }
933
934 /*
935 * Stop data transfer because error(s) occured.
936 */
937 static void atmci_stop_transfer_pdc(struct atmel_mci *host)
938 {
939 atmci_set_pending(host, EVENT_XFER_COMPLETE);
940 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
941 }
942
943 static void atmci_stop_transfer_dma(struct atmel_mci *host)
944 {
945 struct dma_chan *chan = host->data_chan;
946
947 if (chan) {
948 dmaengine_terminate_all(chan);
949 atmci_dma_cleanup(host);
950 } else {
951 /* Data transfer was stopped by the interrupt handler */
952 atmci_set_pending(host, EVENT_XFER_COMPLETE);
953 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
954 }
955 }
956
957 /*
958 * Start a request: prepare data if needed, prepare the command and activate
959 * interrupts.
960 */
961 static void atmci_start_request(struct atmel_mci *host,
962 struct atmel_mci_slot *slot)
963 {
964 struct mmc_request *mrq;
965 struct mmc_command *cmd;
966 struct mmc_data *data;
967 u32 iflags;
968 u32 cmdflags;
969
970 mrq = slot->mrq;
971 host->cur_slot = slot;
972 host->mrq = mrq;
973
974 host->pending_events = 0;
975 host->completed_events = 0;
976 host->data_status = 0;
977
978 if (host->need_reset) {
979 iflags = atmci_readl(host, ATMCI_IMR);
980 iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
981 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
982 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
983 atmci_writel(host, ATMCI_MR, host->mode_reg);
984 if (host->caps.has_cfg_reg)
985 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
986 atmci_writel(host, ATMCI_IER, iflags);
987 host->need_reset = false;
988 }
989 atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
990
991 iflags = atmci_readl(host, ATMCI_IMR);
992 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
993 dev_warn(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
994 iflags);
995
996 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
997 /* Send init sequence (74 clock cycles) */
998 atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
999 while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
1000 cpu_relax();
1001 }
1002 iflags = 0;
1003 data = mrq->data;
1004 if (data) {
1005 atmci_set_timeout(host, slot, data);
1006
1007 /* Must set block count/size before sending command */
1008 atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
1009 | ATMCI_BLKLEN(data->blksz));
1010 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
1011 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
1012
1013 iflags |= host->prepare_data(host, data);
1014 }
1015
1016 iflags |= ATMCI_CMDRDY;
1017 cmd = mrq->cmd;
1018 cmdflags = atmci_prepare_command(slot->mmc, cmd);
1019 atmci_send_command(host, cmd, cmdflags);
1020
1021 if (data)
1022 host->submit_data(host, data);
1023
1024 if (mrq->stop) {
1025 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
1026 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
1027 if (!(data->flags & MMC_DATA_WRITE))
1028 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
1029 if (data->flags & MMC_DATA_STREAM)
1030 host->stop_cmdr |= ATMCI_CMDR_STREAM;
1031 else
1032 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
1033 }
1034
1035 /*
1036 * We could have enabled interrupts earlier, but I suspect
1037 * that would open up a nice can of interesting race
1038 * conditions (e.g. command and data complete, but stop not
1039 * prepared yet.)
1040 */
1041 atmci_writel(host, ATMCI_IER, iflags);
1042 }
1043
1044 static void atmci_queue_request(struct atmel_mci *host,
1045 struct atmel_mci_slot *slot, struct mmc_request *mrq)
1046 {
1047 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1048 host->state);
1049
1050 spin_lock_bh(&host->lock);
1051 slot->mrq = mrq;
1052 if (host->state == STATE_IDLE) {
1053 host->state = STATE_SENDING_CMD;
1054 atmci_start_request(host, slot);
1055 } else {
1056 list_add_tail(&slot->queue_node, &host->queue);
1057 }
1058 spin_unlock_bh(&host->lock);
1059 }
1060
1061 static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1062 {
1063 struct atmel_mci_slot *slot = mmc_priv(mmc);
1064 struct atmel_mci *host = slot->host;
1065 struct mmc_data *data;
1066
1067 WARN_ON(slot->mrq);
1068
1069 /*
1070 * We may "know" the card is gone even though there's still an
1071 * electrical connection. If so, we really need to communicate
1072 * this to the MMC core since there won't be any more
1073 * interrupts as the card is completely removed. Otherwise,
1074 * the MMC core might believe the card is still there even
1075 * though the card was just removed very slowly.
1076 */
1077 if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
1078 mrq->cmd->error = -ENOMEDIUM;
1079 mmc_request_done(mmc, mrq);
1080 return;
1081 }
1082
1083 /* We don't support multiple blocks of weird lengths. */
1084 data = mrq->data;
1085 if (data && data->blocks > 1 && data->blksz & 3) {
1086 mrq->cmd->error = -EINVAL;
1087 mmc_request_done(mmc, mrq);
1088 }
1089
1090 atmci_queue_request(host, slot, mrq);
1091 }
1092
1093 static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1094 {
1095 struct atmel_mci_slot *slot = mmc_priv(mmc);
1096 struct atmel_mci *host = slot->host;
1097 unsigned int i;
1098
1099 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
1100 switch (ios->bus_width) {
1101 case MMC_BUS_WIDTH_1:
1102 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
1103 break;
1104 case MMC_BUS_WIDTH_4:
1105 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
1106 break;
1107 }
1108
1109 if (ios->clock) {
1110 unsigned int clock_min = ~0U;
1111 u32 clkdiv;
1112
1113 spin_lock_bh(&host->lock);
1114 if (!host->mode_reg) {
1115 clk_enable(host->mck);
1116 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1117 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1118 if (host->caps.has_cfg_reg)
1119 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1120 }
1121
1122 /*
1123 * Use mirror of ios->clock to prevent race with mmc
1124 * core ios update when finding the minimum.
1125 */
1126 slot->clock = ios->clock;
1127 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1128 if (host->slot[i] && host->slot[i]->clock
1129 && host->slot[i]->clock < clock_min)
1130 clock_min = host->slot[i]->clock;
1131 }
1132
1133 /* Calculate clock divider */
1134 clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
1135 if (clkdiv > 255) {
1136 dev_warn(&mmc->class_dev,
1137 "clock %u too slow; using %lu\n",
1138 clock_min, host->bus_hz / (2 * 256));
1139 clkdiv = 255;
1140 }
1141
1142 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
1143
1144 /*
1145 * WRPROOF and RDPROOF prevent overruns/underruns by
1146 * stopping the clock when the FIFO is full/empty.
1147 * This state is not expected to last for long.
1148 */
1149 if (host->caps.has_rwproof)
1150 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
1151
1152 if (host->caps.has_cfg_reg) {
1153 /* setup High Speed mode in relation with card capacity */
1154 if (ios->timing == MMC_TIMING_SD_HS)
1155 host->cfg_reg |= ATMCI_CFG_HSMODE;
1156 else
1157 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
1158 }
1159
1160 if (list_empty(&host->queue)) {
1161 atmci_writel(host, ATMCI_MR, host->mode_reg);
1162 if (host->caps.has_cfg_reg)
1163 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1164 } else {
1165 host->need_clock_update = true;
1166 }
1167
1168 spin_unlock_bh(&host->lock);
1169 } else {
1170 bool any_slot_active = false;
1171
1172 spin_lock_bh(&host->lock);
1173 slot->clock = 0;
1174 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1175 if (host->slot[i] && host->slot[i]->clock) {
1176 any_slot_active = true;
1177 break;
1178 }
1179 }
1180 if (!any_slot_active) {
1181 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
1182 if (host->mode_reg) {
1183 atmci_readl(host, ATMCI_MR);
1184 clk_disable(host->mck);
1185 }
1186 host->mode_reg = 0;
1187 }
1188 spin_unlock_bh(&host->lock);
1189 }
1190
1191 switch (ios->power_mode) {
1192 case MMC_POWER_UP:
1193 set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
1194 break;
1195 default:
1196 /*
1197 * TODO: None of the currently available AVR32-based
1198 * boards allow MMC power to be turned off. Implement
1199 * power control when this can be tested properly.
1200 *
1201 * We also need to hook this into the clock management
1202 * somehow so that newly inserted cards aren't
1203 * subjected to a fast clock before we have a chance
1204 * to figure out what the maximum rate is. Currently,
1205 * there's no way to avoid this, and there never will
1206 * be for boards that don't support power control.
1207 */
1208 break;
1209 }
1210 }
1211
1212 static int atmci_get_ro(struct mmc_host *mmc)
1213 {
1214 int read_only = -ENOSYS;
1215 struct atmel_mci_slot *slot = mmc_priv(mmc);
1216
1217 if (gpio_is_valid(slot->wp_pin)) {
1218 read_only = gpio_get_value(slot->wp_pin);
1219 dev_dbg(&mmc->class_dev, "card is %s\n",
1220 read_only ? "read-only" : "read-write");
1221 }
1222
1223 return read_only;
1224 }
1225
1226 static int atmci_get_cd(struct mmc_host *mmc)
1227 {
1228 int present = -ENOSYS;
1229 struct atmel_mci_slot *slot = mmc_priv(mmc);
1230
1231 if (gpio_is_valid(slot->detect_pin)) {
1232 present = !(gpio_get_value(slot->detect_pin) ^
1233 slot->detect_is_active_high);
1234 dev_dbg(&mmc->class_dev, "card is %spresent\n",
1235 present ? "" : "not ");
1236 }
1237
1238 return present;
1239 }
1240
1241 static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1242 {
1243 struct atmel_mci_slot *slot = mmc_priv(mmc);
1244 struct atmel_mci *host = slot->host;
1245
1246 if (enable)
1247 atmci_writel(host, ATMCI_IER, slot->sdio_irq);
1248 else
1249 atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
1250 }
1251
1252 static const struct mmc_host_ops atmci_ops = {
1253 .request = atmci_request,
1254 .set_ios = atmci_set_ios,
1255 .get_ro = atmci_get_ro,
1256 .get_cd = atmci_get_cd,
1257 .enable_sdio_irq = atmci_enable_sdio_irq,
1258 };
1259
1260 /* Called with host->lock held */
1261 static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1262 __releases(&host->lock)
1263 __acquires(&host->lock)
1264 {
1265 struct atmel_mci_slot *slot = NULL;
1266 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1267
1268 WARN_ON(host->cmd || host->data);
1269
1270 /*
1271 * Update the MMC clock rate if necessary. This may be
1272 * necessary if set_ios() is called when a different slot is
1273 * busy transferring data.
1274 */
1275 if (host->need_clock_update) {
1276 atmci_writel(host, ATMCI_MR, host->mode_reg);
1277 if (host->caps.has_cfg_reg)
1278 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1279 }
1280
1281 host->cur_slot->mrq = NULL;
1282 host->mrq = NULL;
1283 if (!list_empty(&host->queue)) {
1284 slot = list_entry(host->queue.next,
1285 struct atmel_mci_slot, queue_node);
1286 list_del(&slot->queue_node);
1287 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
1288 mmc_hostname(slot->mmc));
1289 host->state = STATE_SENDING_CMD;
1290 atmci_start_request(host, slot);
1291 } else {
1292 dev_vdbg(&host->pdev->dev, "list empty\n");
1293 host->state = STATE_IDLE;
1294 }
1295
1296 spin_unlock(&host->lock);
1297 mmc_request_done(prev_mmc, mrq);
1298 spin_lock(&host->lock);
1299 }
1300
1301 static void atmci_command_complete(struct atmel_mci *host,
1302 struct mmc_command *cmd)
1303 {
1304 u32 status = host->cmd_status;
1305
1306 /* Read the response from the card (up to 16 bytes) */
1307 cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
1308 cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
1309 cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
1310 cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
1311
1312 if (status & ATMCI_RTOE)
1313 cmd->error = -ETIMEDOUT;
1314 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1315 cmd->error = -EILSEQ;
1316 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1317 cmd->error = -EIO;
1318 else
1319 cmd->error = 0;
1320
1321 if (cmd->error) {
1322 dev_dbg(&host->pdev->dev,
1323 "command error: status=0x%08x\n", status);
1324
1325 if (cmd->data) {
1326 host->stop_transfer(host);
1327 host->data = NULL;
1328 atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY
1329 | ATMCI_TXRDY | ATMCI_RXRDY
1330 | ATMCI_DATA_ERROR_FLAGS);
1331 }
1332 }
1333 }
1334
1335 static void atmci_detect_change(unsigned long data)
1336 {
1337 struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data;
1338 bool present;
1339 bool present_old;
1340
1341 /*
1342 * atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
1343 * freeing the interrupt. We must not re-enable the interrupt
1344 * if it has been freed, and if we're shutting down, it
1345 * doesn't really matter whether the card is present or not.
1346 */
1347 smp_rmb();
1348 if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
1349 return;
1350
1351 enable_irq(gpio_to_irq(slot->detect_pin));
1352 present = !(gpio_get_value(slot->detect_pin) ^
1353 slot->detect_is_active_high);
1354 present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
1355
1356 dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
1357 present, present_old);
1358
1359 if (present != present_old) {
1360 struct atmel_mci *host = slot->host;
1361 struct mmc_request *mrq;
1362
1363 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1364 present ? "inserted" : "removed");
1365
1366 spin_lock(&host->lock);
1367
1368 if (!present)
1369 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1370 else
1371 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1372
1373 /* Clean up queue if present */
1374 mrq = slot->mrq;
1375 if (mrq) {
1376 if (mrq == host->mrq) {
1377 /*
1378 * Reset controller to terminate any ongoing
1379 * commands or data transfers.
1380 */
1381 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
1382 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
1383 atmci_writel(host, ATMCI_MR, host->mode_reg);
1384 if (host->caps.has_cfg_reg)
1385 atmci_writel(host, ATMCI_CFG, host->cfg_reg);
1386
1387 host->data = NULL;
1388 host->cmd = NULL;
1389
1390 switch (host->state) {
1391 case STATE_IDLE:
1392 break;
1393 case STATE_SENDING_CMD:
1394 mrq->cmd->error = -ENOMEDIUM;
1395 if (!mrq->data)
1396 break;
1397 /* fall through */
1398 case STATE_SENDING_DATA:
1399 mrq->data->error = -ENOMEDIUM;
1400 host->stop_transfer(host);
1401 break;
1402 case STATE_DATA_BUSY:
1403 case STATE_DATA_ERROR:
1404 if (mrq->data->error == -EINPROGRESS)
1405 mrq->data->error = -ENOMEDIUM;
1406 if (!mrq->stop)
1407 break;
1408 /* fall through */
1409 case STATE_SENDING_STOP:
1410 mrq->stop->error = -ENOMEDIUM;
1411 break;
1412 }
1413
1414 atmci_request_end(host, mrq);
1415 } else {
1416 list_del(&slot->queue_node);
1417 mrq->cmd->error = -ENOMEDIUM;
1418 if (mrq->data)
1419 mrq->data->error = -ENOMEDIUM;
1420 if (mrq->stop)
1421 mrq->stop->error = -ENOMEDIUM;
1422
1423 spin_unlock(&host->lock);
1424 mmc_request_done(slot->mmc, mrq);
1425 spin_lock(&host->lock);
1426 }
1427 }
1428 spin_unlock(&host->lock);
1429
1430 mmc_detect_change(slot->mmc, 0);
1431 }
1432 }
1433
1434 static void atmci_tasklet_func(unsigned long priv)
1435 {
1436 struct atmel_mci *host = (struct atmel_mci *)priv;
1437 struct mmc_request *mrq = host->mrq;
1438 struct mmc_data *data = host->data;
1439 struct mmc_command *cmd = host->cmd;
1440 enum atmel_mci_state state = host->state;
1441 enum atmel_mci_state prev_state;
1442 u32 status;
1443
1444 spin_lock(&host->lock);
1445
1446 state = host->state;
1447
1448 dev_vdbg(&host->pdev->dev,
1449 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1450 state, host->pending_events, host->completed_events,
1451 atmci_readl(host, ATMCI_IMR));
1452
1453 do {
1454 prev_state = state;
1455
1456 switch (state) {
1457 case STATE_IDLE:
1458 break;
1459
1460 case STATE_SENDING_CMD:
1461 if (!atmci_test_and_clear_pending(host,
1462 EVENT_CMD_COMPLETE))
1463 break;
1464
1465 host->cmd = NULL;
1466 atmci_set_completed(host, EVENT_CMD_COMPLETE);
1467 atmci_command_complete(host, mrq->cmd);
1468 if (!mrq->data || cmd->error) {
1469 atmci_request_end(host, host->mrq);
1470 goto unlock;
1471 }
1472
1473 prev_state = state = STATE_SENDING_DATA;
1474 /* fall through */
1475
1476 case STATE_SENDING_DATA:
1477 if (atmci_test_and_clear_pending(host,
1478 EVENT_DATA_ERROR)) {
1479 host->stop_transfer(host);
1480 if (data->stop)
1481 atmci_send_stop_cmd(host, data);
1482 state = STATE_DATA_ERROR;
1483 break;
1484 }
1485
1486 if (!atmci_test_and_clear_pending(host,
1487 EVENT_XFER_COMPLETE))
1488 break;
1489
1490 atmci_set_completed(host, EVENT_XFER_COMPLETE);
1491 prev_state = state = STATE_DATA_BUSY;
1492 /* fall through */
1493
1494 case STATE_DATA_BUSY:
1495 if (!atmci_test_and_clear_pending(host,
1496 EVENT_DATA_COMPLETE))
1497 break;
1498
1499 host->data = NULL;
1500 atmci_set_completed(host, EVENT_DATA_COMPLETE);
1501 status = host->data_status;
1502 if (unlikely(status & ATMCI_DATA_ERROR_FLAGS)) {
1503 if (status & ATMCI_DTOE) {
1504 dev_dbg(&host->pdev->dev,
1505 "data timeout error\n");
1506 data->error = -ETIMEDOUT;
1507 } else if (status & ATMCI_DCRCE) {
1508 dev_dbg(&host->pdev->dev,
1509 "data CRC error\n");
1510 data->error = -EILSEQ;
1511 } else {
1512 dev_dbg(&host->pdev->dev,
1513 "data FIFO error (status=%08x)\n",
1514 status);
1515 data->error = -EIO;
1516 }
1517 } else {
1518 data->bytes_xfered = data->blocks * data->blksz;
1519 data->error = 0;
1520 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS);
1521 }
1522
1523 if (!data->stop) {
1524 atmci_request_end(host, host->mrq);
1525 goto unlock;
1526 }
1527
1528 prev_state = state = STATE_SENDING_STOP;
1529 if (!data->error)
1530 atmci_send_stop_cmd(host, data);
1531 /* fall through */
1532
1533 case STATE_SENDING_STOP:
1534 if (!atmci_test_and_clear_pending(host,
1535 EVENT_CMD_COMPLETE))
1536 break;
1537
1538 host->cmd = NULL;
1539 atmci_command_complete(host, mrq->stop);
1540 atmci_request_end(host, host->mrq);
1541 goto unlock;
1542
1543 case STATE_DATA_ERROR:
1544 if (!atmci_test_and_clear_pending(host,
1545 EVENT_XFER_COMPLETE))
1546 break;
1547
1548 state = STATE_DATA_BUSY;
1549 break;
1550 }
1551 } while (state != prev_state);
1552
1553 host->state = state;
1554
1555 unlock:
1556 spin_unlock(&host->lock);
1557 }
1558
1559 static void atmci_read_data_pio(struct atmel_mci *host)
1560 {
1561 struct scatterlist *sg = host->sg;
1562 void *buf = sg_virt(sg);
1563 unsigned int offset = host->pio_offset;
1564 struct mmc_data *data = host->data;
1565 u32 value;
1566 u32 status;
1567 unsigned int nbytes = 0;
1568
1569 do {
1570 value = atmci_readl(host, ATMCI_RDR);
1571 if (likely(offset + 4 <= sg->length)) {
1572 put_unaligned(value, (u32 *)(buf + offset));
1573
1574 offset += 4;
1575 nbytes += 4;
1576
1577 if (offset == sg->length) {
1578 flush_dcache_page(sg_page(sg));
1579 host->sg = sg = sg_next(sg);
1580 if (!sg)
1581 goto done;
1582
1583 offset = 0;
1584 buf = sg_virt(sg);
1585 }
1586 } else {
1587 unsigned int remaining = sg->length - offset;
1588 memcpy(buf + offset, &value, remaining);
1589 nbytes += remaining;
1590
1591 flush_dcache_page(sg_page(sg));
1592 host->sg = sg = sg_next(sg);
1593 if (!sg)
1594 goto done;
1595
1596 offset = 4 - remaining;
1597 buf = sg_virt(sg);
1598 memcpy(buf, (u8 *)&value + remaining, offset);
1599 nbytes += offset;
1600 }
1601
1602 status = atmci_readl(host, ATMCI_SR);
1603 if (status & ATMCI_DATA_ERROR_FLAGS) {
1604 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
1605 | ATMCI_DATA_ERROR_FLAGS));
1606 host->data_status = status;
1607 data->bytes_xfered += nbytes;
1608 smp_wmb();
1609 atmci_set_pending(host, EVENT_DATA_ERROR);
1610 tasklet_schedule(&host->tasklet);
1611 return;
1612 }
1613 } while (status & ATMCI_RXRDY);
1614
1615 host->pio_offset = offset;
1616 data->bytes_xfered += nbytes;
1617
1618 return;
1619
1620 done:
1621 atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
1622 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1623 data->bytes_xfered += nbytes;
1624 smp_wmb();
1625 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1626 }
1627
1628 static void atmci_write_data_pio(struct atmel_mci *host)
1629 {
1630 struct scatterlist *sg = host->sg;
1631 void *buf = sg_virt(sg);
1632 unsigned int offset = host->pio_offset;
1633 struct mmc_data *data = host->data;
1634 u32 value;
1635 u32 status;
1636 unsigned int nbytes = 0;
1637
1638 do {
1639 if (likely(offset + 4 <= sg->length)) {
1640 value = get_unaligned((u32 *)(buf + offset));
1641 atmci_writel(host, ATMCI_TDR, value);
1642
1643 offset += 4;
1644 nbytes += 4;
1645 if (offset == sg->length) {
1646 host->sg = sg = sg_next(sg);
1647 if (!sg)
1648 goto done;
1649
1650 offset = 0;
1651 buf = sg_virt(sg);
1652 }
1653 } else {
1654 unsigned int remaining = sg->length - offset;
1655
1656 value = 0;
1657 memcpy(&value, buf + offset, remaining);
1658 nbytes += remaining;
1659
1660 host->sg = sg = sg_next(sg);
1661 if (!sg) {
1662 atmci_writel(host, ATMCI_TDR, value);
1663 goto done;
1664 }
1665
1666 offset = 4 - remaining;
1667 buf = sg_virt(sg);
1668 memcpy((u8 *)&value + remaining, buf, offset);
1669 atmci_writel(host, ATMCI_TDR, value);
1670 nbytes += offset;
1671 }
1672
1673 status = atmci_readl(host, ATMCI_SR);
1674 if (status & ATMCI_DATA_ERROR_FLAGS) {
1675 atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
1676 | ATMCI_DATA_ERROR_FLAGS));
1677 host->data_status = status;
1678 data->bytes_xfered += nbytes;
1679 smp_wmb();
1680 atmci_set_pending(host, EVENT_DATA_ERROR);
1681 tasklet_schedule(&host->tasklet);
1682 return;
1683 }
1684 } while (status & ATMCI_TXRDY);
1685
1686 host->pio_offset = offset;
1687 data->bytes_xfered += nbytes;
1688
1689 return;
1690
1691 done:
1692 atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
1693 atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
1694 data->bytes_xfered += nbytes;
1695 smp_wmb();
1696 atmci_set_pending(host, EVENT_XFER_COMPLETE);
1697 }
1698
1699 static void atmci_cmd_interrupt(struct atmel_mci *host, u32 status)
1700 {
1701 atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
1702
1703 host->cmd_status = status;
1704 smp_wmb();
1705 atmci_set_pending(host, EVENT_CMD_COMPLETE);
1706 tasklet_schedule(&host->tasklet);
1707 }
1708
1709 static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
1710 {
1711 int i;
1712
1713 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1714 struct atmel_mci_slot *slot = host->slot[i];
1715 if (slot && (status & slot->sdio_irq)) {
1716 mmc_signal_sdio_irq(slot->mmc);
1717 }
1718 }
1719 }
1720
1721
1722 static irqreturn_t atmci_interrupt(int irq, void *dev_id)
1723 {
1724 struct atmel_mci *host = dev_id;
1725 u32 status, mask, pending;
1726 unsigned int pass_count = 0;
1727
1728 do {
1729 status = atmci_readl(host, ATMCI_SR);
1730 mask = atmci_readl(host, ATMCI_IMR);
1731 pending = status & mask;
1732 if (!pending)
1733 break;
1734
1735 if (pending & ATMCI_DATA_ERROR_FLAGS) {
1736 atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
1737 | ATMCI_RXRDY | ATMCI_TXRDY);
1738 pending &= atmci_readl(host, ATMCI_IMR);
1739
1740 host->data_status = status;
1741 smp_wmb();
1742 atmci_set_pending(host, EVENT_DATA_ERROR);
1743 tasklet_schedule(&host->tasklet);
1744 }
1745
1746 if (pending & ATMCI_TXBUFE) {
1747 atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
1748 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
1749 /*
1750 * We can receive this interruption before having configured
1751 * the second pdc buffer, so we need to reconfigure first and
1752 * second buffers again
1753 */
1754 if (host->data_size) {
1755 atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
1756 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
1757 atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
1758 } else {
1759 atmci_pdc_complete(host);
1760 }
1761 } else if (pending & ATMCI_ENDTX) {
1762 atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
1763
1764 if (host->data_size) {
1765 atmci_pdc_set_single_buf(host,
1766 XFER_TRANSMIT, PDC_SECOND_BUF);
1767 atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
1768 }
1769 }
1770
1771 if (pending & ATMCI_RXBUFF) {
1772 atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
1773 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
1774 /*
1775 * We can receive this interruption before having configured
1776 * the second pdc buffer, so we need to reconfigure first and
1777 * second buffers again
1778 */
1779 if (host->data_size) {
1780 atmci_pdc_set_both_buf(host, XFER_RECEIVE);
1781 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
1782 atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
1783 } else {
1784 atmci_pdc_complete(host);
1785 }
1786 } else if (pending & ATMCI_ENDRX) {
1787 atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
1788
1789 if (host->data_size) {
1790 atmci_pdc_set_single_buf(host,
1791 XFER_RECEIVE, PDC_SECOND_BUF);
1792 atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
1793 }
1794 }
1795
1796
1797 if (pending & ATMCI_NOTBUSY) {
1798 atmci_writel(host, ATMCI_IDR,
1799 ATMCI_DATA_ERROR_FLAGS | ATMCI_NOTBUSY);
1800 if (!host->data_status)
1801 host->data_status = status;
1802 smp_wmb();
1803 atmci_set_pending(host, EVENT_DATA_COMPLETE);
1804 tasklet_schedule(&host->tasklet);
1805 }
1806 if (pending & ATMCI_RXRDY)
1807 atmci_read_data_pio(host);
1808 if (pending & ATMCI_TXRDY)
1809 atmci_write_data_pio(host);
1810
1811 if (pending & ATMCI_CMDRDY)
1812 atmci_cmd_interrupt(host, status);
1813
1814 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1815 atmci_sdio_interrupt(host, status);
1816
1817 } while (pass_count++ < 5);
1818
1819 return pass_count ? IRQ_HANDLED : IRQ_NONE;
1820 }
1821
1822 static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
1823 {
1824 struct atmel_mci_slot *slot = dev_id;
1825
1826 /*
1827 * Disable interrupts until the pin has stabilized and check
1828 * the state then. Use mod_timer() since we may be in the
1829 * middle of the timer routine when this interrupt triggers.
1830 */
1831 disable_irq_nosync(irq);
1832 mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
1833
1834 return IRQ_HANDLED;
1835 }
1836
1837 static int __init atmci_init_slot(struct atmel_mci *host,
1838 struct mci_slot_pdata *slot_data, unsigned int id,
1839 u32 sdc_reg, u32 sdio_irq)
1840 {
1841 struct mmc_host *mmc;
1842 struct atmel_mci_slot *slot;
1843
1844 mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
1845 if (!mmc)
1846 return -ENOMEM;
1847
1848 slot = mmc_priv(mmc);
1849 slot->mmc = mmc;
1850 slot->host = host;
1851 slot->detect_pin = slot_data->detect_pin;
1852 slot->wp_pin = slot_data->wp_pin;
1853 slot->detect_is_active_high = slot_data->detect_is_active_high;
1854 slot->sdc_reg = sdc_reg;
1855 slot->sdio_irq = sdio_irq;
1856
1857 mmc->ops = &atmci_ops;
1858 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
1859 mmc->f_max = host->bus_hz / 2;
1860 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1861 if (sdio_irq)
1862 mmc->caps |= MMC_CAP_SDIO_IRQ;
1863 if (host->caps.has_highspeed)
1864 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1865 if (slot_data->bus_width >= 4)
1866 mmc->caps |= MMC_CAP_4_BIT_DATA;
1867
1868 mmc->max_segs = 64;
1869 mmc->max_req_size = 32768 * 512;
1870 mmc->max_blk_size = 32768;
1871 mmc->max_blk_count = 512;
1872
1873 /* Assume card is present initially */
1874 set_bit(ATMCI_CARD_PRESENT, &slot->flags);
1875 if (gpio_is_valid(slot->detect_pin)) {
1876 if (gpio_request(slot->detect_pin, "mmc_detect")) {
1877 dev_dbg(&mmc->class_dev, "no detect pin available\n");
1878 slot->detect_pin = -EBUSY;
1879 } else if (gpio_get_value(slot->detect_pin) ^
1880 slot->detect_is_active_high) {
1881 clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
1882 }
1883 }
1884
1885 if (!gpio_is_valid(slot->detect_pin))
1886 mmc->caps |= MMC_CAP_NEEDS_POLL;
1887
1888 if (gpio_is_valid(slot->wp_pin)) {
1889 if (gpio_request(slot->wp_pin, "mmc_wp")) {
1890 dev_dbg(&mmc->class_dev, "no WP pin available\n");
1891 slot->wp_pin = -EBUSY;
1892 }
1893 }
1894
1895 host->slot[id] = slot;
1896 mmc_add_host(mmc);
1897
1898 if (gpio_is_valid(slot->detect_pin)) {
1899 int ret;
1900
1901 setup_timer(&slot->detect_timer, atmci_detect_change,
1902 (unsigned long)slot);
1903
1904 ret = request_irq(gpio_to_irq(slot->detect_pin),
1905 atmci_detect_interrupt,
1906 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
1907 "mmc-detect", slot);
1908 if (ret) {
1909 dev_dbg(&mmc->class_dev,
1910 "could not request IRQ %d for detect pin\n",
1911 gpio_to_irq(slot->detect_pin));
1912 gpio_free(slot->detect_pin);
1913 slot->detect_pin = -EBUSY;
1914 }
1915 }
1916
1917 atmci_init_debugfs(slot);
1918
1919 return 0;
1920 }
1921
1922 static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
1923 unsigned int id)
1924 {
1925 /* Debugfs stuff is cleaned up by mmc core */
1926
1927 set_bit(ATMCI_SHUTDOWN, &slot->flags);
1928 smp_wmb();
1929
1930 mmc_remove_host(slot->mmc);
1931
1932 if (gpio_is_valid(slot->detect_pin)) {
1933 int pin = slot->detect_pin;
1934
1935 free_irq(gpio_to_irq(pin), slot);
1936 del_timer_sync(&slot->detect_timer);
1937 gpio_free(pin);
1938 }
1939 if (gpio_is_valid(slot->wp_pin))
1940 gpio_free(slot->wp_pin);
1941
1942 slot->host->slot[id] = NULL;
1943 mmc_free_host(slot->mmc);
1944 }
1945
1946 static bool atmci_filter(struct dma_chan *chan, void *slave)
1947 {
1948 struct mci_dma_data *sl = slave;
1949
1950 if (sl && find_slave_dev(sl) == chan->device->dev) {
1951 chan->private = slave_data_ptr(sl);
1952 return true;
1953 } else {
1954 return false;
1955 }
1956 }
1957
1958 static bool atmci_configure_dma(struct atmel_mci *host)
1959 {
1960 struct mci_platform_data *pdata;
1961
1962 if (host == NULL)
1963 return false;
1964
1965 pdata = host->pdev->dev.platform_data;
1966
1967 if (pdata && find_slave_dev(pdata->dma_slave)) {
1968 dma_cap_mask_t mask;
1969
1970 setup_dma_addr(pdata->dma_slave,
1971 host->mapbase + ATMCI_TDR,
1972 host->mapbase + ATMCI_RDR);
1973
1974 /* Try to grab a DMA channel */
1975 dma_cap_zero(mask);
1976 dma_cap_set(DMA_SLAVE, mask);
1977 host->dma.chan =
1978 dma_request_channel(mask, atmci_filter, pdata->dma_slave);
1979 }
1980 if (!host->dma.chan) {
1981 dev_warn(&host->pdev->dev, "no DMA channel available\n");
1982 return false;
1983 } else {
1984 dev_info(&host->pdev->dev,
1985 "Using %s for DMA transfers\n",
1986 dma_chan_name(host->dma.chan));
1987 return true;
1988 }
1989 }
1990
1991 static inline unsigned int atmci_get_version(struct atmel_mci *host)
1992 {
1993 return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
1994 }
1995
1996 /*
1997 * HSMCI (High Speed MCI) module is not fully compatible with MCI module.
1998 * HSMCI provides DMA support and a new config register but no more supports
1999 * PDC.
2000 */
2001 static void __init atmci_get_cap(struct atmel_mci *host)
2002 {
2003 unsigned int version;
2004
2005 version = atmci_get_version(host);
2006 dev_info(&host->pdev->dev,
2007 "version: 0x%x\n", version);
2008
2009 host->caps.has_dma = 0;
2010 host->caps.has_pdc = 0;
2011 host->caps.has_cfg_reg = 0;
2012 host->caps.has_cstor_reg = 0;
2013 host->caps.has_highspeed = 0;
2014 host->caps.has_rwproof = 0;
2015
2016 /* keep only major version number */
2017 switch (version & 0xf00) {
2018 case 0x100:
2019 case 0x200:
2020 host->caps.has_pdc = 1;
2021 host->caps.has_rwproof = 1;
2022 break;
2023 case 0x300:
2024 case 0x400:
2025 case 0x500:
2026 #ifdef CONFIG_AT_HDMAC
2027 host->caps.has_dma = 1;
2028 #else
2029 host->caps.has_dma = 0;
2030 dev_info(&host->pdev->dev,
2031 "has dma capability but dma engine is not selected, then use pio\n");
2032 #endif
2033 host->caps.has_cfg_reg = 1;
2034 host->caps.has_cstor_reg = 1;
2035 host->caps.has_highspeed = 1;
2036 host->caps.has_rwproof = 1;
2037 break;
2038 default:
2039 dev_warn(&host->pdev->dev,
2040 "Unmanaged mci version, set minimum capabilities\n");
2041 break;
2042 }
2043 }
2044
2045 static int __init atmci_probe(struct platform_device *pdev)
2046 {
2047 struct mci_platform_data *pdata;
2048 struct atmel_mci *host;
2049 struct resource *regs;
2050 unsigned int nr_slots;
2051 int irq;
2052 int ret;
2053
2054 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2055 if (!regs)
2056 return -ENXIO;
2057 pdata = pdev->dev.platform_data;
2058 if (!pdata)
2059 return -ENXIO;
2060 irq = platform_get_irq(pdev, 0);
2061 if (irq < 0)
2062 return irq;
2063
2064 host = kzalloc(sizeof(struct atmel_mci), GFP_KERNEL);
2065 if (!host)
2066 return -ENOMEM;
2067
2068 host->pdev = pdev;
2069 spin_lock_init(&host->lock);
2070 INIT_LIST_HEAD(&host->queue);
2071
2072 host->mck = clk_get(&pdev->dev, "mci_clk");
2073 if (IS_ERR(host->mck)) {
2074 ret = PTR_ERR(host->mck);
2075 goto err_clk_get;
2076 }
2077
2078 ret = -ENOMEM;
2079 host->regs = ioremap(regs->start, resource_size(regs));
2080 if (!host->regs)
2081 goto err_ioremap;
2082
2083 clk_enable(host->mck);
2084 atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
2085 host->bus_hz = clk_get_rate(host->mck);
2086 clk_disable(host->mck);
2087
2088 host->mapbase = regs->start;
2089
2090 tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
2091
2092 ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
2093 if (ret)
2094 goto err_request_irq;
2095
2096 /* Get MCI capabilities and set operations according to it */
2097 atmci_get_cap(host);
2098 if (host->caps.has_dma && atmci_configure_dma(host)) {
2099 host->prepare_data = &atmci_prepare_data_dma;
2100 host->submit_data = &atmci_submit_data_dma;
2101 host->stop_transfer = &atmci_stop_transfer_dma;
2102 } else if (host->caps.has_pdc) {
2103 dev_info(&pdev->dev, "using PDC\n");
2104 host->prepare_data = &atmci_prepare_data_pdc;
2105 host->submit_data = &atmci_submit_data_pdc;
2106 host->stop_transfer = &atmci_stop_transfer_pdc;
2107 } else {
2108 dev_info(&pdev->dev, "using PIO\n");
2109 host->prepare_data = &atmci_prepare_data;
2110 host->submit_data = &atmci_submit_data;
2111 host->stop_transfer = &atmci_stop_transfer;
2112 }
2113
2114 platform_set_drvdata(pdev, host);
2115
2116 /* We need at least one slot to succeed */
2117 nr_slots = 0;
2118 ret = -ENODEV;
2119 if (pdata->slot[0].bus_width) {
2120 ret = atmci_init_slot(host, &pdata->slot[0],
2121 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
2122 if (!ret)
2123 nr_slots++;
2124 }
2125 if (pdata->slot[1].bus_width) {
2126 ret = atmci_init_slot(host, &pdata->slot[1],
2127 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
2128 if (!ret)
2129 nr_slots++;
2130 }
2131
2132 if (!nr_slots) {
2133 dev_err(&pdev->dev, "init failed: no slot defined\n");
2134 goto err_init_slot;
2135 }
2136
2137 dev_info(&pdev->dev,
2138 "Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
2139 host->mapbase, irq, nr_slots);
2140
2141 return 0;
2142
2143 err_init_slot:
2144 if (host->dma.chan)
2145 dma_release_channel(host->dma.chan);
2146 free_irq(irq, host);
2147 err_request_irq:
2148 iounmap(host->regs);
2149 err_ioremap:
2150 clk_put(host->mck);
2151 err_clk_get:
2152 kfree(host);
2153 return ret;
2154 }
2155
2156 static int __exit atmci_remove(struct platform_device *pdev)
2157 {
2158 struct atmel_mci *host = platform_get_drvdata(pdev);
2159 unsigned int i;
2160
2161 platform_set_drvdata(pdev, NULL);
2162
2163 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2164 if (host->slot[i])
2165 atmci_cleanup_slot(host->slot[i], i);
2166 }
2167
2168 clk_enable(host->mck);
2169 atmci_writel(host, ATMCI_IDR, ~0UL);
2170 atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
2171 atmci_readl(host, ATMCI_SR);
2172 clk_disable(host->mck);
2173
2174 #ifdef CONFIG_MMC_ATMELMCI_DMA
2175 if (host->dma.chan)
2176 dma_release_channel(host->dma.chan);
2177 #endif
2178
2179 free_irq(platform_get_irq(pdev, 0), host);
2180 iounmap(host->regs);
2181
2182 clk_put(host->mck);
2183 kfree(host);
2184
2185 return 0;
2186 }
2187
2188 #ifdef CONFIG_PM
2189 static int atmci_suspend(struct device *dev)
2190 {
2191 struct atmel_mci *host = dev_get_drvdata(dev);
2192 int i;
2193
2194 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2195 struct atmel_mci_slot *slot = host->slot[i];
2196 int ret;
2197
2198 if (!slot)
2199 continue;
2200 ret = mmc_suspend_host(slot->mmc);
2201 if (ret < 0) {
2202 while (--i >= 0) {
2203 slot = host->slot[i];
2204 if (slot
2205 && test_bit(ATMCI_SUSPENDED, &slot->flags)) {
2206 mmc_resume_host(host->slot[i]->mmc);
2207 clear_bit(ATMCI_SUSPENDED, &slot->flags);
2208 }
2209 }
2210 return ret;
2211 } else {
2212 set_bit(ATMCI_SUSPENDED, &slot->flags);
2213 }
2214 }
2215
2216 return 0;
2217 }
2218
2219 static int atmci_resume(struct device *dev)
2220 {
2221 struct atmel_mci *host = dev_get_drvdata(dev);
2222 int i;
2223 int ret = 0;
2224
2225 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
2226 struct atmel_mci_slot *slot = host->slot[i];
2227 int err;
2228
2229 slot = host->slot[i];
2230 if (!slot)
2231 continue;
2232 if (!test_bit(ATMCI_SUSPENDED, &slot->flags))
2233 continue;
2234 err = mmc_resume_host(slot->mmc);
2235 if (err < 0)
2236 ret = err;
2237 else
2238 clear_bit(ATMCI_SUSPENDED, &slot->flags);
2239 }
2240
2241 return ret;
2242 }
2243 static SIMPLE_DEV_PM_OPS(atmci_pm, atmci_suspend, atmci_resume);
2244 #define ATMCI_PM_OPS (&atmci_pm)
2245 #else
2246 #define ATMCI_PM_OPS NULL
2247 #endif
2248
2249 static struct platform_driver atmci_driver = {
2250 .remove = __exit_p(atmci_remove),
2251 .driver = {
2252 .name = "atmel_mci",
2253 .pm = ATMCI_PM_OPS,
2254 },
2255 };
2256
2257 static int __init atmci_init(void)
2258 {
2259 return platform_driver_probe(&atmci_driver, atmci_probe);
2260 }
2261
2262 static void __exit atmci_exit(void)
2263 {
2264 platform_driver_unregister(&atmci_driver);
2265 }
2266
2267 late_initcall(atmci_init); /* try to load after dma driver when built-in */
2268 module_exit(atmci_exit);
2269
2270 MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
2271 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2272 MODULE_LICENSE("GPL v2");