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usb: Netlogic: Use CPU_XLR in place of NLM_XLR
[zen-stable.git] / drivers / net / ethernet / nvidia / forcedeth.c
blob1dca57013cb2d868f3881a528a3dccc27e7605a9
1 /*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
7 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
31 *
32 * Known bugs:
33 * We suspect that on some hardware no TX done interrupts are generated.
34 * This means recovery from netif_stop_queue only happens if the hw timer
35 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
36 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
37 * If your hardware reliably generates tx done interrupts, then you can remove
38 * DEV_NEED_TIMERIRQ from the driver_data flags.
39 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
40 * superfluous timer interrupts from the nic.
41 */
42
43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44
45 #define FORCEDETH_VERSION "0.64"
46 #define DRV_NAME "forcedeth"
47
48 #include <linux/module.h>
49 #include <linux/types.h>
50 #include <linux/pci.h>
51 #include <linux/interrupt.h>
52 #include <linux/netdevice.h>
53 #include <linux/etherdevice.h>
54 #include <linux/delay.h>
55 #include <linux/sched.h>
56 #include <linux/spinlock.h>
57 #include <linux/ethtool.h>
58 #include <linux/timer.h>
59 #include <linux/skbuff.h>
60 #include <linux/mii.h>
61 #include <linux/random.h>
62 #include <linux/init.h>
63 #include <linux/if_vlan.h>
64 #include <linux/dma-mapping.h>
65 #include <linux/slab.h>
66 #include <linux/uaccess.h>
67 #include <linux/prefetch.h>
68 #include <linux/io.h>
69
70 #include <asm/irq.h>
71 #include <asm/system.h>
72
73 #define TX_WORK_PER_LOOP 64
74 #define RX_WORK_PER_LOOP 64
75
76 /*
77 * Hardware access:
78 */
79
80 #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
81 #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
82 #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
83 #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
84 #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
85 #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
86 #define DEV_HAS_MSI 0x0000040 /* device supports MSI */
87 #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
88 #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
89 #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
90 #define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */
91 #define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */
92 #define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */
93 #define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */
94 #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
95 #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
96 #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
97 #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
98 #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
99 #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
100 #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
101 #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
102 #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
103 #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
104 #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
105 #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
106 #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
107
108 enum {
109 NvRegIrqStatus = 0x000,
110 #define NVREG_IRQSTAT_MIIEVENT 0x040
111 #define NVREG_IRQSTAT_MASK 0x83ff
112 NvRegIrqMask = 0x004,
113 #define NVREG_IRQ_RX_ERROR 0x0001
114 #define NVREG_IRQ_RX 0x0002
115 #define NVREG_IRQ_RX_NOBUF 0x0004
116 #define NVREG_IRQ_TX_ERR 0x0008
117 #define NVREG_IRQ_TX_OK 0x0010
118 #define NVREG_IRQ_TIMER 0x0020
119 #define NVREG_IRQ_LINK 0x0040
120 #define NVREG_IRQ_RX_FORCED 0x0080
121 #define NVREG_IRQ_TX_FORCED 0x0100
122 #define NVREG_IRQ_RECOVER_ERROR 0x8200
123 #define NVREG_IRQMASK_THROUGHPUT 0x00df
124 #define NVREG_IRQMASK_CPU 0x0060
125 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
126 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
127 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
128
129 NvRegUnknownSetupReg6 = 0x008,
130 #define NVREG_UNKSETUP6_VAL 3
131
132 /*
133 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
134 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
135 */
136 NvRegPollingInterval = 0x00c,
137 #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
138 #define NVREG_POLL_DEFAULT_CPU 13
139 NvRegMSIMap0 = 0x020,
140 NvRegMSIMap1 = 0x024,
141 NvRegMSIIrqMask = 0x030,
142 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
143 NvRegMisc1 = 0x080,
144 #define NVREG_MISC1_PAUSE_TX 0x01
145 #define NVREG_MISC1_HD 0x02
146 #define NVREG_MISC1_FORCE 0x3b0f3c
147
148 NvRegMacReset = 0x34,
149 #define NVREG_MAC_RESET_ASSERT 0x0F3
150 NvRegTransmitterControl = 0x084,
151 #define NVREG_XMITCTL_START 0x01
152 #define NVREG_XMITCTL_MGMT_ST 0x40000000
153 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
154 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
155 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
156 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
157 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
158 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
159 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
160 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
161 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
162 #define NVREG_XMITCTL_DATA_START 0x00100000
163 #define NVREG_XMITCTL_DATA_READY 0x00010000
164 #define NVREG_XMITCTL_DATA_ERROR 0x00020000
165 NvRegTransmitterStatus = 0x088,
166 #define NVREG_XMITSTAT_BUSY 0x01
167
168 NvRegPacketFilterFlags = 0x8c,
169 #define NVREG_PFF_PAUSE_RX 0x08
170 #define NVREG_PFF_ALWAYS 0x7F0000
171 #define NVREG_PFF_PROMISC 0x80
172 #define NVREG_PFF_MYADDR 0x20
173 #define NVREG_PFF_LOOPBACK 0x10
174
175 NvRegOffloadConfig = 0x90,
176 #define NVREG_OFFLOAD_HOMEPHY 0x601
177 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
178 NvRegReceiverControl = 0x094,
179 #define NVREG_RCVCTL_START 0x01
180 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
181 NvRegReceiverStatus = 0x98,
182 #define NVREG_RCVSTAT_BUSY 0x01
183
184 NvRegSlotTime = 0x9c,
185 #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
186 #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
187 #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
188 #define NVREG_SLOTTIME_HALF 0x0000ff00
189 #define NVREG_SLOTTIME_DEFAULT 0x00007f00
190 #define NVREG_SLOTTIME_MASK 0x000000ff
191
192 NvRegTxDeferral = 0xA0,
193 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
194 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
195 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
196 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
197 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
198 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
199 NvRegRxDeferral = 0xA4,
200 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
201 NvRegMacAddrA = 0xA8,
202 NvRegMacAddrB = 0xAC,
203 NvRegMulticastAddrA = 0xB0,
204 #define NVREG_MCASTADDRA_FORCE 0x01
205 NvRegMulticastAddrB = 0xB4,
206 NvRegMulticastMaskA = 0xB8,
207 #define NVREG_MCASTMASKA_NONE 0xffffffff
208 NvRegMulticastMaskB = 0xBC,
209 #define NVREG_MCASTMASKB_NONE 0xffff
210
211 NvRegPhyInterface = 0xC0,
212 #define PHY_RGMII 0x10000000
213 NvRegBackOffControl = 0xC4,
214 #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
215 #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
216 #define NVREG_BKOFFCTRL_SELECT 24
217 #define NVREG_BKOFFCTRL_GEAR 12
218
219 NvRegTxRingPhysAddr = 0x100,
220 NvRegRxRingPhysAddr = 0x104,
221 NvRegRingSizes = 0x108,
222 #define NVREG_RINGSZ_TXSHIFT 0
223 #define NVREG_RINGSZ_RXSHIFT 16
224 NvRegTransmitPoll = 0x10c,
225 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
226 NvRegLinkSpeed = 0x110,
227 #define NVREG_LINKSPEED_FORCE 0x10000
228 #define NVREG_LINKSPEED_10 1000
229 #define NVREG_LINKSPEED_100 100
230 #define NVREG_LINKSPEED_1000 50
231 #define NVREG_LINKSPEED_MASK (0xFFF)
232 NvRegUnknownSetupReg5 = 0x130,
233 #define NVREG_UNKSETUP5_BIT31 (1<<31)
234 NvRegTxWatermark = 0x13c,
235 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
236 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
237 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
238 NvRegTxRxControl = 0x144,
239 #define NVREG_TXRXCTL_KICK 0x0001
240 #define NVREG_TXRXCTL_BIT1 0x0002
241 #define NVREG_TXRXCTL_BIT2 0x0004
242 #define NVREG_TXRXCTL_IDLE 0x0008
243 #define NVREG_TXRXCTL_RESET 0x0010
244 #define NVREG_TXRXCTL_RXCHECK 0x0400
245 #define NVREG_TXRXCTL_DESC_1 0
246 #define NVREG_TXRXCTL_DESC_2 0x002100
247 #define NVREG_TXRXCTL_DESC_3 0xc02200
248 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
249 #define NVREG_TXRXCTL_VLANINS 0x00080
250 NvRegTxRingPhysAddrHigh = 0x148,
251 NvRegRxRingPhysAddrHigh = 0x14C,
252 NvRegTxPauseFrame = 0x170,
253 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
254 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
255 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
256 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
257 NvRegTxPauseFrameLimit = 0x174,
258 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
259 NvRegMIIStatus = 0x180,
260 #define NVREG_MIISTAT_ERROR 0x0001
261 #define NVREG_MIISTAT_LINKCHANGE 0x0008
262 #define NVREG_MIISTAT_MASK_RW 0x0007
263 #define NVREG_MIISTAT_MASK_ALL 0x000f
264 NvRegMIIMask = 0x184,
265 #define NVREG_MII_LINKCHANGE 0x0008
266
267 NvRegAdapterControl = 0x188,
268 #define NVREG_ADAPTCTL_START 0x02
269 #define NVREG_ADAPTCTL_LINKUP 0x04
270 #define NVREG_ADAPTCTL_PHYVALID 0x40000
271 #define NVREG_ADAPTCTL_RUNNING 0x100000
272 #define NVREG_ADAPTCTL_PHYSHIFT 24
273 NvRegMIISpeed = 0x18c,
274 #define NVREG_MIISPEED_BIT8 (1<<8)
275 #define NVREG_MIIDELAY 5
276 NvRegMIIControl = 0x190,
277 #define NVREG_MIICTL_INUSE 0x08000
278 #define NVREG_MIICTL_WRITE 0x00400
279 #define NVREG_MIICTL_ADDRSHIFT 5
280 NvRegMIIData = 0x194,
281 NvRegTxUnicast = 0x1a0,
282 NvRegTxMulticast = 0x1a4,
283 NvRegTxBroadcast = 0x1a8,
284 NvRegWakeUpFlags = 0x200,
285 #define NVREG_WAKEUPFLAGS_VAL 0x7770
286 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
287 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
288 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
289 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
290 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
291 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
292 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
293 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
294 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
295 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
296
297 NvRegMgmtUnitGetVersion = 0x204,
298 #define NVREG_MGMTUNITGETVERSION 0x01
299 NvRegMgmtUnitVersion = 0x208,
300 #define NVREG_MGMTUNITVERSION 0x08
301 NvRegPowerCap = 0x268,
302 #define NVREG_POWERCAP_D3SUPP (1<<30)
303 #define NVREG_POWERCAP_D2SUPP (1<<26)
304 #define NVREG_POWERCAP_D1SUPP (1<<25)
305 NvRegPowerState = 0x26c,
306 #define NVREG_POWERSTATE_POWEREDUP 0x8000
307 #define NVREG_POWERSTATE_VALID 0x0100
308 #define NVREG_POWERSTATE_MASK 0x0003
309 #define NVREG_POWERSTATE_D0 0x0000
310 #define NVREG_POWERSTATE_D1 0x0001
311 #define NVREG_POWERSTATE_D2 0x0002
312 #define NVREG_POWERSTATE_D3 0x0003
313 NvRegMgmtUnitControl = 0x278,
314 #define NVREG_MGMTUNITCONTROL_INUSE 0x20000
315 NvRegTxCnt = 0x280,
316 NvRegTxZeroReXmt = 0x284,
317 NvRegTxOneReXmt = 0x288,
318 NvRegTxManyReXmt = 0x28c,
319 NvRegTxLateCol = 0x290,
320 NvRegTxUnderflow = 0x294,
321 NvRegTxLossCarrier = 0x298,
322 NvRegTxExcessDef = 0x29c,
323 NvRegTxRetryErr = 0x2a0,
324 NvRegRxFrameErr = 0x2a4,
325 NvRegRxExtraByte = 0x2a8,
326 NvRegRxLateCol = 0x2ac,
327 NvRegRxRunt = 0x2b0,
328 NvRegRxFrameTooLong = 0x2b4,
329 NvRegRxOverflow = 0x2b8,
330 NvRegRxFCSErr = 0x2bc,
331 NvRegRxFrameAlignErr = 0x2c0,
332 NvRegRxLenErr = 0x2c4,
333 NvRegRxUnicast = 0x2c8,
334 NvRegRxMulticast = 0x2cc,
335 NvRegRxBroadcast = 0x2d0,
336 NvRegTxDef = 0x2d4,
337 NvRegTxFrame = 0x2d8,
338 NvRegRxCnt = 0x2dc,
339 NvRegTxPause = 0x2e0,
340 NvRegRxPause = 0x2e4,
341 NvRegRxDropFrame = 0x2e8,
342 NvRegVlanControl = 0x300,
343 #define NVREG_VLANCONTROL_ENABLE 0x2000
344 NvRegMSIXMap0 = 0x3e0,
345 NvRegMSIXMap1 = 0x3e4,
346 NvRegMSIXIrqStatus = 0x3f0,
347
348 NvRegPowerState2 = 0x600,
349 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
350 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
351 #define NVREG_POWERSTATE2_PHY_RESET 0x0004
352 #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
353 };
354
355 /* Big endian: should work, but is untested */
356 struct ring_desc {
357 __le32 buf;
358 __le32 flaglen;
359 };
360
361 struct ring_desc_ex {
362 __le32 bufhigh;
363 __le32 buflow;
364 __le32 txvlan;
365 __le32 flaglen;
366 };
367
368 union ring_type {
369 struct ring_desc *orig;
370 struct ring_desc_ex *ex;
371 };
372
373 #define FLAG_MASK_V1 0xffff0000
374 #define FLAG_MASK_V2 0xffffc000
375 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
376 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
377
378 #define NV_TX_LASTPACKET (1<<16)
379 #define NV_TX_RETRYERROR (1<<19)
380 #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
381 #define NV_TX_FORCED_INTERRUPT (1<<24)
382 #define NV_TX_DEFERRED (1<<26)
383 #define NV_TX_CARRIERLOST (1<<27)
384 #define NV_TX_LATECOLLISION (1<<28)
385 #define NV_TX_UNDERFLOW (1<<29)
386 #define NV_TX_ERROR (1<<30)
387 #define NV_TX_VALID (1<<31)
388
389 #define NV_TX2_LASTPACKET (1<<29)
390 #define NV_TX2_RETRYERROR (1<<18)
391 #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
392 #define NV_TX2_FORCED_INTERRUPT (1<<30)
393 #define NV_TX2_DEFERRED (1<<25)
394 #define NV_TX2_CARRIERLOST (1<<26)
395 #define NV_TX2_LATECOLLISION (1<<27)
396 #define NV_TX2_UNDERFLOW (1<<28)
397 /* error and valid are the same for both */
398 #define NV_TX2_ERROR (1<<30)
399 #define NV_TX2_VALID (1<<31)
400 #define NV_TX2_TSO (1<<28)
401 #define NV_TX2_TSO_SHIFT 14
402 #define NV_TX2_TSO_MAX_SHIFT 14
403 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
404 #define NV_TX2_CHECKSUM_L3 (1<<27)
405 #define NV_TX2_CHECKSUM_L4 (1<<26)
406
407 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
408
409 #define NV_RX_DESCRIPTORVALID (1<<16)
410 #define NV_RX_MISSEDFRAME (1<<17)
411 #define NV_RX_SUBSTRACT1 (1<<18)
412 #define NV_RX_ERROR1 (1<<23)
413 #define NV_RX_ERROR2 (1<<24)
414 #define NV_RX_ERROR3 (1<<25)
415 #define NV_RX_ERROR4 (1<<26)
416 #define NV_RX_CRCERR (1<<27)
417 #define NV_RX_OVERFLOW (1<<28)
418 #define NV_RX_FRAMINGERR (1<<29)
419 #define NV_RX_ERROR (1<<30)
420 #define NV_RX_AVAIL (1<<31)
421 #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
422
423 #define NV_RX2_CHECKSUMMASK (0x1C000000)
424 #define NV_RX2_CHECKSUM_IP (0x10000000)
425 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
426 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
427 #define NV_RX2_DESCRIPTORVALID (1<<29)
428 #define NV_RX2_SUBSTRACT1 (1<<25)
429 #define NV_RX2_ERROR1 (1<<18)
430 #define NV_RX2_ERROR2 (1<<19)
431 #define NV_RX2_ERROR3 (1<<20)
432 #define NV_RX2_ERROR4 (1<<21)
433 #define NV_RX2_CRCERR (1<<22)
434 #define NV_RX2_OVERFLOW (1<<23)
435 #define NV_RX2_FRAMINGERR (1<<24)
436 /* error and avail are the same for both */
437 #define NV_RX2_ERROR (1<<30)
438 #define NV_RX2_AVAIL (1<<31)
439 #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
440
441 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
442 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
443
444 /* Miscellaneous hardware related defines: */
445 #define NV_PCI_REGSZ_VER1 0x270
446 #define NV_PCI_REGSZ_VER2 0x2d4
447 #define NV_PCI_REGSZ_VER3 0x604
448 #define NV_PCI_REGSZ_MAX 0x604
449
450 /* various timeout delays: all in usec */
451 #define NV_TXRX_RESET_DELAY 4
452 #define NV_TXSTOP_DELAY1 10
453 #define NV_TXSTOP_DELAY1MAX 500000
454 #define NV_TXSTOP_DELAY2 100
455 #define NV_RXSTOP_DELAY1 10
456 #define NV_RXSTOP_DELAY1MAX 500000
457 #define NV_RXSTOP_DELAY2 100
458 #define NV_SETUP5_DELAY 5
459 #define NV_SETUP5_DELAYMAX 50000
460 #define NV_POWERUP_DELAY 5
461 #define NV_POWERUP_DELAYMAX 5000
462 #define NV_MIIBUSY_DELAY 50
463 #define NV_MIIPHY_DELAY 10
464 #define NV_MIIPHY_DELAYMAX 10000
465 #define NV_MAC_RESET_DELAY 64
466
467 #define NV_WAKEUPPATTERNS 5
468 #define NV_WAKEUPMASKENTRIES 4
469
470 /* General driver defaults */
471 #define NV_WATCHDOG_TIMEO (5*HZ)
472
473 #define RX_RING_DEFAULT 512
474 #define TX_RING_DEFAULT 256
475 #define RX_RING_MIN 128
476 #define TX_RING_MIN 64
477 #define RING_MAX_DESC_VER_1 1024
478 #define RING_MAX_DESC_VER_2_3 16384
479
480 /* rx/tx mac addr + type + vlan + align + slack*/
481 #define NV_RX_HEADERS (64)
482 /* even more slack. */
483 #define NV_RX_ALLOC_PAD (64)
484
485 /* maximum mtu size */
486 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
487 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
488
489 #define OOM_REFILL (1+HZ/20)
490 #define POLL_WAIT (1+HZ/100)
491 #define LINK_TIMEOUT (3*HZ)
492 #define STATS_INTERVAL (10*HZ)
493
494 /*
495 * desc_ver values:
496 * The nic supports three different descriptor types:
497 * - DESC_VER_1: Original
498 * - DESC_VER_2: support for jumbo frames.
499 * - DESC_VER_3: 64-bit format.
500 */
501 #define DESC_VER_1 1
502 #define DESC_VER_2 2
503 #define DESC_VER_3 3
504
505 /* PHY defines */
506 #define PHY_OUI_MARVELL 0x5043
507 #define PHY_OUI_CICADA 0x03f1
508 #define PHY_OUI_VITESSE 0x01c1
509 #define PHY_OUI_REALTEK 0x0732
510 #define PHY_OUI_REALTEK2 0x0020
511 #define PHYID1_OUI_MASK 0x03ff
512 #define PHYID1_OUI_SHFT 6
513 #define PHYID2_OUI_MASK 0xfc00
514 #define PHYID2_OUI_SHFT 10
515 #define PHYID2_MODEL_MASK 0x03f0
516 #define PHY_MODEL_REALTEK_8211 0x0110
517 #define PHY_REV_MASK 0x0001
518 #define PHY_REV_REALTEK_8211B 0x0000
519 #define PHY_REV_REALTEK_8211C 0x0001
520 #define PHY_MODEL_REALTEK_8201 0x0200
521 #define PHY_MODEL_MARVELL_E3016 0x0220
522 #define PHY_MARVELL_E3016_INITMASK 0x0300
523 #define PHY_CICADA_INIT1 0x0f000
524 #define PHY_CICADA_INIT2 0x0e00
525 #define PHY_CICADA_INIT3 0x01000
526 #define PHY_CICADA_INIT4 0x0200
527 #define PHY_CICADA_INIT5 0x0004
528 #define PHY_CICADA_INIT6 0x02000
529 #define PHY_VITESSE_INIT_REG1 0x1f
530 #define PHY_VITESSE_INIT_REG2 0x10
531 #define PHY_VITESSE_INIT_REG3 0x11
532 #define PHY_VITESSE_INIT_REG4 0x12
533 #define PHY_VITESSE_INIT_MSK1 0xc
534 #define PHY_VITESSE_INIT_MSK2 0x0180
535 #define PHY_VITESSE_INIT1 0x52b5
536 #define PHY_VITESSE_INIT2 0xaf8a
537 #define PHY_VITESSE_INIT3 0x8
538 #define PHY_VITESSE_INIT4 0x8f8a
539 #define PHY_VITESSE_INIT5 0xaf86
540 #define PHY_VITESSE_INIT6 0x8f86
541 #define PHY_VITESSE_INIT7 0xaf82
542 #define PHY_VITESSE_INIT8 0x0100
543 #define PHY_VITESSE_INIT9 0x8f82
544 #define PHY_VITESSE_INIT10 0x0
545 #define PHY_REALTEK_INIT_REG1 0x1f
546 #define PHY_REALTEK_INIT_REG2 0x19
547 #define PHY_REALTEK_INIT_REG3 0x13
548 #define PHY_REALTEK_INIT_REG4 0x14
549 #define PHY_REALTEK_INIT_REG5 0x18
550 #define PHY_REALTEK_INIT_REG6 0x11
551 #define PHY_REALTEK_INIT_REG7 0x01
552 #define PHY_REALTEK_INIT1 0x0000
553 #define PHY_REALTEK_INIT2 0x8e00
554 #define PHY_REALTEK_INIT3 0x0001
555 #define PHY_REALTEK_INIT4 0xad17
556 #define PHY_REALTEK_INIT5 0xfb54
557 #define PHY_REALTEK_INIT6 0xf5c7
558 #define PHY_REALTEK_INIT7 0x1000
559 #define PHY_REALTEK_INIT8 0x0003
560 #define PHY_REALTEK_INIT9 0x0008
561 #define PHY_REALTEK_INIT10 0x0005
562 #define PHY_REALTEK_INIT11 0x0200
563 #define PHY_REALTEK_INIT_MSK1 0x0003
564
565 #define PHY_GIGABIT 0x0100
566
567 #define PHY_TIMEOUT 0x1
568 #define PHY_ERROR 0x2
569
570 #define PHY_100 0x1
571 #define PHY_1000 0x2
572 #define PHY_HALF 0x100
573
574 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
575 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
576 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
577 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
578 #define NV_PAUSEFRAME_RX_REQ 0x0010
579 #define NV_PAUSEFRAME_TX_REQ 0x0020
580 #define NV_PAUSEFRAME_AUTONEG 0x0040
581
582 /* MSI/MSI-X defines */
583 #define NV_MSI_X_MAX_VECTORS 8
584 #define NV_MSI_X_VECTORS_MASK 0x000f
585 #define NV_MSI_CAPABLE 0x0010
586 #define NV_MSI_X_CAPABLE 0x0020
587 #define NV_MSI_ENABLED 0x0040
588 #define NV_MSI_X_ENABLED 0x0080
589
590 #define NV_MSI_X_VECTOR_ALL 0x0
591 #define NV_MSI_X_VECTOR_RX 0x0
592 #define NV_MSI_X_VECTOR_TX 0x1
593 #define NV_MSI_X_VECTOR_OTHER 0x2
594
595 #define NV_MSI_PRIV_OFFSET 0x68
596 #define NV_MSI_PRIV_VALUE 0xffffffff
597
598 #define NV_RESTART_TX 0x1
599 #define NV_RESTART_RX 0x2
600
601 #define NV_TX_LIMIT_COUNT 16
602
603 #define NV_DYNAMIC_THRESHOLD 4
604 #define NV_DYNAMIC_MAX_QUIET_COUNT 2048
605
606 /* statistics */
607 struct nv_ethtool_str {
608 char name[ETH_GSTRING_LEN];
609 };
610
611 static const struct nv_ethtool_str nv_estats_str[] = {
612 { "tx_bytes" },
613 { "tx_zero_rexmt" },
614 { "tx_one_rexmt" },
615 { "tx_many_rexmt" },
616 { "tx_late_collision" },
617 { "tx_fifo_errors" },
618 { "tx_carrier_errors" },
619 { "tx_excess_deferral" },
620 { "tx_retry_error" },
621 { "rx_frame_error" },
622 { "rx_extra_byte" },
623 { "rx_late_collision" },
624 { "rx_runt" },
625 { "rx_frame_too_long" },
626 { "rx_over_errors" },
627 { "rx_crc_errors" },
628 { "rx_frame_align_error" },
629 { "rx_length_error" },
630 { "rx_unicast" },
631 { "rx_multicast" },
632 { "rx_broadcast" },
633 { "rx_packets" },
634 { "rx_errors_total" },
635 { "tx_errors_total" },
636
637 /* version 2 stats */
638 { "tx_deferral" },
639 { "tx_packets" },
640 { "rx_bytes" },
641 { "tx_pause" },
642 { "rx_pause" },
643 { "rx_drop_frame" },
644
645 /* version 3 stats */
646 { "tx_unicast" },
647 { "tx_multicast" },
648 { "tx_broadcast" }
649 };
650
651 struct nv_ethtool_stats {
652 u64 tx_bytes;
653 u64 tx_zero_rexmt;
654 u64 tx_one_rexmt;
655 u64 tx_many_rexmt;
656 u64 tx_late_collision;
657 u64 tx_fifo_errors;
658 u64 tx_carrier_errors;
659 u64 tx_excess_deferral;
660 u64 tx_retry_error;
661 u64 rx_frame_error;
662 u64 rx_extra_byte;
663 u64 rx_late_collision;
664 u64 rx_runt;
665 u64 rx_frame_too_long;
666 u64 rx_over_errors;
667 u64 rx_crc_errors;
668 u64 rx_frame_align_error;
669 u64 rx_length_error;
670 u64 rx_unicast;
671 u64 rx_multicast;
672 u64 rx_broadcast;
673 u64 rx_packets;
674 u64 rx_errors_total;
675 u64 tx_errors_total;
676
677 /* version 2 stats */
678 u64 tx_deferral;
679 u64 tx_packets;
680 u64 rx_bytes;
681 u64 tx_pause;
682 u64 rx_pause;
683 u64 rx_drop_frame;
684
685 /* version 3 stats */
686 u64 tx_unicast;
687 u64 tx_multicast;
688 u64 tx_broadcast;
689 };
690
691 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
692 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
693 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
694
695 /* diagnostics */
696 #define NV_TEST_COUNT_BASE 3
697 #define NV_TEST_COUNT_EXTENDED 4
698
699 static const struct nv_ethtool_str nv_etests_str[] = {
700 { "link (online/offline)" },
701 { "register (offline) " },
702 { "interrupt (offline) " },
703 { "loopback (offline) " }
704 };
705
706 struct register_test {
707 __u32 reg;
708 __u32 mask;
709 };
710
711 static const struct register_test nv_registers_test[] = {
712 { NvRegUnknownSetupReg6, 0x01 },
713 { NvRegMisc1, 0x03c },
714 { NvRegOffloadConfig, 0x03ff },
715 { NvRegMulticastAddrA, 0xffffffff },
716 { NvRegTxWatermark, 0x0ff },
717 { NvRegWakeUpFlags, 0x07777 },
718 { 0, 0 }
719 };
720
721 struct nv_skb_map {
722 struct sk_buff *skb;
723 dma_addr_t dma;
724 unsigned int dma_len:31;
725 unsigned int dma_single:1;
726 struct ring_desc_ex *first_tx_desc;
727 struct nv_skb_map *next_tx_ctx;
728 };
729
730 /*
731 * SMP locking:
732 * All hardware access under netdev_priv(dev)->lock, except the performance
733 * critical parts:
734 * - rx is (pseudo-) lockless: it relies on the single-threading provided
735 * by the arch code for interrupts.
736 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
737 * needs netdev_priv(dev)->lock :-(
738 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
739 */
740
741 /* in dev: base, irq */
742 struct fe_priv {
743 spinlock_t lock;
744
745 struct net_device *dev;
746 struct napi_struct napi;
747
748 /* General data:
749 * Locking: spin_lock(&np->lock); */
750 struct nv_ethtool_stats estats;
751 int in_shutdown;
752 u32 linkspeed;
753 int duplex;
754 int autoneg;
755 int fixed_mode;
756 int phyaddr;
757 int wolenabled;
758 unsigned int phy_oui;
759 unsigned int phy_model;
760 unsigned int phy_rev;
761 u16 gigabit;
762 int intr_test;
763 int recover_error;
764 int quiet_count;
765
766 /* General data: RO fields */
767 dma_addr_t ring_addr;
768 struct pci_dev *pci_dev;
769 u32 orig_mac[2];
770 u32 events;
771 u32 irqmask;
772 u32 desc_ver;
773 u32 txrxctl_bits;
774 u32 vlanctl_bits;
775 u32 driver_data;
776 u32 device_id;
777 u32 register_size;
778 u32 mac_in_use;
779 int mgmt_version;
780 int mgmt_sema;
781
782 void __iomem *base;
783
784 /* rx specific fields.
785 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
786 */
787 union ring_type get_rx, put_rx, first_rx, last_rx;
788 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
789 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
790 struct nv_skb_map *rx_skb;
791
792 union ring_type rx_ring;
793 unsigned int rx_buf_sz;
794 unsigned int pkt_limit;
795 struct timer_list oom_kick;
796 struct timer_list nic_poll;
797 struct timer_list stats_poll;
798 u32 nic_poll_irq;
799 int rx_ring_size;
800
801 /* media detection workaround.
802 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
803 */
804 int need_linktimer;
805 unsigned long link_timeout;
806 /*
807 * tx specific fields.
808 */
809 union ring_type get_tx, put_tx, first_tx, last_tx;
810 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
811 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
812 struct nv_skb_map *tx_skb;
813
814 union ring_type tx_ring;
815 u32 tx_flags;
816 int tx_ring_size;
817 int tx_limit;
818 u32 tx_pkts_in_progress;
819 struct nv_skb_map *tx_change_owner;
820 struct nv_skb_map *tx_end_flip;
821 int tx_stop;
822
823 /* msi/msi-x fields */
824 u32 msi_flags;
825 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
826
827 /* flow control */
828 u32 pause_flags;
829
830 /* power saved state */
831 u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
832
833 /* for different msi-x irq type */
834 char name_rx[IFNAMSIZ + 3]; /* -rx */
835 char name_tx[IFNAMSIZ + 3]; /* -tx */
836 char name_other[IFNAMSIZ + 6]; /* -other */
837 };
838
839 /*
840 * Maximum number of loops until we assume that a bit in the irq mask
841 * is stuck. Overridable with module param.
842 */
843 static int max_interrupt_work = 4;
844
845 /*
846 * Optimization can be either throuput mode or cpu mode
847 *
848 * Throughput Mode: Every tx and rx packet will generate an interrupt.
849 * CPU Mode: Interrupts are controlled by a timer.
850 */
851 enum {
852 NV_OPTIMIZATION_MODE_THROUGHPUT,
853 NV_OPTIMIZATION_MODE_CPU,
854 NV_OPTIMIZATION_MODE_DYNAMIC
855 };
856 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
857
858 /*
859 * Poll interval for timer irq
860 *
861 * This interval determines how frequent an interrupt is generated.
862 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
863 * Min = 0, and Max = 65535
864 */
865 static int poll_interval = -1;
866
867 /*
868 * MSI interrupts
869 */
870 enum {
871 NV_MSI_INT_DISABLED,
872 NV_MSI_INT_ENABLED
873 };
874 static int msi = NV_MSI_INT_ENABLED;
875
876 /*
877 * MSIX interrupts
878 */
879 enum {
880 NV_MSIX_INT_DISABLED,
881 NV_MSIX_INT_ENABLED
882 };
883 static int msix = NV_MSIX_INT_ENABLED;
884
885 /*
886 * DMA 64bit
887 */
888 enum {
889 NV_DMA_64BIT_DISABLED,
890 NV_DMA_64BIT_ENABLED
891 };
892 static int dma_64bit = NV_DMA_64BIT_ENABLED;
893
894 /*
895 * Crossover Detection
896 * Realtek 8201 phy + some OEM boards do not work properly.
897 */
898 enum {
899 NV_CROSSOVER_DETECTION_DISABLED,
900 NV_CROSSOVER_DETECTION_ENABLED
901 };
902 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
903
904 /*
905 * Power down phy when interface is down (persists through reboot;
906 * older Linux and other OSes may not power it up again)
907 */
908 static int phy_power_down;
909
910 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
911 {
912 return netdev_priv(dev);
913 }
914
915 static inline u8 __iomem *get_hwbase(struct net_device *dev)
916 {
917 return ((struct fe_priv *)netdev_priv(dev))->base;
918 }
919
920 static inline void pci_push(u8 __iomem *base)
921 {
922 /* force out pending posted writes */
923 readl(base);
924 }
925
926 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
927 {
928 return le32_to_cpu(prd->flaglen)
929 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
930 }
931
932 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
933 {
934 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
935 }
936
937 static bool nv_optimized(struct fe_priv *np)
938 {
939 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
940 return false;
941 return true;
942 }
943
944 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
945 int delay, int delaymax)
946 {
947 u8 __iomem *base = get_hwbase(dev);
948
949 pci_push(base);
950 do {
951 udelay(delay);
952 delaymax -= delay;
953 if (delaymax < 0)
954 return 1;
955 } while ((readl(base + offset) & mask) != target);
956 return 0;
957 }
958
959 #define NV_SETUP_RX_RING 0x01
960 #define NV_SETUP_TX_RING 0x02
961
962 static inline u32 dma_low(dma_addr_t addr)
963 {
964 return addr;
965 }
966
967 static inline u32 dma_high(dma_addr_t addr)
968 {
969 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
970 }
971
972 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
973 {
974 struct fe_priv *np = get_nvpriv(dev);
975 u8 __iomem *base = get_hwbase(dev);
976
977 if (!nv_optimized(np)) {
978 if (rxtx_flags & NV_SETUP_RX_RING)
979 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
980 if (rxtx_flags & NV_SETUP_TX_RING)
981 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
982 } else {
983 if (rxtx_flags & NV_SETUP_RX_RING) {
984 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
985 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
986 }
987 if (rxtx_flags & NV_SETUP_TX_RING) {
988 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
989 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
990 }
991 }
992 }
993
994 static void free_rings(struct net_device *dev)
995 {
996 struct fe_priv *np = get_nvpriv(dev);
997
998 if (!nv_optimized(np)) {
999 if (np->rx_ring.orig)
1000 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1001 np->rx_ring.orig, np->ring_addr);
1002 } else {
1003 if (np->rx_ring.ex)
1004 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1005 np->rx_ring.ex, np->ring_addr);
1006 }
1007 kfree(np->rx_skb);
1008 kfree(np->tx_skb);
1009 }
1010
1011 static int using_multi_irqs(struct net_device *dev)
1012 {
1013 struct fe_priv *np = get_nvpriv(dev);
1014
1015 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1016 ((np->msi_flags & NV_MSI_X_ENABLED) &&
1017 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1018 return 0;
1019 else
1020 return 1;
1021 }
1022
1023 static void nv_txrx_gate(struct net_device *dev, bool gate)
1024 {
1025 struct fe_priv *np = get_nvpriv(dev);
1026 u8 __iomem *base = get_hwbase(dev);
1027 u32 powerstate;
1028
1029 if (!np->mac_in_use &&
1030 (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1031 powerstate = readl(base + NvRegPowerState2);
1032 if (gate)
1033 powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1034 else
1035 powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1036 writel(powerstate, base + NvRegPowerState2);
1037 }
1038 }
1039
1040 static void nv_enable_irq(struct net_device *dev)
1041 {
1042 struct fe_priv *np = get_nvpriv(dev);
1043
1044 if (!using_multi_irqs(dev)) {
1045 if (np->msi_flags & NV_MSI_X_ENABLED)
1046 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1047 else
1048 enable_irq(np->pci_dev->irq);
1049 } else {
1050 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1051 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1052 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1053 }
1054 }
1055
1056 static void nv_disable_irq(struct net_device *dev)
1057 {
1058 struct fe_priv *np = get_nvpriv(dev);
1059
1060 if (!using_multi_irqs(dev)) {
1061 if (np->msi_flags & NV_MSI_X_ENABLED)
1062 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1063 else
1064 disable_irq(np->pci_dev->irq);
1065 } else {
1066 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1067 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1068 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1069 }
1070 }
1071
1072 /* In MSIX mode, a write to irqmask behaves as XOR */
1073 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1074 {
1075 u8 __iomem *base = get_hwbase(dev);
1076
1077 writel(mask, base + NvRegIrqMask);
1078 }
1079
1080 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1081 {
1082 struct fe_priv *np = get_nvpriv(dev);
1083 u8 __iomem *base = get_hwbase(dev);
1084
1085 if (np->msi_flags & NV_MSI_X_ENABLED) {
1086 writel(mask, base + NvRegIrqMask);
1087 } else {
1088 if (np->msi_flags & NV_MSI_ENABLED)
1089 writel(0, base + NvRegMSIIrqMask);
1090 writel(0, base + NvRegIrqMask);
1091 }
1092 }
1093
1094 static void nv_napi_enable(struct net_device *dev)
1095 {
1096 struct fe_priv *np = get_nvpriv(dev);
1097
1098 napi_enable(&np->napi);
1099 }
1100
1101 static void nv_napi_disable(struct net_device *dev)
1102 {
1103 struct fe_priv *np = get_nvpriv(dev);
1104
1105 napi_disable(&np->napi);
1106 }
1107
1108 #define MII_READ (-1)
1109 /* mii_rw: read/write a register on the PHY.
1110 *
1111 * Caller must guarantee serialization
1112 */
1113 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1114 {
1115 u8 __iomem *base = get_hwbase(dev);
1116 u32 reg;
1117 int retval;
1118
1119 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1120
1121 reg = readl(base + NvRegMIIControl);
1122 if (reg & NVREG_MIICTL_INUSE) {
1123 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1124 udelay(NV_MIIBUSY_DELAY);
1125 }
1126
1127 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1128 if (value != MII_READ) {
1129 writel(value, base + NvRegMIIData);
1130 reg |= NVREG_MIICTL_WRITE;
1131 }
1132 writel(reg, base + NvRegMIIControl);
1133
1134 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1135 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
1136 retval = -1;
1137 } else if (value != MII_READ) {
1138 /* it was a write operation - fewer failures are detectable */
1139 retval = 0;
1140 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1141 retval = -1;
1142 } else {
1143 retval = readl(base + NvRegMIIData);
1144 }
1145
1146 return retval;
1147 }
1148
1149 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1150 {
1151 struct fe_priv *np = netdev_priv(dev);
1152 u32 miicontrol;
1153 unsigned int tries = 0;
1154
1155 miicontrol = BMCR_RESET | bmcr_setup;
1156 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
1157 return -1;
1158
1159 /* wait for 500ms */
1160 msleep(500);
1161
1162 /* must wait till reset is deasserted */
1163 while (miicontrol & BMCR_RESET) {
1164 usleep_range(10000, 20000);
1165 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1166 /* FIXME: 100 tries seem excessive */
1167 if (tries++ > 100)
1168 return -1;
1169 }
1170 return 0;
1171 }
1172
1173 static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1174 {
1175 static const struct {
1176 int reg;
1177 int init;
1178 } ri[] = {
1179 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1180 { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
1181 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
1182 { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
1183 { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
1184 { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
1185 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1186 };
1187 int i;
1188
1189 for (i = 0; i < ARRAY_SIZE(ri); i++) {
1190 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
1191 return PHY_ERROR;
1192 }
1193
1194 return 0;
1195 }
1196
1197 static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
1198 {
1199 u32 reg;
1200 u8 __iomem *base = get_hwbase(dev);
1201 u32 powerstate = readl(base + NvRegPowerState2);
1202
1203 /* need to perform hw phy reset */
1204 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1205 writel(powerstate, base + NvRegPowerState2);
1206 msleep(25);
1207
1208 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1209 writel(powerstate, base + NvRegPowerState2);
1210 msleep(25);
1211
1212 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1213 reg |= PHY_REALTEK_INIT9;
1214 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1215 return PHY_ERROR;
1216 if (mii_rw(dev, np->phyaddr,
1217 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
1218 return PHY_ERROR;
1219 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1220 if (!(reg & PHY_REALTEK_INIT11)) {
1221 reg |= PHY_REALTEK_INIT11;
1222 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1223 return PHY_ERROR;
1224 }
1225 if (mii_rw(dev, np->phyaddr,
1226 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1227 return PHY_ERROR;
1228
1229 return 0;
1230 }
1231
1232 static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
1233 {
1234 u32 phy_reserved;
1235
1236 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1237 phy_reserved = mii_rw(dev, np->phyaddr,
1238 PHY_REALTEK_INIT_REG6, MII_READ);
1239 phy_reserved |= PHY_REALTEK_INIT7;
1240 if (mii_rw(dev, np->phyaddr,
1241 PHY_REALTEK_INIT_REG6, phy_reserved))
1242 return PHY_ERROR;
1243 }
1244
1245 return 0;
1246 }
1247
1248 static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
1249 {
1250 u32 phy_reserved;
1251
1252 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1253 if (mii_rw(dev, np->phyaddr,
1254 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
1255 return PHY_ERROR;
1256 phy_reserved = mii_rw(dev, np->phyaddr,
1257 PHY_REALTEK_INIT_REG2, MII_READ);
1258 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1259 phy_reserved |= PHY_REALTEK_INIT3;
1260 if (mii_rw(dev, np->phyaddr,
1261 PHY_REALTEK_INIT_REG2, phy_reserved))
1262 return PHY_ERROR;
1263 if (mii_rw(dev, np->phyaddr,
1264 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1265 return PHY_ERROR;
1266 }
1267
1268 return 0;
1269 }
1270
1271 static int init_cicada(struct net_device *dev, struct fe_priv *np,
1272 u32 phyinterface)
1273 {
1274 u32 phy_reserved;
1275
1276 if (phyinterface & PHY_RGMII) {
1277 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1278 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1279 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1280 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1281 return PHY_ERROR;
1282 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1283 phy_reserved |= PHY_CICADA_INIT5;
1284 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1285 return PHY_ERROR;
1286 }
1287 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1288 phy_reserved |= PHY_CICADA_INIT6;
1289 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1290 return PHY_ERROR;
1291
1292 return 0;
1293 }
1294
1295 static int init_vitesse(struct net_device *dev, struct fe_priv *np)
1296 {
1297 u32 phy_reserved;
1298
1299 if (mii_rw(dev, np->phyaddr,
1300 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
1301 return PHY_ERROR;
1302 if (mii_rw(dev, np->phyaddr,
1303 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
1304 return PHY_ERROR;
1305 phy_reserved = mii_rw(dev, np->phyaddr,
1306 PHY_VITESSE_INIT_REG4, MII_READ);
1307 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1308 return PHY_ERROR;
1309 phy_reserved = mii_rw(dev, np->phyaddr,
1310 PHY_VITESSE_INIT_REG3, MII_READ);
1311 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1312 phy_reserved |= PHY_VITESSE_INIT3;
1313 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1314 return PHY_ERROR;
1315 if (mii_rw(dev, np->phyaddr,
1316 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
1317 return PHY_ERROR;
1318 if (mii_rw(dev, np->phyaddr,
1319 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
1320 return PHY_ERROR;
1321 phy_reserved = mii_rw(dev, np->phyaddr,
1322 PHY_VITESSE_INIT_REG4, MII_READ);
1323 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1324 phy_reserved |= PHY_VITESSE_INIT3;
1325 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1326 return PHY_ERROR;
1327 phy_reserved = mii_rw(dev, np->phyaddr,
1328 PHY_VITESSE_INIT_REG3, MII_READ);
1329 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1330 return PHY_ERROR;
1331 if (mii_rw(dev, np->phyaddr,
1332 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
1333 return PHY_ERROR;
1334 if (mii_rw(dev, np->phyaddr,
1335 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
1336 return PHY_ERROR;
1337 phy_reserved = mii_rw(dev, np->phyaddr,
1338 PHY_VITESSE_INIT_REG4, MII_READ);
1339 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1340 return PHY_ERROR;
1341 phy_reserved = mii_rw(dev, np->phyaddr,
1342 PHY_VITESSE_INIT_REG3, MII_READ);
1343 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1344 phy_reserved |= PHY_VITESSE_INIT8;
1345 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1346 return PHY_ERROR;
1347 if (mii_rw(dev, np->phyaddr,
1348 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
1349 return PHY_ERROR;
1350 if (mii_rw(dev, np->phyaddr,
1351 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
1352 return PHY_ERROR;
1353
1354 return 0;
1355 }
1356
1357 static int phy_init(struct net_device *dev)
1358 {
1359 struct fe_priv *np = get_nvpriv(dev);
1360 u8 __iomem *base = get_hwbase(dev);
1361 u32 phyinterface;
1362 u32 mii_status, mii_control, mii_control_1000, reg;
1363
1364 /* phy errata for E3016 phy */
1365 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1366 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1367 reg &= ~PHY_MARVELL_E3016_INITMASK;
1368 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1369 netdev_info(dev, "%s: phy write to errata reg failed\n",
1370 pci_name(np->pci_dev));
1371 return PHY_ERROR;
1372 }
1373 }
1374 if (np->phy_oui == PHY_OUI_REALTEK) {
1375 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1376 np->phy_rev == PHY_REV_REALTEK_8211B) {
1377 if (init_realtek_8211b(dev, np)) {
1378 netdev_info(dev, "%s: phy init failed\n",
1379 pci_name(np->pci_dev));
1380 return PHY_ERROR;
1381 }
1382 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1383 np->phy_rev == PHY_REV_REALTEK_8211C) {
1384 if (init_realtek_8211c(dev, np)) {
1385 netdev_info(dev, "%s: phy init failed\n",
1386 pci_name(np->pci_dev));
1387 return PHY_ERROR;
1388 }
1389 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1390 if (init_realtek_8201(dev, np)) {
1391 netdev_info(dev, "%s: phy init failed\n",
1392 pci_name(np->pci_dev));
1393 return PHY_ERROR;
1394 }
1395 }
1396 }
1397
1398 /* set advertise register */
1399 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1400 reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1401 ADVERTISE_100HALF | ADVERTISE_100FULL |
1402 ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1403 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1404 netdev_info(dev, "%s: phy write to advertise failed\n",
1405 pci_name(np->pci_dev));
1406 return PHY_ERROR;
1407 }
1408
1409 /* get phy interface type */
1410 phyinterface = readl(base + NvRegPhyInterface);
1411
1412 /* see if gigabit phy */
1413 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1414 if (mii_status & PHY_GIGABIT) {
1415 np->gigabit = PHY_GIGABIT;
1416 mii_control_1000 = mii_rw(dev, np->phyaddr,
1417 MII_CTRL1000, MII_READ);
1418 mii_control_1000 &= ~ADVERTISE_1000HALF;
1419 if (phyinterface & PHY_RGMII)
1420 mii_control_1000 |= ADVERTISE_1000FULL;
1421 else
1422 mii_control_1000 &= ~ADVERTISE_1000FULL;
1423
1424 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1425 netdev_info(dev, "%s: phy init failed\n",
1426 pci_name(np->pci_dev));
1427 return PHY_ERROR;
1428 }
1429 } else
1430 np->gigabit = 0;
1431
1432 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1433 mii_control |= BMCR_ANENABLE;
1434
1435 if (np->phy_oui == PHY_OUI_REALTEK &&
1436 np->phy_model == PHY_MODEL_REALTEK_8211 &&
1437 np->phy_rev == PHY_REV_REALTEK_8211C) {
1438 /* start autoneg since we already performed hw reset above */
1439 mii_control |= BMCR_ANRESTART;
1440 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1441 netdev_info(dev, "%s: phy init failed\n",
1442 pci_name(np->pci_dev));
1443 return PHY_ERROR;
1444 }
1445 } else {
1446 /* reset the phy
1447 * (certain phys need bmcr to be setup with reset)
1448 */
1449 if (phy_reset(dev, mii_control)) {
1450 netdev_info(dev, "%s: phy reset failed\n",
1451 pci_name(np->pci_dev));
1452 return PHY_ERROR;
1453 }
1454 }
1455
1456 /* phy vendor specific configuration */
1457 if ((np->phy_oui == PHY_OUI_CICADA)) {
1458 if (init_cicada(dev, np, phyinterface)) {
1459 netdev_info(dev, "%s: phy init failed\n",
1460 pci_name(np->pci_dev));
1461 return PHY_ERROR;
1462 }
1463 } else if (np->phy_oui == PHY_OUI_VITESSE) {
1464 if (init_vitesse(dev, np)) {
1465 netdev_info(dev, "%s: phy init failed\n",
1466 pci_name(np->pci_dev));
1467 return PHY_ERROR;
1468 }
1469 } else if (np->phy_oui == PHY_OUI_REALTEK) {
1470 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1471 np->phy_rev == PHY_REV_REALTEK_8211B) {
1472 /* reset could have cleared these out, set them back */
1473 if (init_realtek_8211b(dev, np)) {
1474 netdev_info(dev, "%s: phy init failed\n",
1475 pci_name(np->pci_dev));
1476 return PHY_ERROR;
1477 }
1478 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1479 if (init_realtek_8201(dev, np) ||
1480 init_realtek_8201_cross(dev, np)) {
1481 netdev_info(dev, "%s: phy init failed\n",
1482 pci_name(np->pci_dev));
1483 return PHY_ERROR;
1484 }
1485 }
1486 }
1487
1488 /* some phys clear out pause advertisement on reset, set it back */
1489 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1490
1491 /* restart auto negotiation, power down phy */
1492 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1493 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1494 if (phy_power_down)
1495 mii_control |= BMCR_PDOWN;
1496 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
1497 return PHY_ERROR;
1498
1499 return 0;
1500 }
1501
1502 static void nv_start_rx(struct net_device *dev)
1503 {
1504 struct fe_priv *np = netdev_priv(dev);
1505 u8 __iomem *base = get_hwbase(dev);
1506 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1507
1508 /* Already running? Stop it. */
1509 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1510 rx_ctrl &= ~NVREG_RCVCTL_START;
1511 writel(rx_ctrl, base + NvRegReceiverControl);
1512 pci_push(base);
1513 }
1514 writel(np->linkspeed, base + NvRegLinkSpeed);
1515 pci_push(base);
1516 rx_ctrl |= NVREG_RCVCTL_START;
1517 if (np->mac_in_use)
1518 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1519 writel(rx_ctrl, base + NvRegReceiverControl);
1520 pci_push(base);
1521 }
1522
1523 static void nv_stop_rx(struct net_device *dev)
1524 {
1525 struct fe_priv *np = netdev_priv(dev);
1526 u8 __iomem *base = get_hwbase(dev);
1527 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1528
1529 if (!np->mac_in_use)
1530 rx_ctrl &= ~NVREG_RCVCTL_START;
1531 else
1532 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1533 writel(rx_ctrl, base + NvRegReceiverControl);
1534 if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1535 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
1536 netdev_info(dev, "%s: ReceiverStatus remained busy\n",
1537 __func__);
1538
1539 udelay(NV_RXSTOP_DELAY2);
1540 if (!np->mac_in_use)
1541 writel(0, base + NvRegLinkSpeed);
1542 }
1543
1544 static void nv_start_tx(struct net_device *dev)
1545 {
1546 struct fe_priv *np = netdev_priv(dev);
1547 u8 __iomem *base = get_hwbase(dev);
1548 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1549
1550 tx_ctrl |= NVREG_XMITCTL_START;
1551 if (np->mac_in_use)
1552 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1553 writel(tx_ctrl, base + NvRegTransmitterControl);
1554 pci_push(base);
1555 }
1556
1557 static void nv_stop_tx(struct net_device *dev)
1558 {
1559 struct fe_priv *np = netdev_priv(dev);
1560 u8 __iomem *base = get_hwbase(dev);
1561 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1562
1563 if (!np->mac_in_use)
1564 tx_ctrl &= ~NVREG_XMITCTL_START;
1565 else
1566 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1567 writel(tx_ctrl, base + NvRegTransmitterControl);
1568 if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1569 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
1570 netdev_info(dev, "%s: TransmitterStatus remained busy\n",
1571 __func__);
1572
1573 udelay(NV_TXSTOP_DELAY2);
1574 if (!np->mac_in_use)
1575 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1576 base + NvRegTransmitPoll);
1577 }
1578
1579 static void nv_start_rxtx(struct net_device *dev)
1580 {
1581 nv_start_rx(dev);
1582 nv_start_tx(dev);
1583 }
1584
1585 static void nv_stop_rxtx(struct net_device *dev)
1586 {
1587 nv_stop_rx(dev);
1588 nv_stop_tx(dev);
1589 }
1590
1591 static void nv_txrx_reset(struct net_device *dev)
1592 {
1593 struct fe_priv *np = netdev_priv(dev);
1594 u8 __iomem *base = get_hwbase(dev);
1595
1596 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1597 pci_push(base);
1598 udelay(NV_TXRX_RESET_DELAY);
1599 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1600 pci_push(base);
1601 }
1602
1603 static void nv_mac_reset(struct net_device *dev)
1604 {
1605 struct fe_priv *np = netdev_priv(dev);
1606 u8 __iomem *base = get_hwbase(dev);
1607 u32 temp1, temp2, temp3;
1608
1609 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1610 pci_push(base);
1611
1612 /* save registers since they will be cleared on reset */
1613 temp1 = readl(base + NvRegMacAddrA);
1614 temp2 = readl(base + NvRegMacAddrB);
1615 temp3 = readl(base + NvRegTransmitPoll);
1616
1617 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1618 pci_push(base);
1619 udelay(NV_MAC_RESET_DELAY);
1620 writel(0, base + NvRegMacReset);
1621 pci_push(base);
1622 udelay(NV_MAC_RESET_DELAY);
1623
1624 /* restore saved registers */
1625 writel(temp1, base + NvRegMacAddrA);
1626 writel(temp2, base + NvRegMacAddrB);
1627 writel(temp3, base + NvRegTransmitPoll);
1628
1629 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1630 pci_push(base);
1631 }
1632
1633 static void nv_get_hw_stats(struct net_device *dev)
1634 {
1635 struct fe_priv *np = netdev_priv(dev);
1636 u8 __iomem *base = get_hwbase(dev);
1637
1638 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1639 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1640 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1641 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1642 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1643 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1644 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1645 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1646 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1647 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1648 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1649 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1650 np->estats.rx_runt += readl(base + NvRegRxRunt);
1651 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1652 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1653 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1654 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1655 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1656 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1657 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1658 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1659 np->estats.rx_packets =
1660 np->estats.rx_unicast +
1661 np->estats.rx_multicast +
1662 np->estats.rx_broadcast;
1663 np->estats.rx_errors_total =
1664 np->estats.rx_crc_errors +
1665 np->estats.rx_over_errors +
1666 np->estats.rx_frame_error +
1667 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1668 np->estats.rx_late_collision +
1669 np->estats.rx_runt +
1670 np->estats.rx_frame_too_long;
1671 np->estats.tx_errors_total =
1672 np->estats.tx_late_collision +
1673 np->estats.tx_fifo_errors +
1674 np->estats.tx_carrier_errors +
1675 np->estats.tx_excess_deferral +
1676 np->estats.tx_retry_error;
1677
1678 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1679 np->estats.tx_deferral += readl(base + NvRegTxDef);
1680 np->estats.tx_packets += readl(base + NvRegTxFrame);
1681 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1682 np->estats.tx_pause += readl(base + NvRegTxPause);
1683 np->estats.rx_pause += readl(base + NvRegRxPause);
1684 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1685 np->estats.rx_errors_total += np->estats.rx_drop_frame;
1686 }
1687
1688 if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1689 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1690 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1691 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1692 }
1693 }
1694
1695 /*
1696 * nv_get_stats: dev->get_stats function
1697 * Get latest stats value from the nic.
1698 * Called with read_lock(&dev_base_lock) held for read -
1699 * only synchronized against unregister_netdevice.
1700 */
1701 static struct net_device_stats *nv_get_stats(struct net_device *dev)
1702 {
1703 struct fe_priv *np = netdev_priv(dev);
1704
1705 /* If the nic supports hw counters then retrieve latest values */
1706 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3)) {
1707 nv_get_hw_stats(dev);
1708
1709 /* copy to net_device stats */
1710 dev->stats.tx_packets = np->estats.tx_packets;
1711 dev->stats.rx_bytes = np->estats.rx_bytes;
1712 dev->stats.tx_bytes = np->estats.tx_bytes;
1713 dev->stats.tx_fifo_errors = np->estats.tx_fifo_errors;
1714 dev->stats.tx_carrier_errors = np->estats.tx_carrier_errors;
1715 dev->stats.rx_crc_errors = np->estats.rx_crc_errors;
1716 dev->stats.rx_over_errors = np->estats.rx_over_errors;
1717 dev->stats.rx_fifo_errors = np->estats.rx_drop_frame;
1718 dev->stats.rx_errors = np->estats.rx_errors_total;
1719 dev->stats.tx_errors = np->estats.tx_errors_total;
1720 }
1721
1722 return &dev->stats;
1723 }
1724
1725 /*
1726 * nv_alloc_rx: fill rx ring entries.
1727 * Return 1 if the allocations for the skbs failed and the
1728 * rx engine is without Available descriptors
1729 */
1730 static int nv_alloc_rx(struct net_device *dev)
1731 {
1732 struct fe_priv *np = netdev_priv(dev);
1733 struct ring_desc *less_rx;
1734
1735 less_rx = np->get_rx.orig;
1736 if (less_rx-- == np->first_rx.orig)
1737 less_rx = np->last_rx.orig;
1738
1739 while (np->put_rx.orig != less_rx) {
1740 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1741 if (skb) {
1742 np->put_rx_ctx->skb = skb;
1743 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1744 skb->data,
1745 skb_tailroom(skb),
1746 PCI_DMA_FROMDEVICE);
1747 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1748 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1749 wmb();
1750 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1751 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1752 np->put_rx.orig = np->first_rx.orig;
1753 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1754 np->put_rx_ctx = np->first_rx_ctx;
1755 } else
1756 return 1;
1757 }
1758 return 0;
1759 }
1760
1761 static int nv_alloc_rx_optimized(struct net_device *dev)
1762 {
1763 struct fe_priv *np = netdev_priv(dev);
1764 struct ring_desc_ex *less_rx;
1765
1766 less_rx = np->get_rx.ex;
1767 if (less_rx-- == np->first_rx.ex)
1768 less_rx = np->last_rx.ex;
1769
1770 while (np->put_rx.ex != less_rx) {
1771 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz + NV_RX_ALLOC_PAD);
1772 if (skb) {
1773 np->put_rx_ctx->skb = skb;
1774 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1775 skb->data,
1776 skb_tailroom(skb),
1777 PCI_DMA_FROMDEVICE);
1778 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1779 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1780 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1781 wmb();
1782 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1783 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1784 np->put_rx.ex = np->first_rx.ex;
1785 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1786 np->put_rx_ctx = np->first_rx_ctx;
1787 } else
1788 return 1;
1789 }
1790 return 0;
1791 }
1792
1793 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1794 static void nv_do_rx_refill(unsigned long data)
1795 {
1796 struct net_device *dev = (struct net_device *) data;
1797 struct fe_priv *np = netdev_priv(dev);
1798
1799 /* Just reschedule NAPI rx processing */
1800 napi_schedule(&np->napi);
1801 }
1802
1803 static void nv_init_rx(struct net_device *dev)
1804 {
1805 struct fe_priv *np = netdev_priv(dev);
1806 int i;
1807
1808 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1809
1810 if (!nv_optimized(np))
1811 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1812 else
1813 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1814 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1815 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1816
1817 for (i = 0; i < np->rx_ring_size; i++) {
1818 if (!nv_optimized(np)) {
1819 np->rx_ring.orig[i].flaglen = 0;
1820 np->rx_ring.orig[i].buf = 0;
1821 } else {
1822 np->rx_ring.ex[i].flaglen = 0;
1823 np->rx_ring.ex[i].txvlan = 0;
1824 np->rx_ring.ex[i].bufhigh = 0;
1825 np->rx_ring.ex[i].buflow = 0;
1826 }
1827 np->rx_skb[i].skb = NULL;
1828 np->rx_skb[i].dma = 0;
1829 }
1830 }
1831
1832 static void nv_init_tx(struct net_device *dev)
1833 {
1834 struct fe_priv *np = netdev_priv(dev);
1835 int i;
1836
1837 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1838
1839 if (!nv_optimized(np))
1840 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1841 else
1842 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1843 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1844 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1845 np->tx_pkts_in_progress = 0;
1846 np->tx_change_owner = NULL;
1847 np->tx_end_flip = NULL;
1848 np->tx_stop = 0;
1849
1850 for (i = 0; i < np->tx_ring_size; i++) {
1851 if (!nv_optimized(np)) {
1852 np->tx_ring.orig[i].flaglen = 0;
1853 np->tx_ring.orig[i].buf = 0;
1854 } else {
1855 np->tx_ring.ex[i].flaglen = 0;
1856 np->tx_ring.ex[i].txvlan = 0;
1857 np->tx_ring.ex[i].bufhigh = 0;
1858 np->tx_ring.ex[i].buflow = 0;
1859 }
1860 np->tx_skb[i].skb = NULL;
1861 np->tx_skb[i].dma = 0;
1862 np->tx_skb[i].dma_len = 0;
1863 np->tx_skb[i].dma_single = 0;
1864 np->tx_skb[i].first_tx_desc = NULL;
1865 np->tx_skb[i].next_tx_ctx = NULL;
1866 }
1867 }
1868
1869 static int nv_init_ring(struct net_device *dev)
1870 {
1871 struct fe_priv *np = netdev_priv(dev);
1872
1873 nv_init_tx(dev);
1874 nv_init_rx(dev);
1875
1876 if (!nv_optimized(np))
1877 return nv_alloc_rx(dev);
1878 else
1879 return nv_alloc_rx_optimized(dev);
1880 }
1881
1882 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1883 {
1884 if (tx_skb->dma) {
1885 if (tx_skb->dma_single)
1886 pci_unmap_single(np->pci_dev, tx_skb->dma,
1887 tx_skb->dma_len,
1888 PCI_DMA_TODEVICE);
1889 else
1890 pci_unmap_page(np->pci_dev, tx_skb->dma,
1891 tx_skb->dma_len,
1892 PCI_DMA_TODEVICE);
1893 tx_skb->dma = 0;
1894 }
1895 }
1896
1897 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1898 {
1899 nv_unmap_txskb(np, tx_skb);
1900 if (tx_skb->skb) {
1901 dev_kfree_skb_any(tx_skb->skb);
1902 tx_skb->skb = NULL;
1903 return 1;
1904 }
1905 return 0;
1906 }
1907
1908 static void nv_drain_tx(struct net_device *dev)
1909 {
1910 struct fe_priv *np = netdev_priv(dev);
1911 unsigned int i;
1912
1913 for (i = 0; i < np->tx_ring_size; i++) {
1914 if (!nv_optimized(np)) {
1915 np->tx_ring.orig[i].flaglen = 0;
1916 np->tx_ring.orig[i].buf = 0;
1917 } else {
1918 np->tx_ring.ex[i].flaglen = 0;
1919 np->tx_ring.ex[i].txvlan = 0;
1920 np->tx_ring.ex[i].bufhigh = 0;
1921 np->tx_ring.ex[i].buflow = 0;
1922 }
1923 if (nv_release_txskb(np, &np->tx_skb[i]))
1924 dev->stats.tx_dropped++;
1925 np->tx_skb[i].dma = 0;
1926 np->tx_skb[i].dma_len = 0;
1927 np->tx_skb[i].dma_single = 0;
1928 np->tx_skb[i].first_tx_desc = NULL;
1929 np->tx_skb[i].next_tx_ctx = NULL;
1930 }
1931 np->tx_pkts_in_progress = 0;
1932 np->tx_change_owner = NULL;
1933 np->tx_end_flip = NULL;
1934 }
1935
1936 static void nv_drain_rx(struct net_device *dev)
1937 {
1938 struct fe_priv *np = netdev_priv(dev);
1939 int i;
1940
1941 for (i = 0; i < np->rx_ring_size; i++) {
1942 if (!nv_optimized(np)) {
1943 np->rx_ring.orig[i].flaglen = 0;
1944 np->rx_ring.orig[i].buf = 0;
1945 } else {
1946 np->rx_ring.ex[i].flaglen = 0;
1947 np->rx_ring.ex[i].txvlan = 0;
1948 np->rx_ring.ex[i].bufhigh = 0;
1949 np->rx_ring.ex[i].buflow = 0;
1950 }
1951 wmb();
1952 if (np->rx_skb[i].skb) {
1953 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
1954 (skb_end_pointer(np->rx_skb[i].skb) -
1955 np->rx_skb[i].skb->data),
1956 PCI_DMA_FROMDEVICE);
1957 dev_kfree_skb(np->rx_skb[i].skb);
1958 np->rx_skb[i].skb = NULL;
1959 }
1960 }
1961 }
1962
1963 static void nv_drain_rxtx(struct net_device *dev)
1964 {
1965 nv_drain_tx(dev);
1966 nv_drain_rx(dev);
1967 }
1968
1969 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
1970 {
1971 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
1972 }
1973
1974 static void nv_legacybackoff_reseed(struct net_device *dev)
1975 {
1976 u8 __iomem *base = get_hwbase(dev);
1977 u32 reg;
1978 u32 low;
1979 int tx_status = 0;
1980
1981 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
1982 get_random_bytes(&low, sizeof(low));
1983 reg |= low & NVREG_SLOTTIME_MASK;
1984
1985 /* Need to stop tx before change takes effect.
1986 * Caller has already gained np->lock.
1987 */
1988 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
1989 if (tx_status)
1990 nv_stop_tx(dev);
1991 nv_stop_rx(dev);
1992 writel(reg, base + NvRegSlotTime);
1993 if (tx_status)
1994 nv_start_tx(dev);
1995 nv_start_rx(dev);
1996 }
1997
1998 /* Gear Backoff Seeds */
1999 #define BACKOFF_SEEDSET_ROWS 8
2000 #define BACKOFF_SEEDSET_LFSRS 15
2001
2002 /* Known Good seed sets */
2003 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2004 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2005 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2006 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2007 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2008 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2009 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2010 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
2011 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
2012
2013 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2014 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2015 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2016 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2017 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2018 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2019 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2020 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2021 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
2022
2023 static void nv_gear_backoff_reseed(struct net_device *dev)
2024 {
2025 u8 __iomem *base = get_hwbase(dev);
2026 u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2027 u32 temp, seedset, combinedSeed;
2028 int i;
2029
2030 /* Setup seed for free running LFSR */
2031 /* We are going to read the time stamp counter 3 times
2032 and swizzle bits around to increase randomness */
2033 get_random_bytes(&miniseed1, sizeof(miniseed1));
2034 miniseed1 &= 0x0fff;
2035 if (miniseed1 == 0)
2036 miniseed1 = 0xabc;
2037
2038 get_random_bytes(&miniseed2, sizeof(miniseed2));
2039 miniseed2 &= 0x0fff;
2040 if (miniseed2 == 0)
2041 miniseed2 = 0xabc;
2042 miniseed2_reversed =
2043 ((miniseed2 & 0xF00) >> 8) |
2044 (miniseed2 & 0x0F0) |
2045 ((miniseed2 & 0x00F) << 8);
2046
2047 get_random_bytes(&miniseed3, sizeof(miniseed3));
2048 miniseed3 &= 0x0fff;
2049 if (miniseed3 == 0)
2050 miniseed3 = 0xabc;
2051 miniseed3_reversed =
2052 ((miniseed3 & 0xF00) >> 8) |
2053 (miniseed3 & 0x0F0) |
2054 ((miniseed3 & 0x00F) << 8);
2055
2056 combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2057 (miniseed2 ^ miniseed3_reversed);
2058
2059 /* Seeds can not be zero */
2060 if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2061 combinedSeed |= 0x08;
2062 if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2063 combinedSeed |= 0x8000;
2064
2065 /* No need to disable tx here */
2066 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2067 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2068 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2069 writel(temp, base + NvRegBackOffControl);
2070
2071 /* Setup seeds for all gear LFSRs. */
2072 get_random_bytes(&seedset, sizeof(seedset));
2073 seedset = seedset % BACKOFF_SEEDSET_ROWS;
2074 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
2075 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2076 temp |= main_seedset[seedset][i-1] & 0x3ff;
2077 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2078 writel(temp, base + NvRegBackOffControl);
2079 }
2080 }
2081
2082 /*
2083 * nv_start_xmit: dev->hard_start_xmit function
2084 * Called with netif_tx_lock held.
2085 */
2086 static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2087 {
2088 struct fe_priv *np = netdev_priv(dev);
2089 u32 tx_flags = 0;
2090 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2091 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2092 unsigned int i;
2093 u32 offset = 0;
2094 u32 bcnt;
2095 u32 size = skb_headlen(skb);
2096 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2097 u32 empty_slots;
2098 struct ring_desc *put_tx;
2099 struct ring_desc *start_tx;
2100 struct ring_desc *prev_tx;
2101 struct nv_skb_map *prev_tx_ctx;
2102 unsigned long flags;
2103
2104 /* add fragments to entries count */
2105 for (i = 0; i < fragments; i++) {
2106 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2107
2108 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2109 ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2110 }
2111
2112 spin_lock_irqsave(&np->lock, flags);
2113 empty_slots = nv_get_empty_tx_slots(np);
2114 if (unlikely(empty_slots <= entries)) {
2115 netif_stop_queue(dev);
2116 np->tx_stop = 1;
2117 spin_unlock_irqrestore(&np->lock, flags);
2118 return NETDEV_TX_BUSY;
2119 }
2120 spin_unlock_irqrestore(&np->lock, flags);
2121
2122 start_tx = put_tx = np->put_tx.orig;
2123
2124 /* setup the header buffer */
2125 do {
2126 prev_tx = put_tx;
2127 prev_tx_ctx = np->put_tx_ctx;
2128 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2129 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2130 PCI_DMA_TODEVICE);
2131 np->put_tx_ctx->dma_len = bcnt;
2132 np->put_tx_ctx->dma_single = 1;
2133 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2134 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2135
2136 tx_flags = np->tx_flags;
2137 offset += bcnt;
2138 size -= bcnt;
2139 if (unlikely(put_tx++ == np->last_tx.orig))
2140 put_tx = np->first_tx.orig;
2141 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2142 np->put_tx_ctx = np->first_tx_ctx;
2143 } while (size);
2144
2145 /* setup the fragments */
2146 for (i = 0; i < fragments; i++) {
2147 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2148 u32 frag_size = skb_frag_size(frag);
2149 offset = 0;
2150
2151 do {
2152 prev_tx = put_tx;
2153 prev_tx_ctx = np->put_tx_ctx;
2154 bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2155 np->put_tx_ctx->dma = skb_frag_dma_map(
2156 &np->pci_dev->dev,
2157 frag, offset,
2158 bcnt,
2159 DMA_TO_DEVICE);
2160 np->put_tx_ctx->dma_len = bcnt;
2161 np->put_tx_ctx->dma_single = 0;
2162 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2163 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2164
2165 offset += bcnt;
2166 frag_size -= bcnt;
2167 if (unlikely(put_tx++ == np->last_tx.orig))
2168 put_tx = np->first_tx.orig;
2169 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2170 np->put_tx_ctx = np->first_tx_ctx;
2171 } while (frag_size);
2172 }
2173
2174 /* set last fragment flag */
2175 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2176
2177 /* save skb in this slot's context area */
2178 prev_tx_ctx->skb = skb;
2179
2180 if (skb_is_gso(skb))
2181 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2182 else
2183 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2184 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2185
2186 spin_lock_irqsave(&np->lock, flags);
2187
2188 /* set tx flags */
2189 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2190 np->put_tx.orig = put_tx;
2191
2192 spin_unlock_irqrestore(&np->lock, flags);
2193
2194 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2195 return NETDEV_TX_OK;
2196 }
2197
2198 static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2199 struct net_device *dev)
2200 {
2201 struct fe_priv *np = netdev_priv(dev);
2202 u32 tx_flags = 0;
2203 u32 tx_flags_extra;
2204 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2205 unsigned int i;
2206 u32 offset = 0;
2207 u32 bcnt;
2208 u32 size = skb_headlen(skb);
2209 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2210 u32 empty_slots;
2211 struct ring_desc_ex *put_tx;
2212 struct ring_desc_ex *start_tx;
2213 struct ring_desc_ex *prev_tx;
2214 struct nv_skb_map *prev_tx_ctx;
2215 struct nv_skb_map *start_tx_ctx;
2216 unsigned long flags;
2217
2218 /* add fragments to entries count */
2219 for (i = 0; i < fragments; i++) {
2220 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2221
2222 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2223 ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2224 }
2225
2226 spin_lock_irqsave(&np->lock, flags);
2227 empty_slots = nv_get_empty_tx_slots(np);
2228 if (unlikely(empty_slots <= entries)) {
2229 netif_stop_queue(dev);
2230 np->tx_stop = 1;
2231 spin_unlock_irqrestore(&np->lock, flags);
2232 return NETDEV_TX_BUSY;
2233 }
2234 spin_unlock_irqrestore(&np->lock, flags);
2235
2236 start_tx = put_tx = np->put_tx.ex;
2237 start_tx_ctx = np->put_tx_ctx;
2238
2239 /* setup the header buffer */
2240 do {
2241 prev_tx = put_tx;
2242 prev_tx_ctx = np->put_tx_ctx;
2243 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2244 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2245 PCI_DMA_TODEVICE);
2246 np->put_tx_ctx->dma_len = bcnt;
2247 np->put_tx_ctx->dma_single = 1;
2248 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2249 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2250 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2251
2252 tx_flags = NV_TX2_VALID;
2253 offset += bcnt;
2254 size -= bcnt;
2255 if (unlikely(put_tx++ == np->last_tx.ex))
2256 put_tx = np->first_tx.ex;
2257 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2258 np->put_tx_ctx = np->first_tx_ctx;
2259 } while (size);
2260
2261 /* setup the fragments */
2262 for (i = 0; i < fragments; i++) {
2263 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2264 u32 frag_size = skb_frag_size(frag);
2265 offset = 0;
2266
2267 do {
2268 prev_tx = put_tx;
2269 prev_tx_ctx = np->put_tx_ctx;
2270 bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2271 np->put_tx_ctx->dma = skb_frag_dma_map(
2272 &np->pci_dev->dev,
2273 frag, offset,
2274 bcnt,
2275 DMA_TO_DEVICE);
2276 np->put_tx_ctx->dma_len = bcnt;
2277 np->put_tx_ctx->dma_single = 0;
2278 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2279 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2280 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2281
2282 offset += bcnt;
2283 frag_size -= bcnt;
2284 if (unlikely(put_tx++ == np->last_tx.ex))
2285 put_tx = np->first_tx.ex;
2286 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2287 np->put_tx_ctx = np->first_tx_ctx;
2288 } while (frag_size);
2289 }
2290
2291 /* set last fragment flag */
2292 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2293
2294 /* save skb in this slot's context area */
2295 prev_tx_ctx->skb = skb;
2296
2297 if (skb_is_gso(skb))
2298 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2299 else
2300 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2301 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2302
2303 /* vlan tag */
2304 if (vlan_tx_tag_present(skb))
2305 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2306 vlan_tx_tag_get(skb));
2307 else
2308 start_tx->txvlan = 0;
2309
2310 spin_lock_irqsave(&np->lock, flags);
2311
2312 if (np->tx_limit) {
2313 /* Limit the number of outstanding tx. Setup all fragments, but
2314 * do not set the VALID bit on the first descriptor. Save a pointer
2315 * to that descriptor and also for next skb_map element.
2316 */
2317
2318 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2319 if (!np->tx_change_owner)
2320 np->tx_change_owner = start_tx_ctx;
2321
2322 /* remove VALID bit */
2323 tx_flags &= ~NV_TX2_VALID;
2324 start_tx_ctx->first_tx_desc = start_tx;
2325 start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2326 np->tx_end_flip = np->put_tx_ctx;
2327 } else {
2328 np->tx_pkts_in_progress++;
2329 }
2330 }
2331
2332 /* set tx flags */
2333 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2334 np->put_tx.ex = put_tx;
2335
2336 spin_unlock_irqrestore(&np->lock, flags);
2337
2338 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2339 return NETDEV_TX_OK;
2340 }
2341
2342 static inline void nv_tx_flip_ownership(struct net_device *dev)
2343 {
2344 struct fe_priv *np = netdev_priv(dev);
2345
2346 np->tx_pkts_in_progress--;
2347 if (np->tx_change_owner) {
2348 np->tx_change_owner->first_tx_desc->flaglen |=
2349 cpu_to_le32(NV_TX2_VALID);
2350 np->tx_pkts_in_progress++;
2351
2352 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2353 if (np->tx_change_owner == np->tx_end_flip)
2354 np->tx_change_owner = NULL;
2355
2356 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2357 }
2358 }
2359
2360 /*
2361 * nv_tx_done: check for completed packets, release the skbs.
2362 *
2363 * Caller must own np->lock.
2364 */
2365 static int nv_tx_done(struct net_device *dev, int limit)
2366 {
2367 struct fe_priv *np = netdev_priv(dev);
2368 u32 flags;
2369 int tx_work = 0;
2370 struct ring_desc *orig_get_tx = np->get_tx.orig;
2371
2372 while ((np->get_tx.orig != np->put_tx.orig) &&
2373 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2374 (tx_work < limit)) {
2375
2376 nv_unmap_txskb(np, np->get_tx_ctx);
2377
2378 if (np->desc_ver == DESC_VER_1) {
2379 if (flags & NV_TX_LASTPACKET) {
2380 if (flags & NV_TX_ERROR) {
2381 if ((flags & NV_TX_RETRYERROR) && !(flags & NV_TX_RETRYCOUNT_MASK))
2382 nv_legacybackoff_reseed(dev);
2383 }
2384 dev_kfree_skb_any(np->get_tx_ctx->skb);
2385 np->get_tx_ctx->skb = NULL;
2386 tx_work++;
2387 }
2388 } else {
2389 if (flags & NV_TX2_LASTPACKET) {
2390 if (flags & NV_TX2_ERROR) {
2391 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK))
2392 nv_legacybackoff_reseed(dev);
2393 }
2394 dev_kfree_skb_any(np->get_tx_ctx->skb);
2395 np->get_tx_ctx->skb = NULL;
2396 tx_work++;
2397 }
2398 }
2399 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2400 np->get_tx.orig = np->first_tx.orig;
2401 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2402 np->get_tx_ctx = np->first_tx_ctx;
2403 }
2404 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2405 np->tx_stop = 0;
2406 netif_wake_queue(dev);
2407 }
2408 return tx_work;
2409 }
2410
2411 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2412 {
2413 struct fe_priv *np = netdev_priv(dev);
2414 u32 flags;
2415 int tx_work = 0;
2416 struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
2417
2418 while ((np->get_tx.ex != np->put_tx.ex) &&
2419 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
2420 (tx_work < limit)) {
2421
2422 nv_unmap_txskb(np, np->get_tx_ctx);
2423
2424 if (flags & NV_TX2_LASTPACKET) {
2425 if (flags & NV_TX2_ERROR) {
2426 if ((flags & NV_TX2_RETRYERROR) && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2427 if (np->driver_data & DEV_HAS_GEAR_MODE)
2428 nv_gear_backoff_reseed(dev);
2429 else
2430 nv_legacybackoff_reseed(dev);
2431 }
2432 }
2433
2434 dev_kfree_skb_any(np->get_tx_ctx->skb);
2435 np->get_tx_ctx->skb = NULL;
2436 tx_work++;
2437
2438 if (np->tx_limit)
2439 nv_tx_flip_ownership(dev);
2440 }
2441 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2442 np->get_tx.ex = np->first_tx.ex;
2443 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2444 np->get_tx_ctx = np->first_tx_ctx;
2445 }
2446 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2447 np->tx_stop = 0;
2448 netif_wake_queue(dev);
2449 }
2450 return tx_work;
2451 }
2452
2453 /*
2454 * nv_tx_timeout: dev->tx_timeout function
2455 * Called with netif_tx_lock held.
2456 */
2457 static void nv_tx_timeout(struct net_device *dev)
2458 {
2459 struct fe_priv *np = netdev_priv(dev);
2460 u8 __iomem *base = get_hwbase(dev);
2461 u32 status;
2462 union ring_type put_tx;
2463 int saved_tx_limit;
2464 int i;
2465
2466 if (np->msi_flags & NV_MSI_X_ENABLED)
2467 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2468 else
2469 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2470
2471 netdev_info(dev, "Got tx_timeout. irq: %08x\n", status);
2472
2473 netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
2474 netdev_info(dev, "Dumping tx registers\n");
2475 for (i = 0; i <= np->register_size; i += 32) {
2476 netdev_info(dev,
2477 "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
2478 i,
2479 readl(base + i + 0), readl(base + i + 4),
2480 readl(base + i + 8), readl(base + i + 12),
2481 readl(base + i + 16), readl(base + i + 20),
2482 readl(base + i + 24), readl(base + i + 28));
2483 }
2484 netdev_info(dev, "Dumping tx ring\n");
2485 for (i = 0; i < np->tx_ring_size; i += 4) {
2486 if (!nv_optimized(np)) {
2487 netdev_info(dev,
2488 "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
2489 i,
2490 le32_to_cpu(np->tx_ring.orig[i].buf),
2491 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2492 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2493 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2494 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2495 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2496 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2497 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2498 } else {
2499 netdev_info(dev,
2500 "%03x: %08x %08x %08x // %08x %08x %08x // %08x %08x %08x // %08x %08x %08x\n",
2501 i,
2502 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2503 le32_to_cpu(np->tx_ring.ex[i].buflow),
2504 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2505 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2506 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2507 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2508 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2509 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2510 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2511 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2512 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2513 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2514 }
2515 }
2516
2517 spin_lock_irq(&np->lock);
2518
2519 /* 1) stop tx engine */
2520 nv_stop_tx(dev);
2521
2522 /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2523 saved_tx_limit = np->tx_limit;
2524 np->tx_limit = 0; /* prevent giving HW any limited pkts */
2525 np->tx_stop = 0; /* prevent waking tx queue */
2526 if (!nv_optimized(np))
2527 nv_tx_done(dev, np->tx_ring_size);
2528 else
2529 nv_tx_done_optimized(dev, np->tx_ring_size);
2530
2531 /* save current HW position */
2532 if (np->tx_change_owner)
2533 put_tx.ex = np->tx_change_owner->first_tx_desc;
2534 else
2535 put_tx = np->put_tx;
2536
2537 /* 3) clear all tx state */
2538 nv_drain_tx(dev);
2539 nv_init_tx(dev);
2540
2541 /* 4) restore state to current HW position */
2542 np->get_tx = np->put_tx = put_tx;
2543 np->tx_limit = saved_tx_limit;
2544
2545 /* 5) restart tx engine */
2546 nv_start_tx(dev);
2547 netif_wake_queue(dev);
2548 spin_unlock_irq(&np->lock);
2549 }
2550
2551 /*
2552 * Called when the nic notices a mismatch between the actual data len on the
2553 * wire and the len indicated in the 802 header
2554 */
2555 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2556 {
2557 int hdrlen; /* length of the 802 header */
2558 int protolen; /* length as stored in the proto field */
2559
2560 /* 1) calculate len according to header */
2561 if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2562 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
2563 hdrlen = VLAN_HLEN;
2564 } else {
2565 protolen = ntohs(((struct ethhdr *)packet)->h_proto);
2566 hdrlen = ETH_HLEN;
2567 }
2568 if (protolen > ETH_DATA_LEN)
2569 return datalen; /* Value in proto field not a len, no checks possible */
2570
2571 protolen += hdrlen;
2572 /* consistency checks: */
2573 if (datalen > ETH_ZLEN) {
2574 if (datalen >= protolen) {
2575 /* more data on wire than in 802 header, trim of
2576 * additional data.
2577 */
2578 return protolen;
2579 } else {
2580 /* less data on wire than mentioned in header.
2581 * Discard the packet.
2582 */
2583 return -1;
2584 }
2585 } else {
2586 /* short packet. Accept only if 802 values are also short */
2587 if (protolen > ETH_ZLEN) {
2588 return -1;
2589 }
2590 return datalen;
2591 }
2592 }
2593
2594 static int nv_rx_process(struct net_device *dev, int limit)
2595 {
2596 struct fe_priv *np = netdev_priv(dev);
2597 u32 flags;
2598 int rx_work = 0;
2599 struct sk_buff *skb;
2600 int len;
2601
2602 while ((np->get_rx.orig != np->put_rx.orig) &&
2603 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2604 (rx_work < limit)) {
2605
2606 /*
2607 * the packet is for us - immediately tear down the pci mapping.
2608 * TODO: check if a prefetch of the first cacheline improves
2609 * the performance.
2610 */
2611 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2612 np->get_rx_ctx->dma_len,
2613 PCI_DMA_FROMDEVICE);
2614 skb = np->get_rx_ctx->skb;
2615 np->get_rx_ctx->skb = NULL;
2616
2617 /* look at what we actually got: */
2618 if (np->desc_ver == DESC_VER_1) {
2619 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2620 len = flags & LEN_MASK_V1;
2621 if (unlikely(flags & NV_RX_ERROR)) {
2622 if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2623 len = nv_getlen(dev, skb->data, len);
2624 if (len < 0) {
2625 dev_kfree_skb(skb);
2626 goto next_pkt;
2627 }
2628 }
2629 /* framing errors are soft errors */
2630 else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2631 if (flags & NV_RX_SUBSTRACT1)
2632 len--;
2633 }
2634 /* the rest are hard errors */
2635 else {
2636 if (flags & NV_RX_MISSEDFRAME)
2637 dev->stats.rx_missed_errors++;
2638 dev_kfree_skb(skb);
2639 goto next_pkt;
2640 }
2641 }
2642 } else {
2643 dev_kfree_skb(skb);
2644 goto next_pkt;
2645 }
2646 } else {
2647 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2648 len = flags & LEN_MASK_V2;
2649 if (unlikely(flags & NV_RX2_ERROR)) {
2650 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2651 len = nv_getlen(dev, skb->data, len);
2652 if (len < 0) {
2653 dev_kfree_skb(skb);
2654 goto next_pkt;
2655 }
2656 }
2657 /* framing errors are soft errors */
2658 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2659 if (flags & NV_RX2_SUBSTRACT1)
2660 len--;
2661 }
2662 /* the rest are hard errors */
2663 else {
2664 dev_kfree_skb(skb);
2665 goto next_pkt;
2666 }
2667 }
2668 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2669 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2670 skb->ip_summed = CHECKSUM_UNNECESSARY;
2671 } else {
2672 dev_kfree_skb(skb);
2673 goto next_pkt;
2674 }
2675 }
2676 /* got a valid packet - forward it to the network core */
2677 skb_put(skb, len);
2678 skb->protocol = eth_type_trans(skb, dev);
2679 napi_gro_receive(&np->napi, skb);
2680 dev->stats.rx_packets++;
2681 next_pkt:
2682 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2683 np->get_rx.orig = np->first_rx.orig;
2684 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2685 np->get_rx_ctx = np->first_rx_ctx;
2686
2687 rx_work++;
2688 }
2689
2690 return rx_work;
2691 }
2692
2693 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2694 {
2695 struct fe_priv *np = netdev_priv(dev);
2696 u32 flags;
2697 u32 vlanflags = 0;
2698 int rx_work = 0;
2699 struct sk_buff *skb;
2700 int len;
2701
2702 while ((np->get_rx.ex != np->put_rx.ex) &&
2703 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2704 (rx_work < limit)) {
2705
2706 /*
2707 * the packet is for us - immediately tear down the pci mapping.
2708 * TODO: check if a prefetch of the first cacheline improves
2709 * the performance.
2710 */
2711 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2712 np->get_rx_ctx->dma_len,
2713 PCI_DMA_FROMDEVICE);
2714 skb = np->get_rx_ctx->skb;
2715 np->get_rx_ctx->skb = NULL;
2716
2717 /* look at what we actually got: */
2718 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2719 len = flags & LEN_MASK_V2;
2720 if (unlikely(flags & NV_RX2_ERROR)) {
2721 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2722 len = nv_getlen(dev, skb->data, len);
2723 if (len < 0) {
2724 dev_kfree_skb(skb);
2725 goto next_pkt;
2726 }
2727 }
2728 /* framing errors are soft errors */
2729 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2730 if (flags & NV_RX2_SUBSTRACT1)
2731 len--;
2732 }
2733 /* the rest are hard errors */
2734 else {
2735 dev_kfree_skb(skb);
2736 goto next_pkt;
2737 }
2738 }
2739
2740 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2741 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2742 skb->ip_summed = CHECKSUM_UNNECESSARY;
2743
2744 /* got a valid packet - forward it to the network core */
2745 skb_put(skb, len);
2746 skb->protocol = eth_type_trans(skb, dev);
2747 prefetch(skb->data);
2748
2749 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2750
2751 /*
2752 * There's need to check for NETIF_F_HW_VLAN_RX here.
2753 * Even if vlan rx accel is disabled,
2754 * NV_RX3_VLAN_TAG_PRESENT is pseudo randomly set.
2755 */
2756 if (dev->features & NETIF_F_HW_VLAN_RX &&
2757 vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2758 u16 vid = vlanflags & NV_RX3_VLAN_TAG_MASK;
2759
2760 __vlan_hwaccel_put_tag(skb, vid);
2761 }
2762 napi_gro_receive(&np->napi, skb);
2763 dev->stats.rx_packets++;
2764 } else {
2765 dev_kfree_skb(skb);
2766 }
2767 next_pkt:
2768 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2769 np->get_rx.ex = np->first_rx.ex;
2770 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2771 np->get_rx_ctx = np->first_rx_ctx;
2772
2773 rx_work++;
2774 }
2775
2776 return rx_work;
2777 }
2778
2779 static void set_bufsize(struct net_device *dev)
2780 {
2781 struct fe_priv *np = netdev_priv(dev);
2782
2783 if (dev->mtu <= ETH_DATA_LEN)
2784 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2785 else
2786 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
2787 }
2788
2789 /*
2790 * nv_change_mtu: dev->change_mtu function
2791 * Called with dev_base_lock held for read.
2792 */
2793 static int nv_change_mtu(struct net_device *dev, int new_mtu)
2794 {
2795 struct fe_priv *np = netdev_priv(dev);
2796 int old_mtu;
2797
2798 if (new_mtu < 64 || new_mtu > np->pkt_limit)
2799 return -EINVAL;
2800
2801 old_mtu = dev->mtu;
2802 dev->mtu = new_mtu;
2803
2804 /* return early if the buffer sizes will not change */
2805 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
2806 return 0;
2807 if (old_mtu == new_mtu)
2808 return 0;
2809
2810 /* synchronized against open : rtnl_lock() held by caller */
2811 if (netif_running(dev)) {
2812 u8 __iomem *base = get_hwbase(dev);
2813 /*
2814 * It seems that the nic preloads valid ring entries into an
2815 * internal buffer. The procedure for flushing everything is
2816 * guessed, there is probably a simpler approach.
2817 * Changing the MTU is a rare event, it shouldn't matter.
2818 */
2819 nv_disable_irq(dev);
2820 nv_napi_disable(dev);
2821 netif_tx_lock_bh(dev);
2822 netif_addr_lock(dev);
2823 spin_lock(&np->lock);
2824 /* stop engines */
2825 nv_stop_rxtx(dev);
2826 nv_txrx_reset(dev);
2827 /* drain rx queue */
2828 nv_drain_rxtx(dev);
2829 /* reinit driver view of the rx queue */
2830 set_bufsize(dev);
2831 if (nv_init_ring(dev)) {
2832 if (!np->in_shutdown)
2833 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
2834 }
2835 /* reinit nic view of the rx queue */
2836 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
2837 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
2838 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
2839 base + NvRegRingSizes);
2840 pci_push(base);
2841 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2842 pci_push(base);
2843
2844 /* restart rx engine */
2845 nv_start_rxtx(dev);
2846 spin_unlock(&np->lock);
2847 netif_addr_unlock(dev);
2848 netif_tx_unlock_bh(dev);
2849 nv_napi_enable(dev);
2850 nv_enable_irq(dev);
2851 }
2852 return 0;
2853 }
2854
2855 static void nv_copy_mac_to_hw(struct net_device *dev)
2856 {
2857 u8 __iomem *base = get_hwbase(dev);
2858 u32 mac[2];
2859
2860 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
2861 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
2862 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
2863
2864 writel(mac[0], base + NvRegMacAddrA);
2865 writel(mac[1], base + NvRegMacAddrB);
2866 }
2867
2868 /*
2869 * nv_set_mac_address: dev->set_mac_address function
2870 * Called with rtnl_lock() held.
2871 */
2872 static int nv_set_mac_address(struct net_device *dev, void *addr)
2873 {
2874 struct fe_priv *np = netdev_priv(dev);
2875 struct sockaddr *macaddr = (struct sockaddr *)addr;
2876
2877 if (!is_valid_ether_addr(macaddr->sa_data))
2878 return -EADDRNOTAVAIL;
2879
2880 /* synchronized against open : rtnl_lock() held by caller */
2881 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
2882
2883 if (netif_running(dev)) {
2884 netif_tx_lock_bh(dev);
2885 netif_addr_lock(dev);
2886 spin_lock_irq(&np->lock);
2887
2888 /* stop rx engine */
2889 nv_stop_rx(dev);
2890
2891 /* set mac address */
2892 nv_copy_mac_to_hw(dev);
2893
2894 /* restart rx engine */
2895 nv_start_rx(dev);
2896 spin_unlock_irq(&np->lock);
2897 netif_addr_unlock(dev);
2898 netif_tx_unlock_bh(dev);
2899 } else {
2900 nv_copy_mac_to_hw(dev);
2901 }
2902 return 0;
2903 }
2904
2905 /*
2906 * nv_set_multicast: dev->set_multicast function
2907 * Called with netif_tx_lock held.
2908 */
2909 static void nv_set_multicast(struct net_device *dev)
2910 {
2911 struct fe_priv *np = netdev_priv(dev);
2912 u8 __iomem *base = get_hwbase(dev);
2913 u32 addr[2];
2914 u32 mask[2];
2915 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
2916
2917 memset(addr, 0, sizeof(addr));
2918 memset(mask, 0, sizeof(mask));
2919
2920 if (dev->flags & IFF_PROMISC) {
2921 pff |= NVREG_PFF_PROMISC;
2922 } else {
2923 pff |= NVREG_PFF_MYADDR;
2924
2925 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
2926 u32 alwaysOff[2];
2927 u32 alwaysOn[2];
2928
2929 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
2930 if (dev->flags & IFF_ALLMULTI) {
2931 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
2932 } else {
2933 struct netdev_hw_addr *ha;
2934
2935 netdev_for_each_mc_addr(ha, dev) {
2936 unsigned char *hw_addr = ha->addr;
2937 u32 a, b;
2938
2939 a = le32_to_cpu(*(__le32 *) hw_addr);
2940 b = le16_to_cpu(*(__le16 *) (&hw_addr[4]));
2941 alwaysOn[0] &= a;
2942 alwaysOff[0] &= ~a;
2943 alwaysOn[1] &= b;
2944 alwaysOff[1] &= ~b;
2945 }
2946 }
2947 addr[0] = alwaysOn[0];
2948 addr[1] = alwaysOn[1];
2949 mask[0] = alwaysOn[0] | alwaysOff[0];
2950 mask[1] = alwaysOn[1] | alwaysOff[1];
2951 } else {
2952 mask[0] = NVREG_MCASTMASKA_NONE;
2953 mask[1] = NVREG_MCASTMASKB_NONE;
2954 }
2955 }
2956 addr[0] |= NVREG_MCASTADDRA_FORCE;
2957 pff |= NVREG_PFF_ALWAYS;
2958 spin_lock_irq(&np->lock);
2959 nv_stop_rx(dev);
2960 writel(addr[0], base + NvRegMulticastAddrA);
2961 writel(addr[1], base + NvRegMulticastAddrB);
2962 writel(mask[0], base + NvRegMulticastMaskA);
2963 writel(mask[1], base + NvRegMulticastMaskB);
2964 writel(pff, base + NvRegPacketFilterFlags);
2965 nv_start_rx(dev);
2966 spin_unlock_irq(&np->lock);
2967 }
2968
2969 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
2970 {
2971 struct fe_priv *np = netdev_priv(dev);
2972 u8 __iomem *base = get_hwbase(dev);
2973
2974 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
2975
2976 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
2977 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
2978 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
2979 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
2980 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
2981 } else {
2982 writel(pff, base + NvRegPacketFilterFlags);
2983 }
2984 }
2985 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
2986 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
2987 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
2988 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
2989 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
2990 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
2991 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
2992 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
2993 /* limit the number of tx pause frames to a default of 8 */
2994 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
2995 }
2996 writel(pause_enable, base + NvRegTxPauseFrame);
2997 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
2998 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
2999 } else {
3000 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3001 writel(regmisc, base + NvRegMisc1);
3002 }
3003 }
3004 }
3005
3006 /**
3007 * nv_update_linkspeed: Setup the MAC according to the link partner
3008 * @dev: Network device to be configured
3009 *
3010 * The function queries the PHY and checks if there is a link partner.
3011 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3012 * set to 10 MBit HD.
3013 *
3014 * The function returns 0 if there is no link partner and 1 if there is
3015 * a good link partner.
3016 */
3017 static int nv_update_linkspeed(struct net_device *dev)
3018 {
3019 struct fe_priv *np = netdev_priv(dev);
3020 u8 __iomem *base = get_hwbase(dev);
3021 int adv = 0;
3022 int lpa = 0;
3023 int adv_lpa, adv_pause, lpa_pause;
3024 int newls = np->linkspeed;
3025 int newdup = np->duplex;
3026 int mii_status;
3027 int retval = 0;
3028 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3029 u32 txrxFlags = 0;
3030 u32 phy_exp;
3031
3032 /* BMSR_LSTATUS is latched, read it twice:
3033 * we want the current value.
3034 */
3035 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3036 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3037
3038 if (!(mii_status & BMSR_LSTATUS)) {
3039 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3040 newdup = 0;
3041 retval = 0;
3042 goto set_speed;
3043 }
3044
3045 if (np->autoneg == 0) {
3046 if (np->fixed_mode & LPA_100FULL) {
3047 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3048 newdup = 1;
3049 } else if (np->fixed_mode & LPA_100HALF) {
3050 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3051 newdup = 0;
3052 } else if (np->fixed_mode & LPA_10FULL) {
3053 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3054 newdup = 1;
3055 } else {
3056 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3057 newdup = 0;
3058 }
3059 retval = 1;
3060 goto set_speed;
3061 }
3062 /* check auto negotiation is complete */
3063 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3064 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3065 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3066 newdup = 0;
3067 retval = 0;
3068 goto set_speed;
3069 }
3070
3071 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3072 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3073
3074 retval = 1;
3075 if (np->gigabit == PHY_GIGABIT) {
3076 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3077 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3078
3079 if ((control_1000 & ADVERTISE_1000FULL) &&
3080 (status_1000 & LPA_1000FULL)) {
3081 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3082 newdup = 1;
3083 goto set_speed;
3084 }
3085 }
3086
3087 /* FIXME: handle parallel detection properly */
3088 adv_lpa = lpa & adv;
3089 if (adv_lpa & LPA_100FULL) {
3090 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3091 newdup = 1;
3092 } else if (adv_lpa & LPA_100HALF) {
3093 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3094 newdup = 0;
3095 } else if (adv_lpa & LPA_10FULL) {
3096 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3097 newdup = 1;
3098 } else if (adv_lpa & LPA_10HALF) {
3099 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3100 newdup = 0;
3101 } else {
3102 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3103 newdup = 0;
3104 }
3105
3106 set_speed:
3107 if (np->duplex == newdup && np->linkspeed == newls)
3108 return retval;
3109
3110 np->duplex = newdup;
3111 np->linkspeed = newls;
3112
3113 /* The transmitter and receiver must be restarted for safe update */
3114 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3115 txrxFlags |= NV_RESTART_TX;
3116 nv_stop_tx(dev);
3117 }
3118 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3119 txrxFlags |= NV_RESTART_RX;
3120 nv_stop_rx(dev);
3121 }
3122
3123 if (np->gigabit == PHY_GIGABIT) {
3124 phyreg = readl(base + NvRegSlotTime);
3125 phyreg &= ~(0x3FF00);
3126 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3127 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3128 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3129 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3130 phyreg |= NVREG_SLOTTIME_1000_FULL;
3131 writel(phyreg, base + NvRegSlotTime);
3132 }
3133
3134 phyreg = readl(base + NvRegPhyInterface);
3135 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3136 if (np->duplex == 0)
3137 phyreg |= PHY_HALF;
3138 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3139 phyreg |= PHY_100;
3140 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3141 phyreg |= PHY_1000;
3142 writel(phyreg, base + NvRegPhyInterface);
3143
3144 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3145 if (phyreg & PHY_RGMII) {
3146 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3147 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3148 } else {
3149 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3150 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3151 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3152 else
3153 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3154 } else {
3155 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3156 }
3157 }
3158 } else {
3159 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3160 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3161 else
3162 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3163 }
3164 writel(txreg, base + NvRegTxDeferral);
3165
3166 if (np->desc_ver == DESC_VER_1) {
3167 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3168 } else {
3169 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3170 txreg = NVREG_TX_WM_DESC2_3_1000;
3171 else
3172 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3173 }
3174 writel(txreg, base + NvRegTxWatermark);
3175
3176 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3177 base + NvRegMisc1);
3178 pci_push(base);
3179 writel(np->linkspeed, base + NvRegLinkSpeed);
3180 pci_push(base);
3181
3182 pause_flags = 0;
3183 /* setup pause frame */
3184 if (np->duplex != 0) {
3185 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3186 adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3187 lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
3188
3189 switch (adv_pause) {
3190 case ADVERTISE_PAUSE_CAP:
3191 if (lpa_pause & LPA_PAUSE_CAP) {
3192 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3193 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3194 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3195 }
3196 break;
3197 case ADVERTISE_PAUSE_ASYM:
3198 if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
3199 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3200 break;
3201 case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3202 if (lpa_pause & LPA_PAUSE_CAP) {
3203 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3204 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3205 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3206 }
3207 if (lpa_pause == LPA_PAUSE_ASYM)
3208 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3209 break;
3210 }
3211 } else {
3212 pause_flags = np->pause_flags;
3213 }
3214 }
3215 nv_update_pause(dev, pause_flags);
3216
3217 if (txrxFlags & NV_RESTART_TX)
3218 nv_start_tx(dev);
3219 if (txrxFlags & NV_RESTART_RX)
3220 nv_start_rx(dev);
3221
3222 return retval;
3223 }
3224
3225 static void nv_linkchange(struct net_device *dev)
3226 {
3227 if (nv_update_linkspeed(dev)) {
3228 if (!netif_carrier_ok(dev)) {
3229 netif_carrier_on(dev);
3230 netdev_info(dev, "link up\n");
3231 nv_txrx_gate(dev, false);
3232 nv_start_rx(dev);
3233 }
3234 } else {
3235 if (netif_carrier_ok(dev)) {
3236 netif_carrier_off(dev);
3237 netdev_info(dev, "link down\n");
3238 nv_txrx_gate(dev, true);
3239 nv_stop_rx(dev);
3240 }
3241 }
3242 }
3243
3244 static void nv_link_irq(struct net_device *dev)
3245 {
3246 u8 __iomem *base = get_hwbase(dev);
3247 u32 miistat;
3248
3249 miistat = readl(base + NvRegMIIStatus);
3250 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3251
3252 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3253 nv_linkchange(dev);
3254 }
3255
3256 static void nv_msi_workaround(struct fe_priv *np)
3257 {
3258
3259 /* Need to toggle the msi irq mask within the ethernet device,
3260 * otherwise, future interrupts will not be detected.
3261 */
3262 if (np->msi_flags & NV_MSI_ENABLED) {
3263 u8 __iomem *base = np->base;
3264
3265 writel(0, base + NvRegMSIIrqMask);
3266 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3267 }
3268 }
3269
3270 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3271 {
3272 struct fe_priv *np = netdev_priv(dev);
3273
3274 if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3275 if (total_work > NV_DYNAMIC_THRESHOLD) {
3276 /* transition to poll based interrupts */
3277 np->quiet_count = 0;
3278 if (np->irqmask != NVREG_IRQMASK_CPU) {
3279 np->irqmask = NVREG_IRQMASK_CPU;
3280 return 1;
3281 }
3282 } else {
3283 if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3284 np->quiet_count++;
3285 } else {
3286 /* reached a period of low activity, switch
3287 to per tx/rx packet interrupts */
3288 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3289 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3290 return 1;
3291 }
3292 }
3293 }
3294 }
3295 return 0;
3296 }
3297
3298 static irqreturn_t nv_nic_irq(int foo, void *data)
3299 {
3300 struct net_device *dev = (struct net_device *) data;
3301 struct fe_priv *np = netdev_priv(dev);
3302 u8 __iomem *base = get_hwbase(dev);
3303
3304 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3305 np->events = readl(base + NvRegIrqStatus);
3306 writel(np->events, base + NvRegIrqStatus);
3307 } else {
3308 np->events = readl(base + NvRegMSIXIrqStatus);
3309 writel(np->events, base + NvRegMSIXIrqStatus);
3310 }
3311 if (!(np->events & np->irqmask))
3312 return IRQ_NONE;
3313
3314 nv_msi_workaround(np);
3315
3316 if (napi_schedule_prep(&np->napi)) {
3317 /*
3318 * Disable further irq's (msix not enabled with napi)
3319 */
3320 writel(0, base + NvRegIrqMask);
3321 __napi_schedule(&np->napi);
3322 }
3323
3324 return IRQ_HANDLED;
3325 }
3326
3327 /**
3328 * All _optimized functions are used to help increase performance
3329 * (reduce CPU and increase throughput). They use descripter version 3,
3330 * compiler directives, and reduce memory accesses.
3331 */
3332 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3333 {
3334 struct net_device *dev = (struct net_device *) data;
3335 struct fe_priv *np = netdev_priv(dev);
3336 u8 __iomem *base = get_hwbase(dev);
3337
3338 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3339 np->events = readl(base + NvRegIrqStatus);
3340 writel(np->events, base + NvRegIrqStatus);
3341 } else {
3342 np->events = readl(base + NvRegMSIXIrqStatus);
3343 writel(np->events, base + NvRegMSIXIrqStatus);
3344 }
3345 if (!(np->events & np->irqmask))
3346 return IRQ_NONE;
3347
3348 nv_msi_workaround(np);
3349
3350 if (napi_schedule_prep(&np->napi)) {
3351 /*
3352 * Disable further irq's (msix not enabled with napi)
3353 */
3354 writel(0, base + NvRegIrqMask);
3355 __napi_schedule(&np->napi);
3356 }
3357
3358 return IRQ_HANDLED;
3359 }
3360
3361 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3362 {
3363 struct net_device *dev = (struct net_device *) data;
3364 struct fe_priv *np = netdev_priv(dev);
3365 u8 __iomem *base = get_hwbase(dev);
3366 u32 events;
3367 int i;
3368 unsigned long flags;
3369
3370 for (i = 0;; i++) {
3371 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3372 writel(events, base + NvRegMSIXIrqStatus);
3373 netdev_dbg(dev, "tx irq events: %08x\n", events);
3374 if (!(events & np->irqmask))
3375 break;
3376
3377 spin_lock_irqsave(&np->lock, flags);
3378 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3379 spin_unlock_irqrestore(&np->lock, flags);
3380
3381 if (unlikely(i > max_interrupt_work)) {
3382 spin_lock_irqsave(&np->lock, flags);
3383 /* disable interrupts on the nic */
3384 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3385 pci_push(base);
3386
3387 if (!np->in_shutdown) {
3388 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3389 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3390 }
3391 spin_unlock_irqrestore(&np->lock, flags);
3392 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3393 __func__, i);
3394 break;
3395 }
3396
3397 }
3398
3399 return IRQ_RETVAL(i);
3400 }
3401
3402 static int nv_napi_poll(struct napi_struct *napi, int budget)
3403 {
3404 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3405 struct net_device *dev = np->dev;
3406 u8 __iomem *base = get_hwbase(dev);
3407 unsigned long flags;
3408 int retcode;
3409 int rx_count, tx_work = 0, rx_work = 0;
3410
3411 do {
3412 if (!nv_optimized(np)) {
3413 spin_lock_irqsave(&np->lock, flags);
3414 tx_work += nv_tx_done(dev, np->tx_ring_size);
3415 spin_unlock_irqrestore(&np->lock, flags);
3416
3417 rx_count = nv_rx_process(dev, budget - rx_work);
3418 retcode = nv_alloc_rx(dev);
3419 } else {
3420 spin_lock_irqsave(&np->lock, flags);
3421 tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3422 spin_unlock_irqrestore(&np->lock, flags);
3423
3424 rx_count = nv_rx_process_optimized(dev,
3425 budget - rx_work);
3426 retcode = nv_alloc_rx_optimized(dev);
3427 }
3428 } while (retcode == 0 &&
3429 rx_count > 0 && (rx_work += rx_count) < budget);
3430
3431 if (retcode) {
3432 spin_lock_irqsave(&np->lock, flags);
3433 if (!np->in_shutdown)
3434 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3435 spin_unlock_irqrestore(&np->lock, flags);
3436 }
3437
3438 nv_change_interrupt_mode(dev, tx_work + rx_work);
3439
3440 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3441 spin_lock_irqsave(&np->lock, flags);
3442 nv_link_irq(dev);
3443 spin_unlock_irqrestore(&np->lock, flags);
3444 }
3445 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3446 spin_lock_irqsave(&np->lock, flags);
3447 nv_linkchange(dev);
3448 spin_unlock_irqrestore(&np->lock, flags);
3449 np->link_timeout = jiffies + LINK_TIMEOUT;
3450 }
3451 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3452 spin_lock_irqsave(&np->lock, flags);
3453 if (!np->in_shutdown) {
3454 np->nic_poll_irq = np->irqmask;
3455 np->recover_error = 1;
3456 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3457 }
3458 spin_unlock_irqrestore(&np->lock, flags);
3459 napi_complete(napi);
3460 return rx_work;
3461 }
3462
3463 if (rx_work < budget) {
3464 /* re-enable interrupts
3465 (msix not enabled in napi) */
3466 napi_complete(napi);
3467
3468 writel(np->irqmask, base + NvRegIrqMask);
3469 }
3470 return rx_work;
3471 }
3472
3473 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3474 {
3475 struct net_device *dev = (struct net_device *) data;
3476 struct fe_priv *np = netdev_priv(dev);
3477 u8 __iomem *base = get_hwbase(dev);
3478 u32 events;
3479 int i;
3480 unsigned long flags;
3481
3482 for (i = 0;; i++) {
3483 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3484 writel(events, base + NvRegMSIXIrqStatus);
3485 netdev_dbg(dev, "rx irq events: %08x\n", events);
3486 if (!(events & np->irqmask))
3487 break;
3488
3489 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3490 if (unlikely(nv_alloc_rx_optimized(dev))) {
3491 spin_lock_irqsave(&np->lock, flags);
3492 if (!np->in_shutdown)
3493 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3494 spin_unlock_irqrestore(&np->lock, flags);
3495 }
3496 }
3497
3498 if (unlikely(i > max_interrupt_work)) {
3499 spin_lock_irqsave(&np->lock, flags);
3500 /* disable interrupts on the nic */
3501 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3502 pci_push(base);
3503
3504 if (!np->in_shutdown) {
3505 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3506 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3507 }
3508 spin_unlock_irqrestore(&np->lock, flags);
3509 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3510 __func__, i);
3511 break;
3512 }
3513 }
3514
3515 return IRQ_RETVAL(i);
3516 }
3517
3518 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3519 {
3520 struct net_device *dev = (struct net_device *) data;
3521 struct fe_priv *np = netdev_priv(dev);
3522 u8 __iomem *base = get_hwbase(dev);
3523 u32 events;
3524 int i;
3525 unsigned long flags;
3526
3527 for (i = 0;; i++) {
3528 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3529 writel(events, base + NvRegMSIXIrqStatus);
3530 netdev_dbg(dev, "irq events: %08x\n", events);
3531 if (!(events & np->irqmask))
3532 break;
3533
3534 /* check tx in case we reached max loop limit in tx isr */
3535 spin_lock_irqsave(&np->lock, flags);
3536 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3537 spin_unlock_irqrestore(&np->lock, flags);
3538
3539 if (events & NVREG_IRQ_LINK) {
3540 spin_lock_irqsave(&np->lock, flags);
3541 nv_link_irq(dev);
3542 spin_unlock_irqrestore(&np->lock, flags);
3543 }
3544 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3545 spin_lock_irqsave(&np->lock, flags);
3546 nv_linkchange(dev);
3547 spin_unlock_irqrestore(&np->lock, flags);
3548 np->link_timeout = jiffies + LINK_TIMEOUT;
3549 }
3550 if (events & NVREG_IRQ_RECOVER_ERROR) {
3551 spin_lock_irq(&np->lock);
3552 /* disable interrupts on the nic */
3553 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3554 pci_push(base);
3555
3556 if (!np->in_shutdown) {
3557 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3558 np->recover_error = 1;
3559 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3560 }
3561 spin_unlock_irq(&np->lock);
3562 break;
3563 }
3564 if (unlikely(i > max_interrupt_work)) {
3565 spin_lock_irqsave(&np->lock, flags);
3566 /* disable interrupts on the nic */
3567 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3568 pci_push(base);
3569
3570 if (!np->in_shutdown) {
3571 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3572 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3573 }
3574 spin_unlock_irqrestore(&np->lock, flags);
3575 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3576 __func__, i);
3577 break;
3578 }
3579
3580 }
3581
3582 return IRQ_RETVAL(i);
3583 }
3584
3585 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3586 {
3587 struct net_device *dev = (struct net_device *) data;
3588 struct fe_priv *np = netdev_priv(dev);
3589 u8 __iomem *base = get_hwbase(dev);
3590 u32 events;
3591
3592 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3593 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3594 writel(events & NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3595 } else {
3596 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3597 writel(events & NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3598 }
3599 pci_push(base);
3600 if (!(events & NVREG_IRQ_TIMER))
3601 return IRQ_RETVAL(0);
3602
3603 nv_msi_workaround(np);
3604
3605 spin_lock(&np->lock);
3606 np->intr_test = 1;
3607 spin_unlock(&np->lock);
3608
3609 return IRQ_RETVAL(1);
3610 }
3611
3612 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3613 {
3614 u8 __iomem *base = get_hwbase(dev);
3615 int i;
3616 u32 msixmap = 0;
3617
3618 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3619 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3620 * the remaining 8 interrupts.
3621 */
3622 for (i = 0; i < 8; i++) {
3623 if ((irqmask >> i) & 0x1)
3624 msixmap |= vector << (i << 2);
3625 }
3626 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3627
3628 msixmap = 0;
3629 for (i = 0; i < 8; i++) {
3630 if ((irqmask >> (i + 8)) & 0x1)
3631 msixmap |= vector << (i << 2);
3632 }
3633 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3634 }
3635
3636 static int nv_request_irq(struct net_device *dev, int intr_test)
3637 {
3638 struct fe_priv *np = get_nvpriv(dev);
3639 u8 __iomem *base = get_hwbase(dev);
3640 int ret = 1;
3641 int i;
3642 irqreturn_t (*handler)(int foo, void *data);
3643
3644 if (intr_test) {
3645 handler = nv_nic_irq_test;
3646 } else {
3647 if (nv_optimized(np))
3648 handler = nv_nic_irq_optimized;
3649 else
3650 handler = nv_nic_irq;
3651 }
3652
3653 if (np->msi_flags & NV_MSI_X_CAPABLE) {
3654 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3655 np->msi_x_entry[i].entry = i;
3656 ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK));
3657 if (ret == 0) {
3658 np->msi_flags |= NV_MSI_X_ENABLED;
3659 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3660 /* Request irq for rx handling */
3661 sprintf(np->name_rx, "%s-rx", dev->name);
3662 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3663 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3664 netdev_info(dev,
3665 "request_irq failed for rx %d\n",
3666 ret);
3667 pci_disable_msix(np->pci_dev);
3668 np->msi_flags &= ~NV_MSI_X_ENABLED;
3669 goto out_err;
3670 }
3671 /* Request irq for tx handling */
3672 sprintf(np->name_tx, "%s-tx", dev->name);
3673 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3674 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3675 netdev_info(dev,
3676 "request_irq failed for tx %d\n",
3677 ret);
3678 pci_disable_msix(np->pci_dev);
3679 np->msi_flags &= ~NV_MSI_X_ENABLED;
3680 goto out_free_rx;
3681 }
3682 /* Request irq for link and timer handling */
3683 sprintf(np->name_other, "%s-other", dev->name);
3684 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3685 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3686 netdev_info(dev,
3687 "request_irq failed for link %d\n",
3688 ret);
3689 pci_disable_msix(np->pci_dev);
3690 np->msi_flags &= ~NV_MSI_X_ENABLED;
3691 goto out_free_tx;
3692 }
3693 /* map interrupts to their respective vector */
3694 writel(0, base + NvRegMSIXMap0);
3695 writel(0, base + NvRegMSIXMap1);
3696 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3697 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3698 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3699 } else {
3700 /* Request irq for all interrupts */
3701 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3702 netdev_info(dev,
3703 "request_irq failed %d\n",
3704 ret);
3705 pci_disable_msix(np->pci_dev);
3706 np->msi_flags &= ~NV_MSI_X_ENABLED;
3707 goto out_err;
3708 }
3709
3710 /* map interrupts to vector 0 */
3711 writel(0, base + NvRegMSIXMap0);
3712 writel(0, base + NvRegMSIXMap1);
3713 }
3714 }
3715 }
3716 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
3717 ret = pci_enable_msi(np->pci_dev);
3718 if (ret == 0) {
3719 np->msi_flags |= NV_MSI_ENABLED;
3720 dev->irq = np->pci_dev->irq;
3721 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
3722 netdev_info(dev, "request_irq failed %d\n",
3723 ret);
3724 pci_disable_msi(np->pci_dev);
3725 np->msi_flags &= ~NV_MSI_ENABLED;
3726 dev->irq = np->pci_dev->irq;
3727 goto out_err;
3728 }
3729
3730 /* map interrupts to vector 0 */
3731 writel(0, base + NvRegMSIMap0);
3732 writel(0, base + NvRegMSIMap1);
3733 /* enable msi vector 0 */
3734 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3735 }
3736 }
3737 if (ret != 0) {
3738 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
3739 goto out_err;
3740
3741 }
3742
3743 return 0;
3744 out_free_tx:
3745 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
3746 out_free_rx:
3747 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
3748 out_err:
3749 return 1;
3750 }
3751
3752 static void nv_free_irq(struct net_device *dev)
3753 {
3754 struct fe_priv *np = get_nvpriv(dev);
3755 int i;
3756
3757 if (np->msi_flags & NV_MSI_X_ENABLED) {
3758 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3759 free_irq(np->msi_x_entry[i].vector, dev);
3760 pci_disable_msix(np->pci_dev);
3761 np->msi_flags &= ~NV_MSI_X_ENABLED;
3762 } else {
3763 free_irq(np->pci_dev->irq, dev);
3764 if (np->msi_flags & NV_MSI_ENABLED) {
3765 pci_disable_msi(np->pci_dev);
3766 np->msi_flags &= ~NV_MSI_ENABLED;
3767 }
3768 }
3769 }
3770
3771 static void nv_do_nic_poll(unsigned long data)
3772 {
3773 struct net_device *dev = (struct net_device *) data;
3774 struct fe_priv *np = netdev_priv(dev);
3775 u8 __iomem *base = get_hwbase(dev);
3776 u32 mask = 0;
3777
3778 /*
3779 * First disable irq(s) and then
3780 * reenable interrupts on the nic, we have to do this before calling
3781 * nv_nic_irq because that may decide to do otherwise
3782 */
3783
3784 if (!using_multi_irqs(dev)) {
3785 if (np->msi_flags & NV_MSI_X_ENABLED)
3786 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3787 else
3788 disable_irq_lockdep(np->pci_dev->irq);
3789 mask = np->irqmask;
3790 } else {
3791 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3792 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3793 mask |= NVREG_IRQ_RX_ALL;
3794 }
3795 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3796 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3797 mask |= NVREG_IRQ_TX_ALL;
3798 }
3799 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3800 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3801 mask |= NVREG_IRQ_OTHER;
3802 }
3803 }
3804 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
3805
3806 if (np->recover_error) {
3807 np->recover_error = 0;
3808 netdev_info(dev, "MAC in recoverable error state\n");
3809 if (netif_running(dev)) {
3810 netif_tx_lock_bh(dev);
3811 netif_addr_lock(dev);
3812 spin_lock(&np->lock);
3813 /* stop engines */
3814 nv_stop_rxtx(dev);
3815 if (np->driver_data & DEV_HAS_POWER_CNTRL)
3816 nv_mac_reset(dev);
3817 nv_txrx_reset(dev);
3818 /* drain rx queue */
3819 nv_drain_rxtx(dev);
3820 /* reinit driver view of the rx queue */
3821 set_bufsize(dev);
3822 if (nv_init_ring(dev)) {
3823 if (!np->in_shutdown)
3824 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3825 }
3826 /* reinit nic view of the rx queue */
3827 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3828 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3829 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3830 base + NvRegRingSizes);
3831 pci_push(base);
3832 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3833 pci_push(base);
3834 /* clear interrupts */
3835 if (!(np->msi_flags & NV_MSI_X_ENABLED))
3836 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
3837 else
3838 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
3839
3840 /* restart rx engine */
3841 nv_start_rxtx(dev);
3842 spin_unlock(&np->lock);
3843 netif_addr_unlock(dev);
3844 netif_tx_unlock_bh(dev);
3845 }
3846 }
3847
3848 writel(mask, base + NvRegIrqMask);
3849 pci_push(base);
3850
3851 if (!using_multi_irqs(dev)) {
3852 np->nic_poll_irq = 0;
3853 if (nv_optimized(np))
3854 nv_nic_irq_optimized(0, dev);
3855 else
3856 nv_nic_irq(0, dev);
3857 if (np->msi_flags & NV_MSI_X_ENABLED)
3858 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
3859 else
3860 enable_irq_lockdep(np->pci_dev->irq);
3861 } else {
3862 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
3863 np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
3864 nv_nic_irq_rx(0, dev);
3865 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
3866 }
3867 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
3868 np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
3869 nv_nic_irq_tx(0, dev);
3870 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
3871 }
3872 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
3873 np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
3874 nv_nic_irq_other(0, dev);
3875 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
3876 }
3877 }
3878
3879 }
3880
3881 #ifdef CONFIG_NET_POLL_CONTROLLER
3882 static void nv_poll_controller(struct net_device *dev)
3883 {
3884 nv_do_nic_poll((unsigned long) dev);
3885 }
3886 #endif
3887
3888 static void nv_do_stats_poll(unsigned long data)
3889 {
3890 struct net_device *dev = (struct net_device *) data;
3891 struct fe_priv *np = netdev_priv(dev);
3892
3893 nv_get_hw_stats(dev);
3894
3895 if (!np->in_shutdown)
3896 mod_timer(&np->stats_poll,
3897 round_jiffies(jiffies + STATS_INTERVAL));
3898 }
3899
3900 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
3901 {
3902 struct fe_priv *np = netdev_priv(dev);
3903 strcpy(info->driver, DRV_NAME);
3904 strcpy(info->version, FORCEDETH_VERSION);
3905 strcpy(info->bus_info, pci_name(np->pci_dev));
3906 }
3907
3908 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3909 {
3910 struct fe_priv *np = netdev_priv(dev);
3911 wolinfo->supported = WAKE_MAGIC;
3912
3913 spin_lock_irq(&np->lock);
3914 if (np->wolenabled)
3915 wolinfo->wolopts = WAKE_MAGIC;
3916 spin_unlock_irq(&np->lock);
3917 }
3918
3919 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
3920 {
3921 struct fe_priv *np = netdev_priv(dev);
3922 u8 __iomem *base = get_hwbase(dev);
3923 u32 flags = 0;
3924
3925 if (wolinfo->wolopts == 0) {
3926 np->wolenabled = 0;
3927 } else if (wolinfo->wolopts & WAKE_MAGIC) {
3928 np->wolenabled = 1;
3929 flags = NVREG_WAKEUPFLAGS_ENABLE;
3930 }
3931 if (netif_running(dev)) {
3932 spin_lock_irq(&np->lock);
3933 writel(flags, base + NvRegWakeUpFlags);
3934 spin_unlock_irq(&np->lock);
3935 }
3936 device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
3937 return 0;
3938 }
3939
3940 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3941 {
3942 struct fe_priv *np = netdev_priv(dev);
3943 u32 speed;
3944 int adv;
3945
3946 spin_lock_irq(&np->lock);
3947 ecmd->port = PORT_MII;
3948 if (!netif_running(dev)) {
3949 /* We do not track link speed / duplex setting if the
3950 * interface is disabled. Force a link check */
3951 if (nv_update_linkspeed(dev)) {
3952 if (!netif_carrier_ok(dev))
3953 netif_carrier_on(dev);
3954 } else {
3955 if (netif_carrier_ok(dev))
3956 netif_carrier_off(dev);
3957 }
3958 }
3959
3960 if (netif_carrier_ok(dev)) {
3961 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
3962 case NVREG_LINKSPEED_10:
3963 speed = SPEED_10;
3964 break;
3965 case NVREG_LINKSPEED_100:
3966 speed = SPEED_100;
3967 break;
3968 case NVREG_LINKSPEED_1000:
3969 speed = SPEED_1000;
3970 break;
3971 default:
3972 speed = -1;
3973 break;
3974 }
3975 ecmd->duplex = DUPLEX_HALF;
3976 if (np->duplex)
3977 ecmd->duplex = DUPLEX_FULL;
3978 } else {
3979 speed = -1;
3980 ecmd->duplex = -1;
3981 }
3982 ethtool_cmd_speed_set(ecmd, speed);
3983 ecmd->autoneg = np->autoneg;
3984
3985 ecmd->advertising = ADVERTISED_MII;
3986 if (np->autoneg) {
3987 ecmd->advertising |= ADVERTISED_Autoneg;
3988 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3989 if (adv & ADVERTISE_10HALF)
3990 ecmd->advertising |= ADVERTISED_10baseT_Half;
3991 if (adv & ADVERTISE_10FULL)
3992 ecmd->advertising |= ADVERTISED_10baseT_Full;
3993 if (adv & ADVERTISE_100HALF)
3994 ecmd->advertising |= ADVERTISED_100baseT_Half;
3995 if (adv & ADVERTISE_100FULL)
3996 ecmd->advertising |= ADVERTISED_100baseT_Full;
3997 if (np->gigabit == PHY_GIGABIT) {
3998 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3999 if (adv & ADVERTISE_1000FULL)
4000 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4001 }
4002 }
4003 ecmd->supported = (SUPPORTED_Autoneg |
4004 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4005 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4006 SUPPORTED_MII);
4007 if (np->gigabit == PHY_GIGABIT)
4008 ecmd->supported |= SUPPORTED_1000baseT_Full;
4009
4010 ecmd->phy_address = np->phyaddr;
4011 ecmd->transceiver = XCVR_EXTERNAL;
4012
4013 /* ignore maxtxpkt, maxrxpkt for now */
4014 spin_unlock_irq(&np->lock);
4015 return 0;
4016 }
4017
4018 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4019 {
4020 struct fe_priv *np = netdev_priv(dev);
4021 u32 speed = ethtool_cmd_speed(ecmd);
4022
4023 if (ecmd->port != PORT_MII)
4024 return -EINVAL;
4025 if (ecmd->transceiver != XCVR_EXTERNAL)
4026 return -EINVAL;
4027 if (ecmd->phy_address != np->phyaddr) {
4028 /* TODO: support switching between multiple phys. Should be
4029 * trivial, but not enabled due to lack of test hardware. */
4030 return -EINVAL;
4031 }
4032 if (ecmd->autoneg == AUTONEG_ENABLE) {
4033 u32 mask;
4034
4035 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4036 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4037 if (np->gigabit == PHY_GIGABIT)
4038 mask |= ADVERTISED_1000baseT_Full;
4039
4040 if ((ecmd->advertising & mask) == 0)
4041 return -EINVAL;
4042
4043 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4044 /* Note: autonegotiation disable, speed 1000 intentionally
4045 * forbidden - no one should need that. */
4046
4047 if (speed != SPEED_10 && speed != SPEED_100)
4048 return -EINVAL;
4049 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4050 return -EINVAL;
4051 } else {
4052 return -EINVAL;
4053 }
4054
4055 netif_carrier_off(dev);
4056 if (netif_running(dev)) {
4057 unsigned long flags;
4058
4059 nv_disable_irq(dev);
4060 netif_tx_lock_bh(dev);
4061 netif_addr_lock(dev);
4062 /* with plain spinlock lockdep complains */
4063 spin_lock_irqsave(&np->lock, flags);
4064 /* stop engines */
4065 /* FIXME:
4066 * this can take some time, and interrupts are disabled
4067 * due to spin_lock_irqsave, but let's hope no daemon
4068 * is going to change the settings very often...
4069 * Worst case:
4070 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4071 * + some minor delays, which is up to a second approximately
4072 */
4073 nv_stop_rxtx(dev);
4074 spin_unlock_irqrestore(&np->lock, flags);
4075 netif_addr_unlock(dev);
4076 netif_tx_unlock_bh(dev);
4077 }
4078
4079 if (ecmd->autoneg == AUTONEG_ENABLE) {
4080 int adv, bmcr;
4081
4082 np->autoneg = 1;
4083
4084 /* advertise only what has been requested */
4085 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4086 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4087 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4088 adv |= ADVERTISE_10HALF;
4089 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4090 adv |= ADVERTISE_10FULL;
4091 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4092 adv |= ADVERTISE_100HALF;
4093 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4094 adv |= ADVERTISE_100FULL;
4095 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4096 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4097 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4098 adv |= ADVERTISE_PAUSE_ASYM;
4099 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4100
4101 if (np->gigabit == PHY_GIGABIT) {
4102 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4103 adv &= ~ADVERTISE_1000FULL;
4104 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4105 adv |= ADVERTISE_1000FULL;
4106 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4107 }
4108
4109 if (netif_running(dev))
4110 netdev_info(dev, "link down\n");
4111 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4112 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4113 bmcr |= BMCR_ANENABLE;
4114 /* reset the phy in order for settings to stick,
4115 * and cause autoneg to start */
4116 if (phy_reset(dev, bmcr)) {
4117 netdev_info(dev, "phy reset failed\n");
4118 return -EINVAL;
4119 }
4120 } else {
4121 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4122 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4123 }
4124 } else {
4125 int adv, bmcr;
4126
4127 np->autoneg = 0;
4128
4129 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4130 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4131 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4132 adv |= ADVERTISE_10HALF;
4133 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4134 adv |= ADVERTISE_10FULL;
4135 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4136 adv |= ADVERTISE_100HALF;
4137 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4138 adv |= ADVERTISE_100FULL;
4139 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4140 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */
4141 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4142 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4143 }
4144 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4145 adv |= ADVERTISE_PAUSE_ASYM;
4146 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4147 }
4148 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4149 np->fixed_mode = adv;
4150
4151 if (np->gigabit == PHY_GIGABIT) {
4152 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4153 adv &= ~ADVERTISE_1000FULL;
4154 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4155 }
4156
4157 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4158 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4159 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4160 bmcr |= BMCR_FULLDPLX;
4161 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4162 bmcr |= BMCR_SPEED100;
4163 if (np->phy_oui == PHY_OUI_MARVELL) {
4164 /* reset the phy in order for forced mode settings to stick */
4165 if (phy_reset(dev, bmcr)) {
4166 netdev_info(dev, "phy reset failed\n");
4167 return -EINVAL;
4168 }
4169 } else {
4170 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4171 if (netif_running(dev)) {
4172 /* Wait a bit and then reconfigure the nic. */
4173 udelay(10);
4174 nv_linkchange(dev);
4175 }
4176 }
4177 }
4178
4179 if (netif_running(dev)) {
4180 nv_start_rxtx(dev);
4181 nv_enable_irq(dev);
4182 }
4183
4184 return 0;
4185 }
4186
4187 #define FORCEDETH_REGS_VER 1
4188
4189 static int nv_get_regs_len(struct net_device *dev)
4190 {
4191 struct fe_priv *np = netdev_priv(dev);
4192 return np->register_size;
4193 }
4194
4195 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4196 {
4197 struct fe_priv *np = netdev_priv(dev);
4198 u8 __iomem *base = get_hwbase(dev);
4199 u32 *rbuf = buf;
4200 int i;
4201
4202 regs->version = FORCEDETH_REGS_VER;
4203 spin_lock_irq(&np->lock);
4204 for (i = 0; i <= np->register_size/sizeof(u32); i++)
4205 rbuf[i] = readl(base + i*sizeof(u32));
4206 spin_unlock_irq(&np->lock);
4207 }
4208
4209 static int nv_nway_reset(struct net_device *dev)
4210 {
4211 struct fe_priv *np = netdev_priv(dev);
4212 int ret;
4213
4214 if (np->autoneg) {
4215 int bmcr;
4216
4217 netif_carrier_off(dev);
4218 if (netif_running(dev)) {
4219 nv_disable_irq(dev);
4220 netif_tx_lock_bh(dev);
4221 netif_addr_lock(dev);
4222 spin_lock(&np->lock);
4223 /* stop engines */
4224 nv_stop_rxtx(dev);
4225 spin_unlock(&np->lock);
4226 netif_addr_unlock(dev);
4227 netif_tx_unlock_bh(dev);
4228 netdev_info(dev, "link down\n");
4229 }
4230
4231 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4232 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4233 bmcr |= BMCR_ANENABLE;
4234 /* reset the phy in order for settings to stick*/
4235 if (phy_reset(dev, bmcr)) {
4236 netdev_info(dev, "phy reset failed\n");
4237 return -EINVAL;
4238 }
4239 } else {
4240 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4241 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4242 }
4243
4244 if (netif_running(dev)) {
4245 nv_start_rxtx(dev);
4246 nv_enable_irq(dev);
4247 }
4248 ret = 0;
4249 } else {
4250 ret = -EINVAL;
4251 }
4252
4253 return ret;
4254 }
4255
4256 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4257 {
4258 struct fe_priv *np = netdev_priv(dev);
4259
4260 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4261 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4262
4263 ring->rx_pending = np->rx_ring_size;
4264 ring->tx_pending = np->tx_ring_size;
4265 }
4266
4267 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4268 {
4269 struct fe_priv *np = netdev_priv(dev);
4270 u8 __iomem *base = get_hwbase(dev);
4271 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4272 dma_addr_t ring_addr;
4273
4274 if (ring->rx_pending < RX_RING_MIN ||
4275 ring->tx_pending < TX_RING_MIN ||
4276 ring->rx_mini_pending != 0 ||
4277 ring->rx_jumbo_pending != 0 ||
4278 (np->desc_ver == DESC_VER_1 &&
4279 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4280 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4281 (np->desc_ver != DESC_VER_1 &&
4282 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4283 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4284 return -EINVAL;
4285 }
4286
4287 /* allocate new rings */
4288 if (!nv_optimized(np)) {
4289 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4290 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4291 &ring_addr);
4292 } else {
4293 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4294 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4295 &ring_addr);
4296 }
4297 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4298 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4299 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4300 /* fall back to old rings */
4301 if (!nv_optimized(np)) {
4302 if (rxtx_ring)
4303 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4304 rxtx_ring, ring_addr);
4305 } else {
4306 if (rxtx_ring)
4307 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4308 rxtx_ring, ring_addr);
4309 }
4310
4311 kfree(rx_skbuff);
4312 kfree(tx_skbuff);
4313 goto exit;
4314 }
4315
4316 if (netif_running(dev)) {
4317 nv_disable_irq(dev);
4318 nv_napi_disable(dev);
4319 netif_tx_lock_bh(dev);
4320 netif_addr_lock(dev);
4321 spin_lock(&np->lock);
4322 /* stop engines */
4323 nv_stop_rxtx(dev);
4324 nv_txrx_reset(dev);
4325 /* drain queues */
4326 nv_drain_rxtx(dev);
4327 /* delete queues */
4328 free_rings(dev);
4329 }
4330
4331 /* set new values */
4332 np->rx_ring_size = ring->rx_pending;
4333 np->tx_ring_size = ring->tx_pending;
4334
4335 if (!nv_optimized(np)) {
4336 np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
4337 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4338 } else {
4339 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
4340 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4341 }
4342 np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4343 np->tx_skb = (struct nv_skb_map *)tx_skbuff;
4344 np->ring_addr = ring_addr;
4345
4346 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4347 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4348
4349 if (netif_running(dev)) {
4350 /* reinit driver view of the queues */
4351 set_bufsize(dev);
4352 if (nv_init_ring(dev)) {
4353 if (!np->in_shutdown)
4354 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4355 }
4356
4357 /* reinit nic view of the queues */
4358 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4359 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4360 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4361 base + NvRegRingSizes);
4362 pci_push(base);
4363 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4364 pci_push(base);
4365
4366 /* restart engines */
4367 nv_start_rxtx(dev);
4368 spin_unlock(&np->lock);
4369 netif_addr_unlock(dev);
4370 netif_tx_unlock_bh(dev);
4371 nv_napi_enable(dev);
4372 nv_enable_irq(dev);
4373 }
4374 return 0;
4375 exit:
4376 return -ENOMEM;
4377 }
4378
4379 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4380 {
4381 struct fe_priv *np = netdev_priv(dev);
4382
4383 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4384 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4385 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4386 }
4387
4388 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4389 {
4390 struct fe_priv *np = netdev_priv(dev);
4391 int adv, bmcr;
4392
4393 if ((!np->autoneg && np->duplex == 0) ||
4394 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4395 netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
4396 return -EINVAL;
4397 }
4398 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4399 netdev_info(dev, "hardware does not support tx pause frames\n");
4400 return -EINVAL;
4401 }
4402
4403 netif_carrier_off(dev);
4404 if (netif_running(dev)) {
4405 nv_disable_irq(dev);
4406 netif_tx_lock_bh(dev);
4407 netif_addr_lock(dev);
4408 spin_lock(&np->lock);
4409 /* stop engines */
4410 nv_stop_rxtx(dev);
4411 spin_unlock(&np->lock);
4412 netif_addr_unlock(dev);
4413 netif_tx_unlock_bh(dev);
4414 }
4415
4416 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4417 if (pause->rx_pause)
4418 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4419 if (pause->tx_pause)
4420 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4421
4422 if (np->autoneg && pause->autoneg) {
4423 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4424
4425 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4426 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4427 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4428 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4429 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4430 adv |= ADVERTISE_PAUSE_ASYM;
4431 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4432
4433 if (netif_running(dev))
4434 netdev_info(dev, "link down\n");
4435 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4436 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4437 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4438 } else {
4439 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4440 if (pause->rx_pause)
4441 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4442 if (pause->tx_pause)
4443 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4444
4445 if (!netif_running(dev))
4446 nv_update_linkspeed(dev);
4447 else
4448 nv_update_pause(dev, np->pause_flags);
4449 }
4450
4451 if (netif_running(dev)) {
4452 nv_start_rxtx(dev);
4453 nv_enable_irq(dev);
4454 }
4455 return 0;
4456 }
4457
4458 static u32 nv_fix_features(struct net_device *dev, u32 features)
4459 {
4460 /* vlan is dependent on rx checksum offload */
4461 if (features & (NETIF_F_HW_VLAN_TX|NETIF_F_HW_VLAN_RX))
4462 features |= NETIF_F_RXCSUM;
4463
4464 return features;
4465 }
4466
4467 static void nv_vlan_mode(struct net_device *dev, u32 features)
4468 {
4469 struct fe_priv *np = get_nvpriv(dev);
4470
4471 spin_lock_irq(&np->lock);
4472
4473 if (features & NETIF_F_HW_VLAN_RX)
4474 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP;
4475 else
4476 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4477
4478 if (features & NETIF_F_HW_VLAN_TX)
4479 np->txrxctl_bits |= NVREG_TXRXCTL_VLANINS;
4480 else
4481 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4482
4483 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4484
4485 spin_unlock_irq(&np->lock);
4486 }
4487
4488 static int nv_set_features(struct net_device *dev, u32 features)
4489 {
4490 struct fe_priv *np = netdev_priv(dev);
4491 u8 __iomem *base = get_hwbase(dev);
4492 u32 changed = dev->features ^ features;
4493
4494 if (changed & NETIF_F_RXCSUM) {
4495 spin_lock_irq(&np->lock);
4496
4497 if (features & NETIF_F_RXCSUM)
4498 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4499 else
4500 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4501
4502 if (netif_running(dev))
4503 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4504
4505 spin_unlock_irq(&np->lock);
4506 }
4507
4508 if (changed & (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX))
4509 nv_vlan_mode(dev, features);
4510
4511 return 0;
4512 }
4513
4514 static int nv_get_sset_count(struct net_device *dev, int sset)
4515 {
4516 struct fe_priv *np = netdev_priv(dev);
4517
4518 switch (sset) {
4519 case ETH_SS_TEST:
4520 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4521 return NV_TEST_COUNT_EXTENDED;
4522 else
4523 return NV_TEST_COUNT_BASE;
4524 case ETH_SS_STATS:
4525 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4526 return NV_DEV_STATISTICS_V3_COUNT;
4527 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4528 return NV_DEV_STATISTICS_V2_COUNT;
4529 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4530 return NV_DEV_STATISTICS_V1_COUNT;
4531 else
4532 return 0;
4533 default:
4534 return -EOPNOTSUPP;
4535 }
4536 }
4537
4538 static void nv_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *estats, u64 *buffer)
4539 {
4540 struct fe_priv *np = netdev_priv(dev);
4541
4542 /* update stats */
4543 nv_get_hw_stats(dev);
4544
4545 memcpy(buffer, &np->estats, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4546 }
4547
4548 static int nv_link_test(struct net_device *dev)
4549 {
4550 struct fe_priv *np = netdev_priv(dev);
4551 int mii_status;
4552
4553 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4554 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4555
4556 /* check phy link status */
4557 if (!(mii_status & BMSR_LSTATUS))
4558 return 0;
4559 else
4560 return 1;
4561 }
4562
4563 static int nv_register_test(struct net_device *dev)
4564 {
4565 u8 __iomem *base = get_hwbase(dev);
4566 int i = 0;
4567 u32 orig_read, new_read;
4568
4569 do {
4570 orig_read = readl(base + nv_registers_test[i].reg);
4571
4572 /* xor with mask to toggle bits */
4573 orig_read ^= nv_registers_test[i].mask;
4574
4575 writel(orig_read, base + nv_registers_test[i].reg);
4576
4577 new_read = readl(base + nv_registers_test[i].reg);
4578
4579 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4580 return 0;
4581
4582 /* restore original value */
4583 orig_read ^= nv_registers_test[i].mask;
4584 writel(orig_read, base + nv_registers_test[i].reg);
4585
4586 } while (nv_registers_test[++i].reg != 0);
4587
4588 return 1;
4589 }
4590
4591 static int nv_interrupt_test(struct net_device *dev)
4592 {
4593 struct fe_priv *np = netdev_priv(dev);
4594 u8 __iomem *base = get_hwbase(dev);
4595 int ret = 1;
4596 int testcnt;
4597 u32 save_msi_flags, save_poll_interval = 0;
4598
4599 if (netif_running(dev)) {
4600 /* free current irq */
4601 nv_free_irq(dev);
4602 save_poll_interval = readl(base+NvRegPollingInterval);
4603 }
4604
4605 /* flag to test interrupt handler */
4606 np->intr_test = 0;
4607
4608 /* setup test irq */
4609 save_msi_flags = np->msi_flags;
4610 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4611 np->msi_flags |= 0x001; /* setup 1 vector */
4612 if (nv_request_irq(dev, 1))
4613 return 0;
4614
4615 /* setup timer interrupt */
4616 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4617 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4618
4619 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4620
4621 /* wait for at least one interrupt */
4622 msleep(100);
4623
4624 spin_lock_irq(&np->lock);
4625
4626 /* flag should be set within ISR */
4627 testcnt = np->intr_test;
4628 if (!testcnt)
4629 ret = 2;
4630
4631 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4632 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4633 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4634 else
4635 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4636
4637 spin_unlock_irq(&np->lock);
4638
4639 nv_free_irq(dev);
4640
4641 np->msi_flags = save_msi_flags;
4642
4643 if (netif_running(dev)) {
4644 writel(save_poll_interval, base + NvRegPollingInterval);
4645 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4646 /* restore original irq */
4647 if (nv_request_irq(dev, 0))
4648 return 0;
4649 }
4650
4651 return ret;
4652 }
4653
4654 static int nv_loopback_test(struct net_device *dev)
4655 {
4656 struct fe_priv *np = netdev_priv(dev);
4657 u8 __iomem *base = get_hwbase(dev);
4658 struct sk_buff *tx_skb, *rx_skb;
4659 dma_addr_t test_dma_addr;
4660 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
4661 u32 flags;
4662 int len, i, pkt_len;
4663 u8 *pkt_data;
4664 u32 filter_flags = 0;
4665 u32 misc1_flags = 0;
4666 int ret = 1;
4667
4668 if (netif_running(dev)) {
4669 nv_disable_irq(dev);
4670 filter_flags = readl(base + NvRegPacketFilterFlags);
4671 misc1_flags = readl(base + NvRegMisc1);
4672 } else {
4673 nv_txrx_reset(dev);
4674 }
4675
4676 /* reinit driver view of the rx queue */
4677 set_bufsize(dev);
4678 nv_init_ring(dev);
4679
4680 /* setup hardware for loopback */
4681 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
4682 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
4683
4684 /* reinit nic view of the rx queue */
4685 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4686 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4687 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4688 base + NvRegRingSizes);
4689 pci_push(base);
4690
4691 /* restart rx engine */
4692 nv_start_rxtx(dev);
4693
4694 /* setup packet for tx */
4695 pkt_len = ETH_DATA_LEN;
4696 tx_skb = dev_alloc_skb(pkt_len);
4697 if (!tx_skb) {
4698 netdev_err(dev, "dev_alloc_skb() failed during loopback test\n");
4699 ret = 0;
4700 goto out;
4701 }
4702 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
4703 skb_tailroom(tx_skb),
4704 PCI_DMA_FROMDEVICE);
4705 pkt_data = skb_put(tx_skb, pkt_len);
4706 for (i = 0; i < pkt_len; i++)
4707 pkt_data[i] = (u8)(i & 0xff);
4708
4709 if (!nv_optimized(np)) {
4710 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
4711 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4712 } else {
4713 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
4714 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
4715 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
4716 }
4717 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4718 pci_push(get_hwbase(dev));
4719
4720 msleep(500);
4721
4722 /* check for rx of the packet */
4723 if (!nv_optimized(np)) {
4724 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
4725 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
4726
4727 } else {
4728 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
4729 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
4730 }
4731
4732 if (flags & NV_RX_AVAIL) {
4733 ret = 0;
4734 } else if (np->desc_ver == DESC_VER_1) {
4735 if (flags & NV_RX_ERROR)
4736 ret = 0;
4737 } else {
4738 if (flags & NV_RX2_ERROR)
4739 ret = 0;
4740 }
4741
4742 if (ret) {
4743 if (len != pkt_len) {
4744 ret = 0;
4745 } else {
4746 rx_skb = np->rx_skb[0].skb;
4747 for (i = 0; i < pkt_len; i++) {
4748 if (rx_skb->data[i] != (u8)(i & 0xff)) {
4749 ret = 0;
4750 break;
4751 }
4752 }
4753 }
4754 }
4755
4756 pci_unmap_single(np->pci_dev, test_dma_addr,
4757 (skb_end_pointer(tx_skb) - tx_skb->data),
4758 PCI_DMA_TODEVICE);
4759 dev_kfree_skb_any(tx_skb);
4760 out:
4761 /* stop engines */
4762 nv_stop_rxtx(dev);
4763 nv_txrx_reset(dev);
4764 /* drain rx queue */
4765 nv_drain_rxtx(dev);
4766
4767 if (netif_running(dev)) {
4768 writel(misc1_flags, base + NvRegMisc1);
4769 writel(filter_flags, base + NvRegPacketFilterFlags);
4770 nv_enable_irq(dev);
4771 }
4772
4773 return ret;
4774 }
4775
4776 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
4777 {
4778 struct fe_priv *np = netdev_priv(dev);
4779 u8 __iomem *base = get_hwbase(dev);
4780 int result;
4781 memset(buffer, 0, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(u64));
4782
4783 if (!nv_link_test(dev)) {
4784 test->flags |= ETH_TEST_FL_FAILED;
4785 buffer[0] = 1;
4786 }
4787
4788 if (test->flags & ETH_TEST_FL_OFFLINE) {
4789 if (netif_running(dev)) {
4790 netif_stop_queue(dev);
4791 nv_napi_disable(dev);
4792 netif_tx_lock_bh(dev);
4793 netif_addr_lock(dev);
4794 spin_lock_irq(&np->lock);
4795 nv_disable_hw_interrupts(dev, np->irqmask);
4796 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4797 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4798 else
4799 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4800 /* stop engines */
4801 nv_stop_rxtx(dev);
4802 nv_txrx_reset(dev);
4803 /* drain rx queue */
4804 nv_drain_rxtx(dev);
4805 spin_unlock_irq(&np->lock);
4806 netif_addr_unlock(dev);
4807 netif_tx_unlock_bh(dev);
4808 }
4809
4810 if (!nv_register_test(dev)) {
4811 test->flags |= ETH_TEST_FL_FAILED;
4812 buffer[1] = 1;
4813 }
4814
4815 result = nv_interrupt_test(dev);
4816 if (result != 1) {
4817 test->flags |= ETH_TEST_FL_FAILED;
4818 buffer[2] = 1;
4819 }
4820 if (result == 0) {
4821 /* bail out */
4822 return;
4823 }
4824
4825 if (!nv_loopback_test(dev)) {
4826 test->flags |= ETH_TEST_FL_FAILED;
4827 buffer[3] = 1;
4828 }
4829
4830 if (netif_running(dev)) {
4831 /* reinit driver view of the rx queue */
4832 set_bufsize(dev);
4833 if (nv_init_ring(dev)) {
4834 if (!np->in_shutdown)
4835 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4836 }
4837 /* reinit nic view of the rx queue */
4838 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4839 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4840 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4841 base + NvRegRingSizes);
4842 pci_push(base);
4843 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4844 pci_push(base);
4845 /* restart rx engine */
4846 nv_start_rxtx(dev);
4847 netif_start_queue(dev);
4848 nv_napi_enable(dev);
4849 nv_enable_hw_interrupts(dev, np->irqmask);
4850 }
4851 }
4852 }
4853
4854 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
4855 {
4856 switch (stringset) {
4857 case ETH_SS_STATS:
4858 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
4859 break;
4860 case ETH_SS_TEST:
4861 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
4862 break;
4863 }
4864 }
4865
4866 static const struct ethtool_ops ops = {
4867 .get_drvinfo = nv_get_drvinfo,
4868 .get_link = ethtool_op_get_link,
4869 .get_wol = nv_get_wol,
4870 .set_wol = nv_set_wol,
4871 .get_settings = nv_get_settings,
4872 .set_settings = nv_set_settings,
4873 .get_regs_len = nv_get_regs_len,
4874 .get_regs = nv_get_regs,
4875 .nway_reset = nv_nway_reset,
4876 .get_ringparam = nv_get_ringparam,
4877 .set_ringparam = nv_set_ringparam,
4878 .get_pauseparam = nv_get_pauseparam,
4879 .set_pauseparam = nv_set_pauseparam,
4880 .get_strings = nv_get_strings,
4881 .get_ethtool_stats = nv_get_ethtool_stats,
4882 .get_sset_count = nv_get_sset_count,
4883 .self_test = nv_self_test,
4884 };
4885
4886 /* The mgmt unit and driver use a semaphore to access the phy during init */
4887 static int nv_mgmt_acquire_sema(struct net_device *dev)
4888 {
4889 struct fe_priv *np = netdev_priv(dev);
4890 u8 __iomem *base = get_hwbase(dev);
4891 int i;
4892 u32 tx_ctrl, mgmt_sema;
4893
4894 for (i = 0; i < 10; i++) {
4895 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
4896 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
4897 break;
4898 msleep(500);
4899 }
4900
4901 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
4902 return 0;
4903
4904 for (i = 0; i < 2; i++) {
4905 tx_ctrl = readl(base + NvRegTransmitterControl);
4906 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
4907 writel(tx_ctrl, base + NvRegTransmitterControl);
4908
4909 /* verify that semaphore was acquired */
4910 tx_ctrl = readl(base + NvRegTransmitterControl);
4911 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
4912 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
4913 np->mgmt_sema = 1;
4914 return 1;
4915 } else
4916 udelay(50);
4917 }
4918
4919 return 0;
4920 }
4921
4922 static void nv_mgmt_release_sema(struct net_device *dev)
4923 {
4924 struct fe_priv *np = netdev_priv(dev);
4925 u8 __iomem *base = get_hwbase(dev);
4926 u32 tx_ctrl;
4927
4928 if (np->driver_data & DEV_HAS_MGMT_UNIT) {
4929 if (np->mgmt_sema) {
4930 tx_ctrl = readl(base + NvRegTransmitterControl);
4931 tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
4932 writel(tx_ctrl, base + NvRegTransmitterControl);
4933 }
4934 }
4935 }
4936
4937
4938 static int nv_mgmt_get_version(struct net_device *dev)
4939 {
4940 struct fe_priv *np = netdev_priv(dev);
4941 u8 __iomem *base = get_hwbase(dev);
4942 u32 data_ready = readl(base + NvRegTransmitterControl);
4943 u32 data_ready2 = 0;
4944 unsigned long start;
4945 int ready = 0;
4946
4947 writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
4948 writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
4949 start = jiffies;
4950 while (time_before(jiffies, start + 5*HZ)) {
4951 data_ready2 = readl(base + NvRegTransmitterControl);
4952 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
4953 ready = 1;
4954 break;
4955 }
4956 schedule_timeout_uninterruptible(1);
4957 }
4958
4959 if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
4960 return 0;
4961
4962 np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
4963
4964 return 1;
4965 }
4966
4967 static int nv_open(struct net_device *dev)
4968 {
4969 struct fe_priv *np = netdev_priv(dev);
4970 u8 __iomem *base = get_hwbase(dev);
4971 int ret = 1;
4972 int oom, i;
4973 u32 low;
4974
4975 /* power up phy */
4976 mii_rw(dev, np->phyaddr, MII_BMCR,
4977 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
4978
4979 nv_txrx_gate(dev, false);
4980 /* erase previous misconfiguration */
4981 if (np->driver_data & DEV_HAS_POWER_CNTRL)
4982 nv_mac_reset(dev);
4983 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
4984 writel(0, base + NvRegMulticastAddrB);
4985 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
4986 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
4987 writel(0, base + NvRegPacketFilterFlags);
4988
4989 writel(0, base + NvRegTransmitterControl);
4990 writel(0, base + NvRegReceiverControl);
4991
4992 writel(0, base + NvRegAdapterControl);
4993
4994 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
4995 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
4996
4997 /* initialize descriptor rings */
4998 set_bufsize(dev);
4999 oom = nv_init_ring(dev);
5000
5001 writel(0, base + NvRegLinkSpeed);
5002 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5003 nv_txrx_reset(dev);
5004 writel(0, base + NvRegUnknownSetupReg6);
5005
5006 np->in_shutdown = 0;
5007
5008 /* give hw rings */
5009 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5010 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5011 base + NvRegRingSizes);
5012
5013 writel(np->linkspeed, base + NvRegLinkSpeed);
5014 if (np->desc_ver == DESC_VER_1)
5015 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5016 else
5017 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5018 writel(np->txrxctl_bits, base + NvRegTxRxControl);
5019 writel(np->vlanctl_bits, base + NvRegVlanControl);
5020 pci_push(base);
5021 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5022 if (reg_delay(dev, NvRegUnknownSetupReg5,
5023 NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5024 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
5025 netdev_info(dev,
5026 "%s: SetupReg5, Bit 31 remained off\n", __func__);
5027
5028 writel(0, base + NvRegMIIMask);
5029 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5030 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5031
5032 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5033 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5034 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5035 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5036
5037 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5038
5039 get_random_bytes(&low, sizeof(low));
5040 low &= NVREG_SLOTTIME_MASK;
5041 if (np->desc_ver == DESC_VER_1) {
5042 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5043 } else {
5044 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5045 /* setup legacy backoff */
5046 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5047 } else {
5048 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5049 nv_gear_backoff_reseed(dev);
5050 }
5051 }
5052 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5053 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5054 if (poll_interval == -1) {
5055 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5056 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5057 else
5058 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5059 } else
5060 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5061 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5062 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5063 base + NvRegAdapterControl);
5064 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5065 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5066 if (np->wolenabled)
5067 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5068
5069 i = readl(base + NvRegPowerState);
5070 if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
5071 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5072
5073 pci_push(base);
5074 udelay(10);
5075 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5076
5077 nv_disable_hw_interrupts(dev, np->irqmask);
5078 pci_push(base);
5079 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5080 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5081 pci_push(base);
5082
5083 if (nv_request_irq(dev, 0))
5084 goto out_drain;
5085
5086 /* ask for interrupts */
5087 nv_enable_hw_interrupts(dev, np->irqmask);
5088
5089 spin_lock_irq(&np->lock);
5090 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5091 writel(0, base + NvRegMulticastAddrB);
5092 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5093 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5094 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5095 /* One manual link speed update: Interrupts are enabled, future link
5096 * speed changes cause interrupts and are handled by nv_link_irq().
5097 */
5098 {
5099 u32 miistat;
5100 miistat = readl(base + NvRegMIIStatus);
5101 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5102 }
5103 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5104 * to init hw */
5105 np->linkspeed = 0;
5106 ret = nv_update_linkspeed(dev);
5107 nv_start_rxtx(dev);
5108 netif_start_queue(dev);
5109 nv_napi_enable(dev);
5110
5111 if (ret) {
5112 netif_carrier_on(dev);
5113 } else {
5114 netdev_info(dev, "no link during initialization\n");
5115 netif_carrier_off(dev);
5116 }
5117 if (oom)
5118 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5119
5120 /* start statistics timer */
5121 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5122 mod_timer(&np->stats_poll,
5123 round_jiffies(jiffies + STATS_INTERVAL));
5124
5125 spin_unlock_irq(&np->lock);
5126
5127 return 0;
5128 out_drain:
5129 nv_drain_rxtx(dev);
5130 return ret;
5131 }
5132
5133 static int nv_close(struct net_device *dev)
5134 {
5135 struct fe_priv *np = netdev_priv(dev);
5136 u8 __iomem *base;
5137
5138 spin_lock_irq(&np->lock);
5139 np->in_shutdown = 1;
5140 spin_unlock_irq(&np->lock);
5141 nv_napi_disable(dev);
5142 synchronize_irq(np->pci_dev->irq);
5143
5144 del_timer_sync(&np->oom_kick);
5145 del_timer_sync(&np->nic_poll);
5146 del_timer_sync(&np->stats_poll);
5147
5148 netif_stop_queue(dev);
5149 spin_lock_irq(&np->lock);
5150 nv_stop_rxtx(dev);
5151 nv_txrx_reset(dev);
5152
5153 /* disable interrupts on the nic or we will lock up */
5154 base = get_hwbase(dev);
5155 nv_disable_hw_interrupts(dev, np->irqmask);
5156 pci_push(base);
5157
5158 spin_unlock_irq(&np->lock);
5159
5160 nv_free_irq(dev);
5161
5162 nv_drain_rxtx(dev);
5163
5164 if (np->wolenabled || !phy_power_down) {
5165 nv_txrx_gate(dev, false);
5166 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5167 nv_start_rx(dev);
5168 } else {
5169 /* power down phy */
5170 mii_rw(dev, np->phyaddr, MII_BMCR,
5171 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5172 nv_txrx_gate(dev, true);
5173 }
5174
5175 /* FIXME: power down nic */
5176
5177 return 0;
5178 }
5179
5180 static const struct net_device_ops nv_netdev_ops = {
5181 .ndo_open = nv_open,
5182 .ndo_stop = nv_close,
5183 .ndo_get_stats = nv_get_stats,
5184 .ndo_start_xmit = nv_start_xmit,
5185 .ndo_tx_timeout = nv_tx_timeout,
5186 .ndo_change_mtu = nv_change_mtu,
5187 .ndo_fix_features = nv_fix_features,
5188 .ndo_set_features = nv_set_features,
5189 .ndo_validate_addr = eth_validate_addr,
5190 .ndo_set_mac_address = nv_set_mac_address,
5191 .ndo_set_rx_mode = nv_set_multicast,
5192 #ifdef CONFIG_NET_POLL_CONTROLLER
5193 .ndo_poll_controller = nv_poll_controller,
5194 #endif
5195 };
5196
5197 static const struct net_device_ops nv_netdev_ops_optimized = {
5198 .ndo_open = nv_open,
5199 .ndo_stop = nv_close,
5200 .ndo_get_stats = nv_get_stats,
5201 .ndo_start_xmit = nv_start_xmit_optimized,
5202 .ndo_tx_timeout = nv_tx_timeout,
5203 .ndo_change_mtu = nv_change_mtu,
5204 .ndo_fix_features = nv_fix_features,
5205 .ndo_set_features = nv_set_features,
5206 .ndo_validate_addr = eth_validate_addr,
5207 .ndo_set_mac_address = nv_set_mac_address,
5208 .ndo_set_rx_mode = nv_set_multicast,
5209 #ifdef CONFIG_NET_POLL_CONTROLLER
5210 .ndo_poll_controller = nv_poll_controller,
5211 #endif
5212 };
5213
5214 static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5215 {
5216 struct net_device *dev;
5217 struct fe_priv *np;
5218 unsigned long addr;
5219 u8 __iomem *base;
5220 int err, i;
5221 u32 powerstate, txreg;
5222 u32 phystate_orig = 0, phystate;
5223 int phyinitialized = 0;
5224 static int printed_version;
5225
5226 if (!printed_version++)
5227 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5228 FORCEDETH_VERSION);
5229
5230 dev = alloc_etherdev(sizeof(struct fe_priv));
5231 err = -ENOMEM;
5232 if (!dev)
5233 goto out;
5234
5235 np = netdev_priv(dev);
5236 np->dev = dev;
5237 np->pci_dev = pci_dev;
5238 spin_lock_init(&np->lock);
5239 SET_NETDEV_DEV(dev, &pci_dev->dev);
5240
5241 init_timer(&np->oom_kick);
5242 np->oom_kick.data = (unsigned long) dev;
5243 np->oom_kick.function = nv_do_rx_refill; /* timer handler */
5244 init_timer(&np->nic_poll);
5245 np->nic_poll.data = (unsigned long) dev;
5246 np->nic_poll.function = nv_do_nic_poll; /* timer handler */
5247 init_timer(&np->stats_poll);
5248 np->stats_poll.data = (unsigned long) dev;
5249 np->stats_poll.function = nv_do_stats_poll; /* timer handler */
5250
5251 err = pci_enable_device(pci_dev);
5252 if (err)
5253 goto out_free;
5254
5255 pci_set_master(pci_dev);
5256
5257 err = pci_request_regions(pci_dev, DRV_NAME);
5258 if (err < 0)
5259 goto out_disable;
5260
5261 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5262 np->register_size = NV_PCI_REGSZ_VER3;
5263 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5264 np->register_size = NV_PCI_REGSZ_VER2;
5265 else
5266 np->register_size = NV_PCI_REGSZ_VER1;
5267
5268 err = -EINVAL;
5269 addr = 0;
5270 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5271 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5272 pci_resource_len(pci_dev, i) >= np->register_size) {
5273 addr = pci_resource_start(pci_dev, i);
5274 break;
5275 }
5276 }
5277 if (i == DEVICE_COUNT_RESOURCE) {
5278 dev_info(&pci_dev->dev, "Couldn't find register window\n");
5279 goto out_relreg;
5280 }
5281
5282 /* copy of driver data */
5283 np->driver_data = id->driver_data;
5284 /* copy of device id */
5285 np->device_id = id->device;
5286
5287 /* handle different descriptor versions */
5288 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5289 /* packet format 3: supports 40-bit addressing */
5290 np->desc_ver = DESC_VER_3;
5291 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5292 if (dma_64bit) {
5293 if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5294 dev_info(&pci_dev->dev,
5295 "64-bit DMA failed, using 32-bit addressing\n");
5296 else
5297 dev->features |= NETIF_F_HIGHDMA;
5298 if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5299 dev_info(&pci_dev->dev,
5300 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5301 }
5302 }
5303 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5304 /* packet format 2: supports jumbo frames */
5305 np->desc_ver = DESC_VER_2;
5306 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5307 } else {
5308 /* original packet format */
5309 np->desc_ver = DESC_VER_1;
5310 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5311 }
5312
5313 np->pkt_limit = NV_PKTLIMIT_1;
5314 if (id->driver_data & DEV_HAS_LARGEDESC)
5315 np->pkt_limit = NV_PKTLIMIT_2;
5316
5317 if (id->driver_data & DEV_HAS_CHECKSUM) {
5318 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5319 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG |
5320 NETIF_F_TSO | NETIF_F_RXCSUM;
5321 }
5322
5323 np->vlanctl_bits = 0;
5324 if (id->driver_data & DEV_HAS_VLAN) {
5325 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5326 dev->hw_features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX;
5327 }
5328
5329 dev->features |= dev->hw_features;
5330
5331 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5332 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5333 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5334 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5335 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5336 }
5337
5338 err = -ENOMEM;
5339 np->base = ioremap(addr, np->register_size);
5340 if (!np->base)
5341 goto out_relreg;
5342 dev->base_addr = (unsigned long)np->base;
5343
5344 dev->irq = pci_dev->irq;
5345
5346 np->rx_ring_size = RX_RING_DEFAULT;
5347 np->tx_ring_size = TX_RING_DEFAULT;
5348
5349 if (!nv_optimized(np)) {
5350 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5351 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5352 &np->ring_addr);
5353 if (!np->rx_ring.orig)
5354 goto out_unmap;
5355 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5356 } else {
5357 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5358 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5359 &np->ring_addr);
5360 if (!np->rx_ring.ex)
5361 goto out_unmap;
5362 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5363 }
5364 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5365 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5366 if (!np->rx_skb || !np->tx_skb)
5367 goto out_freering;
5368
5369 if (!nv_optimized(np))
5370 dev->netdev_ops = &nv_netdev_ops;
5371 else
5372 dev->netdev_ops = &nv_netdev_ops_optimized;
5373
5374 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5375 SET_ETHTOOL_OPS(dev, &ops);
5376 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5377
5378 pci_set_drvdata(pci_dev, dev);
5379
5380 /* read the mac address */
5381 base = get_hwbase(dev);
5382 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5383 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5384
5385 /* check the workaround bit for correct mac address order */
5386 txreg = readl(base + NvRegTransmitPoll);
5387 if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5388 /* mac address is already in correct order */
5389 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5390 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5391 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5392 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5393 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5394 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5395 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5396 /* mac address is already in correct order */
5397 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5398 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5399 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5400 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5401 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5402 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5403 /*
5404 * Set orig mac address back to the reversed version.
5405 * This flag will be cleared during low power transition.
5406 * Therefore, we should always put back the reversed address.
5407 */
5408 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5409 (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5410 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5411 } else {
5412 /* need to reverse mac address to correct order */
5413 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5414 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5415 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5416 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5417 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5418 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
5419 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5420 dev_dbg(&pci_dev->dev,
5421 "%s: set workaround bit for reversed mac addr\n",
5422 __func__);
5423 }
5424 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
5425
5426 if (!is_valid_ether_addr(dev->perm_addr)) {
5427 /*
5428 * Bad mac address. At least one bios sets the mac address
5429 * to 01:23:45:67:89:ab
5430 */
5431 dev_err(&pci_dev->dev,
5432 "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
5433 dev->dev_addr);
5434 random_ether_addr(dev->dev_addr);
5435 dev_err(&pci_dev->dev,
5436 "Using random MAC address: %pM\n", dev->dev_addr);
5437 }
5438
5439 /* set mac address */
5440 nv_copy_mac_to_hw(dev);
5441
5442 /* disable WOL */
5443 writel(0, base + NvRegWakeUpFlags);
5444 np->wolenabled = 0;
5445 device_set_wakeup_enable(&pci_dev->dev, false);
5446
5447 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5448
5449 /* take phy and nic out of low power mode */
5450 powerstate = readl(base + NvRegPowerState2);
5451 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5452 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5453 pci_dev->revision >= 0xA3)
5454 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5455 writel(powerstate, base + NvRegPowerState2);
5456 }
5457
5458 if (np->desc_ver == DESC_VER_1)
5459 np->tx_flags = NV_TX_VALID;
5460 else
5461 np->tx_flags = NV_TX2_VALID;
5462
5463 np->msi_flags = 0;
5464 if ((id->driver_data & DEV_HAS_MSI) && msi)
5465 np->msi_flags |= NV_MSI_CAPABLE;
5466
5467 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5468 /* msix has had reported issues when modifying irqmask
5469 as in the case of napi, therefore, disable for now
5470 */
5471 #if 0
5472 np->msi_flags |= NV_MSI_X_CAPABLE;
5473 #endif
5474 }
5475
5476 if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5477 np->irqmask = NVREG_IRQMASK_CPU;
5478 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5479 np->msi_flags |= 0x0001;
5480 } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5481 !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5482 /* start off in throughput mode */
5483 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5484 /* remove support for msix mode */
5485 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5486 } else {
5487 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5488 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5489 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5490 np->msi_flags |= 0x0003;
5491 }
5492
5493 if (id->driver_data & DEV_NEED_TIMERIRQ)
5494 np->irqmask |= NVREG_IRQ_TIMER;
5495 if (id->driver_data & DEV_NEED_LINKTIMER) {
5496 np->need_linktimer = 1;
5497 np->link_timeout = jiffies + LINK_TIMEOUT;
5498 } else {
5499 np->need_linktimer = 0;
5500 }
5501
5502 /* Limit the number of tx's outstanding for hw bug */
5503 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5504 np->tx_limit = 1;
5505 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
5506 pci_dev->revision >= 0xA2)
5507 np->tx_limit = 0;
5508 }
5509
5510 /* clear phy state and temporarily halt phy interrupts */
5511 writel(0, base + NvRegMIIMask);
5512 phystate = readl(base + NvRegAdapterControl);
5513 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5514 phystate_orig = 1;
5515 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5516 writel(phystate, base + NvRegAdapterControl);
5517 }
5518 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5519
5520 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5521 /* management unit running on the mac? */
5522 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5523 (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5524 nv_mgmt_acquire_sema(dev) &&
5525 nv_mgmt_get_version(dev)) {
5526 np->mac_in_use = 1;
5527 if (np->mgmt_version > 0)
5528 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5529 /* management unit setup the phy already? */
5530 if (np->mac_in_use &&
5531 ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5532 NVREG_XMITCTL_SYNC_PHY_INIT)) {
5533 /* phy is inited by mgmt unit */
5534 phyinitialized = 1;
5535 } else {
5536 /* we need to init the phy */
5537 }
5538 }
5539 }
5540
5541 /* find a suitable phy */
5542 for (i = 1; i <= 32; i++) {
5543 int id1, id2;
5544 int phyaddr = i & 0x1F;
5545
5546 spin_lock_irq(&np->lock);
5547 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5548 spin_unlock_irq(&np->lock);
5549 if (id1 < 0 || id1 == 0xffff)
5550 continue;
5551 spin_lock_irq(&np->lock);
5552 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5553 spin_unlock_irq(&np->lock);
5554 if (id2 < 0 || id2 == 0xffff)
5555 continue;
5556
5557 np->phy_model = id2 & PHYID2_MODEL_MASK;
5558 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5559 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5560 np->phyaddr = phyaddr;
5561 np->phy_oui = id1 | id2;
5562
5563 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5564 if (np->phy_oui == PHY_OUI_REALTEK2)
5565 np->phy_oui = PHY_OUI_REALTEK;
5566 /* Setup phy revision for Realtek */
5567 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5568 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5569
5570 break;
5571 }
5572 if (i == 33) {
5573 dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n");
5574 goto out_error;
5575 }
5576
5577 if (!phyinitialized) {
5578 /* reset it */
5579 phy_init(dev);
5580 } else {
5581 /* see if it is a gigabit phy */
5582 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5583 if (mii_status & PHY_GIGABIT)
5584 np->gigabit = PHY_GIGABIT;
5585 }
5586
5587 /* set default link speed settings */
5588 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5589 np->duplex = 0;
5590 np->autoneg = 1;
5591
5592 err = register_netdev(dev);
5593 if (err) {
5594 dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err);
5595 goto out_error;
5596 }
5597
5598 if (id->driver_data & DEV_HAS_VLAN)
5599 nv_vlan_mode(dev, dev->features);
5600
5601 netif_carrier_off(dev);
5602
5603 dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
5604 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
5605
5606 dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5607 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
5608 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
5609 "csum " : "",
5610 dev->features & (NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_TX) ?
5611 "vlan " : "",
5612 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
5613 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
5614 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
5615 np->gigabit == PHY_GIGABIT ? "gbit " : "",
5616 np->need_linktimer ? "lnktim " : "",
5617 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
5618 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
5619 np->desc_ver);
5620
5621 return 0;
5622
5623 out_error:
5624 if (phystate_orig)
5625 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
5626 pci_set_drvdata(pci_dev, NULL);
5627 out_freering:
5628 free_rings(dev);
5629 out_unmap:
5630 iounmap(get_hwbase(dev));
5631 out_relreg:
5632 pci_release_regions(pci_dev);
5633 out_disable:
5634 pci_disable_device(pci_dev);
5635 out_free:
5636 free_netdev(dev);
5637 out:
5638 return err;
5639 }
5640
5641 static void nv_restore_phy(struct net_device *dev)
5642 {
5643 struct fe_priv *np = netdev_priv(dev);
5644 u16 phy_reserved, mii_control;
5645
5646 if (np->phy_oui == PHY_OUI_REALTEK &&
5647 np->phy_model == PHY_MODEL_REALTEK_8201 &&
5648 phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
5649 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
5650 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
5651 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
5652 phy_reserved |= PHY_REALTEK_INIT8;
5653 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
5654 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
5655
5656 /* restart auto negotiation */
5657 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
5658 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
5659 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
5660 }
5661 }
5662
5663 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
5664 {
5665 struct net_device *dev = pci_get_drvdata(pci_dev);
5666 struct fe_priv *np = netdev_priv(dev);
5667 u8 __iomem *base = get_hwbase(dev);
5668
5669 /* special op: write back the misordered MAC address - otherwise
5670 * the next nv_probe would see a wrong address.
5671 */
5672 writel(np->orig_mac[0], base + NvRegMacAddrA);
5673 writel(np->orig_mac[1], base + NvRegMacAddrB);
5674 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
5675 base + NvRegTransmitPoll);
5676 }
5677
5678 static void __devexit nv_remove(struct pci_dev *pci_dev)
5679 {
5680 struct net_device *dev = pci_get_drvdata(pci_dev);
5681
5682 unregister_netdev(dev);
5683
5684 nv_restore_mac_addr(pci_dev);
5685
5686 /* restore any phy related changes */
5687 nv_restore_phy(dev);
5688
5689 nv_mgmt_release_sema(dev);
5690
5691 /* free all structures */
5692 free_rings(dev);
5693 iounmap(get_hwbase(dev));
5694 pci_release_regions(pci_dev);
5695 pci_disable_device(pci_dev);
5696 free_netdev(dev);
5697 pci_set_drvdata(pci_dev, NULL);
5698 }
5699
5700 #ifdef CONFIG_PM_SLEEP
5701 static int nv_suspend(struct device *device)
5702 {
5703 struct pci_dev *pdev = to_pci_dev(device);
5704 struct net_device *dev = pci_get_drvdata(pdev);
5705 struct fe_priv *np = netdev_priv(dev);
5706 u8 __iomem *base = get_hwbase(dev);
5707 int i;
5708
5709 if (netif_running(dev)) {
5710 /* Gross. */
5711 nv_close(dev);
5712 }
5713 netif_device_detach(dev);
5714
5715 /* save non-pci configuration space */
5716 for (i = 0; i <= np->register_size/sizeof(u32); i++)
5717 np->saved_config_space[i] = readl(base + i*sizeof(u32));
5718
5719 return 0;
5720 }
5721
5722 static int nv_resume(struct device *device)
5723 {
5724 struct pci_dev *pdev = to_pci_dev(device);
5725 struct net_device *dev = pci_get_drvdata(pdev);
5726 struct fe_priv *np = netdev_priv(dev);
5727 u8 __iomem *base = get_hwbase(dev);
5728 int i, rc = 0;
5729
5730 /* restore non-pci configuration space */
5731 for (i = 0; i <= np->register_size/sizeof(u32); i++)
5732 writel(np->saved_config_space[i], base+i*sizeof(u32));
5733
5734 if (np->driver_data & DEV_NEED_MSI_FIX)
5735 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
5736
5737 /* restore phy state, including autoneg */
5738 phy_init(dev);
5739
5740 netif_device_attach(dev);
5741 if (netif_running(dev)) {
5742 rc = nv_open(dev);
5743 nv_set_multicast(dev);
5744 }
5745 return rc;
5746 }
5747
5748 static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
5749 #define NV_PM_OPS (&nv_pm_ops)
5750
5751 #else
5752 #define NV_PM_OPS NULL
5753 #endif /* CONFIG_PM_SLEEP */
5754
5755 #ifdef CONFIG_PM
5756 static void nv_shutdown(struct pci_dev *pdev)
5757 {
5758 struct net_device *dev = pci_get_drvdata(pdev);
5759 struct fe_priv *np = netdev_priv(dev);
5760
5761 if (netif_running(dev))
5762 nv_close(dev);
5763
5764 /*
5765 * Restore the MAC so a kernel started by kexec won't get confused.
5766 * If we really go for poweroff, we must not restore the MAC,
5767 * otherwise the MAC for WOL will be reversed at least on some boards.
5768 */
5769 if (system_state != SYSTEM_POWER_OFF)
5770 nv_restore_mac_addr(pdev);
5771
5772 pci_disable_device(pdev);
5773 /*
5774 * Apparently it is not possible to reinitialise from D3 hot,
5775 * only put the device into D3 if we really go for poweroff.
5776 */
5777 if (system_state == SYSTEM_POWER_OFF) {
5778 pci_wake_from_d3(pdev, np->wolenabled);
5779 pci_set_power_state(pdev, PCI_D3hot);
5780 }
5781 }
5782 #else
5783 #define nv_shutdown NULL
5784 #endif /* CONFIG_PM */
5785
5786 static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
5787 { /* nForce Ethernet Controller */
5788 PCI_DEVICE(0x10DE, 0x01C3),
5789 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5790 },
5791 { /* nForce2 Ethernet Controller */
5792 PCI_DEVICE(0x10DE, 0x0066),
5793 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5794 },
5795 { /* nForce3 Ethernet Controller */
5796 PCI_DEVICE(0x10DE, 0x00D6),
5797 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
5798 },
5799 { /* nForce3 Ethernet Controller */
5800 PCI_DEVICE(0x10DE, 0x0086),
5801 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5802 },
5803 { /* nForce3 Ethernet Controller */
5804 PCI_DEVICE(0x10DE, 0x008C),
5805 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5806 },
5807 { /* nForce3 Ethernet Controller */
5808 PCI_DEVICE(0x10DE, 0x00E6),
5809 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5810 },
5811 { /* nForce3 Ethernet Controller */
5812 PCI_DEVICE(0x10DE, 0x00DF),
5813 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
5814 },
5815 { /* CK804 Ethernet Controller */
5816 PCI_DEVICE(0x10DE, 0x0056),
5817 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5818 },
5819 { /* CK804 Ethernet Controller */
5820 PCI_DEVICE(0x10DE, 0x0057),
5821 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5822 },
5823 { /* MCP04 Ethernet Controller */
5824 PCI_DEVICE(0x10DE, 0x0037),
5825 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5826 },
5827 { /* MCP04 Ethernet Controller */
5828 PCI_DEVICE(0x10DE, 0x0038),
5829 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
5830 },
5831 { /* MCP51 Ethernet Controller */
5832 PCI_DEVICE(0x10DE, 0x0268),
5833 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
5834 },
5835 { /* MCP51 Ethernet Controller */
5836 PCI_DEVICE(0x10DE, 0x0269),
5837 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
5838 },
5839 { /* MCP55 Ethernet Controller */
5840 PCI_DEVICE(0x10DE, 0x0372),
5841 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
5842 },
5843 { /* MCP55 Ethernet Controller */
5844 PCI_DEVICE(0x10DE, 0x0373),
5845 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
5846 },
5847 { /* MCP61 Ethernet Controller */
5848 PCI_DEVICE(0x10DE, 0x03E5),
5849 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5850 },
5851 { /* MCP61 Ethernet Controller */
5852 PCI_DEVICE(0x10DE, 0x03E6),
5853 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5854 },
5855 { /* MCP61 Ethernet Controller */
5856 PCI_DEVICE(0x10DE, 0x03EE),
5857 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5858 },
5859 { /* MCP61 Ethernet Controller */
5860 PCI_DEVICE(0x10DE, 0x03EF),
5861 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
5862 },
5863 { /* MCP65 Ethernet Controller */
5864 PCI_DEVICE(0x10DE, 0x0450),
5865 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5866 },
5867 { /* MCP65 Ethernet Controller */
5868 PCI_DEVICE(0x10DE, 0x0451),
5869 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5870 },
5871 { /* MCP65 Ethernet Controller */
5872 PCI_DEVICE(0x10DE, 0x0452),
5873 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5874 },
5875 { /* MCP65 Ethernet Controller */
5876 PCI_DEVICE(0x10DE, 0x0453),
5877 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5878 },
5879 { /* MCP67 Ethernet Controller */
5880 PCI_DEVICE(0x10DE, 0x054C),
5881 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5882 },
5883 { /* MCP67 Ethernet Controller */
5884 PCI_DEVICE(0x10DE, 0x054D),
5885 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5886 },
5887 { /* MCP67 Ethernet Controller */
5888 PCI_DEVICE(0x10DE, 0x054E),
5889 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5890 },
5891 { /* MCP67 Ethernet Controller */
5892 PCI_DEVICE(0x10DE, 0x054F),
5893 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5894 },
5895 { /* MCP73 Ethernet Controller */
5896 PCI_DEVICE(0x10DE, 0x07DC),
5897 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5898 },
5899 { /* MCP73 Ethernet Controller */
5900 PCI_DEVICE(0x10DE, 0x07DD),
5901 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5902 },
5903 { /* MCP73 Ethernet Controller */
5904 PCI_DEVICE(0x10DE, 0x07DE),
5905 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5906 },
5907 { /* MCP73 Ethernet Controller */
5908 PCI_DEVICE(0x10DE, 0x07DF),
5909 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
5910 },
5911 { /* MCP77 Ethernet Controller */
5912 PCI_DEVICE(0x10DE, 0x0760),
5913 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5914 },
5915 { /* MCP77 Ethernet Controller */
5916 PCI_DEVICE(0x10DE, 0x0761),
5917 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5918 },
5919 { /* MCP77 Ethernet Controller */
5920 PCI_DEVICE(0x10DE, 0x0762),
5921 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5922 },
5923 { /* MCP77 Ethernet Controller */
5924 PCI_DEVICE(0x10DE, 0x0763),
5925 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5926 },
5927 { /* MCP79 Ethernet Controller */
5928 PCI_DEVICE(0x10DE, 0x0AB0),
5929 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5930 },
5931 { /* MCP79 Ethernet Controller */
5932 PCI_DEVICE(0x10DE, 0x0AB1),
5933 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5934 },
5935 { /* MCP79 Ethernet Controller */
5936 PCI_DEVICE(0x10DE, 0x0AB2),
5937 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5938 },
5939 { /* MCP79 Ethernet Controller */
5940 PCI_DEVICE(0x10DE, 0x0AB3),
5941 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
5942 },
5943 { /* MCP89 Ethernet Controller */
5944 PCI_DEVICE(0x10DE, 0x0D7D),
5945 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
5946 },
5947 {0,},
5948 };
5949
5950 static struct pci_driver driver = {
5951 .name = DRV_NAME,
5952 .id_table = pci_tbl,
5953 .probe = nv_probe,
5954 .remove = __devexit_p(nv_remove),
5955 .shutdown = nv_shutdown,
5956 .driver.pm = NV_PM_OPS,
5957 };
5958
5959 static int __init init_nic(void)
5960 {
5961 return pci_register_driver(&driver);
5962 }
5963
5964 static void __exit exit_nic(void)
5965 {
5966 pci_unregister_driver(&driver);
5967 }
5968
5969 module_param(max_interrupt_work, int, 0);
5970 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
5971 module_param(optimization_mode, int, 0);
5972 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
5973 module_param(poll_interval, int, 0);
5974 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
5975 module_param(msi, int, 0);
5976 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
5977 module_param(msix, int, 0);
5978 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
5979 module_param(dma_64bit, int, 0);
5980 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
5981 module_param(phy_cross, int, 0);
5982 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
5983 module_param(phy_power_down, int, 0);
5984 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
5985
5986 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
5987 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
5988 MODULE_LICENSE("GPL");
5989
5990 MODULE_DEVICE_TABLE(pci, pci_tbl);
5991
5992 module_init(init_nic);
5993 module_exit(exit_nic);