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spi-topcliff-pch: add recovery processing in case wait-event timeout
[zen-stable.git] / arch / powerpc / sysdev / ppc4xx_pci.c
blob4f05f75423462f7be3b7774cc87ef98cf17023a6
1 /*
2 * PCI / PCI-X / PCI-Express support for 4xx parts
3 *
4 * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
5 *
6 * Most PCI Express code is coming from Stefan Roese implementation for
7 * arch/ppc in the Denx tree, slightly reworked by me.
8 *
9 * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
10 *
11 * Some of that comes itself from a previous implementation for 440SPE only
12 * by Roland Dreier:
13 *
14 * Copyright (c) 2005 Cisco Systems. All rights reserved.
15 * Roland Dreier <rolandd@cisco.com>
16 *
17 */
18
19 #undef DEBUG
20
21 #include <linux/kernel.h>
22 #include <linux/pci.h>
23 #include <linux/init.h>
24 #include <linux/of.h>
25 #include <linux/bootmem.h>
26 #include <linux/delay.h>
27 #include <linux/slab.h>
28
29 #include <asm/io.h>
30 #include <asm/pci-bridge.h>
31 #include <asm/machdep.h>
32 #include <asm/dcr.h>
33 #include <asm/dcr-regs.h>
34 #include <mm/mmu_decl.h>
35
36 #include "ppc4xx_pci.h"
37
38 static int dma_offset_set;
39
40 #define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
41 #define U64_TO_U32_HIGH(val) ((u32)((val) >> 32))
42
43 #define RES_TO_U32_LOW(val) \
44 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_LOW(val) : (val))
45 #define RES_TO_U32_HIGH(val) \
46 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0))
47
48 static inline int ppc440spe_revA(void)
49 {
50 /* Catch both 440SPe variants, with and without RAID6 support */
51 if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890)
52 return 1;
53 else
54 return 0;
55 }
56
57 static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev)
58 {
59 struct pci_controller *hose;
60 int i;
61
62 if (dev->devfn != 0 || dev->bus->self != NULL)
63 return;
64
65 hose = pci_bus_to_host(dev->bus);
66 if (hose == NULL)
67 return;
68
69 if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") &&
70 !of_device_is_compatible(hose->dn, "ibm,plb-pcix") &&
71 !of_device_is_compatible(hose->dn, "ibm,plb-pci"))
72 return;
73
74 if (of_device_is_compatible(hose->dn, "ibm,plb440epx-pci") ||
75 of_device_is_compatible(hose->dn, "ibm,plb440grx-pci")) {
76 hose->indirect_type |= PPC_INDIRECT_TYPE_BROKEN_MRM;
77 }
78
79 /* Hide the PCI host BARs from the kernel as their content doesn't
80 * fit well in the resource management
81 */
82 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
83 dev->resource[i].start = dev->resource[i].end = 0;
84 dev->resource[i].flags = 0;
85 }
86
87 printk(KERN_INFO "PCI: Hiding 4xx host bridge resources %s\n",
88 pci_name(dev));
89 }
90 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_ppc4xx_pci_bridge);
91
92 static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
93 void __iomem *reg,
94 struct resource *res)
95 {
96 u64 size;
97 const u32 *ranges;
98 int rlen;
99 int pna = of_n_addr_cells(hose->dn);
100 int np = pna + 5;
101
102 /* Default */
103 res->start = 0;
104 size = 0x80000000;
105 res->end = size - 1;
106 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
107
108 /* Get dma-ranges property */
109 ranges = of_get_property(hose->dn, "dma-ranges", &rlen);
110 if (ranges == NULL)
111 goto out;
112
113 /* Walk it */
114 while ((rlen -= np * 4) >= 0) {
115 u32 pci_space = ranges[0];
116 u64 pci_addr = of_read_number(ranges + 1, 2);
117 u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3);
118 size = of_read_number(ranges + pna + 3, 2);
119 ranges += np;
120 if (cpu_addr == OF_BAD_ADDR || size == 0)
121 continue;
122
123 /* We only care about memory */
124 if ((pci_space & 0x03000000) != 0x02000000)
125 continue;
126
127 /* We currently only support memory at 0, and pci_addr
128 * within 32 bits space
129 */
130 if (cpu_addr != 0 || pci_addr > 0xffffffff) {
131 printk(KERN_WARNING "%s: Ignored unsupported dma range"
132 " 0x%016llx...0x%016llx -> 0x%016llx\n",
133 hose->dn->full_name,
134 pci_addr, pci_addr + size - 1, cpu_addr);
135 continue;
136 }
137
138 /* Check if not prefetchable */
139 if (!(pci_space & 0x40000000))
140 res->flags &= ~IORESOURCE_PREFETCH;
141
142
143 /* Use that */
144 res->start = pci_addr;
145 /* Beware of 32 bits resources */
146 if (sizeof(resource_size_t) == sizeof(u32) &&
147 (pci_addr + size) > 0x100000000ull)
148 res->end = 0xffffffff;
149 else
150 res->end = res->start + size - 1;
151 break;
152 }
153
154 /* We only support one global DMA offset */
155 if (dma_offset_set && pci_dram_offset != res->start) {
156 printk(KERN_ERR "%s: dma-ranges(s) mismatch\n",
157 hose->dn->full_name);
158 return -ENXIO;
159 }
160
161 /* Check that we can fit all of memory as we don't support
162 * DMA bounce buffers
163 */
164 if (size < total_memory) {
165 printk(KERN_ERR "%s: dma-ranges too small "
166 "(size=%llx total_memory=%llx)\n",
167 hose->dn->full_name, size, (u64)total_memory);
168 return -ENXIO;
169 }
170
171 /* Check we are a power of 2 size and that base is a multiple of size*/
172 if ((size & (size - 1)) != 0 ||
173 (res->start & (size - 1)) != 0) {
174 printk(KERN_ERR "%s: dma-ranges unaligned\n",
175 hose->dn->full_name);
176 return -ENXIO;
177 }
178
179 /* Check that we are fully contained within 32 bits space */
180 if (res->end > 0xffffffff) {
181 printk(KERN_ERR "%s: dma-ranges outside of 32 bits space\n",
182 hose->dn->full_name);
183 return -ENXIO;
184 }
185 out:
186 dma_offset_set = 1;
187 pci_dram_offset = res->start;
188 hose->dma_window_base_cur = res->start;
189 hose->dma_window_size = resource_size(res);
190
191 printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n",
192 pci_dram_offset);
193 printk(KERN_INFO "4xx PCI DMA window base to 0x%016llx\n",
194 (unsigned long long)hose->dma_window_base_cur);
195 printk(KERN_INFO "DMA window size 0x%016llx\n",
196 (unsigned long long)hose->dma_window_size);
197 return 0;
198 }
199
200 /*
201 * 4xx PCI 2.x part
202 */
203
204 static int __init ppc4xx_setup_one_pci_PMM(struct pci_controller *hose,
205 void __iomem *reg,
206 u64 plb_addr,
207 u64 pci_addr,
208 u64 size,
209 unsigned int flags,
210 int index)
211 {
212 u32 ma, pcila, pciha;
213
214 /* Hack warning ! The "old" PCI 2.x cell only let us configure the low
215 * 32-bit of incoming PLB addresses. The top 4 bits of the 36-bit
216 * address are actually hard wired to a value that appears to depend
217 * on the specific SoC. For example, it's 0 on 440EP and 1 on 440EPx.
218 *
219 * The trick here is we just crop those top bits and ignore them when
220 * programming the chip. That means the device-tree has to be right
221 * for the specific part used (we don't print a warning if it's wrong
222 * but on the other hand, you'll crash quickly enough), but at least
223 * this code should work whatever the hard coded value is
224 */
225 plb_addr &= 0xffffffffull;
226
227 /* Note: Due to the above hack, the test below doesn't actually test
228 * if you address is above 4G, but it tests that address and
229 * (address + size) are both contained in the same 4G
230 */
231 if ((plb_addr + size) > 0xffffffffull || !is_power_of_2(size) ||
232 size < 0x1000 || (plb_addr & (size - 1)) != 0) {
233 printk(KERN_WARNING "%s: Resource out of range\n",
234 hose->dn->full_name);
235 return -1;
236 }
237 ma = (0xffffffffu << ilog2(size)) | 1;
238 if (flags & IORESOURCE_PREFETCH)
239 ma |= 2;
240
241 pciha = RES_TO_U32_HIGH(pci_addr);
242 pcila = RES_TO_U32_LOW(pci_addr);
243
244 writel(plb_addr, reg + PCIL0_PMM0LA + (0x10 * index));
245 writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * index));
246 writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * index));
247 writel(ma, reg + PCIL0_PMM0MA + (0x10 * index));
248
249 return 0;
250 }
251
252 static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose,
253 void __iomem *reg)
254 {
255 int i, j, found_isa_hole = 0;
256
257 /* Setup outbound memory windows */
258 for (i = j = 0; i < 3; i++) {
259 struct resource *res = &hose->mem_resources[i];
260
261 /* we only care about memory windows */
262 if (!(res->flags & IORESOURCE_MEM))
263 continue;
264 if (j > 2) {
265 printk(KERN_WARNING "%s: Too many ranges\n",
266 hose->dn->full_name);
267 break;
268 }
269
270 /* Configure the resource */
271 if (ppc4xx_setup_one_pci_PMM(hose, reg,
272 res->start,
273 res->start - hose->pci_mem_offset,
274 resource_size(res),
275 res->flags,
276 j) == 0) {
277 j++;
278
279 /* If the resource PCI address is 0 then we have our
280 * ISA memory hole
281 */
282 if (res->start == hose->pci_mem_offset)
283 found_isa_hole = 1;
284 }
285 }
286
287 /* Handle ISA memory hole if not already covered */
288 if (j <= 2 && !found_isa_hole && hose->isa_mem_size)
289 if (ppc4xx_setup_one_pci_PMM(hose, reg, hose->isa_mem_phys, 0,
290 hose->isa_mem_size, 0, j) == 0)
291 printk(KERN_INFO "%s: Legacy ISA memory support enabled\n",
292 hose->dn->full_name);
293 }
294
295 static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose,
296 void __iomem *reg,
297 const struct resource *res)
298 {
299 resource_size_t size = resource_size(res);
300 u32 sa;
301
302 /* Calculate window size */
303 sa = (0xffffffffu << ilog2(size)) | 1;
304 sa |= 0x1;
305
306 /* RAM is always at 0 local for now */
307 writel(0, reg + PCIL0_PTM1LA);
308 writel(sa, reg + PCIL0_PTM1MS);
309
310 /* Map on PCI side */
311 early_write_config_dword(hose, hose->first_busno, 0,
312 PCI_BASE_ADDRESS_1, res->start);
313 early_write_config_dword(hose, hose->first_busno, 0,
314 PCI_BASE_ADDRESS_2, 0x00000000);
315 early_write_config_word(hose, hose->first_busno, 0,
316 PCI_COMMAND, 0x0006);
317 }
318
319 static void __init ppc4xx_probe_pci_bridge(struct device_node *np)
320 {
321 /* NYI */
322 struct resource rsrc_cfg;
323 struct resource rsrc_reg;
324 struct resource dma_window;
325 struct pci_controller *hose = NULL;
326 void __iomem *reg = NULL;
327 const int *bus_range;
328 int primary = 0;
329
330 /* Check if device is enabled */
331 if (!of_device_is_available(np)) {
332 printk(KERN_INFO "%s: Port disabled via device-tree\n",
333 np->full_name);
334 return;
335 }
336
337 /* Fetch config space registers address */
338 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
339 printk(KERN_ERR "%s: Can't get PCI config register base !",
340 np->full_name);
341 return;
342 }
343 /* Fetch host bridge internal registers address */
344 if (of_address_to_resource(np, 3, &rsrc_reg)) {
345 printk(KERN_ERR "%s: Can't get PCI internal register base !",
346 np->full_name);
347 return;
348 }
349
350 /* Check if primary bridge */
351 if (of_get_property(np, "primary", NULL))
352 primary = 1;
353
354 /* Get bus range if any */
355 bus_range = of_get_property(np, "bus-range", NULL);
356
357 /* Map registers */
358 reg = ioremap(rsrc_reg.start, resource_size(&rsrc_reg));
359 if (reg == NULL) {
360 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
361 goto fail;
362 }
363
364 /* Allocate the host controller data structure */
365 hose = pcibios_alloc_controller(np);
366 if (!hose)
367 goto fail;
368
369 hose->first_busno = bus_range ? bus_range[0] : 0x0;
370 hose->last_busno = bus_range ? bus_range[1] : 0xff;
371
372 /* Setup config space */
373 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
374
375 /* Disable all windows */
376 writel(0, reg + PCIL0_PMM0MA);
377 writel(0, reg + PCIL0_PMM1MA);
378 writel(0, reg + PCIL0_PMM2MA);
379 writel(0, reg + PCIL0_PTM1MS);
380 writel(0, reg + PCIL0_PTM2MS);
381
382 /* Parse outbound mapping resources */
383 pci_process_bridge_OF_ranges(hose, np, primary);
384
385 /* Parse inbound mapping resources */
386 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
387 goto fail;
388
389 /* Configure outbound ranges POMs */
390 ppc4xx_configure_pci_PMMs(hose, reg);
391
392 /* Configure inbound ranges PIMs */
393 ppc4xx_configure_pci_PTMs(hose, reg, &dma_window);
394
395 /* We don't need the registers anymore */
396 iounmap(reg);
397 return;
398
399 fail:
400 if (hose)
401 pcibios_free_controller(hose);
402 if (reg)
403 iounmap(reg);
404 }
405
406 /*
407 * 4xx PCI-X part
408 */
409
410 static int __init ppc4xx_setup_one_pcix_POM(struct pci_controller *hose,
411 void __iomem *reg,
412 u64 plb_addr,
413 u64 pci_addr,
414 u64 size,
415 unsigned int flags,
416 int index)
417 {
418 u32 lah, lal, pciah, pcial, sa;
419
420 if (!is_power_of_2(size) || size < 0x1000 ||
421 (plb_addr & (size - 1)) != 0) {
422 printk(KERN_WARNING "%s: Resource out of range\n",
423 hose->dn->full_name);
424 return -1;
425 }
426
427 /* Calculate register values */
428 lah = RES_TO_U32_HIGH(plb_addr);
429 lal = RES_TO_U32_LOW(plb_addr);
430 pciah = RES_TO_U32_HIGH(pci_addr);
431 pcial = RES_TO_U32_LOW(pci_addr);
432 sa = (0xffffffffu << ilog2(size)) | 0x1;
433
434 /* Program register values */
435 if (index == 0) {
436 writel(lah, reg + PCIX0_POM0LAH);
437 writel(lal, reg + PCIX0_POM0LAL);
438 writel(pciah, reg + PCIX0_POM0PCIAH);
439 writel(pcial, reg + PCIX0_POM0PCIAL);
440 writel(sa, reg + PCIX0_POM0SA);
441 } else {
442 writel(lah, reg + PCIX0_POM1LAH);
443 writel(lal, reg + PCIX0_POM1LAL);
444 writel(pciah, reg + PCIX0_POM1PCIAH);
445 writel(pcial, reg + PCIX0_POM1PCIAL);
446 writel(sa, reg + PCIX0_POM1SA);
447 }
448
449 return 0;
450 }
451
452 static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose,
453 void __iomem *reg)
454 {
455 int i, j, found_isa_hole = 0;
456
457 /* Setup outbound memory windows */
458 for (i = j = 0; i < 3; i++) {
459 struct resource *res = &hose->mem_resources[i];
460
461 /* we only care about memory windows */
462 if (!(res->flags & IORESOURCE_MEM))
463 continue;
464 if (j > 1) {
465 printk(KERN_WARNING "%s: Too many ranges\n",
466 hose->dn->full_name);
467 break;
468 }
469
470 /* Configure the resource */
471 if (ppc4xx_setup_one_pcix_POM(hose, reg,
472 res->start,
473 res->start - hose->pci_mem_offset,
474 resource_size(res),
475 res->flags,
476 j) == 0) {
477 j++;
478
479 /* If the resource PCI address is 0 then we have our
480 * ISA memory hole
481 */
482 if (res->start == hose->pci_mem_offset)
483 found_isa_hole = 1;
484 }
485 }
486
487 /* Handle ISA memory hole if not already covered */
488 if (j <= 1 && !found_isa_hole && hose->isa_mem_size)
489 if (ppc4xx_setup_one_pcix_POM(hose, reg, hose->isa_mem_phys, 0,
490 hose->isa_mem_size, 0, j) == 0)
491 printk(KERN_INFO "%s: Legacy ISA memory support enabled\n",
492 hose->dn->full_name);
493 }
494
495 static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose,
496 void __iomem *reg,
497 const struct resource *res,
498 int big_pim,
499 int enable_msi_hole)
500 {
501 resource_size_t size = resource_size(res);
502 u32 sa;
503
504 /* RAM is always at 0 */
505 writel(0x00000000, reg + PCIX0_PIM0LAH);
506 writel(0x00000000, reg + PCIX0_PIM0LAL);
507
508 /* Calculate window size */
509 sa = (0xffffffffu << ilog2(size)) | 1;
510 sa |= 0x1;
511 if (res->flags & IORESOURCE_PREFETCH)
512 sa |= 0x2;
513 if (enable_msi_hole)
514 sa |= 0x4;
515 writel(sa, reg + PCIX0_PIM0SA);
516 if (big_pim)
517 writel(0xffffffff, reg + PCIX0_PIM0SAH);
518
519 /* Map on PCI side */
520 writel(0x00000000, reg + PCIX0_BAR0H);
521 writel(res->start, reg + PCIX0_BAR0L);
522 writew(0x0006, reg + PCIX0_COMMAND);
523 }
524
525 static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
526 {
527 struct resource rsrc_cfg;
528 struct resource rsrc_reg;
529 struct resource dma_window;
530 struct pci_controller *hose = NULL;
531 void __iomem *reg = NULL;
532 const int *bus_range;
533 int big_pim = 0, msi = 0, primary = 0;
534
535 /* Fetch config space registers address */
536 if (of_address_to_resource(np, 0, &rsrc_cfg)) {
537 printk(KERN_ERR "%s:Can't get PCI-X config register base !",
538 np->full_name);
539 return;
540 }
541 /* Fetch host bridge internal registers address */
542 if (of_address_to_resource(np, 3, &rsrc_reg)) {
543 printk(KERN_ERR "%s: Can't get PCI-X internal register base !",
544 np->full_name);
545 return;
546 }
547
548 /* Check if it supports large PIMs (440GX) */
549 if (of_get_property(np, "large-inbound-windows", NULL))
550 big_pim = 1;
551
552 /* Check if we should enable MSIs inbound hole */
553 if (of_get_property(np, "enable-msi-hole", NULL))
554 msi = 1;
555
556 /* Check if primary bridge */
557 if (of_get_property(np, "primary", NULL))
558 primary = 1;
559
560 /* Get bus range if any */
561 bus_range = of_get_property(np, "bus-range", NULL);
562
563 /* Map registers */
564 reg = ioremap(rsrc_reg.start, resource_size(&rsrc_reg));
565 if (reg == NULL) {
566 printk(KERN_ERR "%s: Can't map registers !", np->full_name);
567 goto fail;
568 }
569
570 /* Allocate the host controller data structure */
571 hose = pcibios_alloc_controller(np);
572 if (!hose)
573 goto fail;
574
575 hose->first_busno = bus_range ? bus_range[0] : 0x0;
576 hose->last_busno = bus_range ? bus_range[1] : 0xff;
577
578 /* Setup config space */
579 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4,
580 PPC_INDIRECT_TYPE_SET_CFG_TYPE);
581
582 /* Disable all windows */
583 writel(0, reg + PCIX0_POM0SA);
584 writel(0, reg + PCIX0_POM1SA);
585 writel(0, reg + PCIX0_POM2SA);
586 writel(0, reg + PCIX0_PIM0SA);
587 writel(0, reg + PCIX0_PIM1SA);
588 writel(0, reg + PCIX0_PIM2SA);
589 if (big_pim) {
590 writel(0, reg + PCIX0_PIM0SAH);
591 writel(0, reg + PCIX0_PIM2SAH);
592 }
593
594 /* Parse outbound mapping resources */
595 pci_process_bridge_OF_ranges(hose, np, primary);
596
597 /* Parse inbound mapping resources */
598 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
599 goto fail;
600
601 /* Configure outbound ranges POMs */
602 ppc4xx_configure_pcix_POMs(hose, reg);
603
604 /* Configure inbound ranges PIMs */
605 ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi);
606
607 /* We don't need the registers anymore */
608 iounmap(reg);
609 return;
610
611 fail:
612 if (hose)
613 pcibios_free_controller(hose);
614 if (reg)
615 iounmap(reg);
616 }
617
618 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
619
620 /*
621 * 4xx PCI-Express part
622 *
623 * We support 3 parts currently based on the compatible property:
624 *
625 * ibm,plb-pciex-440spe
626 * ibm,plb-pciex-405ex
627 * ibm,plb-pciex-460ex
628 *
629 * Anything else will be rejected for now as they are all subtly
630 * different unfortunately.
631 *
632 */
633
634 #define MAX_PCIE_BUS_MAPPED 0x40
635
636 struct ppc4xx_pciex_port
637 {
638 struct pci_controller *hose;
639 struct device_node *node;
640 unsigned int index;
641 int endpoint;
642 int link;
643 int has_ibpre;
644 unsigned int sdr_base;
645 dcr_host_t dcrs;
646 struct resource cfg_space;
647 struct resource utl_regs;
648 void __iomem *utl_base;
649 };
650
651 static struct ppc4xx_pciex_port *ppc4xx_pciex_ports;
652 static unsigned int ppc4xx_pciex_port_count;
653
654 struct ppc4xx_pciex_hwops
655 {
656 bool want_sdr;
657 int (*core_init)(struct device_node *np);
658 int (*port_init_hw)(struct ppc4xx_pciex_port *port);
659 int (*setup_utl)(struct ppc4xx_pciex_port *port);
660 void (*check_link)(struct ppc4xx_pciex_port *port);
661 };
662
663 static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops;
664
665 static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
666 unsigned int sdr_offset,
667 unsigned int mask,
668 unsigned int value,
669 int timeout_ms)
670 {
671 u32 val;
672
673 while(timeout_ms--) {
674 val = mfdcri(SDR0, port->sdr_base + sdr_offset);
675 if ((val & mask) == value) {
676 pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
677 port->index, sdr_offset, timeout_ms, val);
678 return 0;
679 }
680 msleep(1);
681 }
682 return -1;
683 }
684
685 static int __init ppc4xx_pciex_port_reset_sdr(struct ppc4xx_pciex_port *port)
686 {
687 /* Wait for reset to complete */
688 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
689 printk(KERN_WARNING "PCIE%d: PGRST failed\n",
690 port->index);
691 return -1;
692 }
693 return 0;
694 }
695
696
697 static void __init ppc4xx_pciex_check_link_sdr(struct ppc4xx_pciex_port *port)
698 {
699 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index);
700
701 /* Check for card presence detect if supported, if not, just wait for
702 * link unconditionally.
703 *
704 * note that we don't fail if there is no link, we just filter out
705 * config space accesses. That way, it will be easier to implement
706 * hotplug later on.
707 */
708 if (!port->has_ibpre ||
709 !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
710 1 << 28, 1 << 28, 100)) {
711 printk(KERN_INFO
712 "PCIE%d: Device detected, waiting for link...\n",
713 port->index);
714 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
715 0x1000, 0x1000, 2000))
716 printk(KERN_WARNING
717 "PCIE%d: Link up failed\n", port->index);
718 else {
719 printk(KERN_INFO
720 "PCIE%d: link is up !\n", port->index);
721 port->link = 1;
722 }
723 } else
724 printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
725 }
726
727 #ifdef CONFIG_44x
728
729 /* Check various reset bits of the 440SPe PCIe core */
730 static int __init ppc440spe_pciex_check_reset(struct device_node *np)
731 {
732 u32 valPE0, valPE1, valPE2;
733 int err = 0;
734
735 /* SDR0_PEGPLLLCT1 reset */
736 if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) {
737 /*
738 * the PCIe core was probably already initialised
739 * by firmware - let's re-reset RCSSET regs
740 *
741 * -- Shouldn't we also re-reset the whole thing ? -- BenH
742 */
743 pr_debug("PCIE: SDR0_PLLLCT1 already reset.\n");
744 mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000);
745 mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000);
746 mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000);
747 }
748
749 valPE0 = mfdcri(SDR0, PESDR0_440SPE_RCSSET);
750 valPE1 = mfdcri(SDR0, PESDR1_440SPE_RCSSET);
751 valPE2 = mfdcri(SDR0, PESDR2_440SPE_RCSSET);
752
753 /* SDR0_PExRCSSET rstgu */
754 if (!(valPE0 & 0x01000000) ||
755 !(valPE1 & 0x01000000) ||
756 !(valPE2 & 0x01000000)) {
757 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n");
758 err = -1;
759 }
760
761 /* SDR0_PExRCSSET rstdl */
762 if (!(valPE0 & 0x00010000) ||
763 !(valPE1 & 0x00010000) ||
764 !(valPE2 & 0x00010000)) {
765 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n");
766 err = -1;
767 }
768
769 /* SDR0_PExRCSSET rstpyn */
770 if ((valPE0 & 0x00001000) ||
771 (valPE1 & 0x00001000) ||
772 (valPE2 & 0x00001000)) {
773 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n");
774 err = -1;
775 }
776
777 /* SDR0_PExRCSSET hldplb */
778 if ((valPE0 & 0x10000000) ||
779 (valPE1 & 0x10000000) ||
780 (valPE2 & 0x10000000)) {
781 printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n");
782 err = -1;
783 }
784
785 /* SDR0_PExRCSSET rdy */
786 if ((valPE0 & 0x00100000) ||
787 (valPE1 & 0x00100000) ||
788 (valPE2 & 0x00100000)) {
789 printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n");
790 err = -1;
791 }
792
793 /* SDR0_PExRCSSET shutdown */
794 if ((valPE0 & 0x00000100) ||
795 (valPE1 & 0x00000100) ||
796 (valPE2 & 0x00000100)) {
797 printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n");
798 err = -1;
799 }
800
801 return err;
802 }
803
804 /* Global PCIe core initializations for 440SPe core */
805 static int __init ppc440spe_pciex_core_init(struct device_node *np)
806 {
807 int time_out = 20;
808
809 /* Set PLL clock receiver to LVPECL */
810 dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28);
811
812 /* Shouldn't we do all the calibration stuff etc... here ? */
813 if (ppc440spe_pciex_check_reset(np))
814 return -ENXIO;
815
816 if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) {
817 printk(KERN_INFO "PCIE: PESDR_PLLCT2 resistance calibration "
818 "failed (0x%08x)\n",
819 mfdcri(SDR0, PESDR0_PLLLCT2));
820 return -1;
821 }
822
823 /* De-assert reset of PCIe PLL, wait for lock */
824 dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0);
825 udelay(3);
826
827 while (time_out) {
828 if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) {
829 time_out--;
830 udelay(1);
831 } else
832 break;
833 }
834 if (!time_out) {
835 printk(KERN_INFO "PCIE: VCO output not locked\n");
836 return -1;
837 }
838
839 pr_debug("PCIE initialization OK\n");
840
841 return 3;
842 }
843
844 static int __init ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
845 {
846 u32 val = 1 << 24;
847
848 if (port->endpoint)
849 val = PTYPE_LEGACY_ENDPOINT << 20;
850 else
851 val = PTYPE_ROOT_PORT << 20;
852
853 if (port->index == 0)
854 val |= LNKW_X8 << 12;
855 else
856 val |= LNKW_X4 << 12;
857
858 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
859 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);
860 if (ppc440spe_revA())
861 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);
862 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);
863 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);
864 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000);
865 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000);
866 if (port->index == 0) {
867 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1,
868 0x35000000);
869 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1,
870 0x35000000);
871 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1,
872 0x35000000);
873 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
874 0x35000000);
875 }
876 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
877 (1 << 24) | (1 << 16), 1 << 12);
878
879 return ppc4xx_pciex_port_reset_sdr(port);
880 }
881
882 static int __init ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
883 {
884 return ppc440spe_pciex_init_port_hw(port);
885 }
886
887 static int __init ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
888 {
889 int rc = ppc440spe_pciex_init_port_hw(port);
890
891 port->has_ibpre = 1;
892
893 return rc;
894 }
895
896 static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port)
897 {
898 /* XXX Check what that value means... I hate magic */
899 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800);
900
901 /*
902 * Set buffer allocations and then assert VRB and TXE.
903 */
904 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
905 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
906 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000);
907 out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000);
908 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000);
909 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000);
910 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
911 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
912
913 return 0;
914 }
915
916 static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port)
917 {
918 /* Report CRS to the operating system */
919 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
920
921 return 0;
922 }
923
924 static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
925 {
926 .want_sdr = true,
927 .core_init = ppc440spe_pciex_core_init,
928 .port_init_hw = ppc440speA_pciex_init_port_hw,
929 .setup_utl = ppc440speA_pciex_init_utl,
930 .check_link = ppc4xx_pciex_check_link_sdr,
931 };
932
933 static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
934 {
935 .want_sdr = true,
936 .core_init = ppc440spe_pciex_core_init,
937 .port_init_hw = ppc440speB_pciex_init_port_hw,
938 .setup_utl = ppc440speB_pciex_init_utl,
939 .check_link = ppc4xx_pciex_check_link_sdr,
940 };
941
942 static int __init ppc460ex_pciex_core_init(struct device_node *np)
943 {
944 /* Nothing to do, return 2 ports */
945 return 2;
946 }
947
948 static int __init ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
949 {
950 u32 val;
951 u32 utlset1;
952
953 if (port->endpoint)
954 val = PTYPE_LEGACY_ENDPOINT << 20;
955 else
956 val = PTYPE_ROOT_PORT << 20;
957
958 if (port->index == 0) {
959 val |= LNKW_X1 << 12;
960 utlset1 = 0x20000000;
961 } else {
962 val |= LNKW_X4 << 12;
963 utlset1 = 0x20101101;
964 }
965
966 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
967 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
968 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);
969
970 switch (port->index) {
971 case 0:
972 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
973 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
974 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
975
976 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000);
977 break;
978
979 case 1:
980 mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230);
981 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);
982 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);
983 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);
984 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130);
985 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130);
986 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130);
987 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130);
988 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);
989 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);
990 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);
991 mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006);
992
993 mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000);
994 break;
995 }
996
997 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
998 mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
999 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
1000
1001 /* Poll for PHY reset */
1002 /* XXX FIXME add timeout */
1003 switch (port->index) {
1004 case 0:
1005 while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1))
1006 udelay(10);
1007 break;
1008 case 1:
1009 while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1))
1010 udelay(10);
1011 break;
1012 }
1013
1014 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
1015 (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
1016 ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
1017 PESDRx_RCSSET_RSTPYN);
1018
1019 port->has_ibpre = 1;
1020
1021 return ppc4xx_pciex_port_reset_sdr(port);
1022 }
1023
1024 static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
1025 {
1026 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
1027
1028 /*
1029 * Set buffer allocations and then assert VRB and TXE.
1030 */
1031 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c);
1032 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000);
1033 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
1034 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
1035 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000);
1036 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
1037 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
1038 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000);
1039 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
1040
1041 return 0;
1042 }
1043
1044 static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
1045 {
1046 .want_sdr = true,
1047 .core_init = ppc460ex_pciex_core_init,
1048 .port_init_hw = ppc460ex_pciex_init_port_hw,
1049 .setup_utl = ppc460ex_pciex_init_utl,
1050 .check_link = ppc4xx_pciex_check_link_sdr,
1051 };
1052
1053 static int __init ppc460sx_pciex_core_init(struct device_node *np)
1054 {
1055 /* HSS drive amplitude */
1056 mtdcri(SDR0, PESDR0_460SX_HSSL0DAMP, 0xB9843211);
1057 mtdcri(SDR0, PESDR0_460SX_HSSL1DAMP, 0xB9843211);
1058 mtdcri(SDR0, PESDR0_460SX_HSSL2DAMP, 0xB9843211);
1059 mtdcri(SDR0, PESDR0_460SX_HSSL3DAMP, 0xB9843211);
1060 mtdcri(SDR0, PESDR0_460SX_HSSL4DAMP, 0xB9843211);
1061 mtdcri(SDR0, PESDR0_460SX_HSSL5DAMP, 0xB9843211);
1062 mtdcri(SDR0, PESDR0_460SX_HSSL6DAMP, 0xB9843211);
1063 mtdcri(SDR0, PESDR0_460SX_HSSL7DAMP, 0xB9843211);
1064
1065 mtdcri(SDR0, PESDR1_460SX_HSSL0DAMP, 0xB9843211);
1066 mtdcri(SDR0, PESDR1_460SX_HSSL1DAMP, 0xB9843211);
1067 mtdcri(SDR0, PESDR1_460SX_HSSL2DAMP, 0xB9843211);
1068 mtdcri(SDR0, PESDR1_460SX_HSSL3DAMP, 0xB9843211);
1069
1070 mtdcri(SDR0, PESDR2_460SX_HSSL0DAMP, 0xB9843211);
1071 mtdcri(SDR0, PESDR2_460SX_HSSL1DAMP, 0xB9843211);
1072 mtdcri(SDR0, PESDR2_460SX_HSSL2DAMP, 0xB9843211);
1073 mtdcri(SDR0, PESDR2_460SX_HSSL3DAMP, 0xB9843211);
1074
1075 /* HSS TX pre-emphasis */
1076 mtdcri(SDR0, PESDR0_460SX_HSSL0COEFA, 0xDCB98987);
1077 mtdcri(SDR0, PESDR0_460SX_HSSL1COEFA, 0xDCB98987);
1078 mtdcri(SDR0, PESDR0_460SX_HSSL2COEFA, 0xDCB98987);
1079 mtdcri(SDR0, PESDR0_460SX_HSSL3COEFA, 0xDCB98987);
1080 mtdcri(SDR0, PESDR0_460SX_HSSL4COEFA, 0xDCB98987);
1081 mtdcri(SDR0, PESDR0_460SX_HSSL5COEFA, 0xDCB98987);
1082 mtdcri(SDR0, PESDR0_460SX_HSSL6COEFA, 0xDCB98987);
1083 mtdcri(SDR0, PESDR0_460SX_HSSL7COEFA, 0xDCB98987);
1084
1085 mtdcri(SDR0, PESDR1_460SX_HSSL0COEFA, 0xDCB98987);
1086 mtdcri(SDR0, PESDR1_460SX_HSSL1COEFA, 0xDCB98987);
1087 mtdcri(SDR0, PESDR1_460SX_HSSL2COEFA, 0xDCB98987);
1088 mtdcri(SDR0, PESDR1_460SX_HSSL3COEFA, 0xDCB98987);
1089
1090 mtdcri(SDR0, PESDR2_460SX_HSSL0COEFA, 0xDCB98987);
1091 mtdcri(SDR0, PESDR2_460SX_HSSL1COEFA, 0xDCB98987);
1092 mtdcri(SDR0, PESDR2_460SX_HSSL2COEFA, 0xDCB98987);
1093 mtdcri(SDR0, PESDR2_460SX_HSSL3COEFA, 0xDCB98987);
1094
1095 /* HSS TX calibration control */
1096 mtdcri(SDR0, PESDR0_460SX_HSSL1CALDRV, 0x22222222);
1097 mtdcri(SDR0, PESDR1_460SX_HSSL1CALDRV, 0x22220000);
1098 mtdcri(SDR0, PESDR2_460SX_HSSL1CALDRV, 0x22220000);
1099
1100 /* HSS TX slew control */
1101 mtdcri(SDR0, PESDR0_460SX_HSSSLEW, 0xFFFFFFFF);
1102 mtdcri(SDR0, PESDR1_460SX_HSSSLEW, 0xFFFF0000);
1103 mtdcri(SDR0, PESDR2_460SX_HSSSLEW, 0xFFFF0000);
1104
1105 /* Set HSS PRBS enabled */
1106 mtdcri(SDR0, PESDR0_460SX_HSSCTLSET, 0x00001130);
1107 mtdcri(SDR0, PESDR2_460SX_HSSCTLSET, 0x00001130);
1108
1109 udelay(100);
1110
1111 /* De-assert PLLRESET */
1112 dcri_clrset(SDR0, PESDR0_PLLLCT2, 0x00000100, 0);
1113
1114 /* Reset DL, UTL, GPL before configuration */
1115 mtdcri(SDR0, PESDR0_460SX_RCSSET,
1116 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
1117 mtdcri(SDR0, PESDR1_460SX_RCSSET,
1118 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
1119 mtdcri(SDR0, PESDR2_460SX_RCSSET,
1120 PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
1121
1122 udelay(100);
1123
1124 /*
1125 * If bifurcation is not enabled, u-boot would have disabled the
1126 * third PCIe port
1127 */
1128 if (((mfdcri(SDR0, PESDR1_460SX_HSSCTLSET) & 0x00000001) ==
1129 0x00000001)) {
1130 printk(KERN_INFO "PCI: PCIE bifurcation setup successfully.\n");
1131 printk(KERN_INFO "PCI: Total 3 PCIE ports are present\n");
1132 return 3;
1133 }
1134
1135 printk(KERN_INFO "PCI: Total 2 PCIE ports are present\n");
1136 return 2;
1137 }
1138
1139 static int __init ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1140 {
1141
1142 if (port->endpoint)
1143 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
1144 0x01000000, 0);
1145 else
1146 dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
1147 0, 0x01000000);
1148
1149 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
1150 (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL),
1151 PESDRx_RCSSET_RSTPYN);
1152
1153 port->has_ibpre = 1;
1154
1155 return ppc4xx_pciex_port_reset_sdr(port);
1156 }
1157
1158 static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port)
1159 {
1160 /* Max 128 Bytes */
1161 out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000);
1162 /* Assert VRB and TXE - per datasheet turn off addr validation */
1163 out_be32(port->utl_base + PEUTL_PCTL, 0x80800000);
1164 return 0;
1165 }
1166
1167 static void __init ppc460sx_pciex_check_link(struct ppc4xx_pciex_port *port)
1168 {
1169 void __iomem *mbase;
1170 int attempt = 50;
1171
1172 port->link = 0;
1173
1174 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
1175 if (mbase == NULL) {
1176 printk(KERN_ERR "%s: Can't map internal config space !",
1177 port->node->full_name);
1178 goto done;
1179 }
1180
1181 while (attempt && (0 == (in_le32(mbase + PECFG_460SX_DLLSTA)
1182 & PECFG_460SX_DLLSTA_LINKUP))) {
1183 attempt--;
1184 mdelay(10);
1185 }
1186 if (attempt)
1187 port->link = 1;
1188 done:
1189 iounmap(mbase);
1190
1191 }
1192
1193 static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = {
1194 .want_sdr = true,
1195 .core_init = ppc460sx_pciex_core_init,
1196 .port_init_hw = ppc460sx_pciex_init_port_hw,
1197 .setup_utl = ppc460sx_pciex_init_utl,
1198 .check_link = ppc460sx_pciex_check_link,
1199 };
1200
1201 #endif /* CONFIG_44x */
1202
1203 #ifdef CONFIG_40x
1204
1205 static int __init ppc405ex_pciex_core_init(struct device_node *np)
1206 {
1207 /* Nothing to do, return 2 ports */
1208 return 2;
1209 }
1210
1211 static void ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port)
1212 {
1213 /* Assert the PE0_PHY reset */
1214 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000);
1215 msleep(1);
1216
1217 /* deassert the PE0_hotreset */
1218 if (port->endpoint)
1219 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000);
1220 else
1221 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000);
1222
1223 /* poll for phy !reset */
1224 /* XXX FIXME add timeout */
1225 while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000))
1226 ;
1227
1228 /* deassert the PE0_gpl_utl_reset */
1229 mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000);
1230 }
1231
1232 static int __init ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1233 {
1234 u32 val;
1235
1236 if (port->endpoint)
1237 val = PTYPE_LEGACY_ENDPOINT;
1238 else
1239 val = PTYPE_ROOT_PORT;
1240
1241 mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET,
1242 1 << 24 | val << 20 | LNKW_X1 << 12);
1243
1244 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
1245 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
1246 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000);
1247 mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003);
1248
1249 /*
1250 * Only reset the PHY when no link is currently established.
1251 * This is for the Atheros PCIe board which has problems to establish
1252 * the link (again) after this PHY reset. All other currently tested
1253 * PCIe boards don't show this problem.
1254 * This has to be re-tested and fixed in a later release!
1255 */
1256 val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
1257 if (!(val & 0x00001000))
1258 ppc405ex_pcie_phy_reset(port);
1259
1260 dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000); /* guarded on */
1261
1262 port->has_ibpre = 1;
1263
1264 return ppc4xx_pciex_port_reset_sdr(port);
1265 }
1266
1267 static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
1268 {
1269 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
1270
1271 /*
1272 * Set buffer allocations and then assert VRB and TXE.
1273 */
1274 out_be32(port->utl_base + PEUTL_OUTTR, 0x02000000);
1275 out_be32(port->utl_base + PEUTL_INTR, 0x02000000);
1276 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
1277 out_be32(port->utl_base + PEUTL_PBBSZ, 0x21000000);
1278 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
1279 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
1280 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
1281 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066);
1282
1283 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000);
1284
1285 return 0;
1286 }
1287
1288 static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
1289 {
1290 .want_sdr = true,
1291 .core_init = ppc405ex_pciex_core_init,
1292 .port_init_hw = ppc405ex_pciex_init_port_hw,
1293 .setup_utl = ppc405ex_pciex_init_utl,
1294 .check_link = ppc4xx_pciex_check_link_sdr,
1295 };
1296
1297 #endif /* CONFIG_40x */
1298
1299 #ifdef CONFIG_476FPE
1300 static int __init ppc_476fpe_pciex_core_init(struct device_node *np)
1301 {
1302 return 4;
1303 }
1304
1305 static void __init ppc_476fpe_pciex_check_link(struct ppc4xx_pciex_port *port)
1306 {
1307 u32 timeout_ms = 20;
1308 u32 val = 0, mask = (PECFG_TLDLP_LNKUP|PECFG_TLDLP_PRESENT);
1309 void __iomem *mbase = ioremap(port->cfg_space.start + 0x10000000,
1310 0x1000);
1311
1312 printk(KERN_INFO "PCIE%d: Checking link...\n", port->index);
1313
1314 if (mbase == NULL) {
1315 printk(KERN_WARNING "PCIE%d: failed to get cfg space\n",
1316 port->index);
1317 return;
1318 }
1319
1320 while (timeout_ms--) {
1321 val = in_le32(mbase + PECFG_TLDLP);
1322
1323 if ((val & mask) == mask)
1324 break;
1325 msleep(10);
1326 }
1327
1328 if (val & PECFG_TLDLP_PRESENT) {
1329 printk(KERN_INFO "PCIE%d: link is up !\n", port->index);
1330 port->link = 1;
1331 } else
1332 printk(KERN_WARNING "PCIE%d: Link up failed\n", port->index);
1333
1334 iounmap(mbase);
1335 return;
1336 }
1337
1338 static struct ppc4xx_pciex_hwops ppc_476fpe_pcie_hwops __initdata =
1339 {
1340 .core_init = ppc_476fpe_pciex_core_init,
1341 .check_link = ppc_476fpe_pciex_check_link,
1342 };
1343 #endif /* CONFIG_476FPE */
1344
1345 /* Check that the core has been initied and if not, do it */
1346 static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
1347 {
1348 static int core_init;
1349 int count = -ENODEV;
1350
1351 if (core_init++)
1352 return 0;
1353
1354 #ifdef CONFIG_44x
1355 if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) {
1356 if (ppc440spe_revA())
1357 ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops;
1358 else
1359 ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;
1360 }
1361 if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
1362 ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
1363 if (of_device_is_compatible(np, "ibm,plb-pciex-460sx"))
1364 ppc4xx_pciex_hwops = &ppc460sx_pcie_hwops;
1365 #endif /* CONFIG_44x */
1366 #ifdef CONFIG_40x
1367 if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
1368 ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops;
1369 #endif
1370 #ifdef CONFIG_476FPE
1371 if (of_device_is_compatible(np, "ibm,plb-pciex-476fpe"))
1372 ppc4xx_pciex_hwops = &ppc_476fpe_pcie_hwops;
1373 #endif
1374 if (ppc4xx_pciex_hwops == NULL) {
1375 printk(KERN_WARNING "PCIE: unknown host type %s\n",
1376 np->full_name);
1377 return -ENODEV;
1378 }
1379
1380 count = ppc4xx_pciex_hwops->core_init(np);
1381 if (count > 0) {
1382 ppc4xx_pciex_ports =
1383 kzalloc(count * sizeof(struct ppc4xx_pciex_port),
1384 GFP_KERNEL);
1385 if (ppc4xx_pciex_ports) {
1386 ppc4xx_pciex_port_count = count;
1387 return 0;
1388 }
1389 printk(KERN_WARNING "PCIE: failed to allocate ports array\n");
1390 return -ENOMEM;
1391 }
1392 return -ENODEV;
1393 }
1394
1395 static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port)
1396 {
1397 /* We map PCI Express configuration based on the reg property */
1398 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH,
1399 RES_TO_U32_HIGH(port->cfg_space.start));
1400 dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL,
1401 RES_TO_U32_LOW(port->cfg_space.start));
1402
1403 /* XXX FIXME: Use size from reg property. For now, map 512M */
1404 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001);
1405
1406 /* We map UTL registers based on the reg property */
1407 dcr_write(port->dcrs, DCRO_PEGPL_REGBAH,
1408 RES_TO_U32_HIGH(port->utl_regs.start));
1409 dcr_write(port->dcrs, DCRO_PEGPL_REGBAL,
1410 RES_TO_U32_LOW(port->utl_regs.start));
1411
1412 /* XXX FIXME: Use size from reg property */
1413 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001);
1414
1415 /* Disable all other outbound windows */
1416 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0);
1417 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0);
1418 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0);
1419 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
1420 }
1421
1422 static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
1423 {
1424 int rc = 0;
1425
1426 /* Init HW */
1427 if (ppc4xx_pciex_hwops->port_init_hw)
1428 rc = ppc4xx_pciex_hwops->port_init_hw(port);
1429 if (rc != 0)
1430 return rc;
1431
1432 /*
1433 * Initialize mapping: disable all regions and configure
1434 * CFG and REG regions based on resources in the device tree
1435 */
1436 ppc4xx_pciex_port_init_mapping(port);
1437
1438 if (ppc4xx_pciex_hwops->check_link)
1439 ppc4xx_pciex_hwops->check_link(port);
1440
1441 /*
1442 * Map UTL
1443 */
1444 port->utl_base = ioremap(port->utl_regs.start, 0x100);
1445 BUG_ON(port->utl_base == NULL);
1446
1447 /*
1448 * Setup UTL registers --BenH.
1449 */
1450 if (ppc4xx_pciex_hwops->setup_utl)
1451 ppc4xx_pciex_hwops->setup_utl(port);
1452
1453 /*
1454 * Check for VC0 active or PLL Locked and assert RDY.
1455 */
1456 if (port->sdr_base) {
1457 if (of_device_is_compatible(port->node,
1458 "ibm,plb-pciex-460sx")){
1459 if (port->link && ppc4xx_pciex_wait_on_sdr(port,
1460 PESDRn_RCSSTS,
1461 1 << 12, 1 << 12, 5000)) {
1462 printk(KERN_INFO "PCIE%d: PLL not locked\n",
1463 port->index);
1464 port->link = 0;
1465 }
1466 } else if (port->link &&
1467 ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
1468 1 << 16, 1 << 16, 5000)) {
1469 printk(KERN_INFO "PCIE%d: VC0 not active\n",
1470 port->index);
1471 port->link = 0;
1472 }
1473
1474 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
1475 }
1476
1477 msleep(100);
1478
1479 return 0;
1480 }
1481
1482 static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port,
1483 struct pci_bus *bus,
1484 unsigned int devfn)
1485 {
1486 static int message;
1487
1488 /* Endpoint can not generate upstream(remote) config cycles */
1489 if (port->endpoint && bus->number != port->hose->first_busno)
1490 return PCIBIOS_DEVICE_NOT_FOUND;
1491
1492 /* Check we are within the mapped range */
1493 if (bus->number > port->hose->last_busno) {
1494 if (!message) {
1495 printk(KERN_WARNING "Warning! Probing bus %u"
1496 " out of range !\n", bus->number);
1497 message++;
1498 }
1499 return PCIBIOS_DEVICE_NOT_FOUND;
1500 }
1501
1502 /* The root complex has only one device / function */
1503 if (bus->number == port->hose->first_busno && devfn != 0)
1504 return PCIBIOS_DEVICE_NOT_FOUND;
1505
1506 /* The other side of the RC has only one device as well */
1507 if (bus->number == (port->hose->first_busno + 1) &&
1508 PCI_SLOT(devfn) != 0)
1509 return PCIBIOS_DEVICE_NOT_FOUND;
1510
1511 /* Check if we have a link */
1512 if ((bus->number != port->hose->first_busno) && !port->link)
1513 return PCIBIOS_DEVICE_NOT_FOUND;
1514
1515 return 0;
1516 }
1517
1518 static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port,
1519 struct pci_bus *bus,
1520 unsigned int devfn)
1521 {
1522 int relbus;
1523
1524 /* Remove the casts when we finally remove the stupid volatile
1525 * in struct pci_controller
1526 */
1527 if (bus->number == port->hose->first_busno)
1528 return (void __iomem *)port->hose->cfg_addr;
1529
1530 relbus = bus->number - (port->hose->first_busno + 1);
1531 return (void __iomem *)port->hose->cfg_data +
1532 ((relbus << 20) | (devfn << 12));
1533 }
1534
1535 static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
1536 int offset, int len, u32 *val)
1537 {
1538 struct pci_controller *hose = pci_bus_to_host(bus);
1539 struct ppc4xx_pciex_port *port =
1540 &ppc4xx_pciex_ports[hose->indirect_type];
1541 void __iomem *addr;
1542 u32 gpl_cfg;
1543
1544 BUG_ON(hose != port->hose);
1545
1546 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1547 return PCIBIOS_DEVICE_NOT_FOUND;
1548
1549 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1550
1551 /*
1552 * Reading from configuration space of non-existing device can
1553 * generate transaction errors. For the read duration we suppress
1554 * assertion of machine check exceptions to avoid those.
1555 */
1556 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1557 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1558
1559 /* Make sure no CRS is recorded */
1560 out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000);
1561
1562 switch (len) {
1563 case 1:
1564 *val = in_8((u8 *)(addr + offset));
1565 break;
1566 case 2:
1567 *val = in_le16((u16 *)(addr + offset));
1568 break;
1569 default:
1570 *val = in_le32((u32 *)(addr + offset));
1571 break;
1572 }
1573
1574 pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x"
1575 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1576 bus->number, hose->first_busno, hose->last_busno,
1577 devfn, offset, len, addr + offset, *val);
1578
1579 /* Check for CRS (440SPe rev B does that for us but heh ..) */
1580 if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) {
1581 pr_debug("Got CRS !\n");
1582 if (len != 4 || offset != 0)
1583 return PCIBIOS_DEVICE_NOT_FOUND;
1584 *val = 0xffff0001;
1585 }
1586
1587 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1588
1589 return PCIBIOS_SUCCESSFUL;
1590 }
1591
1592 static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
1593 int offset, int len, u32 val)
1594 {
1595 struct pci_controller *hose = pci_bus_to_host(bus);
1596 struct ppc4xx_pciex_port *port =
1597 &ppc4xx_pciex_ports[hose->indirect_type];
1598 void __iomem *addr;
1599 u32 gpl_cfg;
1600
1601 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1602 return PCIBIOS_DEVICE_NOT_FOUND;
1603
1604 addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1605
1606 /*
1607 * Reading from configuration space of non-existing device can
1608 * generate transaction errors. For the read duration we suppress
1609 * assertion of machine check exceptions to avoid those.
1610 */
1611 gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1612 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1613
1614 pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x"
1615 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1616 bus->number, hose->first_busno, hose->last_busno,
1617 devfn, offset, len, addr + offset, val);
1618
1619 switch (len) {
1620 case 1:
1621 out_8((u8 *)(addr + offset), val);
1622 break;
1623 case 2:
1624 out_le16((u16 *)(addr + offset), val);
1625 break;
1626 default:
1627 out_le32((u32 *)(addr + offset), val);
1628 break;
1629 }
1630
1631 dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1632
1633 return PCIBIOS_SUCCESSFUL;
1634 }
1635
1636 static struct pci_ops ppc4xx_pciex_pci_ops =
1637 {
1638 .read = ppc4xx_pciex_read_config,
1639 .write = ppc4xx_pciex_write_config,
1640 };
1641
1642 static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port *port,
1643 struct pci_controller *hose,
1644 void __iomem *mbase,
1645 u64 plb_addr,
1646 u64 pci_addr,
1647 u64 size,
1648 unsigned int flags,
1649 int index)
1650 {
1651 u32 lah, lal, pciah, pcial, sa;
1652
1653 if (!is_power_of_2(size) ||
1654 (index < 2 && size < 0x100000) ||
1655 (index == 2 && size < 0x100) ||
1656 (plb_addr & (size - 1)) != 0) {
1657 printk(KERN_WARNING "%s: Resource out of range\n",
1658 hose->dn->full_name);
1659 return -1;
1660 }
1661
1662 /* Calculate register values */
1663 lah = RES_TO_U32_HIGH(plb_addr);
1664 lal = RES_TO_U32_LOW(plb_addr);
1665 pciah = RES_TO_U32_HIGH(pci_addr);
1666 pcial = RES_TO_U32_LOW(pci_addr);
1667 sa = (0xffffffffu << ilog2(size)) | 0x1;
1668
1669 /* Program register values */
1670 switch (index) {
1671 case 0:
1672 out_le32(mbase + PECFG_POM0LAH, pciah);
1673 out_le32(mbase + PECFG_POM0LAL, pcial);
1674 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah);
1675 dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal);
1676 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff);
1677 /*Enabled and single region */
1678 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx"))
1679 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
1680 sa | DCRO_PEGPL_460SX_OMR1MSKL_UOT
1681 | DCRO_PEGPL_OMRxMSKL_VAL);
1682 else if (of_device_is_compatible(port->node, "ibm,plb-pciex-476fpe"))
1683 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
1684 sa | DCRO_PEGPL_476FPE_OMR1MSKL_UOT
1685 | DCRO_PEGPL_OMRxMSKL_VAL);
1686 else
1687 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
1688 sa | DCRO_PEGPL_OMR1MSKL_UOT
1689 | DCRO_PEGPL_OMRxMSKL_VAL);
1690 break;
1691 case 1:
1692 out_le32(mbase + PECFG_POM1LAH, pciah);
1693 out_le32(mbase + PECFG_POM1LAL, pcial);
1694 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah);
1695 dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal);
1696 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff);
1697 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL,
1698 sa | DCRO_PEGPL_OMRxMSKL_VAL);
1699 break;
1700 case 2:
1701 out_le32(mbase + PECFG_POM2LAH, pciah);
1702 out_le32(mbase + PECFG_POM2LAL, pcial);
1703 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah);
1704 dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal);
1705 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff);
1706 /* Note that 3 here means enabled | IO space !!! */
1707 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL,
1708 sa | DCRO_PEGPL_OMR3MSKL_IO
1709 | DCRO_PEGPL_OMRxMSKL_VAL);
1710 break;
1711 }
1712
1713 return 0;
1714 }
1715
1716 static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port,
1717 struct pci_controller *hose,
1718 void __iomem *mbase)
1719 {
1720 int i, j, found_isa_hole = 0;
1721
1722 /* Setup outbound memory windows */
1723 for (i = j = 0; i < 3; i++) {
1724 struct resource *res = &hose->mem_resources[i];
1725
1726 /* we only care about memory windows */
1727 if (!(res->flags & IORESOURCE_MEM))
1728 continue;
1729 if (j > 1) {
1730 printk(KERN_WARNING "%s: Too many ranges\n",
1731 port->node->full_name);
1732 break;
1733 }
1734
1735 /* Configure the resource */
1736 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1737 res->start,
1738 res->start - hose->pci_mem_offset,
1739 resource_size(res),
1740 res->flags,
1741 j) == 0) {
1742 j++;
1743
1744 /* If the resource PCI address is 0 then we have our
1745 * ISA memory hole
1746 */
1747 if (res->start == hose->pci_mem_offset)
1748 found_isa_hole = 1;
1749 }
1750 }
1751
1752 /* Handle ISA memory hole if not already covered */
1753 if (j <= 1 && !found_isa_hole && hose->isa_mem_size)
1754 if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1755 hose->isa_mem_phys, 0,
1756 hose->isa_mem_size, 0, j) == 0)
1757 printk(KERN_INFO "%s: Legacy ISA memory support enabled\n",
1758 hose->dn->full_name);
1759
1760 /* Configure IO, always 64K starting at 0. We hard wire it to 64K !
1761 * Note also that it -has- to be region index 2 on this HW
1762 */
1763 if (hose->io_resource.flags & IORESOURCE_IO)
1764 ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1765 hose->io_base_phys, 0,
1766 0x10000, IORESOURCE_IO, 2);
1767 }
1768
1769 static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
1770 struct pci_controller *hose,
1771 void __iomem *mbase,
1772 struct resource *res)
1773 {
1774 resource_size_t size = resource_size(res);
1775 u64 sa;
1776
1777 if (port->endpoint) {
1778 resource_size_t ep_addr = 0;
1779 resource_size_t ep_size = 32 << 20;
1780
1781 /* Currently we map a fixed 64MByte window to PLB address
1782 * 0 (SDRAM). This should probably be configurable via a dts
1783 * property.
1784 */
1785
1786 /* Calculate window size */
1787 sa = (0xffffffffffffffffull << ilog2(ep_size));
1788
1789 /* Setup BAR0 */
1790 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1791 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa) |
1792 PCI_BASE_ADDRESS_MEM_TYPE_64);
1793
1794 /* Disable BAR1 & BAR2 */
1795 out_le32(mbase + PECFG_BAR1MPA, 0);
1796 out_le32(mbase + PECFG_BAR2HMPA, 0);
1797 out_le32(mbase + PECFG_BAR2LMPA, 0);
1798
1799 out_le32(mbase + PECFG_PIM01SAH, RES_TO_U32_HIGH(sa));
1800 out_le32(mbase + PECFG_PIM01SAL, RES_TO_U32_LOW(sa));
1801
1802 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(ep_addr));
1803 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(ep_addr));
1804 } else {
1805 /* Calculate window size */
1806 sa = (0xffffffffffffffffull << ilog2(size));
1807 if (res->flags & IORESOURCE_PREFETCH)
1808 sa |= PCI_BASE_ADDRESS_MEM_PREFETCH;
1809
1810 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx") ||
1811 of_device_is_compatible(port->node, "ibm,plb-pciex-476fpe"))
1812 sa |= PCI_BASE_ADDRESS_MEM_TYPE_64;
1813
1814 out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1815 out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa));
1816
1817 /* The setup of the split looks weird to me ... let's see
1818 * if it works
1819 */
1820 out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
1821 out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
1822 out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
1823 out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
1824 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
1825 out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
1826
1827 out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start));
1828 out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start));
1829 }
1830
1831 /* Enable inbound mapping */
1832 out_le32(mbase + PECFG_PIMEN, 0x1);
1833
1834 /* Enable I/O, Mem, and Busmaster cycles */
1835 out_le16(mbase + PCI_COMMAND,
1836 in_le16(mbase + PCI_COMMAND) |
1837 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1838 }
1839
1840 static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port)
1841 {
1842 struct resource dma_window;
1843 struct pci_controller *hose = NULL;
1844 const int *bus_range;
1845 int primary = 0, busses;
1846 void __iomem *mbase = NULL, *cfg_data = NULL;
1847 const u32 *pval;
1848 u32 val;
1849
1850 /* Check if primary bridge */
1851 if (of_get_property(port->node, "primary", NULL))
1852 primary = 1;
1853
1854 /* Get bus range if any */
1855 bus_range = of_get_property(port->node, "bus-range", NULL);
1856
1857 /* Allocate the host controller data structure */
1858 hose = pcibios_alloc_controller(port->node);
1859 if (!hose)
1860 goto fail;
1861
1862 /* We stick the port number in "indirect_type" so the config space
1863 * ops can retrieve the port data structure easily
1864 */
1865 hose->indirect_type = port->index;
1866
1867 /* Get bus range */
1868 hose->first_busno = bus_range ? bus_range[0] : 0x0;
1869 hose->last_busno = bus_range ? bus_range[1] : 0xff;
1870
1871 /* Because of how big mapping the config space is (1M per bus), we
1872 * limit how many busses we support. In the long run, we could replace
1873 * that with something akin to kmap_atomic instead. We set aside 1 bus
1874 * for the host itself too.
1875 */
1876 busses = hose->last_busno - hose->first_busno; /* This is off by 1 */
1877 if (busses > MAX_PCIE_BUS_MAPPED) {
1878 busses = MAX_PCIE_BUS_MAPPED;
1879 hose->last_busno = hose->first_busno + busses;
1880 }
1881
1882 if (!port->endpoint) {
1883 /* Only map the external config space in cfg_data for
1884 * PCIe root-complexes. External space is 1M per bus
1885 */
1886 cfg_data = ioremap(port->cfg_space.start +
1887 (hose->first_busno + 1) * 0x100000,
1888 busses * 0x100000);
1889 if (cfg_data == NULL) {
1890 printk(KERN_ERR "%s: Can't map external config space !",
1891 port->node->full_name);
1892 goto fail;
1893 }
1894 hose->cfg_data = cfg_data;
1895 }
1896
1897 /* Always map the host config space in cfg_addr.
1898 * Internal space is 4K
1899 */
1900 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
1901 if (mbase == NULL) {
1902 printk(KERN_ERR "%s: Can't map internal config space !",
1903 port->node->full_name);
1904 goto fail;
1905 }
1906 hose->cfg_addr = mbase;
1907
1908 pr_debug("PCIE %s, bus %d..%d\n", port->node->full_name,
1909 hose->first_busno, hose->last_busno);
1910 pr_debug(" config space mapped at: root @0x%p, other @0x%p\n",
1911 hose->cfg_addr, hose->cfg_data);
1912
1913 /* Setup config space */
1914 hose->ops = &ppc4xx_pciex_pci_ops;
1915 port->hose = hose;
1916 mbase = (void __iomem *)hose->cfg_addr;
1917
1918 if (!port->endpoint) {
1919 /*
1920 * Set bus numbers on our root port
1921 */
1922 out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno);
1923 out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1);
1924 out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno);
1925 }
1926
1927 /*
1928 * OMRs are already reset, also disable PIMs
1929 */
1930 out_le32(mbase + PECFG_PIMEN, 0);
1931
1932 /* Parse outbound mapping resources */
1933 pci_process_bridge_OF_ranges(hose, port->node, primary);
1934
1935 /* Parse inbound mapping resources */
1936 if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0)
1937 goto fail;
1938
1939 /* Configure outbound ranges POMs */
1940 ppc4xx_configure_pciex_POMs(port, hose, mbase);
1941
1942 /* Configure inbound ranges PIMs */
1943 ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window);
1944
1945 /* The root complex doesn't show up if we don't set some vendor
1946 * and device IDs into it. The defaults below are the same bogus
1947 * one that the initial code in arch/ppc had. This can be
1948 * overwritten by setting the "vendor-id/device-id" properties
1949 * in the pciex node.
1950 */
1951
1952 /* Get the (optional) vendor-/device-id from the device-tree */
1953 pval = of_get_property(port->node, "vendor-id", NULL);
1954 if (pval) {
1955 val = *pval;
1956 } else {
1957 if (!port->endpoint)
1958 val = 0xaaa0 + port->index;
1959 else
1960 val = 0xeee0 + port->index;
1961 }
1962 out_le16(mbase + 0x200, val);
1963
1964 pval = of_get_property(port->node, "device-id", NULL);
1965 if (pval) {
1966 val = *pval;
1967 } else {
1968 if (!port->endpoint)
1969 val = 0xbed0 + port->index;
1970 else
1971 val = 0xfed0 + port->index;
1972 }
1973 out_le16(mbase + 0x202, val);
1974
1975 /* Enable Bus master, memory, and io space */
1976 if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx"))
1977 out_le16(mbase + 0x204, 0x7);
1978
1979 if (!port->endpoint) {
1980 /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
1981 out_le32(mbase + 0x208, 0x06040001);
1982
1983 printk(KERN_INFO "PCIE%d: successfully set as root-complex\n",
1984 port->index);
1985 } else {
1986 /* Set Class Code to Processor/PPC */
1987 out_le32(mbase + 0x208, 0x0b200001);
1988
1989 printk(KERN_INFO "PCIE%d: successfully set as endpoint\n",
1990 port->index);
1991 }
1992
1993 return;
1994 fail:
1995 if (hose)
1996 pcibios_free_controller(hose);
1997 if (cfg_data)
1998 iounmap(cfg_data);
1999 if (mbase)
2000 iounmap(mbase);
2001 }
2002
2003 static void __init ppc4xx_probe_pciex_bridge(struct device_node *np)
2004 {
2005 struct ppc4xx_pciex_port *port;
2006 const u32 *pval;
2007 int portno;
2008 unsigned int dcrs;
2009 const char *val;
2010
2011 /* First, proceed to core initialization as we assume there's
2012 * only one PCIe core in the system
2013 */
2014 if (ppc4xx_pciex_check_core_init(np))
2015 return;
2016
2017 /* Get the port number from the device-tree */
2018 pval = of_get_property(np, "port", NULL);
2019 if (pval == NULL) {
2020 printk(KERN_ERR "PCIE: Can't find port number for %s\n",
2021 np->full_name);
2022 return;
2023 }
2024 portno = *pval;
2025 if (portno >= ppc4xx_pciex_port_count) {
2026 printk(KERN_ERR "PCIE: port number out of range for %s\n",
2027 np->full_name);
2028 return;
2029 }
2030 port = &ppc4xx_pciex_ports[portno];
2031 port->index = portno;
2032
2033 /*
2034 * Check if device is enabled
2035 */
2036 if (!of_device_is_available(np)) {
2037 printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index);
2038 return;
2039 }
2040
2041 port->node = of_node_get(np);
2042 if (ppc4xx_pciex_hwops->want_sdr) {
2043 pval = of_get_property(np, "sdr-base", NULL);
2044 if (pval == NULL) {
2045 printk(KERN_ERR "PCIE: missing sdr-base for %s\n",
2046 np->full_name);
2047 return;
2048 }
2049 port->sdr_base = *pval;
2050 }
2051
2052 /* Check if device_type property is set to "pci" or "pci-endpoint".
2053 * Resulting from this setup this PCIe port will be configured
2054 * as root-complex or as endpoint.
2055 */
2056 val = of_get_property(port->node, "device_type", NULL);
2057 if (!strcmp(val, "pci-endpoint")) {
2058 port->endpoint = 1;
2059 } else if (!strcmp(val, "pci")) {
2060 port->endpoint = 0;
2061 } else {
2062 printk(KERN_ERR "PCIE: missing or incorrect device_type for %s\n",
2063 np->full_name);
2064 return;
2065 }
2066
2067 /* Fetch config space registers address */
2068 if (of_address_to_resource(np, 0, &port->cfg_space)) {
2069 printk(KERN_ERR "%s: Can't get PCI-E config space !",
2070 np->full_name);
2071 return;
2072 }
2073 /* Fetch host bridge internal registers address */
2074 if (of_address_to_resource(np, 1, &port->utl_regs)) {
2075 printk(KERN_ERR "%s: Can't get UTL register base !",
2076 np->full_name);
2077 return;
2078 }
2079
2080 /* Map DCRs */
2081 dcrs = dcr_resource_start(np, 0);
2082 if (dcrs == 0) {
2083 printk(KERN_ERR "%s: Can't get DCR register base !",
2084 np->full_name);
2085 return;
2086 }
2087 port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
2088
2089 /* Initialize the port specific registers */
2090 if (ppc4xx_pciex_port_init(port)) {
2091 printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index);
2092 return;
2093 }
2094
2095 /* Setup the linux hose data structure */
2096 ppc4xx_pciex_port_setup_hose(port);
2097 }
2098
2099 #endif /* CONFIG_PPC4xx_PCI_EXPRESS */
2100
2101 static int __init ppc4xx_pci_find_bridges(void)
2102 {
2103 struct device_node *np;
2104
2105 pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0);
2106
2107 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
2108 for_each_compatible_node(np, NULL, "ibm,plb-pciex")
2109 ppc4xx_probe_pciex_bridge(np);
2110 #endif
2111 for_each_compatible_node(np, NULL, "ibm,plb-pcix")
2112 ppc4xx_probe_pcix_bridge(np);
2113 for_each_compatible_node(np, NULL, "ibm,plb-pci")
2114 ppc4xx_probe_pci_bridge(np);
2115
2116 return 0;
2117 }
2118 arch_initcall(ppc4xx_pci_find_bridges);
2119