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spi-topcliff-pch: add recovery processing in case wait-event timeout
[zen-stable.git] / drivers / scsi / isci / host.c
blob418391b1c3616b07f2976467720565d7e9ee4479
1 /*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * BSD LICENSE
25 *
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
27 * All rights reserved.
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions
31 * are met:
32 *
33 * * Redistributions of source code must retain the above copyright
34 * notice, this list of conditions and the following disclaimer.
35 * * Redistributions in binary form must reproduce the above copyright
36 * notice, this list of conditions and the following disclaimer in
37 * the documentation and/or other materials provided with the
38 * distribution.
39 * * Neither the name of Intel Corporation nor the names of its
40 * contributors may be used to endorse or promote products derived
41 * from this software without specific prior written permission.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55 #include <linux/circ_buf.h>
56 #include <linux/device.h>
57 #include <scsi/sas.h>
58 #include "host.h"
59 #include "isci.h"
60 #include "port.h"
61 #include "host.h"
62 #include "probe_roms.h"
63 #include "remote_device.h"
64 #include "request.h"
65 #include "scu_completion_codes.h"
66 #include "scu_event_codes.h"
67 #include "registers.h"
68 #include "scu_remote_node_context.h"
69 #include "scu_task_context.h"
70
71 #define SCU_CONTEXT_RAM_INIT_STALL_TIME 200
72
73 #define smu_max_ports(dcc_value) \
74 (\
75 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \
76 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT) + 1 \
77 )
78
79 #define smu_max_task_contexts(dcc_value) \
80 (\
81 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \
82 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT) + 1 \
83 )
84
85 #define smu_max_rncs(dcc_value) \
86 (\
87 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \
88 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT) + 1 \
89 )
90
91 #define SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT 100
92
93 /**
94 *
95 *
96 * The number of milliseconds to wait while a given phy is consuming power
97 * before allowing another set of phys to consume power. Ultimately, this will
98 * be specified by OEM parameter.
99 */
100 #define SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL 500
101
102 /**
103 * NORMALIZE_PUT_POINTER() -
104 *
105 * This macro will normalize the completion queue put pointer so its value can
106 * be used as an array inde
107 */
108 #define NORMALIZE_PUT_POINTER(x) \
109 ((x) & SMU_COMPLETION_QUEUE_PUT_POINTER_MASK)
110
111
112 /**
113 * NORMALIZE_EVENT_POINTER() -
114 *
115 * This macro will normalize the completion queue event entry so its value can
116 * be used as an index.
117 */
118 #define NORMALIZE_EVENT_POINTER(x) \
119 (\
120 ((x) & SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK) \
121 >> SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT \
122 )
123
124 /**
125 * NORMALIZE_GET_POINTER() -
126 *
127 * This macro will normalize the completion queue get pointer so its value can
128 * be used as an index into an array
129 */
130 #define NORMALIZE_GET_POINTER(x) \
131 ((x) & SMU_COMPLETION_QUEUE_GET_POINTER_MASK)
132
133 /**
134 * NORMALIZE_GET_POINTER_CYCLE_BIT() -
135 *
136 * This macro will normalize the completion queue cycle pointer so it matches
137 * the completion queue cycle bit
138 */
139 #define NORMALIZE_GET_POINTER_CYCLE_BIT(x) \
140 ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT))
141
142 /**
143 * COMPLETION_QUEUE_CYCLE_BIT() -
144 *
145 * This macro will return the cycle bit of the completion queue entry
146 */
147 #define COMPLETION_QUEUE_CYCLE_BIT(x) ((x) & 0x80000000)
148
149 /* Init the state machine and call the state entry function (if any) */
150 void sci_init_sm(struct sci_base_state_machine *sm,
151 const struct sci_base_state *state_table, u32 initial_state)
152 {
153 sci_state_transition_t handler;
154
155 sm->initial_state_id = initial_state;
156 sm->previous_state_id = initial_state;
157 sm->current_state_id = initial_state;
158 sm->state_table = state_table;
159
160 handler = sm->state_table[initial_state].enter_state;
161 if (handler)
162 handler(sm);
163 }
164
165 /* Call the state exit fn, update the current state, call the state entry fn */
166 void sci_change_state(struct sci_base_state_machine *sm, u32 next_state)
167 {
168 sci_state_transition_t handler;
169
170 handler = sm->state_table[sm->current_state_id].exit_state;
171 if (handler)
172 handler(sm);
173
174 sm->previous_state_id = sm->current_state_id;
175 sm->current_state_id = next_state;
176
177 handler = sm->state_table[sm->current_state_id].enter_state;
178 if (handler)
179 handler(sm);
180 }
181
182 static bool sci_controller_completion_queue_has_entries(struct isci_host *ihost)
183 {
184 u32 get_value = ihost->completion_queue_get;
185 u32 get_index = get_value & SMU_COMPLETION_QUEUE_GET_POINTER_MASK;
186
187 if (NORMALIZE_GET_POINTER_CYCLE_BIT(get_value) ==
188 COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index]))
189 return true;
190
191 return false;
192 }
193
194 static bool sci_controller_isr(struct isci_host *ihost)
195 {
196 if (sci_controller_completion_queue_has_entries(ihost)) {
197 return true;
198 } else {
199 /*
200 * we have a spurious interrupt it could be that we have already
201 * emptied the completion queue from a previous interrupt */
202 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
203
204 /*
205 * There is a race in the hardware that could cause us not to be notified
206 * of an interrupt completion if we do not take this step. We will mask
207 * then unmask the interrupts so if there is another interrupt pending
208 * the clearing of the interrupt source we get the next interrupt message. */
209 writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
210 writel(0, &ihost->smu_registers->interrupt_mask);
211 }
212
213 return false;
214 }
215
216 irqreturn_t isci_msix_isr(int vec, void *data)
217 {
218 struct isci_host *ihost = data;
219
220 if (sci_controller_isr(ihost))
221 tasklet_schedule(&ihost->completion_tasklet);
222
223 return IRQ_HANDLED;
224 }
225
226 static bool sci_controller_error_isr(struct isci_host *ihost)
227 {
228 u32 interrupt_status;
229
230 interrupt_status =
231 readl(&ihost->smu_registers->interrupt_status);
232 interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND);
233
234 if (interrupt_status != 0) {
235 /*
236 * There is an error interrupt pending so let it through and handle
237 * in the callback */
238 return true;
239 }
240
241 /*
242 * There is a race in the hardware that could cause us not to be notified
243 * of an interrupt completion if we do not take this step. We will mask
244 * then unmask the error interrupts so if there was another interrupt
245 * pending we will be notified.
246 * Could we write the value of (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)? */
247 writel(0xff, &ihost->smu_registers->interrupt_mask);
248 writel(0, &ihost->smu_registers->interrupt_mask);
249
250 return false;
251 }
252
253 static void sci_controller_task_completion(struct isci_host *ihost, u32 ent)
254 {
255 u32 index = SCU_GET_COMPLETION_INDEX(ent);
256 struct isci_request *ireq = ihost->reqs[index];
257
258 /* Make sure that we really want to process this IO request */
259 if (test_bit(IREQ_ACTIVE, &ireq->flags) &&
260 ireq->io_tag != SCI_CONTROLLER_INVALID_IO_TAG &&
261 ISCI_TAG_SEQ(ireq->io_tag) == ihost->io_request_sequence[index])
262 /* Yep this is a valid io request pass it along to the
263 * io request handler
264 */
265 sci_io_request_tc_completion(ireq, ent);
266 }
267
268 static void sci_controller_sdma_completion(struct isci_host *ihost, u32 ent)
269 {
270 u32 index;
271 struct isci_request *ireq;
272 struct isci_remote_device *idev;
273
274 index = SCU_GET_COMPLETION_INDEX(ent);
275
276 switch (scu_get_command_request_type(ent)) {
277 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_TC:
278 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_TC:
279 ireq = ihost->reqs[index];
280 dev_warn(&ihost->pdev->dev, "%s: %x for io request %p\n",
281 __func__, ent, ireq);
282 /* @todo For a post TC operation we need to fail the IO
283 * request
284 */
285 break;
286 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_RNC:
287 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_OTHER_RNC:
288 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_RNC:
289 idev = ihost->device_table[index];
290 dev_warn(&ihost->pdev->dev, "%s: %x for device %p\n",
291 __func__, ent, idev);
292 /* @todo For a port RNC operation we need to fail the
293 * device
294 */
295 break;
296 default:
297 dev_warn(&ihost->pdev->dev, "%s: unknown completion type %x\n",
298 __func__, ent);
299 break;
300 }
301 }
302
303 static void sci_controller_unsolicited_frame(struct isci_host *ihost, u32 ent)
304 {
305 u32 index;
306 u32 frame_index;
307
308 struct scu_unsolicited_frame_header *frame_header;
309 struct isci_phy *iphy;
310 struct isci_remote_device *idev;
311
312 enum sci_status result = SCI_FAILURE;
313
314 frame_index = SCU_GET_FRAME_INDEX(ent);
315
316 frame_header = ihost->uf_control.buffers.array[frame_index].header;
317 ihost->uf_control.buffers.array[frame_index].state = UNSOLICITED_FRAME_IN_USE;
318
319 if (SCU_GET_FRAME_ERROR(ent)) {
320 /*
321 * / @todo If the IAF frame or SIGNATURE FIS frame has an error will
322 * / this cause a problem? We expect the phy initialization will
323 * / fail if there is an error in the frame. */
324 sci_controller_release_frame(ihost, frame_index);
325 return;
326 }
327
328 if (frame_header->is_address_frame) {
329 index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
330 iphy = &ihost->phys[index];
331 result = sci_phy_frame_handler(iphy, frame_index);
332 } else {
333
334 index = SCU_GET_COMPLETION_INDEX(ent);
335
336 if (index == SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
337 /*
338 * This is a signature fis or a frame from a direct attached SATA
339 * device that has not yet been created. In either case forwared
340 * the frame to the PE and let it take care of the frame data. */
341 index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
342 iphy = &ihost->phys[index];
343 result = sci_phy_frame_handler(iphy, frame_index);
344 } else {
345 if (index < ihost->remote_node_entries)
346 idev = ihost->device_table[index];
347 else
348 idev = NULL;
349
350 if (idev != NULL)
351 result = sci_remote_device_frame_handler(idev, frame_index);
352 else
353 sci_controller_release_frame(ihost, frame_index);
354 }
355 }
356
357 if (result != SCI_SUCCESS) {
358 /*
359 * / @todo Is there any reason to report some additional error message
360 * / when we get this failure notifiction? */
361 }
362 }
363
364 static void sci_controller_event_completion(struct isci_host *ihost, u32 ent)
365 {
366 struct isci_remote_device *idev;
367 struct isci_request *ireq;
368 struct isci_phy *iphy;
369 u32 index;
370
371 index = SCU_GET_COMPLETION_INDEX(ent);
372
373 switch (scu_get_event_type(ent)) {
374 case SCU_EVENT_TYPE_SMU_COMMAND_ERROR:
375 /* / @todo The driver did something wrong and we need to fix the condtion. */
376 dev_err(&ihost->pdev->dev,
377 "%s: SCIC Controller 0x%p received SMU command error "
378 "0x%x\n",
379 __func__,
380 ihost,
381 ent);
382 break;
383
384 case SCU_EVENT_TYPE_SMU_PCQ_ERROR:
385 case SCU_EVENT_TYPE_SMU_ERROR:
386 case SCU_EVENT_TYPE_FATAL_MEMORY_ERROR:
387 /*
388 * / @todo This is a hardware failure and its likely that we want to
389 * / reset the controller. */
390 dev_err(&ihost->pdev->dev,
391 "%s: SCIC Controller 0x%p received fatal controller "
392 "event 0x%x\n",
393 __func__,
394 ihost,
395 ent);
396 break;
397
398 case SCU_EVENT_TYPE_TRANSPORT_ERROR:
399 ireq = ihost->reqs[index];
400 sci_io_request_event_handler(ireq, ent);
401 break;
402
403 case SCU_EVENT_TYPE_PTX_SCHEDULE_EVENT:
404 switch (scu_get_event_specifier(ent)) {
405 case SCU_EVENT_SPECIFIC_SMP_RESPONSE_NO_PE:
406 case SCU_EVENT_SPECIFIC_TASK_TIMEOUT:
407 ireq = ihost->reqs[index];
408 if (ireq != NULL)
409 sci_io_request_event_handler(ireq, ent);
410 else
411 dev_warn(&ihost->pdev->dev,
412 "%s: SCIC Controller 0x%p received "
413 "event 0x%x for io request object "
414 "that doesnt exist.\n",
415 __func__,
416 ihost,
417 ent);
418
419 break;
420
421 case SCU_EVENT_SPECIFIC_IT_NEXUS_TIMEOUT:
422 idev = ihost->device_table[index];
423 if (idev != NULL)
424 sci_remote_device_event_handler(idev, ent);
425 else
426 dev_warn(&ihost->pdev->dev,
427 "%s: SCIC Controller 0x%p received "
428 "event 0x%x for remote device object "
429 "that doesnt exist.\n",
430 __func__,
431 ihost,
432 ent);
433
434 break;
435 }
436 break;
437
438 case SCU_EVENT_TYPE_BROADCAST_CHANGE:
439 /*
440 * direct the broadcast change event to the phy first and then let
441 * the phy redirect the broadcast change to the port object */
442 case SCU_EVENT_TYPE_ERR_CNT_EVENT:
443 /*
444 * direct error counter event to the phy object since that is where
445 * we get the event notification. This is a type 4 event. */
446 case SCU_EVENT_TYPE_OSSP_EVENT:
447 index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
448 iphy = &ihost->phys[index];
449 sci_phy_event_handler(iphy, ent);
450 break;
451
452 case SCU_EVENT_TYPE_RNC_SUSPEND_TX:
453 case SCU_EVENT_TYPE_RNC_SUSPEND_TX_RX:
454 case SCU_EVENT_TYPE_RNC_OPS_MISC:
455 if (index < ihost->remote_node_entries) {
456 idev = ihost->device_table[index];
457
458 if (idev != NULL)
459 sci_remote_device_event_handler(idev, ent);
460 } else
461 dev_err(&ihost->pdev->dev,
462 "%s: SCIC Controller 0x%p received event 0x%x "
463 "for remote device object 0x%0x that doesnt "
464 "exist.\n",
465 __func__,
466 ihost,
467 ent,
468 index);
469
470 break;
471
472 default:
473 dev_warn(&ihost->pdev->dev,
474 "%s: SCIC Controller received unknown event code %x\n",
475 __func__,
476 ent);
477 break;
478 }
479 }
480
481 static void sci_controller_process_completions(struct isci_host *ihost)
482 {
483 u32 completion_count = 0;
484 u32 ent;
485 u32 get_index;
486 u32 get_cycle;
487 u32 event_get;
488 u32 event_cycle;
489
490 dev_dbg(&ihost->pdev->dev,
491 "%s: completion queue begining get:0x%08x\n",
492 __func__,
493 ihost->completion_queue_get);
494
495 /* Get the component parts of the completion queue */
496 get_index = NORMALIZE_GET_POINTER(ihost->completion_queue_get);
497 get_cycle = SMU_CQGR_CYCLE_BIT & ihost->completion_queue_get;
498
499 event_get = NORMALIZE_EVENT_POINTER(ihost->completion_queue_get);
500 event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & ihost->completion_queue_get;
501
502 while (
503 NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle)
504 == COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index])
505 ) {
506 completion_count++;
507
508 ent = ihost->completion_queue[get_index];
509
510 /* increment the get pointer and check for rollover to toggle the cycle bit */
511 get_cycle ^= ((get_index+1) & SCU_MAX_COMPLETION_QUEUE_ENTRIES) <<
512 (SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT - SCU_MAX_COMPLETION_QUEUE_SHIFT);
513 get_index = (get_index+1) & (SCU_MAX_COMPLETION_QUEUE_ENTRIES-1);
514
515 dev_dbg(&ihost->pdev->dev,
516 "%s: completion queue entry:0x%08x\n",
517 __func__,
518 ent);
519
520 switch (SCU_GET_COMPLETION_TYPE(ent)) {
521 case SCU_COMPLETION_TYPE_TASK:
522 sci_controller_task_completion(ihost, ent);
523 break;
524
525 case SCU_COMPLETION_TYPE_SDMA:
526 sci_controller_sdma_completion(ihost, ent);
527 break;
528
529 case SCU_COMPLETION_TYPE_UFI:
530 sci_controller_unsolicited_frame(ihost, ent);
531 break;
532
533 case SCU_COMPLETION_TYPE_EVENT:
534 sci_controller_event_completion(ihost, ent);
535 break;
536
537 case SCU_COMPLETION_TYPE_NOTIFY: {
538 event_cycle ^= ((event_get+1) & SCU_MAX_EVENTS) <<
539 (SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT - SCU_MAX_EVENTS_SHIFT);
540 event_get = (event_get+1) & (SCU_MAX_EVENTS-1);
541
542 sci_controller_event_completion(ihost, ent);
543 break;
544 }
545 default:
546 dev_warn(&ihost->pdev->dev,
547 "%s: SCIC Controller received unknown "
548 "completion type %x\n",
549 __func__,
550 ent);
551 break;
552 }
553 }
554
555 /* Update the get register if we completed one or more entries */
556 if (completion_count > 0) {
557 ihost->completion_queue_get =
558 SMU_CQGR_GEN_BIT(ENABLE) |
559 SMU_CQGR_GEN_BIT(EVENT_ENABLE) |
560 event_cycle |
561 SMU_CQGR_GEN_VAL(EVENT_POINTER, event_get) |
562 get_cycle |
563 SMU_CQGR_GEN_VAL(POINTER, get_index);
564
565 writel(ihost->completion_queue_get,
566 &ihost->smu_registers->completion_queue_get);
567
568 }
569
570 dev_dbg(&ihost->pdev->dev,
571 "%s: completion queue ending get:0x%08x\n",
572 __func__,
573 ihost->completion_queue_get);
574
575 }
576
577 static void sci_controller_error_handler(struct isci_host *ihost)
578 {
579 u32 interrupt_status;
580
581 interrupt_status =
582 readl(&ihost->smu_registers->interrupt_status);
583
584 if ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) &&
585 sci_controller_completion_queue_has_entries(ihost)) {
586
587 sci_controller_process_completions(ihost);
588 writel(SMU_ISR_QUEUE_SUSPEND, &ihost->smu_registers->interrupt_status);
589 } else {
590 dev_err(&ihost->pdev->dev, "%s: status: %#x\n", __func__,
591 interrupt_status);
592
593 sci_change_state(&ihost->sm, SCIC_FAILED);
594
595 return;
596 }
597
598 /* If we dont process any completions I am not sure that we want to do this.
599 * We are in the middle of a hardware fault and should probably be reset.
600 */
601 writel(0, &ihost->smu_registers->interrupt_mask);
602 }
603
604 irqreturn_t isci_intx_isr(int vec, void *data)
605 {
606 irqreturn_t ret = IRQ_NONE;
607 struct isci_host *ihost = data;
608
609 if (sci_controller_isr(ihost)) {
610 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
611 tasklet_schedule(&ihost->completion_tasklet);
612 ret = IRQ_HANDLED;
613 } else if (sci_controller_error_isr(ihost)) {
614 spin_lock(&ihost->scic_lock);
615 sci_controller_error_handler(ihost);
616 spin_unlock(&ihost->scic_lock);
617 ret = IRQ_HANDLED;
618 }
619
620 return ret;
621 }
622
623 irqreturn_t isci_error_isr(int vec, void *data)
624 {
625 struct isci_host *ihost = data;
626
627 if (sci_controller_error_isr(ihost))
628 sci_controller_error_handler(ihost);
629
630 return IRQ_HANDLED;
631 }
632
633 /**
634 * isci_host_start_complete() - This function is called by the core library,
635 * through the ISCI Module, to indicate controller start status.
636 * @isci_host: This parameter specifies the ISCI host object
637 * @completion_status: This parameter specifies the completion status from the
638 * core library.
639 *
640 */
641 static void isci_host_start_complete(struct isci_host *ihost, enum sci_status completion_status)
642 {
643 if (completion_status != SCI_SUCCESS)
644 dev_info(&ihost->pdev->dev,
645 "controller start timed out, continuing...\n");
646 isci_host_change_state(ihost, isci_ready);
647 clear_bit(IHOST_START_PENDING, &ihost->flags);
648 wake_up(&ihost->eventq);
649 }
650
651 int isci_host_scan_finished(struct Scsi_Host *shost, unsigned long time)
652 {
653 struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha;
654
655 if (test_bit(IHOST_START_PENDING, &ihost->flags))
656 return 0;
657
658 /* todo: use sas_flush_discovery once it is upstream */
659 scsi_flush_work(shost);
660
661 scsi_flush_work(shost);
662
663 dev_dbg(&ihost->pdev->dev,
664 "%s: ihost->status = %d, time = %ld\n",
665 __func__, isci_host_get_state(ihost), time);
666
667 return 1;
668
669 }
670
671 /**
672 * sci_controller_get_suggested_start_timeout() - This method returns the
673 * suggested sci_controller_start() timeout amount. The user is free to
674 * use any timeout value, but this method provides the suggested minimum
675 * start timeout value. The returned value is based upon empirical
676 * information determined as a result of interoperability testing.
677 * @controller: the handle to the controller object for which to return the
678 * suggested start timeout.
679 *
680 * This method returns the number of milliseconds for the suggested start
681 * operation timeout.
682 */
683 static u32 sci_controller_get_suggested_start_timeout(struct isci_host *ihost)
684 {
685 /* Validate the user supplied parameters. */
686 if (!ihost)
687 return 0;
688
689 /*
690 * The suggested minimum timeout value for a controller start operation:
691 *
692 * Signature FIS Timeout
693 * + Phy Start Timeout
694 * + Number of Phy Spin Up Intervals
695 * ---------------------------------
696 * Number of milliseconds for the controller start operation.
697 *
698 * NOTE: The number of phy spin up intervals will be equivalent
699 * to the number of phys divided by the number phys allowed
700 * per interval - 1 (once OEM parameters are supported).
701 * Currently we assume only 1 phy per interval. */
702
703 return SCIC_SDS_SIGNATURE_FIS_TIMEOUT
704 + SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT
705 + ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
706 }
707
708 static void sci_controller_enable_interrupts(struct isci_host *ihost)
709 {
710 BUG_ON(ihost->smu_registers == NULL);
711 writel(0, &ihost->smu_registers->interrupt_mask);
712 }
713
714 void sci_controller_disable_interrupts(struct isci_host *ihost)
715 {
716 BUG_ON(ihost->smu_registers == NULL);
717 writel(0xffffffff, &ihost->smu_registers->interrupt_mask);
718 }
719
720 static void sci_controller_enable_port_task_scheduler(struct isci_host *ihost)
721 {
722 u32 port_task_scheduler_value;
723
724 port_task_scheduler_value =
725 readl(&ihost->scu_registers->peg0.ptsg.control);
726 port_task_scheduler_value |=
727 (SCU_PTSGCR_GEN_BIT(ETM_ENABLE) |
728 SCU_PTSGCR_GEN_BIT(PTSG_ENABLE));
729 writel(port_task_scheduler_value,
730 &ihost->scu_registers->peg0.ptsg.control);
731 }
732
733 static void sci_controller_assign_task_entries(struct isci_host *ihost)
734 {
735 u32 task_assignment;
736
737 /*
738 * Assign all the TCs to function 0
739 * TODO: Do we actually need to read this register to write it back?
740 */
741
742 task_assignment =
743 readl(&ihost->smu_registers->task_context_assignment[0]);
744
745 task_assignment |= (SMU_TCA_GEN_VAL(STARTING, 0)) |
746 (SMU_TCA_GEN_VAL(ENDING, ihost->task_context_entries - 1)) |
747 (SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE));
748
749 writel(task_assignment,
750 &ihost->smu_registers->task_context_assignment[0]);
751
752 }
753
754 static void sci_controller_initialize_completion_queue(struct isci_host *ihost)
755 {
756 u32 index;
757 u32 completion_queue_control_value;
758 u32 completion_queue_get_value;
759 u32 completion_queue_put_value;
760
761 ihost->completion_queue_get = 0;
762
763 completion_queue_control_value =
764 (SMU_CQC_QUEUE_LIMIT_SET(SCU_MAX_COMPLETION_QUEUE_ENTRIES - 1) |
765 SMU_CQC_EVENT_LIMIT_SET(SCU_MAX_EVENTS - 1));
766
767 writel(completion_queue_control_value,
768 &ihost->smu_registers->completion_queue_control);
769
770
771 /* Set the completion queue get pointer and enable the queue */
772 completion_queue_get_value = (
773 (SMU_CQGR_GEN_VAL(POINTER, 0))
774 | (SMU_CQGR_GEN_VAL(EVENT_POINTER, 0))
775 | (SMU_CQGR_GEN_BIT(ENABLE))
776 | (SMU_CQGR_GEN_BIT(EVENT_ENABLE))
777 );
778
779 writel(completion_queue_get_value,
780 &ihost->smu_registers->completion_queue_get);
781
782 /* Set the completion queue put pointer */
783 completion_queue_put_value = (
784 (SMU_CQPR_GEN_VAL(POINTER, 0))
785 | (SMU_CQPR_GEN_VAL(EVENT_POINTER, 0))
786 );
787
788 writel(completion_queue_put_value,
789 &ihost->smu_registers->completion_queue_put);
790
791 /* Initialize the cycle bit of the completion queue entries */
792 for (index = 0; index < SCU_MAX_COMPLETION_QUEUE_ENTRIES; index++) {
793 /*
794 * If get.cycle_bit != completion_queue.cycle_bit
795 * its not a valid completion queue entry
796 * so at system start all entries are invalid */
797 ihost->completion_queue[index] = 0x80000000;
798 }
799 }
800
801 static void sci_controller_initialize_unsolicited_frame_queue(struct isci_host *ihost)
802 {
803 u32 frame_queue_control_value;
804 u32 frame_queue_get_value;
805 u32 frame_queue_put_value;
806
807 /* Write the queue size */
808 frame_queue_control_value =
809 SCU_UFQC_GEN_VAL(QUEUE_SIZE, SCU_MAX_UNSOLICITED_FRAMES);
810
811 writel(frame_queue_control_value,
812 &ihost->scu_registers->sdma.unsolicited_frame_queue_control);
813
814 /* Setup the get pointer for the unsolicited frame queue */
815 frame_queue_get_value = (
816 SCU_UFQGP_GEN_VAL(POINTER, 0)
817 | SCU_UFQGP_GEN_BIT(ENABLE_BIT)
818 );
819
820 writel(frame_queue_get_value,
821 &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
822 /* Setup the put pointer for the unsolicited frame queue */
823 frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0);
824 writel(frame_queue_put_value,
825 &ihost->scu_registers->sdma.unsolicited_frame_put_pointer);
826 }
827
828 static void sci_controller_transition_to_ready(struct isci_host *ihost, enum sci_status status)
829 {
830 if (ihost->sm.current_state_id == SCIC_STARTING) {
831 /*
832 * We move into the ready state, because some of the phys/ports
833 * may be up and operational.
834 */
835 sci_change_state(&ihost->sm, SCIC_READY);
836
837 isci_host_start_complete(ihost, status);
838 }
839 }
840
841 static bool is_phy_starting(struct isci_phy *iphy)
842 {
843 enum sci_phy_states state;
844
845 state = iphy->sm.current_state_id;
846 switch (state) {
847 case SCI_PHY_STARTING:
848 case SCI_PHY_SUB_INITIAL:
849 case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
850 case SCI_PHY_SUB_AWAIT_IAF_UF:
851 case SCI_PHY_SUB_AWAIT_SAS_POWER:
852 case SCI_PHY_SUB_AWAIT_SATA_POWER:
853 case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
854 case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
855 case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
856 case SCI_PHY_SUB_FINAL:
857 return true;
858 default:
859 return false;
860 }
861 }
862
863 /**
864 * sci_controller_start_next_phy - start phy
865 * @scic: controller
866 *
867 * If all the phys have been started, then attempt to transition the
868 * controller to the READY state and inform the user
869 * (sci_cb_controller_start_complete()).
870 */
871 static enum sci_status sci_controller_start_next_phy(struct isci_host *ihost)
872 {
873 struct sci_oem_params *oem = &ihost->oem_parameters;
874 struct isci_phy *iphy;
875 enum sci_status status;
876
877 status = SCI_SUCCESS;
878
879 if (ihost->phy_startup_timer_pending)
880 return status;
881
882 if (ihost->next_phy_to_start >= SCI_MAX_PHYS) {
883 bool is_controller_start_complete = true;
884 u32 state;
885 u8 index;
886
887 for (index = 0; index < SCI_MAX_PHYS; index++) {
888 iphy = &ihost->phys[index];
889 state = iphy->sm.current_state_id;
890
891 if (!phy_get_non_dummy_port(iphy))
892 continue;
893
894 /* The controller start operation is complete iff:
895 * - all links have been given an opportunity to start
896 * - have no indication of a connected device
897 * - have an indication of a connected device and it has
898 * finished the link training process.
899 */
900 if ((iphy->is_in_link_training == false && state == SCI_PHY_INITIAL) ||
901 (iphy->is_in_link_training == false && state == SCI_PHY_STOPPED) ||
902 (iphy->is_in_link_training == true && is_phy_starting(iphy)) ||
903 (ihost->port_agent.phy_ready_mask != ihost->port_agent.phy_configured_mask)) {
904 is_controller_start_complete = false;
905 break;
906 }
907 }
908
909 /*
910 * The controller has successfully finished the start process.
911 * Inform the SCI Core user and transition to the READY state. */
912 if (is_controller_start_complete == true) {
913 sci_controller_transition_to_ready(ihost, SCI_SUCCESS);
914 sci_del_timer(&ihost->phy_timer);
915 ihost->phy_startup_timer_pending = false;
916 }
917 } else {
918 iphy = &ihost->phys[ihost->next_phy_to_start];
919
920 if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
921 if (phy_get_non_dummy_port(iphy) == NULL) {
922 ihost->next_phy_to_start++;
923
924 /* Caution recursion ahead be forwarned
925 *
926 * The PHY was never added to a PORT in MPC mode
927 * so start the next phy in sequence This phy
928 * will never go link up and will not draw power
929 * the OEM parameters either configured the phy
930 * incorrectly for the PORT or it was never
931 * assigned to a PORT
932 */
933 return sci_controller_start_next_phy(ihost);
934 }
935 }
936
937 status = sci_phy_start(iphy);
938
939 if (status == SCI_SUCCESS) {
940 sci_mod_timer(&ihost->phy_timer,
941 SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT);
942 ihost->phy_startup_timer_pending = true;
943 } else {
944 dev_warn(&ihost->pdev->dev,
945 "%s: Controller stop operation failed "
946 "to stop phy %d because of status "
947 "%d.\n",
948 __func__,
949 ihost->phys[ihost->next_phy_to_start].phy_index,
950 status);
951 }
952
953 ihost->next_phy_to_start++;
954 }
955
956 return status;
957 }
958
959 static void phy_startup_timeout(unsigned long data)
960 {
961 struct sci_timer *tmr = (struct sci_timer *)data;
962 struct isci_host *ihost = container_of(tmr, typeof(*ihost), phy_timer);
963 unsigned long flags;
964 enum sci_status status;
965
966 spin_lock_irqsave(&ihost->scic_lock, flags);
967
968 if (tmr->cancel)
969 goto done;
970
971 ihost->phy_startup_timer_pending = false;
972
973 do {
974 status = sci_controller_start_next_phy(ihost);
975 } while (status != SCI_SUCCESS);
976
977 done:
978 spin_unlock_irqrestore(&ihost->scic_lock, flags);
979 }
980
981 static u16 isci_tci_active(struct isci_host *ihost)
982 {
983 return CIRC_CNT(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS);
984 }
985
986 static enum sci_status sci_controller_start(struct isci_host *ihost,
987 u32 timeout)
988 {
989 enum sci_status result;
990 u16 index;
991
992 if (ihost->sm.current_state_id != SCIC_INITIALIZED) {
993 dev_warn(&ihost->pdev->dev,
994 "SCIC Controller start operation requested in "
995 "invalid state\n");
996 return SCI_FAILURE_INVALID_STATE;
997 }
998
999 /* Build the TCi free pool */
1000 BUILD_BUG_ON(SCI_MAX_IO_REQUESTS > 1 << sizeof(ihost->tci_pool[0]) * 8);
1001 ihost->tci_head = 0;
1002 ihost->tci_tail = 0;
1003 for (index = 0; index < ihost->task_context_entries; index++)
1004 isci_tci_free(ihost, index);
1005
1006 /* Build the RNi free pool */
1007 sci_remote_node_table_initialize(&ihost->available_remote_nodes,
1008 ihost->remote_node_entries);
1009
1010 /*
1011 * Before anything else lets make sure we will not be
1012 * interrupted by the hardware.
1013 */
1014 sci_controller_disable_interrupts(ihost);
1015
1016 /* Enable the port task scheduler */
1017 sci_controller_enable_port_task_scheduler(ihost);
1018
1019 /* Assign all the task entries to ihost physical function */
1020 sci_controller_assign_task_entries(ihost);
1021
1022 /* Now initialize the completion queue */
1023 sci_controller_initialize_completion_queue(ihost);
1024
1025 /* Initialize the unsolicited frame queue for use */
1026 sci_controller_initialize_unsolicited_frame_queue(ihost);
1027
1028 /* Start all of the ports on this controller */
1029 for (index = 0; index < ihost->logical_port_entries; index++) {
1030 struct isci_port *iport = &ihost->ports[index];
1031
1032 result = sci_port_start(iport);
1033 if (result)
1034 return result;
1035 }
1036
1037 sci_controller_start_next_phy(ihost);
1038
1039 sci_mod_timer(&ihost->timer, timeout);
1040
1041 sci_change_state(&ihost->sm, SCIC_STARTING);
1042
1043 return SCI_SUCCESS;
1044 }
1045
1046 void isci_host_scan_start(struct Scsi_Host *shost)
1047 {
1048 struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha;
1049 unsigned long tmo = sci_controller_get_suggested_start_timeout(ihost);
1050
1051 set_bit(IHOST_START_PENDING, &ihost->flags);
1052
1053 spin_lock_irq(&ihost->scic_lock);
1054 sci_controller_start(ihost, tmo);
1055 sci_controller_enable_interrupts(ihost);
1056 spin_unlock_irq(&ihost->scic_lock);
1057 }
1058
1059 static void isci_host_stop_complete(struct isci_host *ihost, enum sci_status completion_status)
1060 {
1061 isci_host_change_state(ihost, isci_stopped);
1062 sci_controller_disable_interrupts(ihost);
1063 clear_bit(IHOST_STOP_PENDING, &ihost->flags);
1064 wake_up(&ihost->eventq);
1065 }
1066
1067 static void sci_controller_completion_handler(struct isci_host *ihost)
1068 {
1069 /* Empty out the completion queue */
1070 if (sci_controller_completion_queue_has_entries(ihost))
1071 sci_controller_process_completions(ihost);
1072
1073 /* Clear the interrupt and enable all interrupts again */
1074 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
1075 /* Could we write the value of SMU_ISR_COMPLETION? */
1076 writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
1077 writel(0, &ihost->smu_registers->interrupt_mask);
1078 }
1079
1080 /**
1081 * isci_host_completion_routine() - This function is the delayed service
1082 * routine that calls the sci core library's completion handler. It's
1083 * scheduled as a tasklet from the interrupt service routine when interrupts
1084 * in use, or set as the timeout function in polled mode.
1085 * @data: This parameter specifies the ISCI host object
1086 *
1087 */
1088 static void isci_host_completion_routine(unsigned long data)
1089 {
1090 struct isci_host *ihost = (struct isci_host *)data;
1091 struct list_head completed_request_list;
1092 struct list_head errored_request_list;
1093 struct list_head *current_position;
1094 struct list_head *next_position;
1095 struct isci_request *request;
1096 struct isci_request *next_request;
1097 struct sas_task *task;
1098 u16 active;
1099
1100 INIT_LIST_HEAD(&completed_request_list);
1101 INIT_LIST_HEAD(&errored_request_list);
1102
1103 spin_lock_irq(&ihost->scic_lock);
1104
1105 sci_controller_completion_handler(ihost);
1106
1107 /* Take the lists of completed I/Os from the host. */
1108
1109 list_splice_init(&ihost->requests_to_complete,
1110 &completed_request_list);
1111
1112 /* Take the list of errored I/Os from the host. */
1113 list_splice_init(&ihost->requests_to_errorback,
1114 &errored_request_list);
1115
1116 spin_unlock_irq(&ihost->scic_lock);
1117
1118 /* Process any completions in the lists. */
1119 list_for_each_safe(current_position, next_position,
1120 &completed_request_list) {
1121
1122 request = list_entry(current_position, struct isci_request,
1123 completed_node);
1124 task = isci_request_access_task(request);
1125
1126 /* Normal notification (task_done) */
1127 dev_dbg(&ihost->pdev->dev,
1128 "%s: Normal - request/task = %p/%p\n",
1129 __func__,
1130 request,
1131 task);
1132
1133 /* Return the task to libsas */
1134 if (task != NULL) {
1135
1136 task->lldd_task = NULL;
1137 if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
1138
1139 /* If the task is already in the abort path,
1140 * the task_done callback cannot be called.
1141 */
1142 task->task_done(task);
1143 }
1144 }
1145
1146 spin_lock_irq(&ihost->scic_lock);
1147 isci_free_tag(ihost, request->io_tag);
1148 spin_unlock_irq(&ihost->scic_lock);
1149 }
1150 list_for_each_entry_safe(request, next_request, &errored_request_list,
1151 completed_node) {
1152
1153 task = isci_request_access_task(request);
1154
1155 /* Use sas_task_abort */
1156 dev_warn(&ihost->pdev->dev,
1157 "%s: Error - request/task = %p/%p\n",
1158 __func__,
1159 request,
1160 task);
1161
1162 if (task != NULL) {
1163
1164 /* Put the task into the abort path if it's not there
1165 * already.
1166 */
1167 if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED))
1168 sas_task_abort(task);
1169
1170 } else {
1171 /* This is a case where the request has completed with a
1172 * status such that it needed further target servicing,
1173 * but the sas_task reference has already been removed
1174 * from the request. Since it was errored, it was not
1175 * being aborted, so there is nothing to do except free
1176 * it.
1177 */
1178
1179 spin_lock_irq(&ihost->scic_lock);
1180 /* Remove the request from the remote device's list
1181 * of pending requests.
1182 */
1183 list_del_init(&request->dev_node);
1184 isci_free_tag(ihost, request->io_tag);
1185 spin_unlock_irq(&ihost->scic_lock);
1186 }
1187 }
1188
1189 /* the coalesence timeout doubles at each encoding step, so
1190 * update it based on the ilog2 value of the outstanding requests
1191 */
1192 active = isci_tci_active(ihost);
1193 writel(SMU_ICC_GEN_VAL(NUMBER, active) |
1194 SMU_ICC_GEN_VAL(TIMER, ISCI_COALESCE_BASE + ilog2(active)),
1195 &ihost->smu_registers->interrupt_coalesce_control);
1196 }
1197
1198 /**
1199 * sci_controller_stop() - This method will stop an individual controller
1200 * object.This method will invoke the associated user callback upon
1201 * completion. The completion callback is called when the following
1202 * conditions are met: -# the method return status is SCI_SUCCESS. -# the
1203 * controller has been quiesced. This method will ensure that all IO
1204 * requests are quiesced, phys are stopped, and all additional operation by
1205 * the hardware is halted.
1206 * @controller: the handle to the controller object to stop.
1207 * @timeout: This parameter specifies the number of milliseconds in which the
1208 * stop operation should complete.
1209 *
1210 * The controller must be in the STARTED or STOPPED state. Indicate if the
1211 * controller stop method succeeded or failed in some way. SCI_SUCCESS if the
1212 * stop operation successfully began. SCI_WARNING_ALREADY_IN_STATE if the
1213 * controller is already in the STOPPED state. SCI_FAILURE_INVALID_STATE if the
1214 * controller is not either in the STARTED or STOPPED states.
1215 */
1216 static enum sci_status sci_controller_stop(struct isci_host *ihost, u32 timeout)
1217 {
1218 if (ihost->sm.current_state_id != SCIC_READY) {
1219 dev_warn(&ihost->pdev->dev,
1220 "SCIC Controller stop operation requested in "
1221 "invalid state\n");
1222 return SCI_FAILURE_INVALID_STATE;
1223 }
1224
1225 sci_mod_timer(&ihost->timer, timeout);
1226 sci_change_state(&ihost->sm, SCIC_STOPPING);
1227 return SCI_SUCCESS;
1228 }
1229
1230 /**
1231 * sci_controller_reset() - This method will reset the supplied core
1232 * controller regardless of the state of said controller. This operation is
1233 * considered destructive. In other words, all current operations are wiped
1234 * out. No IO completions for outstanding devices occur. Outstanding IO
1235 * requests are not aborted or completed at the actual remote device.
1236 * @controller: the handle to the controller object to reset.
1237 *
1238 * Indicate if the controller reset method succeeded or failed in some way.
1239 * SCI_SUCCESS if the reset operation successfully started. SCI_FATAL_ERROR if
1240 * the controller reset operation is unable to complete.
1241 */
1242 static enum sci_status sci_controller_reset(struct isci_host *ihost)
1243 {
1244 switch (ihost->sm.current_state_id) {
1245 case SCIC_RESET:
1246 case SCIC_READY:
1247 case SCIC_STOPPED:
1248 case SCIC_FAILED:
1249 /*
1250 * The reset operation is not a graceful cleanup, just
1251 * perform the state transition.
1252 */
1253 sci_change_state(&ihost->sm, SCIC_RESETTING);
1254 return SCI_SUCCESS;
1255 default:
1256 dev_warn(&ihost->pdev->dev,
1257 "SCIC Controller reset operation requested in "
1258 "invalid state\n");
1259 return SCI_FAILURE_INVALID_STATE;
1260 }
1261 }
1262
1263 void isci_host_deinit(struct isci_host *ihost)
1264 {
1265 int i;
1266
1267 /* disable output data selects */
1268 for (i = 0; i < isci_gpio_count(ihost); i++)
1269 writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]);
1270
1271 isci_host_change_state(ihost, isci_stopping);
1272 for (i = 0; i < SCI_MAX_PORTS; i++) {
1273 struct isci_port *iport = &ihost->ports[i];
1274 struct isci_remote_device *idev, *d;
1275
1276 list_for_each_entry_safe(idev, d, &iport->remote_dev_list, node) {
1277 if (test_bit(IDEV_ALLOCATED, &idev->flags))
1278 isci_remote_device_stop(ihost, idev);
1279 }
1280 }
1281
1282 set_bit(IHOST_STOP_PENDING, &ihost->flags);
1283
1284 spin_lock_irq(&ihost->scic_lock);
1285 sci_controller_stop(ihost, SCIC_CONTROLLER_STOP_TIMEOUT);
1286 spin_unlock_irq(&ihost->scic_lock);
1287
1288 wait_for_stop(ihost);
1289
1290 /* disable sgpio: where the above wait should give time for the
1291 * enclosure to sample the gpios going inactive
1292 */
1293 writel(0, &ihost->scu_registers->peg0.sgpio.interface_control);
1294
1295 sci_controller_reset(ihost);
1296
1297 /* Cancel any/all outstanding port timers */
1298 for (i = 0; i < ihost->logical_port_entries; i++) {
1299 struct isci_port *iport = &ihost->ports[i];
1300 del_timer_sync(&iport->timer.timer);
1301 }
1302
1303 /* Cancel any/all outstanding phy timers */
1304 for (i = 0; i < SCI_MAX_PHYS; i++) {
1305 struct isci_phy *iphy = &ihost->phys[i];
1306 del_timer_sync(&iphy->sata_timer.timer);
1307 }
1308
1309 del_timer_sync(&ihost->port_agent.timer.timer);
1310
1311 del_timer_sync(&ihost->power_control.timer.timer);
1312
1313 del_timer_sync(&ihost->timer.timer);
1314
1315 del_timer_sync(&ihost->phy_timer.timer);
1316 }
1317
1318 static void __iomem *scu_base(struct isci_host *isci_host)
1319 {
1320 struct pci_dev *pdev = isci_host->pdev;
1321 int id = isci_host->id;
1322
1323 return pcim_iomap_table(pdev)[SCI_SCU_BAR * 2] + SCI_SCU_BAR_SIZE * id;
1324 }
1325
1326 static void __iomem *smu_base(struct isci_host *isci_host)
1327 {
1328 struct pci_dev *pdev = isci_host->pdev;
1329 int id = isci_host->id;
1330
1331 return pcim_iomap_table(pdev)[SCI_SMU_BAR * 2] + SCI_SMU_BAR_SIZE * id;
1332 }
1333
1334 static void isci_user_parameters_get(struct sci_user_parameters *u)
1335 {
1336 int i;
1337
1338 for (i = 0; i < SCI_MAX_PHYS; i++) {
1339 struct sci_phy_user_params *u_phy = &u->phys[i];
1340
1341 u_phy->max_speed_generation = phy_gen;
1342
1343 /* we are not exporting these for now */
1344 u_phy->align_insertion_frequency = 0x7f;
1345 u_phy->in_connection_align_insertion_frequency = 0xff;
1346 u_phy->notify_enable_spin_up_insertion_frequency = 0x33;
1347 }
1348
1349 u->stp_inactivity_timeout = stp_inactive_to;
1350 u->ssp_inactivity_timeout = ssp_inactive_to;
1351 u->stp_max_occupancy_timeout = stp_max_occ_to;
1352 u->ssp_max_occupancy_timeout = ssp_max_occ_to;
1353 u->no_outbound_task_timeout = no_outbound_task_to;
1354 u->max_concurr_spinup = max_concurr_spinup;
1355 }
1356
1357 static void sci_controller_initial_state_enter(struct sci_base_state_machine *sm)
1358 {
1359 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1360
1361 sci_change_state(&ihost->sm, SCIC_RESET);
1362 }
1363
1364 static inline void sci_controller_starting_state_exit(struct sci_base_state_machine *sm)
1365 {
1366 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1367
1368 sci_del_timer(&ihost->timer);
1369 }
1370
1371 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS 853
1372 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS 1280
1373 #define INTERRUPT_COALESCE_TIMEOUT_MAX_US 2700000
1374 #define INTERRUPT_COALESCE_NUMBER_MAX 256
1375 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN 7
1376 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX 28
1377
1378 /**
1379 * sci_controller_set_interrupt_coalescence() - This method allows the user to
1380 * configure the interrupt coalescence.
1381 * @controller: This parameter represents the handle to the controller object
1382 * for which its interrupt coalesce register is overridden.
1383 * @coalesce_number: Used to control the number of entries in the Completion
1384 * Queue before an interrupt is generated. If the number of entries exceed
1385 * this number, an interrupt will be generated. The valid range of the input
1386 * is [0, 256]. A setting of 0 results in coalescing being disabled.
1387 * @coalesce_timeout: Timeout value in microseconds. The valid range of the
1388 * input is [0, 2700000] . A setting of 0 is allowed and results in no
1389 * interrupt coalescing timeout.
1390 *
1391 * Indicate if the user successfully set the interrupt coalesce parameters.
1392 * SCI_SUCCESS The user successfully updated the interrutp coalescence.
1393 * SCI_FAILURE_INVALID_PARAMETER_VALUE The user input value is out of range.
1394 */
1395 static enum sci_status
1396 sci_controller_set_interrupt_coalescence(struct isci_host *ihost,
1397 u32 coalesce_number,
1398 u32 coalesce_timeout)
1399 {
1400 u8 timeout_encode = 0;
1401 u32 min = 0;
1402 u32 max = 0;
1403
1404 /* Check if the input parameters fall in the range. */
1405 if (coalesce_number > INTERRUPT_COALESCE_NUMBER_MAX)
1406 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1407
1408 /*
1409 * Defined encoding for interrupt coalescing timeout:
1410 * Value Min Max Units
1411 * ----- --- --- -----
1412 * 0 - - Disabled
1413 * 1 13.3 20.0 ns
1414 * 2 26.7 40.0
1415 * 3 53.3 80.0
1416 * 4 106.7 160.0
1417 * 5 213.3 320.0
1418 * 6 426.7 640.0
1419 * 7 853.3 1280.0
1420 * 8 1.7 2.6 us
1421 * 9 3.4 5.1
1422 * 10 6.8 10.2
1423 * 11 13.7 20.5
1424 * 12 27.3 41.0
1425 * 13 54.6 81.9
1426 * 14 109.2 163.8
1427 * 15 218.5 327.7
1428 * 16 436.9 655.4
1429 * 17 873.8 1310.7
1430 * 18 1.7 2.6 ms
1431 * 19 3.5 5.2
1432 * 20 7.0 10.5
1433 * 21 14.0 21.0
1434 * 22 28.0 41.9
1435 * 23 55.9 83.9
1436 * 24 111.8 167.8
1437 * 25 223.7 335.5
1438 * 26 447.4 671.1
1439 * 27 894.8 1342.2
1440 * 28 1.8 2.7 s
1441 * Others Undefined */
1442
1443 /*
1444 * Use the table above to decide the encode of interrupt coalescing timeout
1445 * value for register writing. */
1446 if (coalesce_timeout == 0)
1447 timeout_encode = 0;
1448 else{
1449 /* make the timeout value in unit of (10 ns). */
1450 coalesce_timeout = coalesce_timeout * 100;
1451 min = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS / 10;
1452 max = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS / 10;
1453
1454 /* get the encode of timeout for register writing. */
1455 for (timeout_encode = INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN;
1456 timeout_encode <= INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX;
1457 timeout_encode++) {
1458 if (min <= coalesce_timeout && max > coalesce_timeout)
1459 break;
1460 else if (coalesce_timeout >= max && coalesce_timeout < min * 2
1461 && coalesce_timeout <= INTERRUPT_COALESCE_TIMEOUT_MAX_US * 100) {
1462 if ((coalesce_timeout - max) < (2 * min - coalesce_timeout))
1463 break;
1464 else{
1465 timeout_encode++;
1466 break;
1467 }
1468 } else {
1469 max = max * 2;
1470 min = min * 2;
1471 }
1472 }
1473
1474 if (timeout_encode == INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX + 1)
1475 /* the value is out of range. */
1476 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1477 }
1478
1479 writel(SMU_ICC_GEN_VAL(NUMBER, coalesce_number) |
1480 SMU_ICC_GEN_VAL(TIMER, timeout_encode),
1481 &ihost->smu_registers->interrupt_coalesce_control);
1482
1483
1484 ihost->interrupt_coalesce_number = (u16)coalesce_number;
1485 ihost->interrupt_coalesce_timeout = coalesce_timeout / 100;
1486
1487 return SCI_SUCCESS;
1488 }
1489
1490
1491 static void sci_controller_ready_state_enter(struct sci_base_state_machine *sm)
1492 {
1493 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1494
1495 /* set the default interrupt coalescence number and timeout value. */
1496 sci_controller_set_interrupt_coalescence(ihost, 0, 0);
1497 }
1498
1499 static void sci_controller_ready_state_exit(struct sci_base_state_machine *sm)
1500 {
1501 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1502
1503 /* disable interrupt coalescence. */
1504 sci_controller_set_interrupt_coalescence(ihost, 0, 0);
1505 }
1506
1507 static enum sci_status sci_controller_stop_phys(struct isci_host *ihost)
1508 {
1509 u32 index;
1510 enum sci_status status;
1511 enum sci_status phy_status;
1512
1513 status = SCI_SUCCESS;
1514
1515 for (index = 0; index < SCI_MAX_PHYS; index++) {
1516 phy_status = sci_phy_stop(&ihost->phys[index]);
1517
1518 if (phy_status != SCI_SUCCESS &&
1519 phy_status != SCI_FAILURE_INVALID_STATE) {
1520 status = SCI_FAILURE;
1521
1522 dev_warn(&ihost->pdev->dev,
1523 "%s: Controller stop operation failed to stop "
1524 "phy %d because of status %d.\n",
1525 __func__,
1526 ihost->phys[index].phy_index, phy_status);
1527 }
1528 }
1529
1530 return status;
1531 }
1532
1533 static enum sci_status sci_controller_stop_ports(struct isci_host *ihost)
1534 {
1535 u32 index;
1536 enum sci_status port_status;
1537 enum sci_status status = SCI_SUCCESS;
1538
1539 for (index = 0; index < ihost->logical_port_entries; index++) {
1540 struct isci_port *iport = &ihost->ports[index];
1541
1542 port_status = sci_port_stop(iport);
1543
1544 if ((port_status != SCI_SUCCESS) &&
1545 (port_status != SCI_FAILURE_INVALID_STATE)) {
1546 status = SCI_FAILURE;
1547
1548 dev_warn(&ihost->pdev->dev,
1549 "%s: Controller stop operation failed to "
1550 "stop port %d because of status %d.\n",
1551 __func__,
1552 iport->logical_port_index,
1553 port_status);
1554 }
1555 }
1556
1557 return status;
1558 }
1559
1560 static enum sci_status sci_controller_stop_devices(struct isci_host *ihost)
1561 {
1562 u32 index;
1563 enum sci_status status;
1564 enum sci_status device_status;
1565
1566 status = SCI_SUCCESS;
1567
1568 for (index = 0; index < ihost->remote_node_entries; index++) {
1569 if (ihost->device_table[index] != NULL) {
1570 /* / @todo What timeout value do we want to provide to this request? */
1571 device_status = sci_remote_device_stop(ihost->device_table[index], 0);
1572
1573 if ((device_status != SCI_SUCCESS) &&
1574 (device_status != SCI_FAILURE_INVALID_STATE)) {
1575 dev_warn(&ihost->pdev->dev,
1576 "%s: Controller stop operation failed "
1577 "to stop device 0x%p because of "
1578 "status %d.\n",
1579 __func__,
1580 ihost->device_table[index], device_status);
1581 }
1582 }
1583 }
1584
1585 return status;
1586 }
1587
1588 static void sci_controller_stopping_state_enter(struct sci_base_state_machine *sm)
1589 {
1590 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1591
1592 /* Stop all of the components for this controller */
1593 sci_controller_stop_phys(ihost);
1594 sci_controller_stop_ports(ihost);
1595 sci_controller_stop_devices(ihost);
1596 }
1597
1598 static void sci_controller_stopping_state_exit(struct sci_base_state_machine *sm)
1599 {
1600 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1601
1602 sci_del_timer(&ihost->timer);
1603 }
1604
1605 static void sci_controller_reset_hardware(struct isci_host *ihost)
1606 {
1607 /* Disable interrupts so we dont take any spurious interrupts */
1608 sci_controller_disable_interrupts(ihost);
1609
1610 /* Reset the SCU */
1611 writel(0xFFFFFFFF, &ihost->smu_registers->soft_reset_control);
1612
1613 /* Delay for 1ms to before clearing the CQP and UFQPR. */
1614 udelay(1000);
1615
1616 /* The write to the CQGR clears the CQP */
1617 writel(0x00000000, &ihost->smu_registers->completion_queue_get);
1618
1619 /* The write to the UFQGP clears the UFQPR */
1620 writel(0, &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
1621 }
1622
1623 static void sci_controller_resetting_state_enter(struct sci_base_state_machine *sm)
1624 {
1625 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1626
1627 sci_controller_reset_hardware(ihost);
1628 sci_change_state(&ihost->sm, SCIC_RESET);
1629 }
1630
1631 static const struct sci_base_state sci_controller_state_table[] = {
1632 [SCIC_INITIAL] = {
1633 .enter_state = sci_controller_initial_state_enter,
1634 },
1635 [SCIC_RESET] = {},
1636 [SCIC_INITIALIZING] = {},
1637 [SCIC_INITIALIZED] = {},
1638 [SCIC_STARTING] = {
1639 .exit_state = sci_controller_starting_state_exit,
1640 },
1641 [SCIC_READY] = {
1642 .enter_state = sci_controller_ready_state_enter,
1643 .exit_state = sci_controller_ready_state_exit,
1644 },
1645 [SCIC_RESETTING] = {
1646 .enter_state = sci_controller_resetting_state_enter,
1647 },
1648 [SCIC_STOPPING] = {
1649 .enter_state = sci_controller_stopping_state_enter,
1650 .exit_state = sci_controller_stopping_state_exit,
1651 },
1652 [SCIC_STOPPED] = {},
1653 [SCIC_FAILED] = {}
1654 };
1655
1656 static void sci_controller_set_default_config_parameters(struct isci_host *ihost)
1657 {
1658 /* these defaults are overridden by the platform / firmware */
1659 u16 index;
1660
1661 /* Default to APC mode. */
1662 ihost->oem_parameters.controller.mode_type = SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE;
1663
1664 /* Default to APC mode. */
1665 ihost->oem_parameters.controller.max_concurr_spin_up = 1;
1666
1667 /* Default to no SSC operation. */
1668 ihost->oem_parameters.controller.do_enable_ssc = false;
1669
1670 /* Default to short cables on all phys. */
1671 ihost->oem_parameters.controller.cable_selection_mask = 0;
1672
1673 /* Initialize all of the port parameter information to narrow ports. */
1674 for (index = 0; index < SCI_MAX_PORTS; index++) {
1675 ihost->oem_parameters.ports[index].phy_mask = 0;
1676 }
1677
1678 /* Initialize all of the phy parameter information. */
1679 for (index = 0; index < SCI_MAX_PHYS; index++) {
1680 /* Default to 3G (i.e. Gen 2). */
1681 ihost->user_parameters.phys[index].max_speed_generation =
1682 SCIC_SDS_PARM_GEN2_SPEED;
1683
1684 /* the frequencies cannot be 0 */
1685 ihost->user_parameters.phys[index].align_insertion_frequency = 0x7f;
1686 ihost->user_parameters.phys[index].in_connection_align_insertion_frequency = 0xff;
1687 ihost->user_parameters.phys[index].notify_enable_spin_up_insertion_frequency = 0x33;
1688
1689 /*
1690 * Previous Vitesse based expanders had a arbitration issue that
1691 * is worked around by having the upper 32-bits of SAS address
1692 * with a value greater then the Vitesse company identifier.
1693 * Hence, usage of 0x5FCFFFFF. */
1694 ihost->oem_parameters.phys[index].sas_address.low = 0x1 + ihost->id;
1695 ihost->oem_parameters.phys[index].sas_address.high = 0x5FCFFFFF;
1696 }
1697
1698 ihost->user_parameters.stp_inactivity_timeout = 5;
1699 ihost->user_parameters.ssp_inactivity_timeout = 5;
1700 ihost->user_parameters.stp_max_occupancy_timeout = 5;
1701 ihost->user_parameters.ssp_max_occupancy_timeout = 20;
1702 ihost->user_parameters.no_outbound_task_timeout = 2;
1703 }
1704
1705 static void controller_timeout(unsigned long data)
1706 {
1707 struct sci_timer *tmr = (struct sci_timer *)data;
1708 struct isci_host *ihost = container_of(tmr, typeof(*ihost), timer);
1709 struct sci_base_state_machine *sm = &ihost->sm;
1710 unsigned long flags;
1711
1712 spin_lock_irqsave(&ihost->scic_lock, flags);
1713
1714 if (tmr->cancel)
1715 goto done;
1716
1717 if (sm->current_state_id == SCIC_STARTING)
1718 sci_controller_transition_to_ready(ihost, SCI_FAILURE_TIMEOUT);
1719 else if (sm->current_state_id == SCIC_STOPPING) {
1720 sci_change_state(sm, SCIC_FAILED);
1721 isci_host_stop_complete(ihost, SCI_FAILURE_TIMEOUT);
1722 } else /* / @todo Now what do we want to do in this case? */
1723 dev_err(&ihost->pdev->dev,
1724 "%s: Controller timer fired when controller was not "
1725 "in a state being timed.\n",
1726 __func__);
1727
1728 done:
1729 spin_unlock_irqrestore(&ihost->scic_lock, flags);
1730 }
1731
1732 static enum sci_status sci_controller_construct(struct isci_host *ihost,
1733 void __iomem *scu_base,
1734 void __iomem *smu_base)
1735 {
1736 u8 i;
1737
1738 sci_init_sm(&ihost->sm, sci_controller_state_table, SCIC_INITIAL);
1739
1740 ihost->scu_registers = scu_base;
1741 ihost->smu_registers = smu_base;
1742
1743 sci_port_configuration_agent_construct(&ihost->port_agent);
1744
1745 /* Construct the ports for this controller */
1746 for (i = 0; i < SCI_MAX_PORTS; i++)
1747 sci_port_construct(&ihost->ports[i], i, ihost);
1748 sci_port_construct(&ihost->ports[i], SCIC_SDS_DUMMY_PORT, ihost);
1749
1750 /* Construct the phys for this controller */
1751 for (i = 0; i < SCI_MAX_PHYS; i++) {
1752 /* Add all the PHYs to the dummy port */
1753 sci_phy_construct(&ihost->phys[i],
1754 &ihost->ports[SCI_MAX_PORTS], i);
1755 }
1756
1757 ihost->invalid_phy_mask = 0;
1758
1759 sci_init_timer(&ihost->timer, controller_timeout);
1760
1761 /* Initialize the User and OEM parameters to default values. */
1762 sci_controller_set_default_config_parameters(ihost);
1763
1764 return sci_controller_reset(ihost);
1765 }
1766
1767 int sci_oem_parameters_validate(struct sci_oem_params *oem, u8 version)
1768 {
1769 int i;
1770
1771 for (i = 0; i < SCI_MAX_PORTS; i++)
1772 if (oem->ports[i].phy_mask > SCIC_SDS_PARM_PHY_MASK_MAX)
1773 return -EINVAL;
1774
1775 for (i = 0; i < SCI_MAX_PHYS; i++)
1776 if (oem->phys[i].sas_address.high == 0 &&
1777 oem->phys[i].sas_address.low == 0)
1778 return -EINVAL;
1779
1780 if (oem->controller.mode_type == SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE) {
1781 for (i = 0; i < SCI_MAX_PHYS; i++)
1782 if (oem->ports[i].phy_mask != 0)
1783 return -EINVAL;
1784 } else if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
1785 u8 phy_mask = 0;
1786
1787 for (i = 0; i < SCI_MAX_PHYS; i++)
1788 phy_mask |= oem->ports[i].phy_mask;
1789
1790 if (phy_mask == 0)
1791 return -EINVAL;
1792 } else
1793 return -EINVAL;
1794
1795 if (oem->controller.max_concurr_spin_up > MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT ||
1796 oem->controller.max_concurr_spin_up < 1)
1797 return -EINVAL;
1798
1799 if (oem->controller.do_enable_ssc) {
1800 if (version < ISCI_ROM_VER_1_1 && oem->controller.do_enable_ssc != 1)
1801 return -EINVAL;
1802
1803 if (version >= ISCI_ROM_VER_1_1) {
1804 u8 test = oem->controller.ssc_sata_tx_spread_level;
1805
1806 switch (test) {
1807 case 0:
1808 case 2:
1809 case 3:
1810 case 6:
1811 case 7:
1812 break;
1813 default:
1814 return -EINVAL;
1815 }
1816
1817 test = oem->controller.ssc_sas_tx_spread_level;
1818 if (oem->controller.ssc_sas_tx_type == 0) {
1819 switch (test) {
1820 case 0:
1821 case 2:
1822 case 3:
1823 break;
1824 default:
1825 return -EINVAL;
1826 }
1827 } else if (oem->controller.ssc_sas_tx_type == 1) {
1828 switch (test) {
1829 case 0:
1830 case 3:
1831 case 6:
1832 break;
1833 default:
1834 return -EINVAL;
1835 }
1836 }
1837 }
1838 }
1839
1840 return 0;
1841 }
1842
1843 static enum sci_status sci_oem_parameters_set(struct isci_host *ihost)
1844 {
1845 u32 state = ihost->sm.current_state_id;
1846 struct isci_pci_info *pci_info = to_pci_info(ihost->pdev);
1847
1848 if (state == SCIC_RESET ||
1849 state == SCIC_INITIALIZING ||
1850 state == SCIC_INITIALIZED) {
1851 u8 oem_version = pci_info->orom ? pci_info->orom->hdr.version :
1852 ISCI_ROM_VER_1_0;
1853
1854 if (sci_oem_parameters_validate(&ihost->oem_parameters,
1855 oem_version))
1856 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1857
1858 return SCI_SUCCESS;
1859 }
1860
1861 return SCI_FAILURE_INVALID_STATE;
1862 }
1863
1864 static u8 max_spin_up(struct isci_host *ihost)
1865 {
1866 if (ihost->user_parameters.max_concurr_spinup)
1867 return min_t(u8, ihost->user_parameters.max_concurr_spinup,
1868 MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT);
1869 else
1870 return min_t(u8, ihost->oem_parameters.controller.max_concurr_spin_up,
1871 MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT);
1872 }
1873
1874 static void power_control_timeout(unsigned long data)
1875 {
1876 struct sci_timer *tmr = (struct sci_timer *)data;
1877 struct isci_host *ihost = container_of(tmr, typeof(*ihost), power_control.timer);
1878 struct isci_phy *iphy;
1879 unsigned long flags;
1880 u8 i;
1881
1882 spin_lock_irqsave(&ihost->scic_lock, flags);
1883
1884 if (tmr->cancel)
1885 goto done;
1886
1887 ihost->power_control.phys_granted_power = 0;
1888
1889 if (ihost->power_control.phys_waiting == 0) {
1890 ihost->power_control.timer_started = false;
1891 goto done;
1892 }
1893
1894 for (i = 0; i < SCI_MAX_PHYS; i++) {
1895
1896 if (ihost->power_control.phys_waiting == 0)
1897 break;
1898
1899 iphy = ihost->power_control.requesters[i];
1900 if (iphy == NULL)
1901 continue;
1902
1903 if (ihost->power_control.phys_granted_power >= max_spin_up(ihost))
1904 break;
1905
1906 ihost->power_control.requesters[i] = NULL;
1907 ihost->power_control.phys_waiting--;
1908 ihost->power_control.phys_granted_power++;
1909 sci_phy_consume_power_handler(iphy);
1910
1911 if (iphy->protocol == SCIC_SDS_PHY_PROTOCOL_SAS) {
1912 u8 j;
1913
1914 for (j = 0; j < SCI_MAX_PHYS; j++) {
1915 struct isci_phy *requester = ihost->power_control.requesters[j];
1916
1917 /*
1918 * Search the power_control queue to see if there are other phys
1919 * attached to the same remote device. If found, take all of
1920 * them out of await_sas_power state.
1921 */
1922 if (requester != NULL && requester != iphy) {
1923 u8 other = memcmp(requester->frame_rcvd.iaf.sas_addr,
1924 iphy->frame_rcvd.iaf.sas_addr,
1925 sizeof(requester->frame_rcvd.iaf.sas_addr));
1926
1927 if (other == 0) {
1928 ihost->power_control.requesters[j] = NULL;
1929 ihost->power_control.phys_waiting--;
1930 sci_phy_consume_power_handler(requester);
1931 }
1932 }
1933 }
1934 }
1935 }
1936
1937 /*
1938 * It doesn't matter if the power list is empty, we need to start the
1939 * timer in case another phy becomes ready.
1940 */
1941 sci_mod_timer(tmr, SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
1942 ihost->power_control.timer_started = true;
1943
1944 done:
1945 spin_unlock_irqrestore(&ihost->scic_lock, flags);
1946 }
1947
1948 void sci_controller_power_control_queue_insert(struct isci_host *ihost,
1949 struct isci_phy *iphy)
1950 {
1951 BUG_ON(iphy == NULL);
1952
1953 if (ihost->power_control.phys_granted_power < max_spin_up(ihost)) {
1954 ihost->power_control.phys_granted_power++;
1955 sci_phy_consume_power_handler(iphy);
1956
1957 /*
1958 * stop and start the power_control timer. When the timer fires, the
1959 * no_of_phys_granted_power will be set to 0
1960 */
1961 if (ihost->power_control.timer_started)
1962 sci_del_timer(&ihost->power_control.timer);
1963
1964 sci_mod_timer(&ihost->power_control.timer,
1965 SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
1966 ihost->power_control.timer_started = true;
1967
1968 } else {
1969 /*
1970 * There are phys, attached to the same sas address as this phy, are
1971 * already in READY state, this phy don't need wait.
1972 */
1973 u8 i;
1974 struct isci_phy *current_phy;
1975
1976 for (i = 0; i < SCI_MAX_PHYS; i++) {
1977 u8 other;
1978 current_phy = &ihost->phys[i];
1979
1980 other = memcmp(current_phy->frame_rcvd.iaf.sas_addr,
1981 iphy->frame_rcvd.iaf.sas_addr,
1982 sizeof(current_phy->frame_rcvd.iaf.sas_addr));
1983
1984 if (current_phy->sm.current_state_id == SCI_PHY_READY &&
1985 current_phy->protocol == SCIC_SDS_PHY_PROTOCOL_SAS &&
1986 other == 0) {
1987 sci_phy_consume_power_handler(iphy);
1988 break;
1989 }
1990 }
1991
1992 if (i == SCI_MAX_PHYS) {
1993 /* Add the phy in the waiting list */
1994 ihost->power_control.requesters[iphy->phy_index] = iphy;
1995 ihost->power_control.phys_waiting++;
1996 }
1997 }
1998 }
1999
2000 void sci_controller_power_control_queue_remove(struct isci_host *ihost,
2001 struct isci_phy *iphy)
2002 {
2003 BUG_ON(iphy == NULL);
2004
2005 if (ihost->power_control.requesters[iphy->phy_index])
2006 ihost->power_control.phys_waiting--;
2007
2008 ihost->power_control.requesters[iphy->phy_index] = NULL;
2009 }
2010
2011 static int is_long_cable(int phy, unsigned char selection_byte)
2012 {
2013 return !!(selection_byte & (1 << phy));
2014 }
2015
2016 static int is_medium_cable(int phy, unsigned char selection_byte)
2017 {
2018 return !!(selection_byte & (1 << (phy + 4)));
2019 }
2020
2021 static enum cable_selections decode_selection_byte(
2022 int phy,
2023 unsigned char selection_byte)
2024 {
2025 return ((selection_byte & (1 << phy)) ? 1 : 0)
2026 + (selection_byte & (1 << (phy + 4)) ? 2 : 0);
2027 }
2028
2029 static unsigned char *to_cable_select(struct isci_host *ihost)
2030 {
2031 if (is_cable_select_overridden())
2032 return ((unsigned char *)&cable_selection_override)
2033 + ihost->id;
2034 else
2035 return &ihost->oem_parameters.controller.cable_selection_mask;
2036 }
2037
2038 enum cable_selections decode_cable_selection(struct isci_host *ihost, int phy)
2039 {
2040 return decode_selection_byte(phy, *to_cable_select(ihost));
2041 }
2042
2043 char *lookup_cable_names(enum cable_selections selection)
2044 {
2045 static char *cable_names[] = {
2046 [short_cable] = "short",
2047 [long_cable] = "long",
2048 [medium_cable] = "medium",
2049 [undefined_cable] = "<undefined, assumed long>" /* bit 0==1 */
2050 };
2051 return (selection <= undefined_cable) ? cable_names[selection]
2052 : cable_names[undefined_cable];
2053 }
2054
2055 #define AFE_REGISTER_WRITE_DELAY 10
2056
2057 static void sci_controller_afe_initialization(struct isci_host *ihost)
2058 {
2059 struct scu_afe_registers __iomem *afe = &ihost->scu_registers->afe;
2060 const struct sci_oem_params *oem = &ihost->oem_parameters;
2061 struct pci_dev *pdev = ihost->pdev;
2062 u32 afe_status;
2063 u32 phy_id;
2064 unsigned char cable_selection_mask = *to_cable_select(ihost);
2065
2066 /* Clear DFX Status registers */
2067 writel(0x0081000f, &afe->afe_dfx_master_control0);
2068 udelay(AFE_REGISTER_WRITE_DELAY);
2069
2070 if (is_b0(pdev) || is_c0(pdev) || is_c1(pdev)) {
2071 /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement
2072 * Timer, PM Stagger Timer
2073 */
2074 writel(0x0007FFFF, &afe->afe_pmsn_master_control2);
2075 udelay(AFE_REGISTER_WRITE_DELAY);
2076 }
2077
2078 /* Configure bias currents to normal */
2079 if (is_a2(pdev))
2080 writel(0x00005A00, &afe->afe_bias_control);
2081 else if (is_b0(pdev) || is_c0(pdev))
2082 writel(0x00005F00, &afe->afe_bias_control);
2083 else if (is_c1(pdev))
2084 writel(0x00005500, &afe->afe_bias_control);
2085
2086 udelay(AFE_REGISTER_WRITE_DELAY);
2087
2088 /* Enable PLL */
2089 if (is_a2(pdev))
2090 writel(0x80040908, &afe->afe_pll_control0);
2091 else if (is_b0(pdev) || is_c0(pdev))
2092 writel(0x80040A08, &afe->afe_pll_control0);
2093 else if (is_c1(pdev)) {
2094 writel(0x80000B08, &afe->afe_pll_control0);
2095 udelay(AFE_REGISTER_WRITE_DELAY);
2096 writel(0x00000B08, &afe->afe_pll_control0);
2097 udelay(AFE_REGISTER_WRITE_DELAY);
2098 writel(0x80000B08, &afe->afe_pll_control0);
2099 }
2100
2101 udelay(AFE_REGISTER_WRITE_DELAY);
2102
2103 /* Wait for the PLL to lock */
2104 do {
2105 afe_status = readl(&afe->afe_common_block_status);
2106 udelay(AFE_REGISTER_WRITE_DELAY);
2107 } while ((afe_status & 0x00001000) == 0);
2108
2109 if (is_a2(pdev)) {
2110 /* Shorten SAS SNW lock time (RxLock timer value from 76
2111 * us to 50 us)
2112 */
2113 writel(0x7bcc96ad, &afe->afe_pmsn_master_control0);
2114 udelay(AFE_REGISTER_WRITE_DELAY);
2115 }
2116
2117 for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) {
2118 struct scu_afe_transceiver *xcvr = &afe->scu_afe_xcvr[phy_id];
2119 const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id];
2120 int cable_length_long =
2121 is_long_cable(phy_id, cable_selection_mask);
2122 int cable_length_medium =
2123 is_medium_cable(phy_id, cable_selection_mask);
2124
2125 if (is_a2(pdev)) {
2126 /* All defaults, except the Receive Word
2127 * Alignament/Comma Detect Enable....(0xe800)
2128 */
2129 writel(0x00004512, &xcvr->afe_xcvr_control0);
2130 udelay(AFE_REGISTER_WRITE_DELAY);
2131
2132 writel(0x0050100F, &xcvr->afe_xcvr_control1);
2133 udelay(AFE_REGISTER_WRITE_DELAY);
2134 } else if (is_b0(pdev)) {
2135 /* Configure transmitter SSC parameters */
2136 writel(0x00030000, &xcvr->afe_tx_ssc_control);
2137 udelay(AFE_REGISTER_WRITE_DELAY);
2138 } else if (is_c0(pdev)) {
2139 /* Configure transmitter SSC parameters */
2140 writel(0x00010202, &xcvr->afe_tx_ssc_control);
2141 udelay(AFE_REGISTER_WRITE_DELAY);
2142
2143 /* All defaults, except the Receive Word
2144 * Alignament/Comma Detect Enable....(0xe800)
2145 */
2146 writel(0x00014500, &xcvr->afe_xcvr_control0);
2147 udelay(AFE_REGISTER_WRITE_DELAY);
2148 } else if (is_c1(pdev)) {
2149 /* Configure transmitter SSC parameters */
2150 writel(0x00010202, &xcvr->afe_tx_ssc_control);
2151 udelay(AFE_REGISTER_WRITE_DELAY);
2152
2153 /* All defaults, except the Receive Word
2154 * Alignament/Comma Detect Enable....(0xe800)
2155 */
2156 writel(0x0001C500, &xcvr->afe_xcvr_control0);
2157 udelay(AFE_REGISTER_WRITE_DELAY);
2158 }
2159
2160 /* Power up TX and RX out from power down (PWRDNTX and
2161 * PWRDNRX) & increase TX int & ext bias 20%....(0xe85c)
2162 */
2163 if (is_a2(pdev))
2164 writel(0x000003F0, &xcvr->afe_channel_control);
2165 else if (is_b0(pdev)) {
2166 writel(0x000003D7, &xcvr->afe_channel_control);
2167 udelay(AFE_REGISTER_WRITE_DELAY);
2168
2169 writel(0x000003D4, &xcvr->afe_channel_control);
2170 } else if (is_c0(pdev)) {
2171 writel(0x000001E7, &xcvr->afe_channel_control);
2172 udelay(AFE_REGISTER_WRITE_DELAY);
2173
2174 writel(0x000001E4, &xcvr->afe_channel_control);
2175 } else if (is_c1(pdev)) {
2176 writel(cable_length_long ? 0x000002F7 : 0x000001F7,
2177 &xcvr->afe_channel_control);
2178 udelay(AFE_REGISTER_WRITE_DELAY);
2179
2180 writel(cable_length_long ? 0x000002F4 : 0x000001F4,
2181 &xcvr->afe_channel_control);
2182 }
2183 udelay(AFE_REGISTER_WRITE_DELAY);
2184
2185 if (is_a2(pdev)) {
2186 /* Enable TX equalization (0xe824) */
2187 writel(0x00040000, &xcvr->afe_tx_control);
2188 udelay(AFE_REGISTER_WRITE_DELAY);
2189 }
2190
2191 if (is_a2(pdev) || is_b0(pdev))
2192 /* RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0,
2193 * TPD=0x0(TX Power On), RDD=0x0(RX Detect
2194 * Enabled) ....(0xe800)
2195 */
2196 writel(0x00004100, &xcvr->afe_xcvr_control0);
2197 else if (is_c0(pdev))
2198 writel(0x00014100, &xcvr->afe_xcvr_control0);
2199 else if (is_c1(pdev))
2200 writel(0x0001C100, &xcvr->afe_xcvr_control0);
2201 udelay(AFE_REGISTER_WRITE_DELAY);
2202
2203 /* Leave DFE/FFE on */
2204 if (is_a2(pdev))
2205 writel(0x3F11103F, &xcvr->afe_rx_ssc_control0);
2206 else if (is_b0(pdev)) {
2207 writel(0x3F11103F, &xcvr->afe_rx_ssc_control0);
2208 udelay(AFE_REGISTER_WRITE_DELAY);
2209 /* Enable TX equalization (0xe824) */
2210 writel(0x00040000, &xcvr->afe_tx_control);
2211 } else if (is_c0(pdev)) {
2212 writel(0x01400C0F, &xcvr->afe_rx_ssc_control1);
2213 udelay(AFE_REGISTER_WRITE_DELAY);
2214
2215 writel(0x3F6F103F, &xcvr->afe_rx_ssc_control0);
2216 udelay(AFE_REGISTER_WRITE_DELAY);
2217
2218 /* Enable TX equalization (0xe824) */
2219 writel(0x00040000, &xcvr->afe_tx_control);
2220 } else if (is_c1(pdev)) {
2221 writel(cable_length_long ? 0x01500C0C :
2222 cable_length_medium ? 0x01400C0D : 0x02400C0D,
2223 &xcvr->afe_xcvr_control1);
2224 udelay(AFE_REGISTER_WRITE_DELAY);
2225
2226 writel(0x000003E0, &xcvr->afe_dfx_rx_control1);
2227 udelay(AFE_REGISTER_WRITE_DELAY);
2228
2229 writel(cable_length_long ? 0x33091C1F :
2230 cable_length_medium ? 0x3315181F : 0x2B17161F,
2231 &xcvr->afe_rx_ssc_control0);
2232 udelay(AFE_REGISTER_WRITE_DELAY);
2233
2234 /* Enable TX equalization (0xe824) */
2235 writel(0x00040000, &xcvr->afe_tx_control);
2236 }
2237
2238 udelay(AFE_REGISTER_WRITE_DELAY);
2239
2240 writel(oem_phy->afe_tx_amp_control0, &xcvr->afe_tx_amp_control0);
2241 udelay(AFE_REGISTER_WRITE_DELAY);
2242
2243 writel(oem_phy->afe_tx_amp_control1, &xcvr->afe_tx_amp_control1);
2244 udelay(AFE_REGISTER_WRITE_DELAY);
2245
2246 writel(oem_phy->afe_tx_amp_control2, &xcvr->afe_tx_amp_control2);
2247 udelay(AFE_REGISTER_WRITE_DELAY);
2248
2249 writel(oem_phy->afe_tx_amp_control3, &xcvr->afe_tx_amp_control3);
2250 udelay(AFE_REGISTER_WRITE_DELAY);
2251 }
2252
2253 /* Transfer control to the PEs */
2254 writel(0x00010f00, &afe->afe_dfx_master_control0);
2255 udelay(AFE_REGISTER_WRITE_DELAY);
2256 }
2257
2258 static void sci_controller_initialize_power_control(struct isci_host *ihost)
2259 {
2260 sci_init_timer(&ihost->power_control.timer, power_control_timeout);
2261
2262 memset(ihost->power_control.requesters, 0,
2263 sizeof(ihost->power_control.requesters));
2264
2265 ihost->power_control.phys_waiting = 0;
2266 ihost->power_control.phys_granted_power = 0;
2267 }
2268
2269 static enum sci_status sci_controller_initialize(struct isci_host *ihost)
2270 {
2271 struct sci_base_state_machine *sm = &ihost->sm;
2272 enum sci_status result = SCI_FAILURE;
2273 unsigned long i, state, val;
2274
2275 if (ihost->sm.current_state_id != SCIC_RESET) {
2276 dev_warn(&ihost->pdev->dev,
2277 "SCIC Controller initialize operation requested "
2278 "in invalid state\n");
2279 return SCI_FAILURE_INVALID_STATE;
2280 }
2281
2282 sci_change_state(sm, SCIC_INITIALIZING);
2283
2284 sci_init_timer(&ihost->phy_timer, phy_startup_timeout);
2285
2286 ihost->next_phy_to_start = 0;
2287 ihost->phy_startup_timer_pending = false;
2288
2289 sci_controller_initialize_power_control(ihost);
2290
2291 /*
2292 * There is nothing to do here for B0 since we do not have to
2293 * program the AFE registers.
2294 * / @todo The AFE settings are supposed to be correct for the B0 but
2295 * / presently they seem to be wrong. */
2296 sci_controller_afe_initialization(ihost);
2297
2298
2299 /* Take the hardware out of reset */
2300 writel(0, &ihost->smu_registers->soft_reset_control);
2301
2302 /*
2303 * / @todo Provide meaningfull error code for hardware failure
2304 * result = SCI_FAILURE_CONTROLLER_HARDWARE; */
2305 for (i = 100; i >= 1; i--) {
2306 u32 status;
2307
2308 /* Loop until the hardware reports success */
2309 udelay(SCU_CONTEXT_RAM_INIT_STALL_TIME);
2310 status = readl(&ihost->smu_registers->control_status);
2311
2312 if ((status & SCU_RAM_INIT_COMPLETED) == SCU_RAM_INIT_COMPLETED)
2313 break;
2314 }
2315 if (i == 0)
2316 goto out;
2317
2318 /*
2319 * Determine what are the actaul device capacities that the
2320 * hardware will support */
2321 val = readl(&ihost->smu_registers->device_context_capacity);
2322
2323 /* Record the smaller of the two capacity values */
2324 ihost->logical_port_entries = min(smu_max_ports(val), SCI_MAX_PORTS);
2325 ihost->task_context_entries = min(smu_max_task_contexts(val), SCI_MAX_IO_REQUESTS);
2326 ihost->remote_node_entries = min(smu_max_rncs(val), SCI_MAX_REMOTE_DEVICES);
2327
2328 /*
2329 * Make all PEs that are unassigned match up with the
2330 * logical ports
2331 */
2332 for (i = 0; i < ihost->logical_port_entries; i++) {
2333 struct scu_port_task_scheduler_group_registers __iomem
2334 *ptsg = &ihost->scu_registers->peg0.ptsg;
2335
2336 writel(i, &ptsg->protocol_engine[i]);
2337 }
2338
2339 /* Initialize hardware PCI Relaxed ordering in DMA engines */
2340 val = readl(&ihost->scu_registers->sdma.pdma_configuration);
2341 val |= SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
2342 writel(val, &ihost->scu_registers->sdma.pdma_configuration);
2343
2344 val = readl(&ihost->scu_registers->sdma.cdma_configuration);
2345 val |= SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
2346 writel(val, &ihost->scu_registers->sdma.cdma_configuration);
2347
2348 /*
2349 * Initialize the PHYs before the PORTs because the PHY registers
2350 * are accessed during the port initialization.
2351 */
2352 for (i = 0; i < SCI_MAX_PHYS; i++) {
2353 result = sci_phy_initialize(&ihost->phys[i],
2354 &ihost->scu_registers->peg0.pe[i].tl,
2355 &ihost->scu_registers->peg0.pe[i].ll);
2356 if (result != SCI_SUCCESS)
2357 goto out;
2358 }
2359
2360 for (i = 0; i < ihost->logical_port_entries; i++) {
2361 struct isci_port *iport = &ihost->ports[i];
2362
2363 iport->port_task_scheduler_registers = &ihost->scu_registers->peg0.ptsg.port[i];
2364 iport->port_pe_configuration_register = &ihost->scu_registers->peg0.ptsg.protocol_engine[0];
2365 iport->viit_registers = &ihost->scu_registers->peg0.viit[i];
2366 }
2367
2368 result = sci_port_configuration_agent_initialize(ihost, &ihost->port_agent);
2369
2370 out:
2371 /* Advance the controller state machine */
2372 if (result == SCI_SUCCESS)
2373 state = SCIC_INITIALIZED;
2374 else
2375 state = SCIC_FAILED;
2376 sci_change_state(sm, state);
2377
2378 return result;
2379 }
2380
2381 static enum sci_status sci_user_parameters_set(struct isci_host *ihost,
2382 struct sci_user_parameters *sci_parms)
2383 {
2384 u32 state = ihost->sm.current_state_id;
2385
2386 if (state == SCIC_RESET ||
2387 state == SCIC_INITIALIZING ||
2388 state == SCIC_INITIALIZED) {
2389 u16 index;
2390
2391 /*
2392 * Validate the user parameters. If they are not legal, then
2393 * return a failure.
2394 */
2395 for (index = 0; index < SCI_MAX_PHYS; index++) {
2396 struct sci_phy_user_params *user_phy;
2397
2398 user_phy = &sci_parms->phys[index];
2399
2400 if (!((user_phy->max_speed_generation <=
2401 SCIC_SDS_PARM_MAX_SPEED) &&
2402 (user_phy->max_speed_generation >
2403 SCIC_SDS_PARM_NO_SPEED)))
2404 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2405
2406 if (user_phy->in_connection_align_insertion_frequency <
2407 3)
2408 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2409
2410 if ((user_phy->in_connection_align_insertion_frequency <
2411 3) ||
2412 (user_phy->align_insertion_frequency == 0) ||
2413 (user_phy->
2414 notify_enable_spin_up_insertion_frequency ==
2415 0))
2416 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2417 }
2418
2419 if ((sci_parms->stp_inactivity_timeout == 0) ||
2420 (sci_parms->ssp_inactivity_timeout == 0) ||
2421 (sci_parms->stp_max_occupancy_timeout == 0) ||
2422 (sci_parms->ssp_max_occupancy_timeout == 0) ||
2423 (sci_parms->no_outbound_task_timeout == 0))
2424 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
2425
2426 memcpy(&ihost->user_parameters, sci_parms, sizeof(*sci_parms));
2427
2428 return SCI_SUCCESS;
2429 }
2430
2431 return SCI_FAILURE_INVALID_STATE;
2432 }
2433
2434 static int sci_controller_mem_init(struct isci_host *ihost)
2435 {
2436 struct device *dev = &ihost->pdev->dev;
2437 dma_addr_t dma;
2438 size_t size;
2439 int err;
2440
2441 size = SCU_MAX_COMPLETION_QUEUE_ENTRIES * sizeof(u32);
2442 ihost->completion_queue = dmam_alloc_coherent(dev, size, &dma, GFP_KERNEL);
2443 if (!ihost->completion_queue)
2444 return -ENOMEM;
2445
2446 writel(lower_32_bits(dma), &ihost->smu_registers->completion_queue_lower);
2447 writel(upper_32_bits(dma), &ihost->smu_registers->completion_queue_upper);
2448
2449 size = ihost->remote_node_entries * sizeof(union scu_remote_node_context);
2450 ihost->remote_node_context_table = dmam_alloc_coherent(dev, size, &dma,
2451 GFP_KERNEL);
2452 if (!ihost->remote_node_context_table)
2453 return -ENOMEM;
2454
2455 writel(lower_32_bits(dma), &ihost->smu_registers->remote_node_context_lower);
2456 writel(upper_32_bits(dma), &ihost->smu_registers->remote_node_context_upper);
2457
2458 size = ihost->task_context_entries * sizeof(struct scu_task_context),
2459 ihost->task_context_table = dmam_alloc_coherent(dev, size, &dma, GFP_KERNEL);
2460 if (!ihost->task_context_table)
2461 return -ENOMEM;
2462
2463 ihost->task_context_dma = dma;
2464 writel(lower_32_bits(dma), &ihost->smu_registers->host_task_table_lower);
2465 writel(upper_32_bits(dma), &ihost->smu_registers->host_task_table_upper);
2466
2467 err = sci_unsolicited_frame_control_construct(ihost);
2468 if (err)
2469 return err;
2470
2471 /*
2472 * Inform the silicon as to the location of the UF headers and
2473 * address table.
2474 */
2475 writel(lower_32_bits(ihost->uf_control.headers.physical_address),
2476 &ihost->scu_registers->sdma.uf_header_base_address_lower);
2477 writel(upper_32_bits(ihost->uf_control.headers.physical_address),
2478 &ihost->scu_registers->sdma.uf_header_base_address_upper);
2479
2480 writel(lower_32_bits(ihost->uf_control.address_table.physical_address),
2481 &ihost->scu_registers->sdma.uf_address_table_lower);
2482 writel(upper_32_bits(ihost->uf_control.address_table.physical_address),
2483 &ihost->scu_registers->sdma.uf_address_table_upper);
2484
2485 return 0;
2486 }
2487
2488 int isci_host_init(struct isci_host *ihost)
2489 {
2490 int err = 0, i;
2491 enum sci_status status;
2492 struct sci_user_parameters sci_user_params;
2493 struct isci_pci_info *pci_info = to_pci_info(ihost->pdev);
2494
2495 spin_lock_init(&ihost->state_lock);
2496 spin_lock_init(&ihost->scic_lock);
2497 init_waitqueue_head(&ihost->eventq);
2498
2499 isci_host_change_state(ihost, isci_starting);
2500
2501 status = sci_controller_construct(ihost, scu_base(ihost),
2502 smu_base(ihost));
2503
2504 if (status != SCI_SUCCESS) {
2505 dev_err(&ihost->pdev->dev,
2506 "%s: sci_controller_construct failed - status = %x\n",
2507 __func__,
2508 status);
2509 return -ENODEV;
2510 }
2511
2512 ihost->sas_ha.dev = &ihost->pdev->dev;
2513 ihost->sas_ha.lldd_ha = ihost;
2514
2515 /*
2516 * grab initial values stored in the controller object for OEM and USER
2517 * parameters
2518 */
2519 isci_user_parameters_get(&sci_user_params);
2520 status = sci_user_parameters_set(ihost, &sci_user_params);
2521 if (status != SCI_SUCCESS) {
2522 dev_warn(&ihost->pdev->dev,
2523 "%s: sci_user_parameters_set failed\n",
2524 __func__);
2525 return -ENODEV;
2526 }
2527
2528 /* grab any OEM parameters specified in orom */
2529 if (pci_info->orom) {
2530 status = isci_parse_oem_parameters(&ihost->oem_parameters,
2531 pci_info->orom,
2532 ihost->id);
2533 if (status != SCI_SUCCESS) {
2534 dev_warn(&ihost->pdev->dev,
2535 "parsing firmware oem parameters failed\n");
2536 return -EINVAL;
2537 }
2538 }
2539
2540 status = sci_oem_parameters_set(ihost);
2541 if (status != SCI_SUCCESS) {
2542 dev_warn(&ihost->pdev->dev,
2543 "%s: sci_oem_parameters_set failed\n",
2544 __func__);
2545 return -ENODEV;
2546 }
2547
2548 tasklet_init(&ihost->completion_tasklet,
2549 isci_host_completion_routine, (unsigned long)ihost);
2550
2551 INIT_LIST_HEAD(&ihost->requests_to_complete);
2552 INIT_LIST_HEAD(&ihost->requests_to_errorback);
2553
2554 spin_lock_irq(&ihost->scic_lock);
2555 status = sci_controller_initialize(ihost);
2556 spin_unlock_irq(&ihost->scic_lock);
2557 if (status != SCI_SUCCESS) {
2558 dev_warn(&ihost->pdev->dev,
2559 "%s: sci_controller_initialize failed -"
2560 " status = 0x%x\n",
2561 __func__, status);
2562 return -ENODEV;
2563 }
2564
2565 err = sci_controller_mem_init(ihost);
2566 if (err)
2567 return err;
2568
2569 for (i = 0; i < SCI_MAX_PORTS; i++)
2570 isci_port_init(&ihost->ports[i], ihost, i);
2571
2572 for (i = 0; i < SCI_MAX_PHYS; i++)
2573 isci_phy_init(&ihost->phys[i], ihost, i);
2574
2575 /* enable sgpio */
2576 writel(1, &ihost->scu_registers->peg0.sgpio.interface_control);
2577 for (i = 0; i < isci_gpio_count(ihost); i++)
2578 writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]);
2579 writel(0, &ihost->scu_registers->peg0.sgpio.vendor_specific_code);
2580
2581 for (i = 0; i < SCI_MAX_REMOTE_DEVICES; i++) {
2582 struct isci_remote_device *idev = &ihost->devices[i];
2583
2584 INIT_LIST_HEAD(&idev->reqs_in_process);
2585 INIT_LIST_HEAD(&idev->node);
2586 }
2587
2588 for (i = 0; i < SCI_MAX_IO_REQUESTS; i++) {
2589 struct isci_request *ireq;
2590 dma_addr_t dma;
2591
2592 ireq = dmam_alloc_coherent(&ihost->pdev->dev,
2593 sizeof(struct isci_request), &dma,
2594 GFP_KERNEL);
2595 if (!ireq)
2596 return -ENOMEM;
2597
2598 ireq->tc = &ihost->task_context_table[i];
2599 ireq->owning_controller = ihost;
2600 spin_lock_init(&ireq->state_lock);
2601 ireq->request_daddr = dma;
2602 ireq->isci_host = ihost;
2603 ihost->reqs[i] = ireq;
2604 }
2605
2606 return 0;
2607 }
2608
2609 void sci_controller_link_up(struct isci_host *ihost, struct isci_port *iport,
2610 struct isci_phy *iphy)
2611 {
2612 switch (ihost->sm.current_state_id) {
2613 case SCIC_STARTING:
2614 sci_del_timer(&ihost->phy_timer);
2615 ihost->phy_startup_timer_pending = false;
2616 ihost->port_agent.link_up_handler(ihost, &ihost->port_agent,
2617 iport, iphy);
2618 sci_controller_start_next_phy(ihost);
2619 break;
2620 case SCIC_READY:
2621 ihost->port_agent.link_up_handler(ihost, &ihost->port_agent,
2622 iport, iphy);
2623 break;
2624 default:
2625 dev_dbg(&ihost->pdev->dev,
2626 "%s: SCIC Controller linkup event from phy %d in "
2627 "unexpected state %d\n", __func__, iphy->phy_index,
2628 ihost->sm.current_state_id);
2629 }
2630 }
2631
2632 void sci_controller_link_down(struct isci_host *ihost, struct isci_port *iport,
2633 struct isci_phy *iphy)
2634 {
2635 switch (ihost->sm.current_state_id) {
2636 case SCIC_STARTING:
2637 case SCIC_READY:
2638 ihost->port_agent.link_down_handler(ihost, &ihost->port_agent,
2639 iport, iphy);
2640 break;
2641 default:
2642 dev_dbg(&ihost->pdev->dev,
2643 "%s: SCIC Controller linkdown event from phy %d in "
2644 "unexpected state %d\n",
2645 __func__,
2646 iphy->phy_index,
2647 ihost->sm.current_state_id);
2648 }
2649 }
2650
2651 static bool sci_controller_has_remote_devices_stopping(struct isci_host *ihost)
2652 {
2653 u32 index;
2654
2655 for (index = 0; index < ihost->remote_node_entries; index++) {
2656 if ((ihost->device_table[index] != NULL) &&
2657 (ihost->device_table[index]->sm.current_state_id == SCI_DEV_STOPPING))
2658 return true;
2659 }
2660
2661 return false;
2662 }
2663
2664 void sci_controller_remote_device_stopped(struct isci_host *ihost,
2665 struct isci_remote_device *idev)
2666 {
2667 if (ihost->sm.current_state_id != SCIC_STOPPING) {
2668 dev_dbg(&ihost->pdev->dev,
2669 "SCIC Controller 0x%p remote device stopped event "
2670 "from device 0x%p in unexpected state %d\n",
2671 ihost, idev,
2672 ihost->sm.current_state_id);
2673 return;
2674 }
2675
2676 if (!sci_controller_has_remote_devices_stopping(ihost))
2677 sci_change_state(&ihost->sm, SCIC_STOPPED);
2678 }
2679
2680 void sci_controller_post_request(struct isci_host *ihost, u32 request)
2681 {
2682 dev_dbg(&ihost->pdev->dev, "%s[%d]: %#x\n",
2683 __func__, ihost->id, request);
2684
2685 writel(request, &ihost->smu_registers->post_context_port);
2686 }
2687
2688 struct isci_request *sci_request_by_tag(struct isci_host *ihost, u16 io_tag)
2689 {
2690 u16 task_index;
2691 u16 task_sequence;
2692
2693 task_index = ISCI_TAG_TCI(io_tag);
2694
2695 if (task_index < ihost->task_context_entries) {
2696 struct isci_request *ireq = ihost->reqs[task_index];
2697
2698 if (test_bit(IREQ_ACTIVE, &ireq->flags)) {
2699 task_sequence = ISCI_TAG_SEQ(io_tag);
2700
2701 if (task_sequence == ihost->io_request_sequence[task_index])
2702 return ireq;
2703 }
2704 }
2705
2706 return NULL;
2707 }
2708
2709 /**
2710 * This method allocates remote node index and the reserves the remote node
2711 * context space for use. This method can fail if there are no more remote
2712 * node index available.
2713 * @scic: This is the controller object which contains the set of
2714 * free remote node ids
2715 * @sci_dev: This is the device object which is requesting the a remote node
2716 * id
2717 * @node_id: This is the remote node id that is assinged to the device if one
2718 * is available
2719 *
2720 * enum sci_status SCI_FAILURE_OUT_OF_RESOURCES if there are no available remote
2721 * node index available.
2722 */
2723 enum sci_status sci_controller_allocate_remote_node_context(struct isci_host *ihost,
2724 struct isci_remote_device *idev,
2725 u16 *node_id)
2726 {
2727 u16 node_index;
2728 u32 remote_node_count = sci_remote_device_node_count(idev);
2729
2730 node_index = sci_remote_node_table_allocate_remote_node(
2731 &ihost->available_remote_nodes, remote_node_count
2732 );
2733
2734 if (node_index != SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
2735 ihost->device_table[node_index] = idev;
2736
2737 *node_id = node_index;
2738
2739 return SCI_SUCCESS;
2740 }
2741
2742 return SCI_FAILURE_INSUFFICIENT_RESOURCES;
2743 }
2744
2745 void sci_controller_free_remote_node_context(struct isci_host *ihost,
2746 struct isci_remote_device *idev,
2747 u16 node_id)
2748 {
2749 u32 remote_node_count = sci_remote_device_node_count(idev);
2750
2751 if (ihost->device_table[node_id] == idev) {
2752 ihost->device_table[node_id] = NULL;
2753
2754 sci_remote_node_table_release_remote_node_index(
2755 &ihost->available_remote_nodes, remote_node_count, node_id
2756 );
2757 }
2758 }
2759
2760 void sci_controller_copy_sata_response(void *response_buffer,
2761 void *frame_header,
2762 void *frame_buffer)
2763 {
2764 /* XXX type safety? */
2765 memcpy(response_buffer, frame_header, sizeof(u32));
2766
2767 memcpy(response_buffer + sizeof(u32),
2768 frame_buffer,
2769 sizeof(struct dev_to_host_fis) - sizeof(u32));
2770 }
2771
2772 void sci_controller_release_frame(struct isci_host *ihost, u32 frame_index)
2773 {
2774 if (sci_unsolicited_frame_control_release_frame(&ihost->uf_control, frame_index))
2775 writel(ihost->uf_control.get,
2776 &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
2777 }
2778
2779 void isci_tci_free(struct isci_host *ihost, u16 tci)
2780 {
2781 u16 tail = ihost->tci_tail & (SCI_MAX_IO_REQUESTS-1);
2782
2783 ihost->tci_pool[tail] = tci;
2784 ihost->tci_tail = tail + 1;
2785 }
2786
2787 static u16 isci_tci_alloc(struct isci_host *ihost)
2788 {
2789 u16 head = ihost->tci_head & (SCI_MAX_IO_REQUESTS-1);
2790 u16 tci = ihost->tci_pool[head];
2791
2792 ihost->tci_head = head + 1;
2793 return tci;
2794 }
2795
2796 static u16 isci_tci_space(struct isci_host *ihost)
2797 {
2798 return CIRC_SPACE(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS);
2799 }
2800
2801 u16 isci_alloc_tag(struct isci_host *ihost)
2802 {
2803 if (isci_tci_space(ihost)) {
2804 u16 tci = isci_tci_alloc(ihost);
2805 u8 seq = ihost->io_request_sequence[tci];
2806
2807 return ISCI_TAG(seq, tci);
2808 }
2809
2810 return SCI_CONTROLLER_INVALID_IO_TAG;
2811 }
2812
2813 enum sci_status isci_free_tag(struct isci_host *ihost, u16 io_tag)
2814 {
2815 u16 tci = ISCI_TAG_TCI(io_tag);
2816 u16 seq = ISCI_TAG_SEQ(io_tag);
2817
2818 /* prevent tail from passing head */
2819 if (isci_tci_active(ihost) == 0)
2820 return SCI_FAILURE_INVALID_IO_TAG;
2821
2822 if (seq == ihost->io_request_sequence[tci]) {
2823 ihost->io_request_sequence[tci] = (seq+1) & (SCI_MAX_SEQ-1);
2824
2825 isci_tci_free(ihost, tci);
2826
2827 return SCI_SUCCESS;
2828 }
2829 return SCI_FAILURE_INVALID_IO_TAG;
2830 }
2831
2832 enum sci_status sci_controller_start_io(struct isci_host *ihost,
2833 struct isci_remote_device *idev,
2834 struct isci_request *ireq)
2835 {
2836 enum sci_status status;
2837
2838 if (ihost->sm.current_state_id != SCIC_READY) {
2839 dev_warn(&ihost->pdev->dev, "invalid state to start I/O");
2840 return SCI_FAILURE_INVALID_STATE;
2841 }
2842
2843 status = sci_remote_device_start_io(ihost, idev, ireq);
2844 if (status != SCI_SUCCESS)
2845 return status;
2846
2847 set_bit(IREQ_ACTIVE, &ireq->flags);
2848 sci_controller_post_request(ihost, ireq->post_context);
2849 return SCI_SUCCESS;
2850 }
2851
2852 enum sci_status sci_controller_terminate_request(struct isci_host *ihost,
2853 struct isci_remote_device *idev,
2854 struct isci_request *ireq)
2855 {
2856 /* terminate an ongoing (i.e. started) core IO request. This does not
2857 * abort the IO request at the target, but rather removes the IO
2858 * request from the host controller.
2859 */
2860 enum sci_status status;
2861
2862 if (ihost->sm.current_state_id != SCIC_READY) {
2863 dev_warn(&ihost->pdev->dev,
2864 "invalid state to terminate request\n");
2865 return SCI_FAILURE_INVALID_STATE;
2866 }
2867
2868 status = sci_io_request_terminate(ireq);
2869 if (status != SCI_SUCCESS)
2870 return status;
2871
2872 /*
2873 * Utilize the original post context command and or in the POST_TC_ABORT
2874 * request sub-type.
2875 */
2876 sci_controller_post_request(ihost,
2877 ireq->post_context | SCU_CONTEXT_COMMAND_REQUEST_POST_TC_ABORT);
2878 return SCI_SUCCESS;
2879 }
2880
2881 /**
2882 * sci_controller_complete_io() - This method will perform core specific
2883 * completion operations for an IO request. After this method is invoked,
2884 * the user should consider the IO request as invalid until it is properly
2885 * reused (i.e. re-constructed).
2886 * @ihost: The handle to the controller object for which to complete the
2887 * IO request.
2888 * @idev: The handle to the remote device object for which to complete
2889 * the IO request.
2890 * @ireq: the handle to the io request object to complete.
2891 */
2892 enum sci_status sci_controller_complete_io(struct isci_host *ihost,
2893 struct isci_remote_device *idev,
2894 struct isci_request *ireq)
2895 {
2896 enum sci_status status;
2897 u16 index;
2898
2899 switch (ihost->sm.current_state_id) {
2900 case SCIC_STOPPING:
2901 /* XXX: Implement this function */
2902 return SCI_FAILURE;
2903 case SCIC_READY:
2904 status = sci_remote_device_complete_io(ihost, idev, ireq);
2905 if (status != SCI_SUCCESS)
2906 return status;
2907
2908 index = ISCI_TAG_TCI(ireq->io_tag);
2909 clear_bit(IREQ_ACTIVE, &ireq->flags);
2910 return SCI_SUCCESS;
2911 default:
2912 dev_warn(&ihost->pdev->dev, "invalid state to complete I/O");
2913 return SCI_FAILURE_INVALID_STATE;
2914 }
2915
2916 }
2917
2918 enum sci_status sci_controller_continue_io(struct isci_request *ireq)
2919 {
2920 struct isci_host *ihost = ireq->owning_controller;
2921
2922 if (ihost->sm.current_state_id != SCIC_READY) {
2923 dev_warn(&ihost->pdev->dev, "invalid state to continue I/O");
2924 return SCI_FAILURE_INVALID_STATE;
2925 }
2926
2927 set_bit(IREQ_ACTIVE, &ireq->flags);
2928 sci_controller_post_request(ihost, ireq->post_context);
2929 return SCI_SUCCESS;
2930 }
2931
2932 /**
2933 * sci_controller_start_task() - This method is called by the SCIC user to
2934 * send/start a framework task management request.
2935 * @controller: the handle to the controller object for which to start the task
2936 * management request.
2937 * @remote_device: the handle to the remote device object for which to start
2938 * the task management request.
2939 * @task_request: the handle to the task request object to start.
2940 */
2941 enum sci_task_status sci_controller_start_task(struct isci_host *ihost,
2942 struct isci_remote_device *idev,
2943 struct isci_request *ireq)
2944 {
2945 enum sci_status status;
2946
2947 if (ihost->sm.current_state_id != SCIC_READY) {
2948 dev_warn(&ihost->pdev->dev,
2949 "%s: SCIC Controller starting task from invalid "
2950 "state\n",
2951 __func__);
2952 return SCI_TASK_FAILURE_INVALID_STATE;
2953 }
2954
2955 status = sci_remote_device_start_task(ihost, idev, ireq);
2956 switch (status) {
2957 case SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS:
2958 set_bit(IREQ_ACTIVE, &ireq->flags);
2959
2960 /*
2961 * We will let framework know this task request started successfully,
2962 * although core is still woring on starting the request (to post tc when
2963 * RNC is resumed.)
2964 */
2965 return SCI_SUCCESS;
2966 case SCI_SUCCESS:
2967 set_bit(IREQ_ACTIVE, &ireq->flags);
2968 sci_controller_post_request(ihost, ireq->post_context);
2969 break;
2970 default:
2971 break;
2972 }
2973
2974 return status;
2975 }
2976
2977 static int sci_write_gpio_tx_gp(struct isci_host *ihost, u8 reg_index, u8 reg_count, u8 *write_data)
2978 {
2979 int d;
2980
2981 /* no support for TX_GP_CFG */
2982 if (reg_index == 0)
2983 return -EINVAL;
2984
2985 for (d = 0; d < isci_gpio_count(ihost); d++) {
2986 u32 val = 0x444; /* all ODx.n clear */
2987 int i;
2988
2989 for (i = 0; i < 3; i++) {
2990 int bit = (i << 2) + 2;
2991
2992 bit = try_test_sas_gpio_gp_bit(to_sas_gpio_od(d, i),
2993 write_data, reg_index,
2994 reg_count);
2995 if (bit < 0)
2996 break;
2997
2998 /* if od is set, clear the 'invert' bit */
2999 val &= ~(bit << ((i << 2) + 2));
3000 }
3001
3002 if (i < 3)
3003 break;
3004 writel(val, &ihost->scu_registers->peg0.sgpio.output_data_select[d]);
3005 }
3006
3007 /* unless reg_index is > 1, we should always be able to write at
3008 * least one register
3009 */
3010 return d > 0;
3011 }
3012
3013 int isci_gpio_write(struct sas_ha_struct *sas_ha, u8 reg_type, u8 reg_index,
3014 u8 reg_count, u8 *write_data)
3015 {
3016 struct isci_host *ihost = sas_ha->lldd_ha;
3017 int written;
3018
3019 switch (reg_type) {
3020 case SAS_GPIO_REG_TX_GP:
3021 written = sci_write_gpio_tx_gp(ihost, reg_index, reg_count, write_data);
3022 break;
3023 default:
3024 written = -EINVAL;
3025 }
3026
3027 return written;
3028 }